2 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * Copyright 2008 Openmoko, Inc.
6 * Copyright 2008 Simtec Electronics
7 * Ben Dooks <ben@simtec.co.uk>
8 * http://armlinux.simtec.co.uk/
10 * S3C USB2.0 High-speed / OtG driver
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/spinlock.h>
20 #include <linux/interrupt.h>
21 #include <linux/platform_device.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/mutex.h>
24 #include <linux/seq_file.h>
25 #include <linux/delay.h>
27 #include <linux/slab.h>
28 #include <linux/of_platform.h>
30 #include <linux/usb/ch9.h>
31 #include <linux/usb/gadget.h>
32 #include <linux/usb/phy.h>
37 /* conversion functions */
38 static inline struct dwc2_hsotg_req *our_req(struct usb_request *req)
40 return container_of(req, struct dwc2_hsotg_req, req);
43 static inline struct dwc2_hsotg_ep *our_ep(struct usb_ep *ep)
45 return container_of(ep, struct dwc2_hsotg_ep, ep);
48 static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget)
50 return container_of(gadget, struct dwc2_hsotg, gadget);
53 static inline void __orr32(void __iomem *ptr, u32 val)
55 dwc2_writel(dwc2_readl(ptr) | val, ptr);
58 static inline void __bic32(void __iomem *ptr, u32 val)
60 dwc2_writel(dwc2_readl(ptr) & ~val, ptr);
63 static inline struct dwc2_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg,
64 u32 ep_index, u32 dir_in)
67 return hsotg->eps_in[ep_index];
69 return hsotg->eps_out[ep_index];
72 /* forward declaration of functions */
73 static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg);
76 * using_dma - return the DMA status of the driver.
77 * @hsotg: The driver state.
79 * Return true if we're using DMA.
81 * Currently, we have the DMA support code worked into everywhere
82 * that needs it, but the AMBA DMA implementation in the hardware can
83 * only DMA from 32bit aligned addresses. This means that gadgets such
84 * as the CDC Ethernet cannot work as they often pass packets which are
87 * Unfortunately the choice to use DMA or not is global to the controller
88 * and seems to be only settable when the controller is being put through
89 * a core reset. This means we either need to fix the gadgets to take
90 * account of DMA alignment, or add bounce buffers (yuerk).
92 * g_using_dma is set depending on dts flag.
94 static inline bool using_dma(struct dwc2_hsotg *hsotg)
96 return hsotg->g_using_dma;
100 * dwc2_hsotg_en_gsint - enable one or more of the general interrupt
101 * @hsotg: The device state
102 * @ints: A bitmask of the interrupts to enable
104 static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints)
106 u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK);
109 new_gsintmsk = gsintmsk | ints;
111 if (new_gsintmsk != gsintmsk) {
112 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
113 dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK);
118 * dwc2_hsotg_disable_gsint - disable one or more of the general interrupt
119 * @hsotg: The device state
120 * @ints: A bitmask of the interrupts to enable
122 static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints)
124 u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK);
127 new_gsintmsk = gsintmsk & ~ints;
129 if (new_gsintmsk != gsintmsk)
130 dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK);
134 * dwc2_hsotg_ctrl_epint - enable/disable an endpoint irq
135 * @hsotg: The device state
136 * @ep: The endpoint index
137 * @dir_in: True if direction is in.
138 * @en: The enable value, true to enable
140 * Set or clear the mask for an individual endpoint's interrupt
143 static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg,
144 unsigned int ep, unsigned int dir_in,
154 local_irq_save(flags);
155 daint = dwc2_readl(hsotg->regs + DAINTMSK);
160 dwc2_writel(daint, hsotg->regs + DAINTMSK);
161 local_irq_restore(flags);
165 * dwc2_hsotg_init_fifo - initialise non-periodic FIFOs
166 * @hsotg: The device instance.
168 static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg)
175 /* Reset fifo map if not correctly cleared during previous session */
176 WARN_ON(hsotg->fifo_map);
179 /* set RX/NPTX FIFO sizes */
180 dwc2_writel(hsotg->g_rx_fifo_sz, hsotg->regs + GRXFSIZ);
181 dwc2_writel((hsotg->g_rx_fifo_sz << FIFOSIZE_STARTADDR_SHIFT) |
182 (hsotg->g_np_g_tx_fifo_sz << FIFOSIZE_DEPTH_SHIFT),
183 hsotg->regs + GNPTXFSIZ);
186 * arange all the rest of the TX FIFOs, as some versions of this
187 * block have overlapping default addresses. This also ensures
188 * that if the settings have been changed, then they are set to
192 /* start at the end of the GNPTXFSIZ, rounded up */
193 addr = hsotg->g_rx_fifo_sz + hsotg->g_np_g_tx_fifo_sz;
196 * Configure fifos sizes from provided configuration and assign
197 * them to endpoints dynamically according to maxpacket size value of
200 for (ep = 1; ep < MAX_EPS_CHANNELS; ep++) {
201 if (!hsotg->g_tx_fifo_sz[ep])
204 val |= hsotg->g_tx_fifo_sz[ep] << FIFOSIZE_DEPTH_SHIFT;
205 WARN_ONCE(addr + hsotg->g_tx_fifo_sz[ep] > hsotg->fifo_mem,
206 "insufficient fifo memory");
207 addr += hsotg->g_tx_fifo_sz[ep];
209 dwc2_writel(val, hsotg->regs + DPTXFSIZN(ep));
213 * according to p428 of the design guide, we need to ensure that
214 * all fifos are flushed before continuing
217 dwc2_writel(GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH |
218 GRSTCTL_RXFFLSH, hsotg->regs + GRSTCTL);
220 /* wait until the fifos are both flushed */
223 val = dwc2_readl(hsotg->regs + GRSTCTL);
225 if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0)
228 if (--timeout == 0) {
230 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
238 dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout);
242 * @ep: USB endpoint to allocate request for.
243 * @flags: Allocation flags
245 * Allocate a new USB request structure appropriate for the specified endpoint
247 static struct usb_request *dwc2_hsotg_ep_alloc_request(struct usb_ep *ep,
250 struct dwc2_hsotg_req *req;
252 req = kzalloc(sizeof(struct dwc2_hsotg_req), flags);
256 INIT_LIST_HEAD(&req->queue);
262 * is_ep_periodic - return true if the endpoint is in periodic mode.
263 * @hs_ep: The endpoint to query.
265 * Returns true if the endpoint is in periodic mode, meaning it is being
266 * used for an Interrupt or ISO transfer.
268 static inline int is_ep_periodic(struct dwc2_hsotg_ep *hs_ep)
270 return hs_ep->periodic;
274 * dwc2_hsotg_unmap_dma - unmap the DMA memory being used for the request
275 * @hsotg: The device state.
276 * @hs_ep: The endpoint for the request
277 * @hs_req: The request being processed.
279 * This is the reverse of dwc2_hsotg_map_dma(), called for the completion
280 * of a request to ensure the buffer is ready for access by the caller.
282 static void dwc2_hsotg_unmap_dma(struct dwc2_hsotg *hsotg,
283 struct dwc2_hsotg_ep *hs_ep,
284 struct dwc2_hsotg_req *hs_req)
286 struct usb_request *req = &hs_req->req;
288 /* ignore this if we're not moving any data */
289 if (hs_req->req.length == 0)
292 usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->dir_in);
296 * dwc2_hsotg_write_fifo - write packet Data to the TxFIFO
297 * @hsotg: The controller state.
298 * @hs_ep: The endpoint we're going to write for.
299 * @hs_req: The request to write data for.
301 * This is called when the TxFIFO has some space in it to hold a new
302 * transmission and we have something to give it. The actual setup of
303 * the data size is done elsewhere, so all we have to do is to actually
306 * The return value is zero if there is more space (or nothing was done)
307 * otherwise -ENOSPC is returned if the FIFO space was used up.
309 * This routine is only needed for PIO
311 static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg,
312 struct dwc2_hsotg_ep *hs_ep,
313 struct dwc2_hsotg_req *hs_req)
315 bool periodic = is_ep_periodic(hs_ep);
316 u32 gnptxsts = dwc2_readl(hsotg->regs + GNPTXSTS);
317 int buf_pos = hs_req->req.actual;
318 int to_write = hs_ep->size_loaded;
324 to_write -= (buf_pos - hs_ep->last_load);
326 /* if there's nothing to write, get out early */
330 if (periodic && !hsotg->dedicated_fifos) {
331 u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
336 * work out how much data was loaded so we can calculate
337 * how much data is left in the fifo.
340 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
343 * if shared fifo, we cannot write anything until the
344 * previous data has been completely sent.
346 if (hs_ep->fifo_load != 0) {
347 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
351 dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n",
353 hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size);
355 /* how much of the data has moved */
356 size_done = hs_ep->size_loaded - size_left;
358 /* how much data is left in the fifo */
359 can_write = hs_ep->fifo_load - size_done;
360 dev_dbg(hsotg->dev, "%s: => can_write1=%d\n",
361 __func__, can_write);
363 can_write = hs_ep->fifo_size - can_write;
364 dev_dbg(hsotg->dev, "%s: => can_write2=%d\n",
365 __func__, can_write);
367 if (can_write <= 0) {
368 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
371 } else if (hsotg->dedicated_fifos && hs_ep->index != 0) {
372 can_write = dwc2_readl(hsotg->regs + DTXFSTS(hs_ep->index));
377 if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) {
379 "%s: no queue slots available (0x%08x)\n",
382 dwc2_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP);
386 can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts);
387 can_write *= 4; /* fifo size is in 32bit quantities. */
390 max_transfer = hs_ep->ep.maxpacket * hs_ep->mc;
392 dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n",
393 __func__, gnptxsts, can_write, to_write, max_transfer);
396 * limit to 512 bytes of data, it seems at least on the non-periodic
397 * FIFO, requests of >512 cause the endpoint to get stuck with a
398 * fragment of the end of the transfer in it.
400 if (can_write > 512 && !periodic)
404 * limit the write to one max-packet size worth of data, but allow
405 * the transfer to return that it did not run out of fifo space
408 if (to_write > max_transfer) {
409 to_write = max_transfer;
411 /* it's needed only when we do not use dedicated fifos */
412 if (!hsotg->dedicated_fifos)
413 dwc2_hsotg_en_gsint(hsotg,
414 periodic ? GINTSTS_PTXFEMP :
418 /* see if we can write data */
420 if (to_write > can_write) {
421 to_write = can_write;
422 pkt_round = to_write % max_transfer;
425 * Round the write down to an
426 * exact number of packets.
428 * Note, we do not currently check to see if we can ever
429 * write a full packet or not to the FIFO.
433 to_write -= pkt_round;
436 * enable correct FIFO interrupt to alert us when there
440 /* it's needed only when we do not use dedicated fifos */
441 if (!hsotg->dedicated_fifos)
442 dwc2_hsotg_en_gsint(hsotg,
443 periodic ? GINTSTS_PTXFEMP :
447 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
448 to_write, hs_req->req.length, can_write, buf_pos);
453 hs_req->req.actual = buf_pos + to_write;
454 hs_ep->total_data += to_write;
457 hs_ep->fifo_load += to_write;
459 to_write = DIV_ROUND_UP(to_write, 4);
460 data = hs_req->req.buf + buf_pos;
462 iowrite32_rep(hsotg->regs + EPFIFO(hs_ep->index), data, to_write);
464 return (to_write >= can_write) ? -ENOSPC : 0;
468 * get_ep_limit - get the maximum data legnth for this endpoint
469 * @hs_ep: The endpoint
471 * Return the maximum data that can be queued in one go on a given endpoint
472 * so that transfers that are too long can be split.
474 static unsigned get_ep_limit(struct dwc2_hsotg_ep *hs_ep)
476 int index = hs_ep->index;
481 maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1;
482 maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1;
486 maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1;
491 /* we made the constant loading easier above by using +1 */
496 * constrain by packet count if maxpkts*pktsize is greater
497 * than the length register size.
500 if ((maxpkt * hs_ep->ep.maxpacket) < maxsize)
501 maxsize = maxpkt * hs_ep->ep.maxpacket;
507 * dwc2_hsotg_start_req - start a USB request from an endpoint's queue
508 * @hsotg: The controller state.
509 * @hs_ep: The endpoint to process a request for
510 * @hs_req: The request to start.
511 * @continuing: True if we are doing more for the current request.
513 * Start the given request running by setting the endpoint registers
514 * appropriately, and writing any data to the FIFOs.
516 static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg,
517 struct dwc2_hsotg_ep *hs_ep,
518 struct dwc2_hsotg_req *hs_req,
521 struct usb_request *ureq = &hs_req->req;
522 int index = hs_ep->index;
523 int dir_in = hs_ep->dir_in;
533 if (hs_ep->req && !continuing) {
534 dev_err(hsotg->dev, "%s: active request\n", __func__);
537 } else if (hs_ep->req != hs_req && continuing) {
539 "%s: continue different req\n", __func__);
545 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
546 epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
548 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
549 __func__, dwc2_readl(hsotg->regs + epctrl_reg), index,
550 hs_ep->dir_in ? "in" : "out");
552 /* If endpoint is stalled, we will restart request later */
553 ctrl = dwc2_readl(hsotg->regs + epctrl_reg);
555 if (index && ctrl & DXEPCTL_STALL) {
556 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
560 length = ureq->length - ureq->actual;
561 dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n",
562 ureq->length, ureq->actual);
564 maxreq = get_ep_limit(hs_ep);
565 if (length > maxreq) {
566 int round = maxreq % hs_ep->ep.maxpacket;
568 dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n",
569 __func__, length, maxreq, round);
571 /* round down to multiple of packets */
579 packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket);
581 packets = 1; /* send one packet if length is zero. */
583 if (hs_ep->isochronous && length > (hs_ep->mc * hs_ep->ep.maxpacket)) {
584 dev_err(hsotg->dev, "req length > maxpacket*mc\n");
588 if (dir_in && index != 0)
589 if (hs_ep->isochronous)
590 epsize = DXEPTSIZ_MC(packets);
592 epsize = DXEPTSIZ_MC(1);
597 * zero length packet should be programmed on its own and should not
598 * be counted in DIEPTSIZ.PktCnt with other packets.
600 if (dir_in && ureq->zero && !continuing) {
601 /* Test if zlp is actually required. */
602 if ((ureq->length >= hs_ep->ep.maxpacket) &&
603 !(ureq->length % hs_ep->ep.maxpacket))
607 epsize |= DXEPTSIZ_PKTCNT(packets);
608 epsize |= DXEPTSIZ_XFERSIZE(length);
610 dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
611 __func__, packets, length, ureq->length, epsize, epsize_reg);
613 /* store the request as the current one we're doing */
616 /* write size / packets */
617 dwc2_writel(epsize, hsotg->regs + epsize_reg);
619 if (using_dma(hsotg) && !continuing) {
620 unsigned int dma_reg;
623 * write DMA address to control register, buffer already
624 * synced by dwc2_hsotg_ep_queue().
627 dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index);
628 dwc2_writel(ureq->dma, hsotg->regs + dma_reg);
630 dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n",
631 __func__, &ureq->dma, dma_reg);
634 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
635 ctrl |= DXEPCTL_USBACTEP;
637 dev_dbg(hsotg->dev, "ep0 state:%d\n", hsotg->ep0_state);
639 /* For Setup request do not clear NAK */
640 if (!(index == 0 && hsotg->ep0_state == DWC2_EP0_SETUP))
641 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
643 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
644 dwc2_writel(ctrl, hsotg->regs + epctrl_reg);
647 * set these, it seems that DMA support increments past the end
648 * of the packet buffer so we need to calculate the length from
651 hs_ep->size_loaded = length;
652 hs_ep->last_load = ureq->actual;
654 if (dir_in && !using_dma(hsotg)) {
655 /* set these anyway, we may need them for non-periodic in */
656 hs_ep->fifo_load = 0;
658 dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
662 * clear the INTknTXFEmpMsk when we start request, more as a aide
663 * to debugging to see what is going on.
666 dwc2_writel(DIEPMSK_INTKNTXFEMPMSK,
667 hsotg->regs + DIEPINT(index));
670 * Note, trying to clear the NAK here causes problems with transmit
671 * on the S3C6400 ending up with the TXFIFO becoming full.
674 /* check ep is enabled */
675 if (!(dwc2_readl(hsotg->regs + epctrl_reg) & DXEPCTL_EPENA))
677 "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n",
678 index, dwc2_readl(hsotg->regs + epctrl_reg));
680 dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n",
681 __func__, dwc2_readl(hsotg->regs + epctrl_reg));
683 /* enable ep interrupts */
684 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1);
688 * dwc2_hsotg_map_dma - map the DMA memory being used for the request
689 * @hsotg: The device state.
690 * @hs_ep: The endpoint the request is on.
691 * @req: The request being processed.
693 * We've been asked to queue a request, so ensure that the memory buffer
694 * is correctly setup for DMA. If we've been passed an extant DMA address
695 * then ensure the buffer has been synced to memory. If our buffer has no
696 * DMA memory, then we map the memory and mark our request to allow us to
697 * cleanup on completion.
699 static int dwc2_hsotg_map_dma(struct dwc2_hsotg *hsotg,
700 struct dwc2_hsotg_ep *hs_ep,
701 struct usb_request *req)
703 struct dwc2_hsotg_req *hs_req = our_req(req);
706 /* if the length is zero, ignore the DMA data */
707 if (hs_req->req.length == 0)
710 ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in);
717 dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n",
718 __func__, req->buf, req->length);
723 static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg,
724 struct dwc2_hsotg_ep *hs_ep, struct dwc2_hsotg_req *hs_req)
726 void *req_buf = hs_req->req.buf;
728 /* If dma is not being used or buffer is aligned */
729 if (!using_dma(hsotg) || !((long)req_buf & 3))
732 WARN_ON(hs_req->saved_req_buf);
734 dev_dbg(hsotg->dev, "%s: %s: buf=%p length=%d\n", __func__,
735 hs_ep->ep.name, req_buf, hs_req->req.length);
737 hs_req->req.buf = kmalloc(hs_req->req.length, GFP_ATOMIC);
738 if (!hs_req->req.buf) {
739 hs_req->req.buf = req_buf;
741 "%s: unable to allocate memory for bounce buffer\n",
746 /* Save actual buffer */
747 hs_req->saved_req_buf = req_buf;
750 memcpy(hs_req->req.buf, req_buf, hs_req->req.length);
754 static void dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg *hsotg,
755 struct dwc2_hsotg_ep *hs_ep, struct dwc2_hsotg_req *hs_req)
757 /* If dma is not being used or buffer was aligned */
758 if (!using_dma(hsotg) || !hs_req->saved_req_buf)
761 dev_dbg(hsotg->dev, "%s: %s: status=%d actual-length=%d\n", __func__,
762 hs_ep->ep.name, hs_req->req.status, hs_req->req.actual);
764 /* Copy data from bounce buffer on successful out transfer */
765 if (!hs_ep->dir_in && !hs_req->req.status)
766 memcpy(hs_req->saved_req_buf, hs_req->req.buf,
769 /* Free bounce buffer */
770 kfree(hs_req->req.buf);
772 hs_req->req.buf = hs_req->saved_req_buf;
773 hs_req->saved_req_buf = NULL;
776 static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
779 struct dwc2_hsotg_req *hs_req = our_req(req);
780 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
781 struct dwc2_hsotg *hs = hs_ep->parent;
785 dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
786 ep->name, req, req->length, req->buf, req->no_interrupt,
787 req->zero, req->short_not_ok);
789 /* Prevent new request submission when controller is suspended */
790 if (hs->lx_state == DWC2_L2) {
791 dev_dbg(hs->dev, "%s: don't submit request while suspended\n",
796 /* initialise status of the request */
797 INIT_LIST_HEAD(&hs_req->queue);
799 req->status = -EINPROGRESS;
801 ret = dwc2_hsotg_handle_unaligned_buf_start(hs, hs_ep, hs_req);
805 /* if we're using DMA, sync the buffers as necessary */
807 ret = dwc2_hsotg_map_dma(hs, hs_ep, req);
812 first = list_empty(&hs_ep->queue);
813 list_add_tail(&hs_req->queue, &hs_ep->queue);
816 dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
821 static int dwc2_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req,
824 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
825 struct dwc2_hsotg *hs = hs_ep->parent;
826 unsigned long flags = 0;
829 spin_lock_irqsave(&hs->lock, flags);
830 ret = dwc2_hsotg_ep_queue(ep, req, gfp_flags);
831 spin_unlock_irqrestore(&hs->lock, flags);
836 static void dwc2_hsotg_ep_free_request(struct usb_ep *ep,
837 struct usb_request *req)
839 struct dwc2_hsotg_req *hs_req = our_req(req);
845 * dwc2_hsotg_complete_oursetup - setup completion callback
846 * @ep: The endpoint the request was on.
847 * @req: The request completed.
849 * Called on completion of any requests the driver itself
850 * submitted that need cleaning up.
852 static void dwc2_hsotg_complete_oursetup(struct usb_ep *ep,
853 struct usb_request *req)
855 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
856 struct dwc2_hsotg *hsotg = hs_ep->parent;
858 dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req);
860 dwc2_hsotg_ep_free_request(ep, req);
864 * ep_from_windex - convert control wIndex value to endpoint
865 * @hsotg: The driver state.
866 * @windex: The control request wIndex field (in host order).
868 * Convert the given wIndex into a pointer to an driver endpoint
869 * structure, or return NULL if it is not a valid endpoint.
871 static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg,
874 struct dwc2_hsotg_ep *ep;
875 int dir = (windex & USB_DIR_IN) ? 1 : 0;
876 int idx = windex & 0x7F;
881 if (idx > hsotg->num_of_eps)
884 ep = index_to_ep(hsotg, idx, dir);
886 if (idx && ep->dir_in != dir)
893 * dwc2_hsotg_set_test_mode - Enable usb Test Modes
894 * @hsotg: The driver state.
895 * @testmode: requested usb test mode
896 * Enable usb Test Mode requested by the Host.
898 int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode)
900 int dctl = dwc2_readl(hsotg->regs + DCTL);
902 dctl &= ~DCTL_TSTCTL_MASK;
909 dctl |= testmode << DCTL_TSTCTL_SHIFT;
914 dwc2_writel(dctl, hsotg->regs + DCTL);
919 * dwc2_hsotg_send_reply - send reply to control request
920 * @hsotg: The device state
922 * @buff: Buffer for request
923 * @length: Length of reply.
925 * Create a request and queue it on the given endpoint. This is useful as
926 * an internal method of sending replies to certain control requests, etc.
928 static int dwc2_hsotg_send_reply(struct dwc2_hsotg *hsotg,
929 struct dwc2_hsotg_ep *ep,
933 struct usb_request *req;
936 dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length);
938 req = dwc2_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC);
939 hsotg->ep0_reply = req;
941 dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__);
945 req->buf = hsotg->ep0_buff;
946 req->length = length;
948 * zero flag is for sending zlp in DATA IN stage. It has no impact on
952 req->complete = dwc2_hsotg_complete_oursetup;
955 memcpy(req->buf, buff, length);
957 ret = dwc2_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC);
959 dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__);
967 * dwc2_hsotg_process_req_status - process request GET_STATUS
968 * @hsotg: The device state
969 * @ctrl: USB control request
971 static int dwc2_hsotg_process_req_status(struct dwc2_hsotg *hsotg,
972 struct usb_ctrlrequest *ctrl)
974 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
975 struct dwc2_hsotg_ep *ep;
979 dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__);
982 dev_warn(hsotg->dev, "%s: direction out?\n", __func__);
986 switch (ctrl->bRequestType & USB_RECIP_MASK) {
987 case USB_RECIP_DEVICE:
988 reply = cpu_to_le16(0); /* bit 0 => self powered,
989 * bit 1 => remote wakeup */
992 case USB_RECIP_INTERFACE:
993 /* currently, the data result should be zero */
994 reply = cpu_to_le16(0);
997 case USB_RECIP_ENDPOINT:
998 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
1002 reply = cpu_to_le16(ep->halted ? 1 : 0);
1009 if (le16_to_cpu(ctrl->wLength) != 2)
1012 ret = dwc2_hsotg_send_reply(hsotg, ep0, &reply, 2);
1014 dev_err(hsotg->dev, "%s: failed to send reply\n", __func__);
1021 static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value);
1024 * get_ep_head - return the first request on the endpoint
1025 * @hs_ep: The controller endpoint to get
1027 * Get the first request on the endpoint.
1029 static struct dwc2_hsotg_req *get_ep_head(struct dwc2_hsotg_ep *hs_ep)
1031 if (list_empty(&hs_ep->queue))
1034 return list_first_entry(&hs_ep->queue, struct dwc2_hsotg_req, queue);
1038 * dwc2_hsotg_process_req_feature - process request {SET,CLEAR}_FEATURE
1039 * @hsotg: The device state
1040 * @ctrl: USB control request
1042 static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg *hsotg,
1043 struct usb_ctrlrequest *ctrl)
1045 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1046 struct dwc2_hsotg_req *hs_req;
1048 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
1049 struct dwc2_hsotg_ep *ep;
1056 dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",
1057 __func__, set ? "SET" : "CLEAR");
1059 wValue = le16_to_cpu(ctrl->wValue);
1060 wIndex = le16_to_cpu(ctrl->wIndex);
1061 recip = ctrl->bRequestType & USB_RECIP_MASK;
1064 case USB_RECIP_DEVICE:
1066 case USB_DEVICE_TEST_MODE:
1067 if ((wIndex & 0xff) != 0)
1072 hsotg->test_mode = wIndex >> 8;
1073 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1076 "%s: failed to send reply\n", __func__);
1085 case USB_RECIP_ENDPOINT:
1086 ep = ep_from_windex(hsotg, wIndex);
1088 dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n",
1094 case USB_ENDPOINT_HALT:
1095 halted = ep->halted;
1097 dwc2_hsotg_ep_sethalt(&ep->ep, set);
1099 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1102 "%s: failed to send reply\n", __func__);
1107 * we have to complete all requests for ep if it was
1108 * halted, and the halt was cleared by CLEAR_FEATURE
1111 if (!set && halted) {
1113 * If we have request in progress,
1119 list_del_init(&hs_req->queue);
1120 if (hs_req->req.complete) {
1121 spin_unlock(&hsotg->lock);
1122 usb_gadget_giveback_request(
1123 &ep->ep, &hs_req->req);
1124 spin_lock(&hsotg->lock);
1128 /* If we have pending request, then start it */
1130 restart = !list_empty(&ep->queue);
1132 hs_req = get_ep_head(ep);
1133 dwc2_hsotg_start_req(hsotg, ep,
1151 static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg);
1154 * dwc2_hsotg_stall_ep0 - stall ep0
1155 * @hsotg: The device state
1157 * Set stall for ep0 as response for setup request.
1159 static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg *hsotg)
1161 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1165 dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
1166 reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0;
1169 * DxEPCTL_Stall will be cleared by EP once it has
1170 * taken effect, so no need to clear later.
1173 ctrl = dwc2_readl(hsotg->regs + reg);
1174 ctrl |= DXEPCTL_STALL;
1175 ctrl |= DXEPCTL_CNAK;
1176 dwc2_writel(ctrl, hsotg->regs + reg);
1179 "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n",
1180 ctrl, reg, dwc2_readl(hsotg->regs + reg));
1183 * complete won't be called, so we enqueue
1184 * setup request here
1186 dwc2_hsotg_enqueue_setup(hsotg);
1190 * dwc2_hsotg_process_control - process a control request
1191 * @hsotg: The device state
1192 * @ctrl: The control request received
1194 * The controller has received the SETUP phase of a control request, and
1195 * needs to work out what to do next (and whether to pass it on to the
1198 static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg,
1199 struct usb_ctrlrequest *ctrl)
1201 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1206 "ctrl Type=%02x, Req=%02x, V=%04x, I=%04x, L=%04x\n",
1207 ctrl->bRequestType, ctrl->bRequest, ctrl->wValue,
1208 ctrl->wIndex, ctrl->wLength);
1210 if (ctrl->wLength == 0) {
1212 hsotg->ep0_state = DWC2_EP0_STATUS_IN;
1213 } else if (ctrl->bRequestType & USB_DIR_IN) {
1215 hsotg->ep0_state = DWC2_EP0_DATA_IN;
1218 hsotg->ep0_state = DWC2_EP0_DATA_OUT;
1221 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1222 switch (ctrl->bRequest) {
1223 case USB_REQ_SET_ADDRESS:
1224 hsotg->connected = 1;
1225 dcfg = dwc2_readl(hsotg->regs + DCFG);
1226 dcfg &= ~DCFG_DEVADDR_MASK;
1227 dcfg |= (le16_to_cpu(ctrl->wValue) <<
1228 DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK;
1229 dwc2_writel(dcfg, hsotg->regs + DCFG);
1231 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1233 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1236 case USB_REQ_GET_STATUS:
1237 ret = dwc2_hsotg_process_req_status(hsotg, ctrl);
1240 case USB_REQ_CLEAR_FEATURE:
1241 case USB_REQ_SET_FEATURE:
1242 ret = dwc2_hsotg_process_req_feature(hsotg, ctrl);
1247 /* as a fallback, try delivering it to the driver to deal with */
1249 if (ret == 0 && hsotg->driver) {
1250 spin_unlock(&hsotg->lock);
1251 ret = hsotg->driver->setup(&hsotg->gadget, ctrl);
1252 spin_lock(&hsotg->lock);
1254 dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
1258 * the request is either unhandlable, or is not formatted correctly
1259 * so respond with a STALL for the status stage to indicate failure.
1263 dwc2_hsotg_stall_ep0(hsotg);
1267 * dwc2_hsotg_complete_setup - completion of a setup transfer
1268 * @ep: The endpoint the request was on.
1269 * @req: The request completed.
1271 * Called on completion of any requests the driver itself submitted for
1274 static void dwc2_hsotg_complete_setup(struct usb_ep *ep,
1275 struct usb_request *req)
1277 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1278 struct dwc2_hsotg *hsotg = hs_ep->parent;
1280 if (req->status < 0) {
1281 dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status);
1285 spin_lock(&hsotg->lock);
1286 if (req->actual == 0)
1287 dwc2_hsotg_enqueue_setup(hsotg);
1289 dwc2_hsotg_process_control(hsotg, req->buf);
1290 spin_unlock(&hsotg->lock);
1294 * dwc2_hsotg_enqueue_setup - start a request for EP0 packets
1295 * @hsotg: The device state.
1297 * Enqueue a request on EP0 if necessary to received any SETUP packets
1298 * received from the host.
1300 static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg)
1302 struct usb_request *req = hsotg->ctrl_req;
1303 struct dwc2_hsotg_req *hs_req = our_req(req);
1306 dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__);
1310 req->buf = hsotg->ctrl_buff;
1311 req->complete = dwc2_hsotg_complete_setup;
1313 if (!list_empty(&hs_req->queue)) {
1314 dev_dbg(hsotg->dev, "%s already queued???\n", __func__);
1318 hsotg->eps_out[0]->dir_in = 0;
1319 hsotg->eps_out[0]->send_zlp = 0;
1320 hsotg->ep0_state = DWC2_EP0_SETUP;
1322 ret = dwc2_hsotg_ep_queue(&hsotg->eps_out[0]->ep, req, GFP_ATOMIC);
1324 dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret);
1326 * Don't think there's much we can do other than watch the
1332 static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg,
1333 struct dwc2_hsotg_ep *hs_ep)
1336 u8 index = hs_ep->index;
1337 u32 epctl_reg = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
1338 u32 epsiz_reg = hs_ep->dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
1341 dev_dbg(hsotg->dev, "Sending zero-length packet on ep%d\n",
1344 dev_dbg(hsotg->dev, "Receiving zero-length packet on ep%d\n",
1347 dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
1348 DXEPTSIZ_XFERSIZE(0), hsotg->regs +
1351 ctrl = dwc2_readl(hsotg->regs + epctl_reg);
1352 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
1353 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
1354 ctrl |= DXEPCTL_USBACTEP;
1355 dwc2_writel(ctrl, hsotg->regs + epctl_reg);
1359 * dwc2_hsotg_complete_request - complete a request given to us
1360 * @hsotg: The device state.
1361 * @hs_ep: The endpoint the request was on.
1362 * @hs_req: The request to complete.
1363 * @result: The result code (0 => Ok, otherwise errno)
1365 * The given request has finished, so call the necessary completion
1366 * if it has one and then look to see if we can start a new request
1369 * Note, expects the ep to already be locked as appropriate.
1371 static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg,
1372 struct dwc2_hsotg_ep *hs_ep,
1373 struct dwc2_hsotg_req *hs_req,
1379 dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__);
1383 dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n",
1384 hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete);
1387 * only replace the status if we've not already set an error
1388 * from a previous transaction
1391 if (hs_req->req.status == -EINPROGRESS)
1392 hs_req->req.status = result;
1394 if (using_dma(hsotg))
1395 dwc2_hsotg_unmap_dma(hsotg, hs_ep, hs_req);
1397 dwc2_hsotg_handle_unaligned_buf_complete(hsotg, hs_ep, hs_req);
1400 list_del_init(&hs_req->queue);
1403 * call the complete request with the locks off, just in case the
1404 * request tries to queue more work for this endpoint.
1407 if (hs_req->req.complete) {
1408 spin_unlock(&hsotg->lock);
1409 usb_gadget_giveback_request(&hs_ep->ep, &hs_req->req);
1410 spin_lock(&hsotg->lock);
1414 * Look to see if there is anything else to do. Note, the completion
1415 * of the previous request may have caused a new request to be started
1416 * so be careful when doing this.
1419 if (!hs_ep->req && result >= 0) {
1420 restart = !list_empty(&hs_ep->queue);
1422 hs_req = get_ep_head(hs_ep);
1423 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, false);
1429 * dwc2_hsotg_rx_data - receive data from the FIFO for an endpoint
1430 * @hsotg: The device state.
1431 * @ep_idx: The endpoint index for the data
1432 * @size: The size of data in the fifo, in bytes
1434 * The FIFO status shows there is data to read from the FIFO for a given
1435 * endpoint, so sort out whether we need to read the data into a request
1436 * that has been made for that endpoint.
1438 static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size)
1440 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx];
1441 struct dwc2_hsotg_req *hs_req = hs_ep->req;
1442 void __iomem *fifo = hsotg->regs + EPFIFO(ep_idx);
1449 u32 epctl = dwc2_readl(hsotg->regs + DOEPCTL(ep_idx));
1453 "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n",
1454 __func__, size, ep_idx, epctl);
1456 /* dump the data from the FIFO, we've nothing we can do */
1457 for (ptr = 0; ptr < size; ptr += 4)
1458 (void)dwc2_readl(fifo);
1464 read_ptr = hs_req->req.actual;
1465 max_req = hs_req->req.length - read_ptr;
1467 dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n",
1468 __func__, to_read, max_req, read_ptr, hs_req->req.length);
1470 if (to_read > max_req) {
1472 * more data appeared than we where willing
1473 * to deal with in this request.
1476 /* currently we don't deal this */
1480 hs_ep->total_data += to_read;
1481 hs_req->req.actual += to_read;
1482 to_read = DIV_ROUND_UP(to_read, 4);
1485 * note, we might over-write the buffer end by 3 bytes depending on
1486 * alignment of the data.
1488 ioread32_rep(fifo, hs_req->req.buf + read_ptr, to_read);
1492 * dwc2_hsotg_ep0_zlp - send/receive zero-length packet on control endpoint
1493 * @hsotg: The device instance
1494 * @dir_in: If IN zlp
1496 * Generate a zero-length IN packet request for terminating a SETUP
1499 * Note, since we don't write any data to the TxFIFO, then it is
1500 * currently believed that we do not need to wait for any space in
1503 static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in)
1505 /* eps_out[0] is used in both directions */
1506 hsotg->eps_out[0]->dir_in = dir_in;
1507 hsotg->ep0_state = dir_in ? DWC2_EP0_STATUS_IN : DWC2_EP0_STATUS_OUT;
1509 dwc2_hsotg_program_zlp(hsotg, hsotg->eps_out[0]);
1512 static void dwc2_hsotg_change_ep_iso_parity(struct dwc2_hsotg *hsotg,
1517 ctrl = dwc2_readl(hsotg->regs + epctl_reg);
1518 if (ctrl & DXEPCTL_EOFRNUM)
1519 ctrl |= DXEPCTL_SETEVENFR;
1521 ctrl |= DXEPCTL_SETODDFR;
1522 dwc2_writel(ctrl, hsotg->regs + epctl_reg);
1526 * dwc2_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
1527 * @hsotg: The device instance
1528 * @epnum: The endpoint received from
1530 * The RXFIFO has delivered an OutDone event, which means that the data
1531 * transfer for an OUT endpoint has been completed, either by a short
1532 * packet or by the finish of a transfer.
1534 static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum)
1536 u32 epsize = dwc2_readl(hsotg->regs + DOEPTSIZ(epnum));
1537 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum];
1538 struct dwc2_hsotg_req *hs_req = hs_ep->req;
1539 struct usb_request *req = &hs_req->req;
1540 unsigned size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
1544 dev_dbg(hsotg->dev, "%s: no request active\n", __func__);
1548 if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_OUT) {
1549 dev_dbg(hsotg->dev, "zlp packet received\n");
1550 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
1551 dwc2_hsotg_enqueue_setup(hsotg);
1555 if (using_dma(hsotg)) {
1559 * Calculate the size of the transfer by checking how much
1560 * is left in the endpoint size register and then working it
1561 * out from the amount we loaded for the transfer.
1563 * We need to do this as DMA pointers are always 32bit aligned
1564 * so may overshoot/undershoot the transfer.
1567 size_done = hs_ep->size_loaded - size_left;
1568 size_done += hs_ep->last_load;
1570 req->actual = size_done;
1573 /* if there is more request to do, schedule new transfer */
1574 if (req->actual < req->length && size_left == 0) {
1575 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
1579 if (req->actual < req->length && req->short_not_ok) {
1580 dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",
1581 __func__, req->actual, req->length);
1584 * todo - what should we return here? there's no one else
1585 * even bothering to check the status.
1589 if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
1590 /* Move to STATUS IN */
1591 dwc2_hsotg_ep0_zlp(hsotg, true);
1596 * Slave mode OUT transfers do not go through XferComplete so
1597 * adjust the ISOC parity here.
1599 if (!using_dma(hsotg)) {
1600 hs_ep->has_correct_parity = 1;
1601 if (hs_ep->isochronous && hs_ep->interval == 1)
1602 dwc2_hsotg_change_ep_iso_parity(hsotg, DOEPCTL(epnum));
1605 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
1609 * dwc2_hsotg_read_frameno - read current frame number
1610 * @hsotg: The device instance
1612 * Return the current frame number
1614 static u32 dwc2_hsotg_read_frameno(struct dwc2_hsotg *hsotg)
1618 dsts = dwc2_readl(hsotg->regs + DSTS);
1619 dsts &= DSTS_SOFFN_MASK;
1620 dsts >>= DSTS_SOFFN_SHIFT;
1626 * dwc2_hsotg_handle_rx - RX FIFO has data
1627 * @hsotg: The device instance
1629 * The IRQ handler has detected that the RX FIFO has some data in it
1630 * that requires processing, so find out what is in there and do the
1633 * The RXFIFO is a true FIFO, the packets coming out are still in packet
1634 * chunks, so if you have x packets received on an endpoint you'll get x
1635 * FIFO events delivered, each with a packet's worth of data in it.
1637 * When using DMA, we should not be processing events from the RXFIFO
1638 * as the actual data should be sent to the memory directly and we turn
1639 * on the completion interrupts to get notifications of transfer completion.
1641 static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg)
1643 u32 grxstsr = dwc2_readl(hsotg->regs + GRXSTSP);
1644 u32 epnum, status, size;
1646 WARN_ON(using_dma(hsotg));
1648 epnum = grxstsr & GRXSTS_EPNUM_MASK;
1649 status = grxstsr & GRXSTS_PKTSTS_MASK;
1651 size = grxstsr & GRXSTS_BYTECNT_MASK;
1652 size >>= GRXSTS_BYTECNT_SHIFT;
1654 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
1655 __func__, grxstsr, size, epnum);
1657 switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) {
1658 case GRXSTS_PKTSTS_GLOBALOUTNAK:
1659 dev_dbg(hsotg->dev, "GLOBALOUTNAK\n");
1662 case GRXSTS_PKTSTS_OUTDONE:
1663 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
1664 dwc2_hsotg_read_frameno(hsotg));
1666 if (!using_dma(hsotg))
1667 dwc2_hsotg_handle_outdone(hsotg, epnum);
1670 case GRXSTS_PKTSTS_SETUPDONE:
1672 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1673 dwc2_hsotg_read_frameno(hsotg),
1674 dwc2_readl(hsotg->regs + DOEPCTL(0)));
1676 * Call dwc2_hsotg_handle_outdone here if it was not called from
1677 * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't
1678 * generate GRXSTS_PKTSTS_OUTDONE for setup packet.
1680 if (hsotg->ep0_state == DWC2_EP0_SETUP)
1681 dwc2_hsotg_handle_outdone(hsotg, epnum);
1684 case GRXSTS_PKTSTS_OUTRX:
1685 dwc2_hsotg_rx_data(hsotg, epnum, size);
1688 case GRXSTS_PKTSTS_SETUPRX:
1690 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1691 dwc2_hsotg_read_frameno(hsotg),
1692 dwc2_readl(hsotg->regs + DOEPCTL(0)));
1694 WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP);
1696 dwc2_hsotg_rx_data(hsotg, epnum, size);
1700 dev_warn(hsotg->dev, "%s: unknown status %08x\n",
1703 dwc2_hsotg_dump(hsotg);
1709 * dwc2_hsotg_ep0_mps - turn max packet size into register setting
1710 * @mps: The maximum packet size in bytes.
1712 static u32 dwc2_hsotg_ep0_mps(unsigned int mps)
1716 return D0EPCTL_MPS_64;
1718 return D0EPCTL_MPS_32;
1720 return D0EPCTL_MPS_16;
1722 return D0EPCTL_MPS_8;
1725 /* bad max packet size, warn and return invalid result */
1731 * dwc2_hsotg_set_ep_maxpacket - set endpoint's max-packet field
1732 * @hsotg: The driver state.
1733 * @ep: The index number of the endpoint
1734 * @mps: The maximum packet size in bytes
1736 * Configure the maximum packet size for the given endpoint, updating
1737 * the hardware control registers to reflect this.
1739 static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg,
1740 unsigned int ep, unsigned int mps, unsigned int dir_in)
1742 struct dwc2_hsotg_ep *hs_ep;
1743 void __iomem *regs = hsotg->regs;
1748 hs_ep = index_to_ep(hsotg, ep, dir_in);
1753 /* EP0 is a special case */
1754 mpsval = dwc2_hsotg_ep0_mps(mps);
1757 hs_ep->ep.maxpacket = mps;
1760 mpsval = mps & DXEPCTL_MPS_MASK;
1763 mcval = ((mps >> 11) & 0x3) + 1;
1767 hs_ep->ep.maxpacket = mpsval;
1771 reg = dwc2_readl(regs + DIEPCTL(ep));
1772 reg &= ~DXEPCTL_MPS_MASK;
1774 dwc2_writel(reg, regs + DIEPCTL(ep));
1776 reg = dwc2_readl(regs + DOEPCTL(ep));
1777 reg &= ~DXEPCTL_MPS_MASK;
1779 dwc2_writel(reg, regs + DOEPCTL(ep));
1785 dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps);
1789 * dwc2_hsotg_txfifo_flush - flush Tx FIFO
1790 * @hsotg: The driver state
1791 * @idx: The index for the endpoint (0..15)
1793 static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx)
1798 dwc2_writel(GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH,
1799 hsotg->regs + GRSTCTL);
1801 /* wait until the fifo is flushed */
1805 val = dwc2_readl(hsotg->regs + GRSTCTL);
1807 if ((val & (GRSTCTL_TXFFLSH)) == 0)
1810 if (--timeout == 0) {
1812 "%s: timeout flushing fifo (GRSTCTL=%08x)\n",
1822 * dwc2_hsotg_trytx - check to see if anything needs transmitting
1823 * @hsotg: The driver state
1824 * @hs_ep: The driver endpoint to check.
1826 * Check to see if there is a request that has data to send, and if so
1827 * make an attempt to write data into the FIFO.
1829 static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg,
1830 struct dwc2_hsotg_ep *hs_ep)
1832 struct dwc2_hsotg_req *hs_req = hs_ep->req;
1834 if (!hs_ep->dir_in || !hs_req) {
1836 * if request is not enqueued, we disable interrupts
1837 * for endpoints, excepting ep0
1839 if (hs_ep->index != 0)
1840 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index,
1845 if (hs_req->req.actual < hs_req->req.length) {
1846 dev_dbg(hsotg->dev, "trying to write more for ep%d\n",
1848 return dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
1855 * dwc2_hsotg_complete_in - complete IN transfer
1856 * @hsotg: The device state.
1857 * @hs_ep: The endpoint that has just completed.
1859 * An IN transfer has been completed, update the transfer's state and then
1860 * call the relevant completion routines.
1862 static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg,
1863 struct dwc2_hsotg_ep *hs_ep)
1865 struct dwc2_hsotg_req *hs_req = hs_ep->req;
1866 u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
1867 int size_left, size_done;
1870 dev_dbg(hsotg->dev, "XferCompl but no req\n");
1874 /* Finish ZLP handling for IN EP0 transactions */
1875 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_IN) {
1876 dev_dbg(hsotg->dev, "zlp packet sent\n");
1877 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
1878 if (hsotg->test_mode) {
1881 ret = dwc2_hsotg_set_test_mode(hsotg, hsotg->test_mode);
1883 dev_dbg(hsotg->dev, "Invalid Test #%d\n",
1885 dwc2_hsotg_stall_ep0(hsotg);
1889 dwc2_hsotg_enqueue_setup(hsotg);
1894 * Calculate the size of the transfer by checking how much is left
1895 * in the endpoint size register and then working it out from
1896 * the amount we loaded for the transfer.
1898 * We do this even for DMA, as the transfer may have incremented
1899 * past the end of the buffer (DMA transfers are always 32bit
1903 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
1905 size_done = hs_ep->size_loaded - size_left;
1906 size_done += hs_ep->last_load;
1908 if (hs_req->req.actual != size_done)
1909 dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n",
1910 __func__, hs_req->req.actual, size_done);
1912 hs_req->req.actual = size_done;
1913 dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n",
1914 hs_req->req.length, hs_req->req.actual, hs_req->req.zero);
1916 if (!size_left && hs_req->req.actual < hs_req->req.length) {
1917 dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__);
1918 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
1922 /* Zlp for all endpoints, for ep0 only in DATA IN stage */
1923 if (hs_ep->send_zlp) {
1924 dwc2_hsotg_program_zlp(hsotg, hs_ep);
1925 hs_ep->send_zlp = 0;
1926 /* transfer will be completed on next complete interrupt */
1930 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_DATA_IN) {
1931 /* Move to STATUS OUT */
1932 dwc2_hsotg_ep0_zlp(hsotg, false);
1936 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
1940 * dwc2_hsotg_epint - handle an in/out endpoint interrupt
1941 * @hsotg: The driver state
1942 * @idx: The index for the endpoint (0..15)
1943 * @dir_in: Set if this is an IN endpoint
1945 * Process and clear any interrupt pending for an individual endpoint
1947 static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx,
1950 struct dwc2_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in);
1951 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
1952 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
1953 u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx);
1957 ints = dwc2_readl(hsotg->regs + epint_reg);
1958 ctrl = dwc2_readl(hsotg->regs + epctl_reg);
1960 /* Clear endpoint interrupts */
1961 dwc2_writel(ints, hsotg->regs + epint_reg);
1964 dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n",
1965 __func__, idx, dir_in ? "in" : "out");
1969 dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
1970 __func__, idx, dir_in ? "in" : "out", ints);
1972 /* Don't process XferCompl interrupt if it is a setup packet */
1973 if (idx == 0 && (ints & (DXEPINT_SETUP | DXEPINT_SETUP_RCVD)))
1974 ints &= ~DXEPINT_XFERCOMPL;
1976 if (ints & DXEPINT_XFERCOMPL) {
1977 hs_ep->has_correct_parity = 1;
1978 if (hs_ep->isochronous && hs_ep->interval == 1)
1979 dwc2_hsotg_change_ep_iso_parity(hsotg, epctl_reg);
1982 "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n",
1983 __func__, dwc2_readl(hsotg->regs + epctl_reg),
1984 dwc2_readl(hsotg->regs + epsiz_reg));
1987 * we get OutDone from the FIFO, so we only need to look
1988 * at completing IN requests here
1991 dwc2_hsotg_complete_in(hsotg, hs_ep);
1993 if (idx == 0 && !hs_ep->req)
1994 dwc2_hsotg_enqueue_setup(hsotg);
1995 } else if (using_dma(hsotg)) {
1997 * We're using DMA, we need to fire an OutDone here
1998 * as we ignore the RXFIFO.
2001 dwc2_hsotg_handle_outdone(hsotg, idx);
2005 if (ints & DXEPINT_EPDISBLD) {
2006 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
2009 int epctl = dwc2_readl(hsotg->regs + epctl_reg);
2011 dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index);
2013 if ((epctl & DXEPCTL_STALL) &&
2014 (epctl & DXEPCTL_EPTYPE_BULK)) {
2015 int dctl = dwc2_readl(hsotg->regs + DCTL);
2017 dctl |= DCTL_CGNPINNAK;
2018 dwc2_writel(dctl, hsotg->regs + DCTL);
2023 if (ints & DXEPINT_AHBERR)
2024 dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
2026 if (ints & DXEPINT_SETUP) { /* Setup or Timeout */
2027 dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__);
2029 if (using_dma(hsotg) && idx == 0) {
2031 * this is the notification we've received a
2032 * setup packet. In non-DMA mode we'd get this
2033 * from the RXFIFO, instead we need to process
2040 dwc2_hsotg_handle_outdone(hsotg, 0);
2044 if (ints & DXEPINT_BACK2BACKSETUP)
2045 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
2047 if (dir_in && !hs_ep->isochronous) {
2048 /* not sure if this is important, but we'll clear it anyway */
2049 if (ints & DIEPMSK_INTKNTXFEMPMSK) {
2050 dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
2054 /* this probably means something bad is happening */
2055 if (ints & DIEPMSK_INTKNEPMISMSK) {
2056 dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
2060 /* FIFO has space or is empty (see GAHBCFG) */
2061 if (hsotg->dedicated_fifos &&
2062 ints & DIEPMSK_TXFIFOEMPTY) {
2063 dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n",
2065 if (!using_dma(hsotg))
2066 dwc2_hsotg_trytx(hsotg, hs_ep);
2072 * dwc2_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
2073 * @hsotg: The device state.
2075 * Handle updating the device settings after the enumeration phase has
2078 static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg)
2080 u32 dsts = dwc2_readl(hsotg->regs + DSTS);
2081 int ep0_mps = 0, ep_mps = 8;
2084 * This should signal the finish of the enumeration phase
2085 * of the USB handshaking, so we should now know what rate
2089 dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts);
2092 * note, since we're limited by the size of transfer on EP0, and
2093 * it seems IN transfers must be a even number of packets we do
2094 * not advertise a 64byte MPS on EP0.
2097 /* catch both EnumSpd_FS and EnumSpd_FS48 */
2098 switch ((dsts & DSTS_ENUMSPD_MASK) >> DSTS_ENUMSPD_SHIFT) {
2099 case DSTS_ENUMSPD_FS:
2100 case DSTS_ENUMSPD_FS48:
2101 hsotg->gadget.speed = USB_SPEED_FULL;
2102 ep0_mps = EP0_MPS_LIMIT;
2106 case DSTS_ENUMSPD_HS:
2107 hsotg->gadget.speed = USB_SPEED_HIGH;
2108 ep0_mps = EP0_MPS_LIMIT;
2112 case DSTS_ENUMSPD_LS:
2113 hsotg->gadget.speed = USB_SPEED_LOW;
2115 * note, we don't actually support LS in this driver at the
2116 * moment, and the documentation seems to imply that it isn't
2117 * supported by the PHYs on some of the devices.
2121 dev_info(hsotg->dev, "new device is %s\n",
2122 usb_speed_string(hsotg->gadget.speed));
2125 * we should now know the maximum packet size for an
2126 * endpoint, so set the endpoints to a default value.
2131 /* Initialize ep0 for both in and out directions */
2132 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 1);
2133 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0);
2134 for (i = 1; i < hsotg->num_of_eps; i++) {
2135 if (hsotg->eps_in[i])
2136 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, 1);
2137 if (hsotg->eps_out[i])
2138 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, 0);
2142 /* ensure after enumeration our EP0 is active */
2144 dwc2_hsotg_enqueue_setup(hsotg);
2146 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2147 dwc2_readl(hsotg->regs + DIEPCTL0),
2148 dwc2_readl(hsotg->regs + DOEPCTL0));
2152 * kill_all_requests - remove all requests from the endpoint's queue
2153 * @hsotg: The device state.
2154 * @ep: The endpoint the requests may be on.
2155 * @result: The result code to use.
2157 * Go through the requests on the given endpoint and mark them
2158 * completed with the given result code.
2160 static void kill_all_requests(struct dwc2_hsotg *hsotg,
2161 struct dwc2_hsotg_ep *ep,
2164 struct dwc2_hsotg_req *req, *treq;
2169 list_for_each_entry_safe(req, treq, &ep->queue, queue)
2170 dwc2_hsotg_complete_request(hsotg, ep, req,
2173 if (!hsotg->dedicated_fifos)
2175 size = (dwc2_readl(hsotg->regs + DTXFSTS(ep->index)) & 0xffff) * 4;
2176 if (size < ep->fifo_size)
2177 dwc2_hsotg_txfifo_flush(hsotg, ep->fifo_index);
2181 * dwc2_hsotg_disconnect - disconnect service
2182 * @hsotg: The device state.
2184 * The device has been disconnected. Remove all current
2185 * transactions and signal the gadget driver that this
2188 void dwc2_hsotg_disconnect(struct dwc2_hsotg *hsotg)
2192 if (!hsotg->connected)
2195 hsotg->connected = 0;
2196 hsotg->test_mode = 0;
2198 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
2199 if (hsotg->eps_in[ep])
2200 kill_all_requests(hsotg, hsotg->eps_in[ep],
2202 if (hsotg->eps_out[ep])
2203 kill_all_requests(hsotg, hsotg->eps_out[ep],
2207 call_gadget(hsotg, disconnect);
2208 hsotg->lx_state = DWC2_L3;
2212 * dwc2_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
2213 * @hsotg: The device state:
2214 * @periodic: True if this is a periodic FIFO interrupt
2216 static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic)
2218 struct dwc2_hsotg_ep *ep;
2221 /* look through for any more data to transmit */
2222 for (epno = 0; epno < hsotg->num_of_eps; epno++) {
2223 ep = index_to_ep(hsotg, epno, 1);
2231 if ((periodic && !ep->periodic) ||
2232 (!periodic && ep->periodic))
2235 ret = dwc2_hsotg_trytx(hsotg, ep);
2241 /* IRQ flags which will trigger a retry around the IRQ loop */
2242 #define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \
2247 * dwc2_hsotg_core_init - issue softreset to the core
2248 * @hsotg: The device state
2250 * Issue a soft reset to the core, and await the core finishing it.
2252 void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
2258 /* Kill any ep0 requests as controller will be reinitialized */
2259 kill_all_requests(hsotg, hsotg->eps_out[0], -ECONNRESET);
2262 if (dwc2_core_reset(hsotg))
2266 * we must now enable ep0 ready for host detection and then
2267 * set configuration.
2270 /* set the PLL on, remove the HNP/SRP and set the PHY */
2271 val = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5;
2272 dwc2_writel(hsotg->phyif | GUSBCFG_TOUTCAL(7) |
2273 (val << GUSBCFG_USBTRDTIM_SHIFT), hsotg->regs + GUSBCFG);
2275 dwc2_hsotg_init_fifo(hsotg);
2278 __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON);
2280 dwc2_writel(DCFG_EPMISCNT(1) | DCFG_DEVSPD_HS, hsotg->regs + DCFG);
2282 /* Clear any pending OTG interrupts */
2283 dwc2_writel(0xffffffff, hsotg->regs + GOTGINT);
2285 /* Clear any pending interrupts */
2286 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
2287 intmsk = GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT |
2288 GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF |
2289 GINTSTS_USBRST | GINTSTS_RESETDET |
2290 GINTSTS_ENUMDONE | GINTSTS_OTGINT |
2291 GINTSTS_USBSUSP | GINTSTS_WKUPINT |
2292 GINTSTS_INCOMPL_SOIN | GINTSTS_INCOMPL_SOOUT;
2294 if (hsotg->core_params->external_id_pin_ctl <= 0)
2295 intmsk |= GINTSTS_CONIDSTSCHNG;
2297 dwc2_writel(intmsk, hsotg->regs + GINTMSK);
2299 if (using_dma(hsotg))
2300 dwc2_writel(GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN |
2301 (GAHBCFG_HBSTLEN_INCR4 << GAHBCFG_HBSTLEN_SHIFT),
2302 hsotg->regs + GAHBCFG);
2304 dwc2_writel(((hsotg->dedicated_fifos) ?
2305 (GAHBCFG_NP_TXF_EMP_LVL |
2306 GAHBCFG_P_TXF_EMP_LVL) : 0) |
2307 GAHBCFG_GLBL_INTR_EN, hsotg->regs + GAHBCFG);
2310 * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts
2311 * when we have no data to transfer. Otherwise we get being flooded by
2315 dwc2_writel(((hsotg->dedicated_fifos && !using_dma(hsotg)) ?
2316 DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) |
2317 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK |
2318 DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
2319 DIEPMSK_INTKNEPMISMSK,
2320 hsotg->regs + DIEPMSK);
2323 * don't need XferCompl, we get that from RXFIFO in slave mode. In
2324 * DMA mode we may need this.
2326 dwc2_writel((using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK |
2327 DIEPMSK_TIMEOUTMSK) : 0) |
2328 DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK |
2330 hsotg->regs + DOEPMSK);
2332 dwc2_writel(0, hsotg->regs + DAINTMSK);
2334 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2335 dwc2_readl(hsotg->regs + DIEPCTL0),
2336 dwc2_readl(hsotg->regs + DOEPCTL0));
2338 /* enable in and out endpoint interrupts */
2339 dwc2_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT);
2342 * Enable the RXFIFO when in slave mode, as this is how we collect
2343 * the data. In DMA mode, we get events from the FIFO but also
2344 * things we cannot process, so do not use it.
2346 if (!using_dma(hsotg))
2347 dwc2_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL);
2349 /* Enable interrupts for EP0 in and out */
2350 dwc2_hsotg_ctrl_epint(hsotg, 0, 0, 1);
2351 dwc2_hsotg_ctrl_epint(hsotg, 0, 1, 1);
2353 if (!is_usb_reset) {
2354 __orr32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE);
2355 udelay(10); /* see openiboot */
2356 __bic32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE);
2359 dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg->regs + DCTL));
2362 * DxEPCTL_USBActEp says RO in manual, but seems to be set by
2363 * writing to the EPCTL register..
2366 /* set to read 1 8byte packet */
2367 dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
2368 DXEPTSIZ_XFERSIZE(8), hsotg->regs + DOEPTSIZ0);
2370 dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
2371 DXEPCTL_CNAK | DXEPCTL_EPENA |
2373 hsotg->regs + DOEPCTL0);
2375 /* enable, but don't activate EP0in */
2376 dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
2377 DXEPCTL_USBACTEP, hsotg->regs + DIEPCTL0);
2379 dwc2_hsotg_enqueue_setup(hsotg);
2381 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2382 dwc2_readl(hsotg->regs + DIEPCTL0),
2383 dwc2_readl(hsotg->regs + DOEPCTL0));
2385 /* clear global NAKs */
2386 val = DCTL_CGOUTNAK | DCTL_CGNPINNAK;
2388 val |= DCTL_SFTDISCON;
2389 __orr32(hsotg->regs + DCTL, val);
2391 /* must be at-least 3ms to allow bus to see disconnect */
2394 hsotg->lx_state = DWC2_L0;
2397 static void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg)
2399 /* set the soft-disconnect bit */
2400 __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON);
2403 void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg)
2405 /* remove the soft-disconnect and let's go */
2406 __bic32(hsotg->regs + DCTL, DCTL_SFTDISCON);
2410 * dwc2_hsotg_irq - handle device interrupt
2411 * @irq: The IRQ number triggered
2412 * @pw: The pw value when registered the handler.
2414 static irqreturn_t dwc2_hsotg_irq(int irq, void *pw)
2416 struct dwc2_hsotg *hsotg = pw;
2417 int retry_count = 8;
2421 spin_lock(&hsotg->lock);
2423 gintsts = dwc2_readl(hsotg->regs + GINTSTS);
2424 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
2426 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
2427 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
2431 if (gintsts & GINTSTS_RESETDET) {
2432 dev_dbg(hsotg->dev, "%s: USBRstDet\n", __func__);
2434 dwc2_writel(GINTSTS_RESETDET, hsotg->regs + GINTSTS);
2436 /* This event must be used only if controller is suspended */
2437 if (hsotg->lx_state == DWC2_L2) {
2438 dwc2_exit_hibernation(hsotg, true);
2439 hsotg->lx_state = DWC2_L0;
2443 if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) {
2445 u32 usb_status = dwc2_readl(hsotg->regs + GOTGCTL);
2446 u32 connected = hsotg->connected;
2448 dev_dbg(hsotg->dev, "%s: USBRst\n", __func__);
2449 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
2450 dwc2_readl(hsotg->regs + GNPTXSTS));
2452 dwc2_writel(GINTSTS_USBRST, hsotg->regs + GINTSTS);
2454 /* Report disconnection if it is not already done. */
2455 dwc2_hsotg_disconnect(hsotg);
2457 if (usb_status & GOTGCTL_BSESVLD && connected)
2458 dwc2_hsotg_core_init_disconnected(hsotg, true);
2461 if (gintsts & GINTSTS_ENUMDONE) {
2462 dwc2_writel(GINTSTS_ENUMDONE, hsotg->regs + GINTSTS);
2464 dwc2_hsotg_irq_enumdone(hsotg);
2467 if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) {
2468 u32 daint = dwc2_readl(hsotg->regs + DAINT);
2469 u32 daintmsk = dwc2_readl(hsotg->regs + DAINTMSK);
2470 u32 daint_out, daint_in;
2474 daint_out = daint >> DAINT_OUTEP_SHIFT;
2475 daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT);
2477 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
2479 for (ep = 0; ep < hsotg->num_of_eps && daint_out;
2480 ep++, daint_out >>= 1) {
2482 dwc2_hsotg_epint(hsotg, ep, 0);
2485 for (ep = 0; ep < hsotg->num_of_eps && daint_in;
2486 ep++, daint_in >>= 1) {
2488 dwc2_hsotg_epint(hsotg, ep, 1);
2492 /* check both FIFOs */
2494 if (gintsts & GINTSTS_NPTXFEMP) {
2495 dev_dbg(hsotg->dev, "NPTxFEmp\n");
2498 * Disable the interrupt to stop it happening again
2499 * unless one of these endpoint routines decides that
2500 * it needs re-enabling
2503 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP);
2504 dwc2_hsotg_irq_fifoempty(hsotg, false);
2507 if (gintsts & GINTSTS_PTXFEMP) {
2508 dev_dbg(hsotg->dev, "PTxFEmp\n");
2510 /* See note in GINTSTS_NPTxFEmp */
2512 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP);
2513 dwc2_hsotg_irq_fifoempty(hsotg, true);
2516 if (gintsts & GINTSTS_RXFLVL) {
2518 * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
2519 * we need to retry dwc2_hsotg_handle_rx if this is still
2523 dwc2_hsotg_handle_rx(hsotg);
2526 if (gintsts & GINTSTS_ERLYSUSP) {
2527 dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n");
2528 dwc2_writel(GINTSTS_ERLYSUSP, hsotg->regs + GINTSTS);
2532 * these next two seem to crop-up occasionally causing the core
2533 * to shutdown the USB transfer, so try clearing them and logging
2537 if (gintsts & GINTSTS_GOUTNAKEFF) {
2538 dev_info(hsotg->dev, "GOUTNakEff triggered\n");
2540 __orr32(hsotg->regs + DCTL, DCTL_CGOUTNAK);
2542 dwc2_hsotg_dump(hsotg);
2545 if (gintsts & GINTSTS_GINNAKEFF) {
2546 dev_info(hsotg->dev, "GINNakEff triggered\n");
2548 __orr32(hsotg->regs + DCTL, DCTL_CGNPINNAK);
2550 dwc2_hsotg_dump(hsotg);
2553 if (gintsts & GINTSTS_INCOMPL_SOIN) {
2555 struct dwc2_hsotg_ep *hs_ep;
2557 dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOIN\n", __func__);
2558 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
2559 hs_ep = hsotg->eps_in[idx];
2561 if (!hs_ep->isochronous || hs_ep->has_correct_parity)
2564 epctl_reg = DIEPCTL(idx);
2565 dwc2_hsotg_change_ep_iso_parity(hsotg, epctl_reg);
2567 dwc2_writel(GINTSTS_INCOMPL_SOIN, hsotg->regs + GINTSTS);
2570 if (gintsts & GINTSTS_INCOMPL_SOOUT) {
2572 struct dwc2_hsotg_ep *hs_ep;
2574 dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOOUT\n", __func__);
2575 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
2576 hs_ep = hsotg->eps_out[idx];
2578 if (!hs_ep->isochronous || hs_ep->has_correct_parity)
2581 epctl_reg = DOEPCTL(idx);
2582 dwc2_hsotg_change_ep_iso_parity(hsotg, epctl_reg);
2584 dwc2_writel(GINTSTS_INCOMPL_SOOUT, hsotg->regs + GINTSTS);
2588 * if we've had fifo events, we should try and go around the
2589 * loop again to see if there's any point in returning yet.
2592 if (gintsts & IRQ_RETRY_MASK && --retry_count > 0)
2595 spin_unlock(&hsotg->lock);
2601 * dwc2_hsotg_ep_enable - enable the given endpoint
2602 * @ep: The USB endpint to configure
2603 * @desc: The USB endpoint descriptor to configure with.
2605 * This is called from the USB gadget code's usb_ep_enable().
2607 static int dwc2_hsotg_ep_enable(struct usb_ep *ep,
2608 const struct usb_endpoint_descriptor *desc)
2610 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
2611 struct dwc2_hsotg *hsotg = hs_ep->parent;
2612 unsigned long flags;
2613 unsigned int index = hs_ep->index;
2617 unsigned int dir_in;
2618 unsigned int i, val, size;
2622 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
2623 __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes,
2624 desc->wMaxPacketSize, desc->bInterval);
2626 /* not to be called for EP0 */
2627 WARN_ON(index == 0);
2629 dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
2630 if (dir_in != hs_ep->dir_in) {
2631 dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__);
2635 mps = usb_endpoint_maxp(desc);
2637 /* note, we handle this here instead of dwc2_hsotg_set_ep_maxpacket */
2639 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
2640 epctrl = dwc2_readl(hsotg->regs + epctrl_reg);
2642 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
2643 __func__, epctrl, epctrl_reg);
2645 spin_lock_irqsave(&hsotg->lock, flags);
2647 epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK);
2648 epctrl |= DXEPCTL_MPS(mps);
2651 * mark the endpoint as active, otherwise the core may ignore
2652 * transactions entirely for this endpoint
2654 epctrl |= DXEPCTL_USBACTEP;
2657 * set the NAK status on the endpoint, otherwise we might try and
2658 * do something with data that we've yet got a request to process
2659 * since the RXFIFO will take data for an endpoint even if the
2660 * size register hasn't been set.
2663 epctrl |= DXEPCTL_SNAK;
2665 /* update the endpoint state */
2666 dwc2_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps, dir_in);
2668 /* default, set to non-periodic */
2669 hs_ep->isochronous = 0;
2670 hs_ep->periodic = 0;
2672 hs_ep->interval = desc->bInterval;
2673 hs_ep->has_correct_parity = 0;
2675 if (hs_ep->interval > 1 && hs_ep->mc > 1)
2676 dev_err(hsotg->dev, "MC > 1 when interval is not 1\n");
2678 switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
2679 case USB_ENDPOINT_XFER_ISOC:
2680 epctrl |= DXEPCTL_EPTYPE_ISO;
2681 epctrl |= DXEPCTL_SETEVENFR;
2682 hs_ep->isochronous = 1;
2684 hs_ep->periodic = 1;
2687 case USB_ENDPOINT_XFER_BULK:
2688 epctrl |= DXEPCTL_EPTYPE_BULK;
2691 case USB_ENDPOINT_XFER_INT:
2693 hs_ep->periodic = 1;
2695 epctrl |= DXEPCTL_EPTYPE_INTERRUPT;
2698 case USB_ENDPOINT_XFER_CONTROL:
2699 epctrl |= DXEPCTL_EPTYPE_CONTROL;
2703 /* If fifo is already allocated for this ep */
2704 if (hs_ep->fifo_index) {
2705 size = hs_ep->ep.maxpacket * hs_ep->mc;
2706 /* If bigger fifo is required deallocate current one */
2707 if (size > hs_ep->fifo_size) {
2708 hsotg->fifo_map &= ~(1 << hs_ep->fifo_index);
2709 hs_ep->fifo_index = 0;
2710 hs_ep->fifo_size = 0;
2715 * if the hardware has dedicated fifos, we must give each IN EP
2716 * a unique tx-fifo even if it is non-periodic.
2718 if (dir_in && hsotg->dedicated_fifos && !hs_ep->fifo_index) {
2720 u32 fifo_size = UINT_MAX;
2721 size = hs_ep->ep.maxpacket*hs_ep->mc;
2722 for (i = 1; i < hsotg->num_of_eps; ++i) {
2723 if (hsotg->fifo_map & (1<<i))
2725 val = dwc2_readl(hsotg->regs + DPTXFSIZN(i));
2726 val = (val >> FIFOSIZE_DEPTH_SHIFT)*4;
2729 /* Search for smallest acceptable fifo */
2730 if (val < fifo_size) {
2737 "%s: No suitable fifo found\n", __func__);
2741 hsotg->fifo_map |= 1 << fifo_index;
2742 epctrl |= DXEPCTL_TXFNUM(fifo_index);
2743 hs_ep->fifo_index = fifo_index;
2744 hs_ep->fifo_size = fifo_size;
2747 /* for non control endpoints, set PID to D0 */
2749 epctrl |= DXEPCTL_SETD0PID;
2751 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
2754 dwc2_writel(epctrl, hsotg->regs + epctrl_reg);
2755 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
2756 __func__, dwc2_readl(hsotg->regs + epctrl_reg));
2758 /* enable the endpoint interrupt */
2759 dwc2_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
2762 spin_unlock_irqrestore(&hsotg->lock, flags);
2767 * dwc2_hsotg_ep_disable - disable given endpoint
2768 * @ep: The endpoint to disable.
2770 static int dwc2_hsotg_ep_disable(struct usb_ep *ep)
2772 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
2773 struct dwc2_hsotg *hsotg = hs_ep->parent;
2774 int dir_in = hs_ep->dir_in;
2775 int index = hs_ep->index;
2776 unsigned long flags;
2780 dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep);
2782 if (ep == &hsotg->eps_out[0]->ep) {
2783 dev_err(hsotg->dev, "%s: called for ep0\n", __func__);
2787 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
2789 spin_lock_irqsave(&hsotg->lock, flags);
2791 hsotg->fifo_map &= ~(1<<hs_ep->fifo_index);
2792 hs_ep->fifo_index = 0;
2793 hs_ep->fifo_size = 0;
2795 ctrl = dwc2_readl(hsotg->regs + epctrl_reg);
2796 ctrl &= ~DXEPCTL_EPENA;
2797 ctrl &= ~DXEPCTL_USBACTEP;
2798 ctrl |= DXEPCTL_SNAK;
2800 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
2801 dwc2_writel(ctrl, hsotg->regs + epctrl_reg);
2803 /* disable endpoint interrupts */
2804 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
2806 /* terminate all requests with shutdown */
2807 kill_all_requests(hsotg, hs_ep, -ESHUTDOWN);
2809 spin_unlock_irqrestore(&hsotg->lock, flags);
2814 * on_list - check request is on the given endpoint
2815 * @ep: The endpoint to check.
2816 * @test: The request to test if it is on the endpoint.
2818 static bool on_list(struct dwc2_hsotg_ep *ep, struct dwc2_hsotg_req *test)
2820 struct dwc2_hsotg_req *req, *treq;
2822 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
2830 static int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hs_otg, u32 reg,
2831 u32 bit, u32 timeout)
2835 for (i = 0; i < timeout; i++) {
2836 if (dwc2_readl(hs_otg->regs + reg) & bit)
2844 static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
2845 struct dwc2_hsotg_ep *hs_ep)
2850 epctrl_reg = hs_ep->dir_in ? DIEPCTL(hs_ep->index) :
2851 DOEPCTL(hs_ep->index);
2852 epint_reg = hs_ep->dir_in ? DIEPINT(hs_ep->index) :
2853 DOEPINT(hs_ep->index);
2855 dev_dbg(hsotg->dev, "%s: stopping transfer on %s\n", __func__,
2857 if (hs_ep->dir_in) {
2858 __orr32(hsotg->regs + epctrl_reg, DXEPCTL_SNAK);
2859 /* Wait for Nak effect */
2860 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg,
2861 DXEPINT_INEPNAKEFF, 100))
2862 dev_warn(hsotg->dev,
2863 "%s: timeout DIEPINT.NAKEFF\n", __func__);
2865 /* Clear any pending nak effect interrupt */
2866 dwc2_writel(GINTSTS_GOUTNAKEFF, hsotg->regs + GINTSTS);
2868 __orr32(hsotg->regs + DCTL, DCTL_SGOUTNAK);
2870 /* Wait for global nak to take effect */
2871 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
2872 GINTSTS_GOUTNAKEFF, 100))
2873 dev_warn(hsotg->dev,
2874 "%s: timeout GINTSTS.GOUTNAKEFF\n", __func__);
2878 __orr32(hsotg->regs + epctrl_reg, DXEPCTL_EPDIS | DXEPCTL_SNAK);
2880 /* Wait for ep to be disabled */
2881 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, DXEPINT_EPDISBLD, 100))
2882 dev_warn(hsotg->dev,
2883 "%s: timeout DOEPCTL.EPDisable\n", __func__);
2885 if (hs_ep->dir_in) {
2886 if (hsotg->dedicated_fifos) {
2887 dwc2_writel(GRSTCTL_TXFNUM(hs_ep->fifo_index) |
2888 GRSTCTL_TXFFLSH, hsotg->regs + GRSTCTL);
2889 /* Wait for fifo flush */
2890 if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL,
2891 GRSTCTL_TXFFLSH, 100))
2892 dev_warn(hsotg->dev,
2893 "%s: timeout flushing fifos\n",
2896 /* TODO: Flush shared tx fifo */
2898 /* Remove global NAKs */
2899 __bic32(hsotg->regs + DCTL, DCTL_SGOUTNAK);
2904 * dwc2_hsotg_ep_dequeue - dequeue given endpoint
2905 * @ep: The endpoint to dequeue.
2906 * @req: The request to be removed from a queue.
2908 static int dwc2_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
2910 struct dwc2_hsotg_req *hs_req = our_req(req);
2911 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
2912 struct dwc2_hsotg *hs = hs_ep->parent;
2913 unsigned long flags;
2915 dev_dbg(hs->dev, "ep_dequeue(%p,%p)\n", ep, req);
2917 spin_lock_irqsave(&hs->lock, flags);
2919 if (!on_list(hs_ep, hs_req)) {
2920 spin_unlock_irqrestore(&hs->lock, flags);
2924 /* Dequeue already started request */
2925 if (req == &hs_ep->req->req)
2926 dwc2_hsotg_ep_stop_xfr(hs, hs_ep);
2928 dwc2_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET);
2929 spin_unlock_irqrestore(&hs->lock, flags);
2935 * dwc2_hsotg_ep_sethalt - set halt on a given endpoint
2936 * @ep: The endpoint to set halt.
2937 * @value: Set or unset the halt.
2939 static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value)
2941 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
2942 struct dwc2_hsotg *hs = hs_ep->parent;
2943 int index = hs_ep->index;
2948 dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value);
2952 dwc2_hsotg_stall_ep0(hs);
2955 "%s: can't clear halt on ep0\n", __func__);
2959 if (hs_ep->dir_in) {
2960 epreg = DIEPCTL(index);
2961 epctl = dwc2_readl(hs->regs + epreg);
2964 epctl |= DXEPCTL_STALL | DXEPCTL_SNAK;
2965 if (epctl & DXEPCTL_EPENA)
2966 epctl |= DXEPCTL_EPDIS;
2968 epctl &= ~DXEPCTL_STALL;
2969 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
2970 if (xfertype == DXEPCTL_EPTYPE_BULK ||
2971 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
2972 epctl |= DXEPCTL_SETD0PID;
2974 dwc2_writel(epctl, hs->regs + epreg);
2977 epreg = DOEPCTL(index);
2978 epctl = dwc2_readl(hs->regs + epreg);
2981 epctl |= DXEPCTL_STALL;
2983 epctl &= ~DXEPCTL_STALL;
2984 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
2985 if (xfertype == DXEPCTL_EPTYPE_BULK ||
2986 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
2987 epctl |= DXEPCTL_SETD0PID;
2989 dwc2_writel(epctl, hs->regs + epreg);
2992 hs_ep->halted = value;
2998 * dwc2_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held
2999 * @ep: The endpoint to set halt.
3000 * @value: Set or unset the halt.
3002 static int dwc2_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value)
3004 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
3005 struct dwc2_hsotg *hs = hs_ep->parent;
3006 unsigned long flags = 0;
3009 spin_lock_irqsave(&hs->lock, flags);
3010 ret = dwc2_hsotg_ep_sethalt(ep, value);
3011 spin_unlock_irqrestore(&hs->lock, flags);
3016 static struct usb_ep_ops dwc2_hsotg_ep_ops = {
3017 .enable = dwc2_hsotg_ep_enable,
3018 .disable = dwc2_hsotg_ep_disable,
3019 .alloc_request = dwc2_hsotg_ep_alloc_request,
3020 .free_request = dwc2_hsotg_ep_free_request,
3021 .queue = dwc2_hsotg_ep_queue_lock,
3022 .dequeue = dwc2_hsotg_ep_dequeue,
3023 .set_halt = dwc2_hsotg_ep_sethalt_lock,
3024 /* note, don't believe we have any call for the fifo routines */
3028 * dwc2_hsotg_init - initalize the usb core
3029 * @hsotg: The driver state
3031 static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg)
3034 /* unmask subset of endpoint interrupts */
3036 dwc2_writel(DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
3037 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK,
3038 hsotg->regs + DIEPMSK);
3040 dwc2_writel(DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK |
3041 DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK,
3042 hsotg->regs + DOEPMSK);
3044 dwc2_writel(0, hsotg->regs + DAINTMSK);
3046 /* Be in disconnected state until gadget is registered */
3047 __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON);
3051 dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
3052 dwc2_readl(hsotg->regs + GRXFSIZ),
3053 dwc2_readl(hsotg->regs + GNPTXFSIZ));
3055 dwc2_hsotg_init_fifo(hsotg);
3057 /* set the PLL on, remove the HNP/SRP and set the PHY */
3058 trdtim = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5;
3059 dwc2_writel(hsotg->phyif | GUSBCFG_TOUTCAL(7) |
3060 (trdtim << GUSBCFG_USBTRDTIM_SHIFT),
3061 hsotg->regs + GUSBCFG);
3063 if (using_dma(hsotg))
3064 __orr32(hsotg->regs + GAHBCFG, GAHBCFG_DMA_EN);
3068 * dwc2_hsotg_udc_start - prepare the udc for work
3069 * @gadget: The usb gadget state
3070 * @driver: The usb gadget driver
3072 * Perform initialization to prepare udc device and driver
3075 static int dwc2_hsotg_udc_start(struct usb_gadget *gadget,
3076 struct usb_gadget_driver *driver)
3078 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
3079 unsigned long flags;
3083 pr_err("%s: called with no device\n", __func__);
3088 dev_err(hsotg->dev, "%s: no driver\n", __func__);
3092 if (driver->max_speed < USB_SPEED_FULL)
3093 dev_err(hsotg->dev, "%s: bad speed\n", __func__);
3095 if (!driver->setup) {
3096 dev_err(hsotg->dev, "%s: missing entry points\n", __func__);
3100 WARN_ON(hsotg->driver);
3102 driver->driver.bus = NULL;
3103 hsotg->driver = driver;
3104 hsotg->gadget.dev.of_node = hsotg->dev->of_node;
3105 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
3107 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) {
3108 ret = dwc2_lowlevel_hw_enable(hsotg);
3113 if (!IS_ERR_OR_NULL(hsotg->uphy))
3114 otg_set_peripheral(hsotg->uphy->otg, &hsotg->gadget);
3116 spin_lock_irqsave(&hsotg->lock, flags);
3117 dwc2_hsotg_init(hsotg);
3118 dwc2_hsotg_core_init_disconnected(hsotg, false);
3120 spin_unlock_irqrestore(&hsotg->lock, flags);
3122 dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
3127 hsotg->driver = NULL;
3132 * dwc2_hsotg_udc_stop - stop the udc
3133 * @gadget: The usb gadget state
3134 * @driver: The usb gadget driver
3136 * Stop udc hw block and stay tunned for future transmissions
3138 static int dwc2_hsotg_udc_stop(struct usb_gadget *gadget)
3140 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
3141 unsigned long flags = 0;
3147 /* all endpoints should be shutdown */
3148 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
3149 if (hsotg->eps_in[ep])
3150 dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep);
3151 if (hsotg->eps_out[ep])
3152 dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep);
3155 spin_lock_irqsave(&hsotg->lock, flags);
3157 hsotg->driver = NULL;
3158 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
3161 spin_unlock_irqrestore(&hsotg->lock, flags);
3163 if (!IS_ERR_OR_NULL(hsotg->uphy))
3164 otg_set_peripheral(hsotg->uphy->otg, NULL);
3166 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
3167 dwc2_lowlevel_hw_disable(hsotg);
3173 * dwc2_hsotg_gadget_getframe - read the frame number
3174 * @gadget: The usb gadget state
3176 * Read the {micro} frame number
3178 static int dwc2_hsotg_gadget_getframe(struct usb_gadget *gadget)
3180 return dwc2_hsotg_read_frameno(to_hsotg(gadget));
3184 * dwc2_hsotg_pullup - connect/disconnect the USB PHY
3185 * @gadget: The usb gadget state
3186 * @is_on: Current state of the USB PHY
3188 * Connect/Disconnect the USB PHY pullup
3190 static int dwc2_hsotg_pullup(struct usb_gadget *gadget, int is_on)
3192 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
3193 unsigned long flags = 0;
3195 dev_dbg(hsotg->dev, "%s: is_on: %d op_state: %d\n", __func__, is_on,
3198 /* Don't modify pullup state while in host mode */
3199 if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
3200 hsotg->enabled = is_on;
3204 spin_lock_irqsave(&hsotg->lock, flags);
3207 dwc2_hsotg_core_init_disconnected(hsotg, false);
3208 dwc2_hsotg_core_connect(hsotg);
3210 dwc2_hsotg_core_disconnect(hsotg);
3211 dwc2_hsotg_disconnect(hsotg);
3215 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
3216 spin_unlock_irqrestore(&hsotg->lock, flags);
3221 static int dwc2_hsotg_vbus_session(struct usb_gadget *gadget, int is_active)
3223 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
3224 unsigned long flags;
3226 dev_dbg(hsotg->dev, "%s: is_active: %d\n", __func__, is_active);
3227 spin_lock_irqsave(&hsotg->lock, flags);
3230 * If controller is hibernated, it must exit from hibernation
3231 * before being initialized / de-initialized
3233 if (hsotg->lx_state == DWC2_L2)
3234 dwc2_exit_hibernation(hsotg, false);
3237 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
3239 dwc2_hsotg_core_init_disconnected(hsotg, false);
3241 dwc2_hsotg_core_connect(hsotg);
3243 dwc2_hsotg_core_disconnect(hsotg);
3244 dwc2_hsotg_disconnect(hsotg);
3247 spin_unlock_irqrestore(&hsotg->lock, flags);
3252 * dwc2_hsotg_vbus_draw - report bMaxPower field
3253 * @gadget: The usb gadget state
3254 * @mA: Amount of current
3256 * Report how much power the device may consume to the phy.
3258 static int dwc2_hsotg_vbus_draw(struct usb_gadget *gadget, unsigned mA)
3260 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
3262 if (IS_ERR_OR_NULL(hsotg->uphy))
3264 return usb_phy_set_power(hsotg->uphy, mA);
3267 static const struct usb_gadget_ops dwc2_hsotg_gadget_ops = {
3268 .get_frame = dwc2_hsotg_gadget_getframe,
3269 .udc_start = dwc2_hsotg_udc_start,
3270 .udc_stop = dwc2_hsotg_udc_stop,
3271 .pullup = dwc2_hsotg_pullup,
3272 .vbus_session = dwc2_hsotg_vbus_session,
3273 .vbus_draw = dwc2_hsotg_vbus_draw,
3277 * dwc2_hsotg_initep - initialise a single endpoint
3278 * @hsotg: The device state.
3279 * @hs_ep: The endpoint to be initialised.
3280 * @epnum: The endpoint number
3282 * Initialise the given endpoint (as part of the probe and device state
3283 * creation) to give to the gadget driver. Setup the endpoint name, any
3284 * direction information and other state that may be required.
3286 static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg,
3287 struct dwc2_hsotg_ep *hs_ep,
3300 hs_ep->dir_in = dir_in;
3301 hs_ep->index = epnum;
3303 snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir);
3305 INIT_LIST_HEAD(&hs_ep->queue);
3306 INIT_LIST_HEAD(&hs_ep->ep.ep_list);
3308 /* add to the list of endpoints known by the gadget driver */
3310 list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list);
3312 hs_ep->parent = hsotg;
3313 hs_ep->ep.name = hs_ep->name;
3314 usb_ep_set_maxpacket_limit(&hs_ep->ep, epnum ? 1024 : EP0_MPS_LIMIT);
3315 hs_ep->ep.ops = &dwc2_hsotg_ep_ops;
3318 hs_ep->ep.caps.type_control = true;
3320 hs_ep->ep.caps.type_iso = true;
3321 hs_ep->ep.caps.type_bulk = true;
3322 hs_ep->ep.caps.type_int = true;
3326 hs_ep->ep.caps.dir_in = true;
3328 hs_ep->ep.caps.dir_out = true;
3331 * if we're using dma, we need to set the next-endpoint pointer
3332 * to be something valid.
3335 if (using_dma(hsotg)) {
3336 u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15);
3338 dwc2_writel(next, hsotg->regs + DIEPCTL(epnum));
3340 dwc2_writel(next, hsotg->regs + DOEPCTL(epnum));
3345 * dwc2_hsotg_hw_cfg - read HW configuration registers
3346 * @param: The device state
3348 * Read the USB core HW configuration registers
3350 static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg *hsotg)
3356 /* check hardware configuration */
3358 hsotg->num_of_eps = hsotg->hw_params.num_dev_ep;
3361 hsotg->num_of_eps++;
3363 hsotg->eps_in[0] = devm_kzalloc(hsotg->dev, sizeof(struct dwc2_hsotg_ep),
3365 if (!hsotg->eps_in[0])
3367 /* Same dwc2_hsotg_ep is used in both directions for ep0 */
3368 hsotg->eps_out[0] = hsotg->eps_in[0];
3370 cfg = hsotg->hw_params.dev_ep_dirs;
3371 for (i = 1, cfg >>= 2; i < hsotg->num_of_eps; i++, cfg >>= 2) {
3373 /* Direction in or both */
3374 if (!(ep_type & 2)) {
3375 hsotg->eps_in[i] = devm_kzalloc(hsotg->dev,
3376 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
3377 if (!hsotg->eps_in[i])
3380 /* Direction out or both */
3381 if (!(ep_type & 1)) {
3382 hsotg->eps_out[i] = devm_kzalloc(hsotg->dev,
3383 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
3384 if (!hsotg->eps_out[i])
3389 hsotg->fifo_mem = hsotg->hw_params.total_fifo_size;
3390 hsotg->dedicated_fifos = hsotg->hw_params.en_multiple_tx_fifo;
3392 dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n",
3394 hsotg->dedicated_fifos ? "dedicated" : "shared",
3400 * dwc2_hsotg_dump - dump state of the udc
3401 * @param: The device state
3403 static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg)
3406 struct device *dev = hsotg->dev;
3407 void __iomem *regs = hsotg->regs;
3411 dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
3412 dwc2_readl(regs + DCFG), dwc2_readl(regs + DCTL),
3413 dwc2_readl(regs + DIEPMSK));
3415 dev_info(dev, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n",
3416 dwc2_readl(regs + GAHBCFG), dwc2_readl(regs + GHWCFG1));
3418 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
3419 dwc2_readl(regs + GRXFSIZ), dwc2_readl(regs + GNPTXFSIZ));
3421 /* show periodic fifo settings */
3423 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3424 val = dwc2_readl(regs + DPTXFSIZN(idx));
3425 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
3426 val >> FIFOSIZE_DEPTH_SHIFT,
3427 val & FIFOSIZE_STARTADDR_MASK);
3430 for (idx = 0; idx < hsotg->num_of_eps; idx++) {
3432 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
3433 dwc2_readl(regs + DIEPCTL(idx)),
3434 dwc2_readl(regs + DIEPTSIZ(idx)),
3435 dwc2_readl(regs + DIEPDMA(idx)));
3437 val = dwc2_readl(regs + DOEPCTL(idx));
3439 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
3440 idx, dwc2_readl(regs + DOEPCTL(idx)),
3441 dwc2_readl(regs + DOEPTSIZ(idx)),
3442 dwc2_readl(regs + DOEPDMA(idx)));
3446 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
3447 dwc2_readl(regs + DVBUSDIS), dwc2_readl(regs + DVBUSPULSE));
3452 static void dwc2_hsotg_of_probe(struct dwc2_hsotg *hsotg)
3454 struct device_node *np = hsotg->dev->of_node;
3458 /* Enable dma if requested in device tree */
3459 hsotg->g_using_dma = of_property_read_bool(np, "g-use-dma");
3462 * Register TX periodic fifo size per endpoint.
3463 * EP0 is excluded since it has no fifo configuration.
3465 if (!of_find_property(np, "g-tx-fifo-size", &len))
3470 /* Read tx fifo sizes other than ep0 */
3471 if (of_property_read_u32_array(np, "g-tx-fifo-size",
3472 &hsotg->g_tx_fifo_sz[1], len))
3478 /* Make remaining TX fifos unavailable */
3479 if (len < MAX_EPS_CHANNELS) {
3480 for (i = len; i < MAX_EPS_CHANNELS; i++)
3481 hsotg->g_tx_fifo_sz[i] = 0;
3485 /* Register RX fifo size */
3486 of_property_read_u32(np, "g-rx-fifo-size", &hsotg->g_rx_fifo_sz);
3488 /* Register NPTX fifo size */
3489 of_property_read_u32(np, "g-np-tx-fifo-size",
3490 &hsotg->g_np_g_tx_fifo_sz);
3493 static inline void dwc2_hsotg_of_probe(struct dwc2_hsotg *hsotg) { }
3497 * dwc2_gadget_init - init function for gadget
3498 * @dwc2: The data structure for the DWC2 driver.
3499 * @irq: The IRQ number for the controller.
3501 int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq)
3503 struct device *dev = hsotg->dev;
3507 u32 p_tx_fifo[] = DWC2_G_P_LEGACY_TX_FIFO_SIZE;
3509 /* Initialize to legacy fifo configuration values */
3510 hsotg->g_rx_fifo_sz = 2048;
3511 hsotg->g_np_g_tx_fifo_sz = 1024;
3512 memcpy(&hsotg->g_tx_fifo_sz[1], p_tx_fifo, sizeof(p_tx_fifo));
3513 /* Device tree specific probe */
3514 dwc2_hsotg_of_probe(hsotg);
3516 /* Check against largest possible value. */
3517 if (hsotg->g_np_g_tx_fifo_sz >
3518 hsotg->hw_params.dev_nperio_tx_fifo_size) {
3519 dev_warn(dev, "Specified GNPTXFDEP=%d > %d\n",
3520 hsotg->g_np_g_tx_fifo_sz,
3521 hsotg->hw_params.dev_nperio_tx_fifo_size);
3522 hsotg->g_np_g_tx_fifo_sz =
3523 hsotg->hw_params.dev_nperio_tx_fifo_size;
3526 /* Dump fifo information */
3527 dev_dbg(dev, "NonPeriodic TXFIFO size: %d\n",
3528 hsotg->g_np_g_tx_fifo_sz);
3529 dev_dbg(dev, "RXFIFO size: %d\n", hsotg->g_rx_fifo_sz);
3530 for (i = 0; i < MAX_EPS_CHANNELS; i++)
3531 dev_dbg(dev, "Periodic TXFIFO%2d size: %d\n", i,
3532 hsotg->g_tx_fifo_sz[i]);
3534 hsotg->gadget.max_speed = USB_SPEED_HIGH;
3535 hsotg->gadget.ops = &dwc2_hsotg_gadget_ops;
3536 hsotg->gadget.name = dev_name(dev);
3537 if (hsotg->dr_mode == USB_DR_MODE_OTG)
3538 hsotg->gadget.is_otg = 1;
3539 else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
3540 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
3542 ret = dwc2_hsotg_hw_cfg(hsotg);
3544 dev_err(hsotg->dev, "Hardware configuration failed: %d\n", ret);
3548 hsotg->ctrl_buff = devm_kzalloc(hsotg->dev,
3549 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
3550 if (!hsotg->ctrl_buff) {
3551 dev_err(dev, "failed to allocate ctrl request buff\n");
3555 hsotg->ep0_buff = devm_kzalloc(hsotg->dev,
3556 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
3557 if (!hsotg->ep0_buff) {
3558 dev_err(dev, "failed to allocate ctrl reply buff\n");
3562 ret = devm_request_irq(hsotg->dev, irq, dwc2_hsotg_irq, IRQF_SHARED,
3563 dev_name(hsotg->dev), hsotg);
3565 dev_err(dev, "cannot claim IRQ for gadget\n");
3569 /* hsotg->num_of_eps holds number of EPs other than ep0 */
3571 if (hsotg->num_of_eps == 0) {
3572 dev_err(dev, "wrong number of EPs (zero)\n");
3576 /* setup endpoint information */
3578 INIT_LIST_HEAD(&hsotg->gadget.ep_list);
3579 hsotg->gadget.ep0 = &hsotg->eps_out[0]->ep;
3581 /* allocate EP0 request */
3583 hsotg->ctrl_req = dwc2_hsotg_ep_alloc_request(&hsotg->eps_out[0]->ep,
3585 if (!hsotg->ctrl_req) {
3586 dev_err(dev, "failed to allocate ctrl req\n");
3590 /* initialise the endpoints now the core has been initialised */
3591 for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) {
3592 if (hsotg->eps_in[epnum])
3593 dwc2_hsotg_initep(hsotg, hsotg->eps_in[epnum],
3595 if (hsotg->eps_out[epnum])
3596 dwc2_hsotg_initep(hsotg, hsotg->eps_out[epnum],
3600 ret = usb_add_gadget_udc(dev, &hsotg->gadget);
3604 dwc2_hsotg_dump(hsotg);
3610 * dwc2_hsotg_remove - remove function for hsotg driver
3611 * @pdev: The platform information for the driver
3613 int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg)
3615 usb_del_gadget_udc(&hsotg->gadget);
3620 int dwc2_hsotg_suspend(struct dwc2_hsotg *hsotg)
3622 unsigned long flags;
3624 if (hsotg->lx_state != DWC2_L0)
3627 if (hsotg->driver) {
3630 dev_info(hsotg->dev, "suspending usb gadget %s\n",
3631 hsotg->driver->driver.name);
3633 spin_lock_irqsave(&hsotg->lock, flags);
3635 dwc2_hsotg_core_disconnect(hsotg);
3636 dwc2_hsotg_disconnect(hsotg);
3637 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
3638 spin_unlock_irqrestore(&hsotg->lock, flags);
3640 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
3641 if (hsotg->eps_in[ep])
3642 dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep);
3643 if (hsotg->eps_out[ep])
3644 dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep);
3651 int dwc2_hsotg_resume(struct dwc2_hsotg *hsotg)
3653 unsigned long flags;
3655 if (hsotg->lx_state == DWC2_L2)
3658 if (hsotg->driver) {
3659 dev_info(hsotg->dev, "resuming usb gadget %s\n",
3660 hsotg->driver->driver.name);
3662 spin_lock_irqsave(&hsotg->lock, flags);
3663 dwc2_hsotg_core_init_disconnected(hsotg, false);
3665 dwc2_hsotg_core_connect(hsotg);
3666 spin_unlock_irqrestore(&hsotg->lock, flags);