drivers/usb/dwc2/hcd.c

   1 /*
   2  * hcd.c - DesignWare HS OTG Controller host-mode routines
   3  *
   4  * Copyright (C) 2004-2013 Synopsys, Inc.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions, and the following disclaimer,
  11  *    without modification.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. The names of the above-listed copyright holders may not be used
  16  *    to endorse or promote products derived from this software without
  17  *    specific prior written permission.
  18  *
  19  * ALTERNATIVELY, this software may be distributed under the terms of the
  20  * GNU General Public License ("GPL") as published by the Free Software
  21  * Foundation; either version 2 of the License, or (at your option) any
  22  * later version.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  25  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  26  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  27  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  28  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  29  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  30  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  31  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  32  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  33  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  34  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35  */
  36
  37 /*
  38  * This file contains the core HCD code, and implements the Linux hc_driver
  39  * API
  40  */
  41 #include <linux/kernel.h>
  42 #include <linux/module.h>
  43 #include <linux/spinlock.h>
  44 #include <linux/interrupt.h>
  45 #include <linux/platform_device.h>
  46 #include <linux/dma-mapping.h>
  47 #include <linux/delay.h>
  48 #include <linux/io.h>
  49 #include <linux/slab.h>
  50 #include <linux/usb.h>
  51
  52 #include <linux/usb/hcd.h>
  53 #include <linux/usb/ch11.h>
  54
  55 #include "core.h"
  56 #include "hcd.h"
  57
  58 static void dwc2_port_resume(struct dwc2_hsotg *hsotg);
  59
  60 /*
  61  * =========================================================================
  62  *  Host Core Layer Functions
  63  * =========================================================================
  64  */
  65
  66 /**
  67  * dwc2_enable_common_interrupts() - Initializes the commmon interrupts,
  68  * used in both device and host modes
  69  *
  70  * @hsotg: Programming view of the DWC_otg controller
  71  */
  72 static void dwc2_enable_common_interrupts(struct dwc2_hsotg *hsotg)
  73 {
  74         u32 intmsk;
  75
  76         /* Clear any pending OTG Interrupts */
  77         dwc2_writel(0xffffffff, hsotg->regs + GOTGINT);
  78
  79         /* Clear any pending interrupts */
  80         dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
  81
  82         /* Enable the interrupts in the GINTMSK */
  83         intmsk = GINTSTS_MODEMIS | GINTSTS_OTGINT;
  84
  85         if (!hsotg->params.host_dma)
  86                 intmsk |= GINTSTS_RXFLVL;
  87         if (!hsotg->params.external_id_pin_ctl)
  88                 intmsk |= GINTSTS_CONIDSTSCHNG;
  89
  90         intmsk |= GINTSTS_WKUPINT | GINTSTS_USBSUSP |
  91                   GINTSTS_SESSREQINT;
  92
  93         dwc2_writel(intmsk, hsotg->regs + GINTMSK);
  94 }
  95
  96 /*
  97  * Initializes the FSLSPClkSel field of the HCFG register depending on the
  98  * PHY type
  99  */
 100 static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg)
 101 {
 102         u32 hcfg, val;
 103
 104         if ((hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
 105              hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
 106              hsotg->params.ulpi_fs_ls) ||
 107             hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) {
 108                 /* Full speed PHY */
 109                 val = HCFG_FSLSPCLKSEL_48_MHZ;
 110         } else {
 111                 /* High speed PHY running at full speed or high speed */
 112                 val = HCFG_FSLSPCLKSEL_30_60_MHZ;
 113         }
 114
 115         dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val);
 116         hcfg = dwc2_readl(hsotg->regs + HCFG);
 117         hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
 118         hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT;
 119         dwc2_writel(hcfg, hsotg->regs + HCFG);
 120 }
 121
 122 static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
 123 {
 124         u32 usbcfg, i2cctl;
 125         int retval = 0;
 126
 127         /*
 128          * core_init() is now called on every switch so only call the
 129          * following for the first time through
 130          */
 131         if (select_phy) {
 132                 dev_dbg(hsotg->dev, "FS PHY selected\n");
 133
 134                 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
 135                 if (!(usbcfg & GUSBCFG_PHYSEL)) {
 136                         usbcfg |= GUSBCFG_PHYSEL;
 137                         dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
 138
 139                         /* Reset after a PHY select */
 140                         retval = dwc2_core_reset_and_force_dr_mode(hsotg);
 141
 142                         if (retval) {
 143                                 dev_err(hsotg->dev,
 144                                         "%s: Reset failed, aborting", __func__);
 145                                 return retval;
 146                         }
 147                 }
 148         }
 149
 150         /*
 151          * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also
 152          * do this on HNP Dev/Host mode switches (done in dev_init and
 153          * host_init).
 154          */
 155         if (dwc2_is_host_mode(hsotg))
 156                 dwc2_init_fs_ls_pclk_sel(hsotg);
 157
 158         if (hsotg->params.i2c_enable) {
 159                 dev_dbg(hsotg->dev, "FS PHY enabling I2C\n");
 160
 161                 /* Program GUSBCFG.OtgUtmiFsSel to I2C */
 162                 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
 163                 usbcfg |= GUSBCFG_OTG_UTMI_FS_SEL;
 164                 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
 165
 166                 /* Program GI2CCTL.I2CEn */
 167                 i2cctl = dwc2_readl(hsotg->regs + GI2CCTL);
 168                 i2cctl &= ~GI2CCTL_I2CDEVADDR_MASK;
 169                 i2cctl |= 1 << GI2CCTL_I2CDEVADDR_SHIFT;
 170                 i2cctl &= ~GI2CCTL_I2CEN;
 171                 dwc2_writel(i2cctl, hsotg->regs + GI2CCTL);
 172                 i2cctl |= GI2CCTL_I2CEN;
 173                 dwc2_writel(i2cctl, hsotg->regs + GI2CCTL);
 174         }
 175
 176         return retval;
 177 }
 178
 179 static int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
 180 {
 181         u32 usbcfg, usbcfg_old;
 182         int retval = 0;
 183
 184         if (!select_phy)
 185                 return 0;
 186
 187         usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
 188         usbcfg_old = usbcfg;
 189
 190         /*
 191          * HS PHY parameters. These parameters are preserved during soft reset
 192          * so only program the first time. Do a soft reset immediately after
 193          * setting phyif.
 194          */
 195         switch (hsotg->params.phy_type) {
 196         case DWC2_PHY_TYPE_PARAM_ULPI:
 197                 /* ULPI interface */
 198                 dev_dbg(hsotg->dev, "HS ULPI PHY selected\n");
 199                 usbcfg |= GUSBCFG_ULPI_UTMI_SEL;
 200                 usbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL);
 201                 if (hsotg->params.phy_ulpi_ddr)
 202                         usbcfg |= GUSBCFG_DDRSEL;
 203                 break;
 204         case DWC2_PHY_TYPE_PARAM_UTMI:
 205                 /* UTMI+ interface */
 206                 dev_dbg(hsotg->dev, "HS UTMI+ PHY selected\n");
 207                 usbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16);
 208                 if (hsotg->params.phy_utmi_width == 16)
 209                         usbcfg |= GUSBCFG_PHYIF16;
 210                 break;
 211         default:
 212                 dev_err(hsotg->dev, "FS PHY selected at HS!\n");
 213                 break;
 214         }
 215
 216         if (usbcfg != usbcfg_old) {
 217                 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
 218
 219                 /* Reset after setting the PHY parameters */
 220                 retval = dwc2_core_reset_and_force_dr_mode(hsotg);
 221                 if (retval) {
 222                         dev_err(hsotg->dev,
 223                                 "%s: Reset failed, aborting", __func__);
 224                         return retval;
 225                 }
 226         }
 227
 228         return retval;
 229 }
 230
 231 static int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
 232 {
 233         u32 usbcfg;
 234         int retval = 0;
 235
 236         if ((hsotg->params.speed == DWC2_SPEED_PARAM_FULL ||
 237              hsotg->params.speed == DWC2_SPEED_PARAM_LOW) &&
 238             hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) {
 239                 /* If FS/LS mode with FS/LS PHY */
 240                 retval = dwc2_fs_phy_init(hsotg, select_phy);
 241                 if (retval)
 242                         return retval;
 243         } else {
 244                 /* High speed PHY */
 245                 retval = dwc2_hs_phy_init(hsotg, select_phy);
 246                 if (retval)
 247                         return retval;
 248         }
 249
 250         if (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
 251             hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
 252             hsotg->params.ulpi_fs_ls) {
 253                 dev_dbg(hsotg->dev, "Setting ULPI FSLS\n");
 254                 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
 255                 usbcfg |= GUSBCFG_ULPI_FS_LS;
 256                 usbcfg |= GUSBCFG_ULPI_CLK_SUSP_M;
 257                 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
 258         } else {
 259                 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
 260                 usbcfg &= ~GUSBCFG_ULPI_FS_LS;
 261                 usbcfg &= ~GUSBCFG_ULPI_CLK_SUSP_M;
 262                 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
 263         }
 264
 265         return retval;
 266 }
 267
 268 static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg)
 269 {
 270         u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
 271
 272         switch (hsotg->hw_params.arch) {
 273         case GHWCFG2_EXT_DMA_ARCH:
 274                 dev_err(hsotg->dev, "External DMA Mode not supported\n");
 275                 return -EINVAL;
 276
 277         case GHWCFG2_INT_DMA_ARCH:
 278                 dev_dbg(hsotg->dev, "Internal DMA Mode\n");
 279                 if (hsotg->params.ahbcfg != -1) {
 280                         ahbcfg &= GAHBCFG_CTRL_MASK;
 281                         ahbcfg |= hsotg->params.ahbcfg &
 282                                   ~GAHBCFG_CTRL_MASK;
 283                 }
 284                 break;
 285
 286         case GHWCFG2_SLAVE_ONLY_ARCH:
 287         default:
 288                 dev_dbg(hsotg->dev, "Slave Only Mode\n");
 289                 break;
 290         }
 291
 292         dev_dbg(hsotg->dev, "host_dma:%d dma_desc_enable:%d\n",
 293                 hsotg->params.host_dma,
 294                 hsotg->params.dma_desc_enable);
 295
 296         if (hsotg->params.host_dma) {
 297                 if (hsotg->params.dma_desc_enable)
 298                         dev_dbg(hsotg->dev, "Using Descriptor DMA mode\n");
 299                 else
 300                         dev_dbg(hsotg->dev, "Using Buffer DMA mode\n");
 301         } else {
 302                 dev_dbg(hsotg->dev, "Using Slave mode\n");
 303                 hsotg->params.dma_desc_enable = false;
 304         }
 305
 306         if (hsotg->params.host_dma)
 307                 ahbcfg |= GAHBCFG_DMA_EN;
 308
 309         dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
 310
 311         return 0;
 312 }
 313
 314 static void dwc2_gusbcfg_init(struct dwc2_hsotg *hsotg)
 315 {
 316         u32 usbcfg;
 317
 318         usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
 319         usbcfg &= ~(GUSBCFG_HNPCAP | GUSBCFG_SRPCAP);
 320
 321         switch (hsotg->hw_params.op_mode) {
 322         case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
 323                 if (hsotg->params.otg_cap ==
 324                                 DWC2_CAP_PARAM_HNP_SRP_CAPABLE)
 325                         usbcfg |= GUSBCFG_HNPCAP;
 326                 if (hsotg->params.otg_cap !=
 327                                 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE)
 328                         usbcfg |= GUSBCFG_SRPCAP;
 329                 break;
 330
 331         case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
 332         case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
 333         case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
 334                 if (hsotg->params.otg_cap !=
 335                                 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE)
 336                         usbcfg |= GUSBCFG_SRPCAP;
 337                 break;
 338
 339         case GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE:
 340         case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE:
 341         case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST:
 342         default:
 343                 break;
 344         }
 345
 346         dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
 347 }
 348
 349 /**
 350  * dwc2_enable_host_interrupts() - Enables the Host mode interrupts
 351  *
 352  * @hsotg: Programming view of DWC_otg controller
 353  */
 354 static void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg)
 355 {
 356         u32 intmsk;
 357
 358         dev_dbg(hsotg->dev, "%s()\n", __func__);
 359
 360         /* Disable all interrupts */
 361         dwc2_writel(0, hsotg->regs + GINTMSK);
 362         dwc2_writel(0, hsotg->regs + HAINTMSK);
 363
 364         /* Enable the common interrupts */
 365         dwc2_enable_common_interrupts(hsotg);
 366
 367         /* Enable host mode interrupts without disturbing common interrupts */
 368         intmsk = dwc2_readl(hsotg->regs + GINTMSK);
 369         intmsk |= GINTSTS_DISCONNINT | GINTSTS_PRTINT | GINTSTS_HCHINT;
 370         dwc2_writel(intmsk, hsotg->regs + GINTMSK);
 371 }
 372
 373 /**
 374  * dwc2_disable_host_interrupts() - Disables the Host Mode interrupts
 375  *
 376  * @hsotg: Programming view of DWC_otg controller
 377  */
 378 static void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg)
 379 {
 380         u32 intmsk = dwc2_readl(hsotg->regs + GINTMSK);
 381
 382         /* Disable host mode interrupts without disturbing common interrupts */
 383         intmsk &= ~(GINTSTS_SOF | GINTSTS_PRTINT | GINTSTS_HCHINT |
 384                     GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP | GINTSTS_DISCONNINT);
 385         dwc2_writel(intmsk, hsotg->regs + GINTMSK);
 386 }
 387
 388 /*
 389  * dwc2_calculate_dynamic_fifo() - Calculates the default fifo size
 390  * For system that have a total fifo depth that is smaller than the default
 391  * RX + TX fifo size.
 392  *
 393  * @hsotg: Programming view of DWC_otg controller
 394  */
 395 static void dwc2_calculate_dynamic_fifo(struct dwc2_hsotg *hsotg)
 396 {
 397         struct dwc2_core_params *params = &hsotg->params;
 398         struct dwc2_hw_params *hw = &hsotg->hw_params;
 399         u32 rxfsiz, nptxfsiz, ptxfsiz, total_fifo_size;
 400
 401         total_fifo_size = hw->total_fifo_size;
 402         rxfsiz = params->host_rx_fifo_size;
 403         nptxfsiz = params->host_nperio_tx_fifo_size;
 404         ptxfsiz = params->host_perio_tx_fifo_size;
 405
 406         /*
 407          * Will use Method 2 defined in the DWC2 spec: minimum FIFO depth
 408          * allocation with support for high bandwidth endpoints. Synopsys
 409          * defines MPS(Max Packet size) for a periodic EP=1024, and for
 410          * non-periodic as 512.
 411          */
 412         if (total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz)) {
 413                 /*
 414                  * For Buffer DMA mode/Scatter Gather DMA mode
 415                  * 2 * ((Largest Packet size / 4) + 1 + 1) + n
 416                  * with n = number of host channel.
 417                  * 2 * ((1024/4) + 2) = 516
 418                  */
 419                 rxfsiz = 516 + hw->host_channels;
 420
 421                 /*
 422                  * min non-periodic tx fifo depth
 423                  * 2 * (largest non-periodic USB packet used / 4)
 424                  * 2 * (512/4) = 256
 425                  */
 426                 nptxfsiz = 256;
 427
 428                 /*
 429                  * min periodic tx fifo depth
 430                  * (largest packet size*MC)/4
 431                  * (1024 * 3)/4 = 768
 432                  */
 433                 ptxfsiz = 768;
 434
 435                 params->host_rx_fifo_size = rxfsiz;
 436                 params->host_nperio_tx_fifo_size = nptxfsiz;
 437                 params->host_perio_tx_fifo_size = ptxfsiz;
 438         }
 439
 440         /*
 441          * If the summation of RX, NPTX and PTX fifo sizes is still
 442          * bigger than the total_fifo_size, then we have a problem.
 443          *
 444          * We won't be able to allocate as many endpoints. Right now,
 445          * we're just printing an error message, but ideally this FIFO
 446          * allocation algorithm would be improved in the future.
 447          *
 448          * FIXME improve this FIFO allocation algorithm.
 449          */
 450         if (unlikely(total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz)))
 451                 dev_err(hsotg->dev, "invalid fifo sizes\n");
 452 }
 453
 454 static void dwc2_config_fifos(struct dwc2_hsotg *hsotg)
 455 {
 456         struct dwc2_core_params *params = &hsotg->params;
 457         u32 nptxfsiz, hptxfsiz, dfifocfg, grxfsiz;
 458
 459         if (!params->enable_dynamic_fifo)
 460                 return;
 461
 462         dwc2_calculate_dynamic_fifo(hsotg);
 463
 464         /* Rx FIFO */
 465         grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ);
 466         dev_dbg(hsotg->dev, "initial grxfsiz=%08x\n", grxfsiz);
 467         grxfsiz &= ~GRXFSIZ_DEPTH_MASK;
 468         grxfsiz |= params->host_rx_fifo_size <<
 469                    GRXFSIZ_DEPTH_SHIFT & GRXFSIZ_DEPTH_MASK;
 470         dwc2_writel(grxfsiz, hsotg->regs + GRXFSIZ);
 471         dev_dbg(hsotg->dev, "new grxfsiz=%08x\n",
 472                 dwc2_readl(hsotg->regs + GRXFSIZ));
 473
 474         /* Non-periodic Tx FIFO */
 475         dev_dbg(hsotg->dev, "initial gnptxfsiz=%08x\n",
 476                 dwc2_readl(hsotg->regs + GNPTXFSIZ));
 477         nptxfsiz = params->host_nperio_tx_fifo_size <<
 478                    FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK;
 479         nptxfsiz |= params->host_rx_fifo_size <<
 480                     FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK;
 481         dwc2_writel(nptxfsiz, hsotg->regs + GNPTXFSIZ);
 482         dev_dbg(hsotg->dev, "new gnptxfsiz=%08x\n",
 483                 dwc2_readl(hsotg->regs + GNPTXFSIZ));
 484
 485         /* Periodic Tx FIFO */
 486         dev_dbg(hsotg->dev, "initial hptxfsiz=%08x\n",
 487                 dwc2_readl(hsotg->regs + HPTXFSIZ));
 488         hptxfsiz = params->host_perio_tx_fifo_size <<
 489                    FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK;
 490         hptxfsiz |= (params->host_rx_fifo_size +
 491                      params->host_nperio_tx_fifo_size) <<
 492                     FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK;
 493         dwc2_writel(hptxfsiz, hsotg->regs + HPTXFSIZ);
 494         dev_dbg(hsotg->dev, "new hptxfsiz=%08x\n",
 495                 dwc2_readl(hsotg->regs + HPTXFSIZ));
 496
 497         if (hsotg->params.en_multiple_tx_fifo &&
 498             hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_91a) {
 499                 /*
 500                  * This feature was implemented in 2.91a version
 501                  * Global DFIFOCFG calculation for Host mode -
 502                  * include RxFIFO, NPTXFIFO and HPTXFIFO
 503                  */
 504                 dfifocfg = dwc2_readl(hsotg->regs + GDFIFOCFG);
 505                 dfifocfg &= ~GDFIFOCFG_EPINFOBASE_MASK;
 506                 dfifocfg |= (params->host_rx_fifo_size +
 507                              params->host_nperio_tx_fifo_size +
 508                              params->host_perio_tx_fifo_size) <<
 509                             GDFIFOCFG_EPINFOBASE_SHIFT &
 510                             GDFIFOCFG_EPINFOBASE_MASK;
 511                 dwc2_writel(dfifocfg, hsotg->regs + GDFIFOCFG);
 512         }
 513 }
 514
 515 /**
 516  * dwc2_calc_frame_interval() - Calculates the correct frame Interval value for
 517  * the HFIR register according to PHY type and speed
 518  *
 519  * @hsotg: Programming view of DWC_otg controller
 520  *
 521  * NOTE: The caller can modify the value of the HFIR register only after the
 522  * Port Enable bit of the Host Port Control and Status register (HPRT.EnaPort)
 523  * has been set
 524  */
 525 u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg)
 526 {
 527         u32 usbcfg;
 528         u32 hprt0;
 529         int clock = 60; /* default value */
 530
 531         usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
 532         hprt0 = dwc2_readl(hsotg->regs + HPRT0);
 533
 534         if (!(usbcfg & GUSBCFG_PHYSEL) && (usbcfg & GUSBCFG_ULPI_UTMI_SEL) &&
 535             !(usbcfg & GUSBCFG_PHYIF16))
 536                 clock = 60;
 537         if ((usbcfg & GUSBCFG_PHYSEL) && hsotg->hw_params.fs_phy_type ==
 538             GHWCFG2_FS_PHY_TYPE_SHARED_ULPI)
 539                 clock = 48;
 540         if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
 541             !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16))
 542                 clock = 30;
 543         if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
 544             !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && !(usbcfg & GUSBCFG_PHYIF16))
 545                 clock = 60;
 546         if ((usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
 547             !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16))
 548                 clock = 48;
 549         if ((usbcfg & GUSBCFG_PHYSEL) && !(usbcfg & GUSBCFG_PHYIF16) &&
 550             hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_SHARED_UTMI)
 551                 clock = 48;
 552         if ((usbcfg & GUSBCFG_PHYSEL) &&
 553             hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED)
 554                 clock = 48;
 555
 556         if ((hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT == HPRT0_SPD_HIGH_SPEED)
 557                 /* High speed case */
 558                 return 125 * clock - 1;
 559
 560         /* FS/LS case */
 561         return 1000 * clock - 1;
 562 }
 563
 564 /**
 565  * dwc2_read_packet() - Reads a packet from the Rx FIFO into the destination
 566  * buffer
 567  *
 568  * @core_if: Programming view of DWC_otg controller
 569  * @dest:    Destination buffer for the packet
 570  * @bytes:   Number of bytes to copy to the destination
 571  */
 572 void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes)
 573 {
 574         u32 __iomem *fifo = hsotg->regs + HCFIFO(0);
 575         u32 *data_buf = (u32 *)dest;
 576         int word_count = (bytes + 3) / 4;
 577         int i;
 578
 579         /*
 580          * Todo: Account for the case where dest is not dword aligned. This
 581          * requires reading data from the FIFO into a u32 temp buffer, then
 582          * moving it into the data buffer.
 583          */
 584
 585         dev_vdbg(hsotg->dev, "%s(%p,%p,%d)\n", __func__, hsotg, dest, bytes);
 586
 587         for (i = 0; i < word_count; i++, data_buf++)
 588                 *data_buf = dwc2_readl(fifo);
 589 }
 590
 591 /**
 592  * dwc2_dump_channel_info() - Prints the state of a host channel
 593  *
 594  * @hsotg: Programming view of DWC_otg controller
 595  * @chan:  Pointer to the channel to dump
 596  *
 597  * Must be called with interrupt disabled and spinlock held
 598  *
 599  * NOTE: This function will be removed once the peripheral controller code
 600  * is integrated and the driver is stable
 601  */
 602 static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg,
 603                                    struct dwc2_host_chan *chan)
 604 {
 605 #ifdef VERBOSE_DEBUG
 606         int num_channels = hsotg->params.host_channels;
 607         struct dwc2_qh *qh;
 608         u32 hcchar;
 609         u32 hcsplt;
 610         u32 hctsiz;
 611         u32 hc_dma;
 612         int i;
 613
 614         if (!chan)
 615                 return;
 616
 617         hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
 618         hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num));
 619         hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chan->hc_num));
 620         hc_dma = dwc2_readl(hsotg->regs + HCDMA(chan->hc_num));
 621
 622         dev_dbg(hsotg->dev, "  Assigned to channel %p:\n", chan);
 623         dev_dbg(hsotg->dev, "    hcchar 0x%08x, hcsplt 0x%08x\n",
 624                 hcchar, hcsplt);
 625         dev_dbg(hsotg->dev, "    hctsiz 0x%08x, hc_dma 0x%08x\n",
 626                 hctsiz, hc_dma);
 627         dev_dbg(hsotg->dev, "    dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
 628                 chan->dev_addr, chan->ep_num, chan->ep_is_in);
 629         dev_dbg(hsotg->dev, "    ep_type: %d\n", chan->ep_type);
 630         dev_dbg(hsotg->dev, "    max_packet: %d\n", chan->max_packet);
 631         dev_dbg(hsotg->dev, "    data_pid_start: %d\n", chan->data_pid_start);
 632         dev_dbg(hsotg->dev, "    xfer_started: %d\n", chan->xfer_started);
 633         dev_dbg(hsotg->dev, "    halt_status: %d\n", chan->halt_status);
 634         dev_dbg(hsotg->dev, "    xfer_buf: %p\n", chan->xfer_buf);
 635         dev_dbg(hsotg->dev, "    xfer_dma: %08lx\n",
 636                 (unsigned long)chan->xfer_dma);
 637         dev_dbg(hsotg->dev, "    xfer_len: %d\n", chan->xfer_len);
 638         dev_dbg(hsotg->dev, "    qh: %p\n", chan->qh);
 639         dev_dbg(hsotg->dev, "  NP inactive sched:\n");
 640         list_for_each_entry(qh, &hsotg->non_periodic_sched_inactive,
 641                             qh_list_entry)
 642                 dev_dbg(hsotg->dev, "    %p\n", qh);
 643         dev_dbg(hsotg->dev, "  NP active sched:\n");
 644         list_for_each_entry(qh, &hsotg->non_periodic_sched_active,
 645                             qh_list_entry)
 646                 dev_dbg(hsotg->dev, "    %p\n", qh);
 647         dev_dbg(hsotg->dev, "  Channels:\n");
 648         for (i = 0; i < num_channels; i++) {
 649                 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
 650
 651                 dev_dbg(hsotg->dev, "    %2d: %p\n", i, chan);
 652         }
 653 #endif /* VERBOSE_DEBUG */
 654 }
 655
 656 static int _dwc2_hcd_start(struct usb_hcd *hcd);
 657
 658 static void dwc2_host_start(struct dwc2_hsotg *hsotg)
 659 {
 660         struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
 661
 662         hcd->self.is_b_host = dwc2_hcd_is_b_host(hsotg);
 663         _dwc2_hcd_start(hcd);
 664 }
 665
 666 static void dwc2_host_disconnect(struct dwc2_hsotg *hsotg)
 667 {
 668         struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
 669
 670         hcd->self.is_b_host = 0;
 671 }
 672
 673 static void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context,
 674                                int *hub_addr, int *hub_port)
 675 {
 676         struct urb *urb = context;
 677
 678         if (urb->dev->tt)
 679                 *hub_addr = urb->dev->tt->hub->devnum;
 680         else
 681                 *hub_addr = 0;
 682         *hub_port = urb->dev->ttport;
 683 }
 684
 685 /*
 686  * =========================================================================
 687  *  Low Level Host Channel Access Functions
 688  * =========================================================================
 689  */
 690
 691 static void dwc2_hc_enable_slave_ints(struct dwc2_hsotg *hsotg,
 692                                       struct dwc2_host_chan *chan)
 693 {
 694         u32 hcintmsk = HCINTMSK_CHHLTD;
 695
 696         switch (chan->ep_type) {
 697         case USB_ENDPOINT_XFER_CONTROL:
 698         case USB_ENDPOINT_XFER_BULK:
 699                 dev_vdbg(hsotg->dev, "control/bulk\n");
 700                 hcintmsk |= HCINTMSK_XFERCOMPL;
 701                 hcintmsk |= HCINTMSK_STALL;
 702                 hcintmsk |= HCINTMSK_XACTERR;
 703                 hcintmsk |= HCINTMSK_DATATGLERR;
 704                 if (chan->ep_is_in) {
 705                         hcintmsk |= HCINTMSK_BBLERR;
 706                 } else {
 707                         hcintmsk |= HCINTMSK_NAK;
 708                         hcintmsk |= HCINTMSK_NYET;
 709                         if (chan->do_ping)
 710                                 hcintmsk |= HCINTMSK_ACK;
 711                 }
 712
 713                 if (chan->do_split) {
 714                         hcintmsk |= HCINTMSK_NAK;
 715                         if (chan->complete_split)
 716                                 hcintmsk |= HCINTMSK_NYET;
 717                         else
 718                                 hcintmsk |= HCINTMSK_ACK;
 719                 }
 720
 721                 if (chan->error_state)
 722                         hcintmsk |= HCINTMSK_ACK;
 723                 break;
 724
 725         case USB_ENDPOINT_XFER_INT:
 726                 if (dbg_perio())
 727                         dev_vdbg(hsotg->dev, "intr\n");
 728                 hcintmsk |= HCINTMSK_XFERCOMPL;
 729                 hcintmsk |= HCINTMSK_NAK;
 730                 hcintmsk |= HCINTMSK_STALL;
 731                 hcintmsk |= HCINTMSK_XACTERR;
 732                 hcintmsk |= HCINTMSK_DATATGLERR;
 733                 hcintmsk |= HCINTMSK_FRMOVRUN;
 734
 735                 if (chan->ep_is_in)
 736                         hcintmsk |= HCINTMSK_BBLERR;
 737                 if (chan->error_state)
 738                         hcintmsk |= HCINTMSK_ACK;
 739                 if (chan->do_split) {
 740                         if (chan->complete_split)
 741                                 hcintmsk |= HCINTMSK_NYET;
 742                         else
 743                                 hcintmsk |= HCINTMSK_ACK;
 744                 }
 745                 break;
 746
 747         case USB_ENDPOINT_XFER_ISOC:
 748                 if (dbg_perio())
 749                         dev_vdbg(hsotg->dev, "isoc\n");
 750                 hcintmsk |= HCINTMSK_XFERCOMPL;
 751                 hcintmsk |= HCINTMSK_FRMOVRUN;
 752                 hcintmsk |= HCINTMSK_ACK;
 753
 754                 if (chan->ep_is_in) {
 755                         hcintmsk |= HCINTMSK_XACTERR;
 756                         hcintmsk |= HCINTMSK_BBLERR;
 757                 }
 758                 break;
 759         default:
 760                 dev_err(hsotg->dev, "## Unknown EP type ##\n");
 761                 break;
 762         }
 763
 764         dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
 765         if (dbg_hc(chan))
 766                 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);
 767 }
 768
 769 static void dwc2_hc_enable_dma_ints(struct dwc2_hsotg *hsotg,
 770                                     struct dwc2_host_chan *chan)
 771 {
 772         u32 hcintmsk = HCINTMSK_CHHLTD;
 773
 774         /*
 775          * For Descriptor DMA mode core halts the channel on AHB error.
 776          * Interrupt is not required.
 777          */
 778         if (!hsotg->params.dma_desc_enable) {
 779                 if (dbg_hc(chan))
 780                         dev_vdbg(hsotg->dev, "desc DMA disabled\n");
 781                 hcintmsk |= HCINTMSK_AHBERR;
 782         } else {
 783                 if (dbg_hc(chan))
 784                         dev_vdbg(hsotg->dev, "desc DMA enabled\n");
 785                 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
 786                         hcintmsk |= HCINTMSK_XFERCOMPL;
 787         }
 788
 789         if (chan->error_state && !chan->do_split &&
 790             chan->ep_type != USB_ENDPOINT_XFER_ISOC) {
 791                 if (dbg_hc(chan))
 792                         dev_vdbg(hsotg->dev, "setting ACK\n");
 793                 hcintmsk |= HCINTMSK_ACK;
 794                 if (chan->ep_is_in) {
 795                         hcintmsk |= HCINTMSK_DATATGLERR;
 796                         if (chan->ep_type != USB_ENDPOINT_XFER_INT)
 797                                 hcintmsk |= HCINTMSK_NAK;
 798                 }
 799         }
 800
 801         dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
 802         if (dbg_hc(chan))
 803                 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);
 804 }
 805
 806 static void dwc2_hc_enable_ints(struct dwc2_hsotg *hsotg,
 807                                 struct dwc2_host_chan *chan)
 808 {
 809         u32 intmsk;
 810
 811         if (hsotg->params.host_dma) {
 812                 if (dbg_hc(chan))
 813                         dev_vdbg(hsotg->dev, "DMA enabled\n");
 814                 dwc2_hc_enable_dma_ints(hsotg, chan);
 815         } else {
 816                 if (dbg_hc(chan))
 817                         dev_vdbg(hsotg->dev, "DMA disabled\n");
 818                 dwc2_hc_enable_slave_ints(hsotg, chan);
 819         }
 820
 821         /* Enable the top level host channel interrupt */
 822         intmsk = dwc2_readl(hsotg->regs + HAINTMSK);
 823         intmsk |= 1 << chan->hc_num;
 824         dwc2_writel(intmsk, hsotg->regs + HAINTMSK);
 825         if (dbg_hc(chan))
 826                 dev_vdbg(hsotg->dev, "set HAINTMSK to %08x\n", intmsk);
 827
 828         /* Make sure host channel interrupts are enabled */
 829         intmsk = dwc2_readl(hsotg->regs + GINTMSK);
 830         intmsk |= GINTSTS_HCHINT;
 831         dwc2_writel(intmsk, hsotg->regs + GINTMSK);
 832         if (dbg_hc(chan))
 833                 dev_vdbg(hsotg->dev, "set GINTMSK to %08x\n", intmsk);
 834 }
 835
 836 /**
 837  * dwc2_hc_init() - Prepares a host channel for transferring packets to/from
 838  * a specific endpoint
 839  *
 840  * @hsotg: Programming view of DWC_otg controller
 841  * @chan:  Information needed to initialize the host channel
 842  *
 843  * The HCCHARn register is set up with the characteristics specified in chan.
 844  * Host channel interrupts that may need to be serviced while this transfer is
 845  * in progress are enabled.
 846  */
 847 static void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
 848 {
 849         u8 hc_num = chan->hc_num;
 850         u32 hcintmsk;
 851         u32 hcchar;
 852         u32 hcsplt = 0;
 853
 854         if (dbg_hc(chan))
 855                 dev_vdbg(hsotg->dev, "%s()\n", __func__);
 856
 857         /* Clear old interrupt conditions for this host channel */
 858         hcintmsk = 0xffffffff;
 859         hcintmsk &= ~HCINTMSK_RESERVED14_31;
 860         dwc2_writel(hcintmsk, hsotg->regs + HCINT(hc_num));
 861
 862         /* Enable channel interrupts required for this transfer */
 863         dwc2_hc_enable_ints(hsotg, chan);
 864
 865         /*
 866          * Program the HCCHARn register with the endpoint characteristics for
 867          * the current transfer
 868          */
 869         hcchar = chan->dev_addr << HCCHAR_DEVADDR_SHIFT & HCCHAR_DEVADDR_MASK;
 870         hcchar |= chan->ep_num << HCCHAR_EPNUM_SHIFT & HCCHAR_EPNUM_MASK;
 871         if (chan->ep_is_in)
 872                 hcchar |= HCCHAR_EPDIR;
 873         if (chan->speed == USB_SPEED_LOW)
 874                 hcchar |= HCCHAR_LSPDDEV;
 875         hcchar |= chan->ep_type << HCCHAR_EPTYPE_SHIFT & HCCHAR_EPTYPE_MASK;
 876         hcchar |= chan->max_packet << HCCHAR_MPS_SHIFT & HCCHAR_MPS_MASK;
 877         dwc2_writel(hcchar, hsotg->regs + HCCHAR(hc_num));
 878         if (dbg_hc(chan)) {
 879                 dev_vdbg(hsotg->dev, "set HCCHAR(%d) to %08x\n",
 880                          hc_num, hcchar);
 881
 882                 dev_vdbg(hsotg->dev, "%s: Channel %d\n",
 883                          __func__, hc_num);
 884                 dev_vdbg(hsotg->dev, "   Dev Addr: %d\n",
 885                          chan->dev_addr);
 886                 dev_vdbg(hsotg->dev, "   Ep Num: %d\n",
 887                          chan->ep_num);
 888                 dev_vdbg(hsotg->dev, "   Is In: %d\n",
 889                          chan->ep_is_in);
 890                 dev_vdbg(hsotg->dev, "   Is Low Speed: %d\n",
 891                          chan->speed == USB_SPEED_LOW);
 892                 dev_vdbg(hsotg->dev, "   Ep Type: %d\n",
 893                          chan->ep_type);
 894                 dev_vdbg(hsotg->dev, "   Max Pkt: %d\n",
 895                          chan->max_packet);
 896         }
 897
 898         /* Program the HCSPLT register for SPLITs */
 899         if (chan->do_split) {
 900                 if (dbg_hc(chan))
 901                         dev_vdbg(hsotg->dev,
 902                                  "Programming HC %d with split --> %s\n",
 903                                  hc_num,
 904                                  chan->complete_split ? "CSPLIT" : "SSPLIT");
 905                 if (chan->complete_split)
 906                         hcsplt |= HCSPLT_COMPSPLT;
 907                 hcsplt |= chan->xact_pos << HCSPLT_XACTPOS_SHIFT &
 908                           HCSPLT_XACTPOS_MASK;
 909                 hcsplt |= chan->hub_addr << HCSPLT_HUBADDR_SHIFT &
 910                           HCSPLT_HUBADDR_MASK;
 911                 hcsplt |= chan->hub_port << HCSPLT_PRTADDR_SHIFT &
 912                           HCSPLT_PRTADDR_MASK;
 913                 if (dbg_hc(chan)) {
 914                         dev_vdbg(hsotg->dev, "    comp split %d\n",
 915                                  chan->complete_split);
 916                         dev_vdbg(hsotg->dev, "    xact pos %d\n",
 917                                  chan->xact_pos);
 918                         dev_vdbg(hsotg->dev, "    hub addr %d\n",
 919                                  chan->hub_addr);
 920                         dev_vdbg(hsotg->dev, "    hub port %d\n",
 921                                  chan->hub_port);
 922                         dev_vdbg(hsotg->dev, "    is_in %d\n",
 923                                  chan->ep_is_in);
 924                         dev_vdbg(hsotg->dev, "    Max Pkt %d\n",
 925                                  chan->max_packet);
 926                         dev_vdbg(hsotg->dev, "    xferlen %d\n",
 927                                  chan->xfer_len);
 928                 }
 929         }
 930
 931         dwc2_writel(hcsplt, hsotg->regs + HCSPLT(hc_num));
 932 }
 933
 934 /**
 935  * dwc2_hc_halt() - Attempts to halt a host channel
 936  *
 937  * @hsotg:       Controller register interface
 938  * @chan:        Host channel to halt
 939  * @halt_status: Reason for halting the channel
 940  *
 941  * This function should only be called in Slave mode or to abort a transfer in
 942  * either Slave mode or DMA mode. Under normal circumstances in DMA mode, the
 943  * controller halts the channel when the transfer is complete or a condition
 944  * occurs that requires application intervention.
 945  *
 946  * In slave mode, checks for a free request queue entry, then sets the Channel
 947  * Enable and Channel Disable bits of the Host Channel Characteristics
 948  * register of the specified channel to intiate the halt. If there is no free
 949  * request queue entry, sets only the Channel Disable bit of the HCCHARn
 950  * register to flush requests for this channel. In the latter case, sets a
 951  * flag to indicate that the host channel needs to be halted when a request
 952  * queue slot is open.
 953  *
 954  * In DMA mode, always sets the Channel Enable and Channel Disable bits of the
 955  * HCCHARn register. The controller ensures there is space in the request
 956  * queue before submitting the halt request.
 957  *
 958  * Some time may elapse before the core flushes any posted requests for this
 959  * host channel and halts. The Channel Halted interrupt handler completes the
 960  * deactivation of the host channel.
 961  */
 962 void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
 963                   enum dwc2_halt_status halt_status)
 964 {
 965         u32 nptxsts, hptxsts, hcchar;
 966
 967         if (dbg_hc(chan))
 968                 dev_vdbg(hsotg->dev, "%s()\n", __func__);
 969         if (halt_status == DWC2_HC_XFER_NO_HALT_STATUS)
 970                 dev_err(hsotg->dev, "!!! halt_status = %d !!!\n", halt_status);
 971
 972         if (halt_status == DWC2_HC_XFER_URB_DEQUEUE ||
 973             halt_status == DWC2_HC_XFER_AHB_ERR) {
 974                 /*
 975                  * Disable all channel interrupts except Ch Halted. The QTD
 976                  * and QH state associated with this transfer has been cleared
 977                  * (in the case of URB_DEQUEUE), so the channel needs to be
 978                  * shut down carefully to prevent crashes.
 979                  */
 980                 u32 hcintmsk = HCINTMSK_CHHLTD;
 981
 982                 dev_vdbg(hsotg->dev, "dequeue/error\n");
 983                 dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
 984
 985                 /*
 986                  * Make sure no other interrupts besides halt are currently
 987                  * pending. Handling another interrupt could cause a crash due
 988                  * to the QTD and QH state.
 989                  */
 990                 dwc2_writel(~hcintmsk, hsotg->regs + HCINT(chan->hc_num));
 991
 992                 /*
 993                  * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR
 994                  * even if the channel was already halted for some other
 995                  * reason
 996                  */
 997                 chan->halt_status = halt_status;
 998
 999                 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1000                 if (!(hcchar & HCCHAR_CHENA)) {
1001                         /*
1002                          * The channel is either already halted or it hasn't
1003                          * started yet. In DMA mode, the transfer may halt if
1004                          * it finishes normally or a condition occurs that
1005                          * requires driver intervention. Don't want to halt
1006                          * the channel again. In either Slave or DMA mode,
1007                          * it's possible that the transfer has been assigned
1008                          * to a channel, but not started yet when an URB is
1009                          * dequeued. Don't want to halt a channel that hasn't
1010                          * started yet.
1011                          */
1012                         return;
1013                 }
1014         }
1015         if (chan->halt_pending) {
1016                 /*
1017                  * A halt has already been issued for this channel. This might
1018                  * happen when a transfer is aborted by a higher level in
1019                  * the stack.
1020                  */
1021                 dev_vdbg(hsotg->dev,
1022                          "*** %s: Channel %d, chan->halt_pending already set ***\n",
1023                          __func__, chan->hc_num);
1024                 return;
1025         }
1026
1027         hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1028
1029         /* No need to set the bit in DDMA for disabling the channel */
1030         /* TODO check it everywhere channel is disabled */
1031         if (!hsotg->params.dma_desc_enable) {
1032                 if (dbg_hc(chan))
1033                         dev_vdbg(hsotg->dev, "desc DMA disabled\n");
1034                 hcchar |= HCCHAR_CHENA;
1035         } else {
1036                 if (dbg_hc(chan))
1037                         dev_dbg(hsotg->dev, "desc DMA enabled\n");
1038         }
1039         hcchar |= HCCHAR_CHDIS;
1040
1041         if (!hsotg->params.host_dma) {
1042                 if (dbg_hc(chan))
1043                         dev_vdbg(hsotg->dev, "DMA not enabled\n");
1044                 hcchar |= HCCHAR_CHENA;
1045
1046                 /* Check for space in the request queue to issue the halt */
1047                 if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL ||
1048                     chan->ep_type == USB_ENDPOINT_XFER_BULK) {
1049                         dev_vdbg(hsotg->dev, "control/bulk\n");
1050                         nptxsts = dwc2_readl(hsotg->regs + GNPTXSTS);
1051                         if ((nptxsts & TXSTS_QSPCAVAIL_MASK) == 0) {
1052                                 dev_vdbg(hsotg->dev, "Disabling channel\n");
1053                                 hcchar &= ~HCCHAR_CHENA;
1054                         }
1055                 } else {
1056                         if (dbg_perio())
1057                                 dev_vdbg(hsotg->dev, "isoc/intr\n");
1058                         hptxsts = dwc2_readl(hsotg->regs + HPTXSTS);
1059                         if ((hptxsts & TXSTS_QSPCAVAIL_MASK) == 0 ||
1060                             hsotg->queuing_high_bandwidth) {
1061                                 if (dbg_perio())
1062                                         dev_vdbg(hsotg->dev, "Disabling channel\n");
1063                                 hcchar &= ~HCCHAR_CHENA;
1064                         }
1065                 }
1066         } else {
1067                 if (dbg_hc(chan))
1068                         dev_vdbg(hsotg->dev, "DMA enabled\n");
1069         }
1070
1071         dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1072         chan->halt_status = halt_status;
1073
1074         if (hcchar & HCCHAR_CHENA) {
1075                 if (dbg_hc(chan))
1076                         dev_vdbg(hsotg->dev, "Channel enabled\n");
1077                 chan->halt_pending = 1;
1078                 chan->halt_on_queue = 0;
1079         } else {
1080                 if (dbg_hc(chan))
1081                         dev_vdbg(hsotg->dev, "Channel disabled\n");
1082                 chan->halt_on_queue = 1;
1083         }
1084
1085         if (dbg_hc(chan)) {
1086                 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1087                          chan->hc_num);
1088                 dev_vdbg(hsotg->dev, "   hcchar: 0x%08x\n",
1089                          hcchar);
1090                 dev_vdbg(hsotg->dev, "   halt_pending: %d\n",
1091                          chan->halt_pending);
1092                 dev_vdbg(hsotg->dev, "   halt_on_queue: %d\n",
1093                          chan->halt_on_queue);
1094                 dev_vdbg(hsotg->dev, "   halt_status: %d\n",
1095                          chan->halt_status);
1096         }
1097 }
1098
1099 /**
1100  * dwc2_hc_cleanup() - Clears the transfer state for a host channel
1101  *
1102  * @hsotg: Programming view of DWC_otg controller
1103  * @chan:  Identifies the host channel to clean up
1104  *
1105  * This function is normally called after a transfer is done and the host
1106  * channel is being released
1107  */
1108 void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
1109 {
1110         u32 hcintmsk;
1111
1112         chan->xfer_started = 0;
1113
1114         list_del_init(&chan->split_order_list_entry);
1115
1116         /*
1117          * Clear channel interrupt enables and any unhandled channel interrupt
1118          * conditions
1119          */
1120         dwc2_writel(0, hsotg->regs + HCINTMSK(chan->hc_num));
1121         hcintmsk = 0xffffffff;
1122         hcintmsk &= ~HCINTMSK_RESERVED14_31;
1123         dwc2_writel(hcintmsk, hsotg->regs + HCINT(chan->hc_num));
1124 }
1125
1126 /**
1127  * dwc2_hc_set_even_odd_frame() - Sets the channel property that indicates in
1128  * which frame a periodic transfer should occur
1129  *
1130  * @hsotg:  Programming view of DWC_otg controller
1131  * @chan:   Identifies the host channel to set up and its properties
1132  * @hcchar: Current value of the HCCHAR register for the specified host channel
1133  *
1134  * This function has no effect on non-periodic transfers
1135  */
1136 static void dwc2_hc_set_even_odd_frame(struct dwc2_hsotg *hsotg,
1137                                        struct dwc2_host_chan *chan, u32 *hcchar)
1138 {
1139         if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1140             chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1141                 int host_speed;
1142                 int xfer_ns;
1143                 int xfer_us;
1144                 int bytes_in_fifo;
1145                 u16 fifo_space;
1146                 u16 frame_number;
1147                 u16 wire_frame;
1148
1149                 /*
1150                  * Try to figure out if we're an even or odd frame. If we set
1151                  * even and the current frame number is even the the transfer
1152                  * will happen immediately.  Similar if both are odd. If one is
1153                  * even and the other is odd then the transfer will happen when
1154                  * the frame number ticks.
1155                  *
1156                  * There's a bit of a balancing act to get this right.
1157                  * Sometimes we may want to send data in the current frame (AK
1158                  * right away).  We might want to do this if the frame number
1159                  * _just_ ticked, but we might also want to do this in order
1160                  * to continue a split transaction that happened late in a
1161                  * microframe (so we didn't know to queue the next transfer
1162                  * until the frame number had ticked).  The problem is that we
1163                  * need a lot of knowledge to know if there's actually still
1164                  * time to send things or if it would be better to wait until
1165                  * the next frame.
1166                  *
1167                  * We can look at how much time is left in the current frame
1168                  * and make a guess about whether we'll have time to transfer.
1169                  * We'll do that.
1170                  */
1171
1172                 /* Get speed host is running at */
1173                 host_speed = (chan->speed != USB_SPEED_HIGH &&
1174                               !chan->do_split) ? chan->speed : USB_SPEED_HIGH;
1175
1176                 /* See how many bytes are in the periodic FIFO right now */
1177                 fifo_space = (dwc2_readl(hsotg->regs + HPTXSTS) &
1178                               TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT;
1179                 bytes_in_fifo = sizeof(u32) *
1180                                 (hsotg->params.host_perio_tx_fifo_size -
1181                                  fifo_space);
1182
1183                 /*
1184                  * Roughly estimate bus time for everything in the periodic
1185                  * queue + our new transfer.  This is "rough" because we're
1186                  * using a function that makes takes into account IN/OUT
1187                  * and INT/ISO and we're just slamming in one value for all
1188                  * transfers.  This should be an over-estimate and that should
1189                  * be OK, but we can probably tighten it.
1190                  */
1191                 xfer_ns = usb_calc_bus_time(host_speed, false, false,
1192                                             chan->xfer_len + bytes_in_fifo);
1193                 xfer_us = NS_TO_US(xfer_ns);
1194
1195                 /* See what frame number we'll be at by the time we finish */
1196                 frame_number = dwc2_hcd_get_future_frame_number(hsotg, xfer_us);
1197
1198                 /* This is when we were scheduled to be on the wire */
1199                 wire_frame = dwc2_frame_num_inc(chan->qh->next_active_frame, 1);
1200
1201                 /*
1202                  * If we'd finish _after_ the frame we're scheduled in then
1203                  * it's hopeless.  Just schedule right away and hope for the
1204                  * best.  Note that it _might_ be wise to call back into the
1205                  * scheduler to pick a better frame, but this is better than
1206                  * nothing.
1207                  */
1208                 if (dwc2_frame_num_gt(frame_number, wire_frame)) {
1209                         dwc2_sch_vdbg(hsotg,
1210                                       "QH=%p EO MISS fr=%04x=>%04x (%+d)\n",
1211                                       chan->qh, wire_frame, frame_number,
1212                                       dwc2_frame_num_dec(frame_number,
1213                                                          wire_frame));
1214                         wire_frame = frame_number;
1215
1216                         /*
1217                          * We picked a different frame number; communicate this
1218                          * back to the scheduler so it doesn't try to schedule
1219                          * another in the same frame.
1220                          *
1221                          * Remember that next_active_frame is 1 before the wire
1222                          * frame.
1223                          */
1224                         chan->qh->next_active_frame =
1225                                 dwc2_frame_num_dec(frame_number, 1);
1226                 }
1227
1228                 if (wire_frame & 1)
1229                         *hcchar |= HCCHAR_ODDFRM;
1230                 else
1231                         *hcchar &= ~HCCHAR_ODDFRM;
1232         }
1233 }
1234
1235 static void dwc2_set_pid_isoc(struct dwc2_host_chan *chan)
1236 {
1237         /* Set up the initial PID for the transfer */
1238         if (chan->speed == USB_SPEED_HIGH) {
1239                 if (chan->ep_is_in) {
1240                         if (chan->multi_count == 1)
1241                                 chan->data_pid_start = DWC2_HC_PID_DATA0;
1242                         else if (chan->multi_count == 2)
1243                                 chan->data_pid_start = DWC2_HC_PID_DATA1;
1244                         else
1245                                 chan->data_pid_start = DWC2_HC_PID_DATA2;
1246                 } else {
1247                         if (chan->multi_count == 1)
1248                                 chan->data_pid_start = DWC2_HC_PID_DATA0;
1249                         else
1250                                 chan->data_pid_start = DWC2_HC_PID_MDATA;
1251                 }
1252         } else {
1253                 chan->data_pid_start = DWC2_HC_PID_DATA0;
1254         }
1255 }
1256
1257 /**
1258  * dwc2_hc_write_packet() - Writes a packet into the Tx FIFO associated with
1259  * the Host Channel
1260  *
1261  * @hsotg: Programming view of DWC_otg controller
1262  * @chan:  Information needed to initialize the host channel
1263  *
1264  * This function should only be called in Slave mode. For a channel associated
1265  * with a non-periodic EP, the non-periodic Tx FIFO is written. For a channel
1266  * associated with a periodic EP, the periodic Tx FIFO is written.
1267  *
1268  * Upon return the xfer_buf and xfer_count fields in chan are incremented by
1269  * the number of bytes written to the Tx FIFO.
1270  */
1271 static void dwc2_hc_write_packet(struct dwc2_hsotg *hsotg,
1272                                  struct dwc2_host_chan *chan)
1273 {
1274         u32 i;
1275         u32 remaining_count;
1276         u32 byte_count;
1277         u32 dword_count;
1278         u32 __iomem *data_fifo;
1279         u32 *data_buf = (u32 *)chan->xfer_buf;
1280
1281         if (dbg_hc(chan))
1282                 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1283
1284         data_fifo = (u32 __iomem *)(hsotg->regs + HCFIFO(chan->hc_num));
1285
1286         remaining_count = chan->xfer_len - chan->xfer_count;
1287         if (remaining_count > chan->max_packet)
1288                 byte_count = chan->max_packet;
1289         else
1290                 byte_count = remaining_count;
1291
1292         dword_count = (byte_count + 3) / 4;
1293
1294         if (((unsigned long)data_buf & 0x3) == 0) {
1295                 /* xfer_buf is DWORD aligned */
1296                 for (i = 0; i < dword_count; i++, data_buf++)
1297                         dwc2_writel(*data_buf, data_fifo);
1298         } else {
1299                 /* xfer_buf is not DWORD aligned */
1300                 for (i = 0; i < dword_count; i++, data_buf++) {
1301                         u32 data = data_buf[0] | data_buf[1] << 8 |
1302                                    data_buf[2] << 16 | data_buf[3] << 24;
1303                         dwc2_writel(data, data_fifo);
1304                 }
1305         }
1306
1307         chan->xfer_count += byte_count;
1308         chan->xfer_buf += byte_count;
1309 }
1310
1311 /**
1312  * dwc2_hc_do_ping() - Starts a PING transfer
1313  *
1314  * @hsotg: Programming view of DWC_otg controller
1315  * @chan:  Information needed to initialize the host channel
1316  *
1317  * This function should only be called in Slave mode. The Do Ping bit is set in
1318  * the HCTSIZ register, then the channel is enabled.
1319  */
1320 static void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg,
1321                             struct dwc2_host_chan *chan)
1322 {
1323         u32 hcchar;
1324         u32 hctsiz;
1325
1326         if (dbg_hc(chan))
1327                 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1328                          chan->hc_num);
1329
1330         hctsiz = TSIZ_DOPNG;
1331         hctsiz |= 1 << TSIZ_PKTCNT_SHIFT;
1332         dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
1333
1334         hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1335         hcchar |= HCCHAR_CHENA;
1336         hcchar &= ~HCCHAR_CHDIS;
1337         dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1338 }
1339
1340 /**
1341  * dwc2_hc_start_transfer() - Does the setup for a data transfer for a host
1342  * channel and starts the transfer
1343  *
1344  * @hsotg: Programming view of DWC_otg controller
1345  * @chan:  Information needed to initialize the host channel. The xfer_len value
1346  *         may be reduced to accommodate the max widths of the XferSize and
1347  *         PktCnt fields in the HCTSIZn register. The multi_count value may be
1348  *         changed to reflect the final xfer_len value.
1349  *
1350  * This function may be called in either Slave mode or DMA mode. In Slave mode,
1351  * the caller must ensure that there is sufficient space in the request queue
1352  * and Tx Data FIFO.
1353  *
1354  * For an OUT transfer in Slave mode, it loads a data packet into the
1355  * appropriate FIFO. If necessary, additional data packets are loaded in the
1356  * Host ISR.
1357  *
1358  * For an IN transfer in Slave mode, a data packet is requested. The data
1359  * packets are unloaded from the Rx FIFO in the Host ISR. If necessary,
1360  * additional data packets are requested in the Host ISR.
1361  *
1362  * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ
1363  * register along with a packet count of 1 and the channel is enabled. This
1364  * causes a single PING transaction to occur. Other fields in HCTSIZ are
1365  * simply set to 0 since no data transfer occurs in this case.
1366  *
1367  * For a PING transfer in DMA mode, the HCTSIZ register is initialized with
1368  * all the information required to perform the subsequent data transfer. In
1369  * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the
1370  * controller performs the entire PING protocol, then starts the data
1371  * transfer.
1372  */
1373 static void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg,
1374                                    struct dwc2_host_chan *chan)
1375 {
1376         u32 max_hc_xfer_size = hsotg->params.max_transfer_size;
1377         u16 max_hc_pkt_count = hsotg->params.max_packet_count;
1378         u32 hcchar;
1379         u32 hctsiz = 0;
1380         u16 num_packets;
1381         u32 ec_mc;
1382
1383         if (dbg_hc(chan))
1384                 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1385
1386         if (chan->do_ping) {
1387                 if (!hsotg->params.host_dma) {
1388                         if (dbg_hc(chan))
1389                                 dev_vdbg(hsotg->dev, "ping, no DMA\n");
1390                         dwc2_hc_do_ping(hsotg, chan);
1391                         chan->xfer_started = 1;
1392                         return;
1393                 }
1394
1395                 if (dbg_hc(chan))
1396                         dev_vdbg(hsotg->dev, "ping, DMA\n");
1397
1398                 hctsiz |= TSIZ_DOPNG;
1399         }
1400
1401         if (chan->do_split) {
1402                 if (dbg_hc(chan))
1403                         dev_vdbg(hsotg->dev, "split\n");
1404                 num_packets = 1;
1405
1406                 if (chan->complete_split && !chan->ep_is_in)
1407                         /*
1408                          * For CSPLIT OUT Transfer, set the size to 0 so the
1409                          * core doesn't expect any data written to the FIFO
1410                          */
1411                         chan->xfer_len = 0;
1412                 else if (chan->ep_is_in || chan->xfer_len > chan->max_packet)
1413                         chan->xfer_len = chan->max_packet;
1414                 else if (!chan->ep_is_in && chan->xfer_len > 188)
1415                         chan->xfer_len = 188;
1416
1417                 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT &
1418                           TSIZ_XFERSIZE_MASK;
1419
1420                 /* For split set ec_mc for immediate retries */
1421                 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1422                     chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1423                         ec_mc = 3;
1424                 else
1425                         ec_mc = 1;
1426         } else {
1427                 if (dbg_hc(chan))
1428                         dev_vdbg(hsotg->dev, "no split\n");
1429                 /*
1430                  * Ensure that the transfer length and packet count will fit
1431                  * in the widths allocated for them in the HCTSIZn register
1432                  */
1433                 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1434                     chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1435                         /*
1436                          * Make sure the transfer size is no larger than one
1437                          * (micro)frame's worth of data. (A check was done
1438                          * when the periodic transfer was accepted to ensure
1439                          * that a (micro)frame's worth of data can be
1440                          * programmed into a channel.)
1441                          */
1442                         u32 max_periodic_len =
1443                                 chan->multi_count * chan->max_packet;
1444
1445                         if (chan->xfer_len > max_periodic_len)
1446                                 chan->xfer_len = max_periodic_len;
1447                 } else if (chan->xfer_len > max_hc_xfer_size) {
1448                         /*
1449                          * Make sure that xfer_len is a multiple of max packet
1450                          * size
1451                          */
1452                         chan->xfer_len =
1453                                 max_hc_xfer_size - chan->max_packet + 1;
1454                 }
1455
1456                 if (chan->xfer_len > 0) {
1457                         num_packets = (chan->xfer_len + chan->max_packet - 1) /
1458                                         chan->max_packet;
1459                         if (num_packets > max_hc_pkt_count) {
1460                                 num_packets = max_hc_pkt_count;
1461                                 chan->xfer_len = num_packets * chan->max_packet;
1462                         }
1463                 } else {
1464                         /* Need 1 packet for transfer length of 0 */
1465                         num_packets = 1;
1466                 }
1467
1468                 if (chan->ep_is_in)
1469                         /*
1470                          * Always program an integral # of max packets for IN
1471                          * transfers
1472                          */
1473                         chan->xfer_len = num_packets * chan->max_packet;
1474
1475                 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1476                     chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1477                         /*
1478                          * Make sure that the multi_count field matches the
1479                          * actual transfer length
1480                          */
1481                         chan->multi_count = num_packets;
1482
1483                 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1484                         dwc2_set_pid_isoc(chan);
1485
1486                 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT &
1487                           TSIZ_XFERSIZE_MASK;
1488
1489                 /* The ec_mc gets the multi_count for non-split */
1490                 ec_mc = chan->multi_count;
1491         }
1492
1493         chan->start_pkt_count = num_packets;
1494         hctsiz |= num_packets << TSIZ_PKTCNT_SHIFT & TSIZ_PKTCNT_MASK;
1495         hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT &
1496                   TSIZ_SC_MC_PID_MASK;
1497         dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
1498         if (dbg_hc(chan)) {
1499                 dev_vdbg(hsotg->dev, "Wrote %08x to HCTSIZ(%d)\n",
1500                          hctsiz, chan->hc_num);
1501
1502                 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1503                          chan->hc_num);
1504                 dev_vdbg(hsotg->dev, "   Xfer Size: %d\n",
1505                          (hctsiz & TSIZ_XFERSIZE_MASK) >>
1506                          TSIZ_XFERSIZE_SHIFT);
1507                 dev_vdbg(hsotg->dev, "   Num Pkts: %d\n",
1508                          (hctsiz & TSIZ_PKTCNT_MASK) >>
1509                          TSIZ_PKTCNT_SHIFT);
1510                 dev_vdbg(hsotg->dev, "   Start PID: %d\n",
1511                          (hctsiz & TSIZ_SC_MC_PID_MASK) >>
1512                          TSIZ_SC_MC_PID_SHIFT);
1513         }
1514
1515         if (hsotg->params.host_dma) {
1516                 dwc2_writel((u32)chan->xfer_dma,
1517                             hsotg->regs + HCDMA(chan->hc_num));
1518                 if (dbg_hc(chan))
1519                         dev_vdbg(hsotg->dev, "Wrote %08lx to HCDMA(%d)\n",
1520                                  (unsigned long)chan->xfer_dma, chan->hc_num);
1521         }
1522
1523         /* Start the split */
1524         if (chan->do_split) {
1525                 u32 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num));
1526
1527                 hcsplt |= HCSPLT_SPLTENA;
1528                 dwc2_writel(hcsplt, hsotg->regs + HCSPLT(chan->hc_num));
1529         }
1530
1531         hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1532         hcchar &= ~HCCHAR_MULTICNT_MASK;
1533         hcchar |= (ec_mc << HCCHAR_MULTICNT_SHIFT) & HCCHAR_MULTICNT_MASK;
1534         dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar);
1535
1536         if (hcchar & HCCHAR_CHDIS)
1537                 dev_warn(hsotg->dev,
1538                          "%s: chdis set, channel %d, hcchar 0x%08x\n",
1539                          __func__, chan->hc_num, hcchar);
1540
1541         /* Set host channel enable after all other setup is complete */
1542         hcchar |= HCCHAR_CHENA;
1543         hcchar &= ~HCCHAR_CHDIS;
1544
1545         if (dbg_hc(chan))
1546                 dev_vdbg(hsotg->dev, "   Multi Cnt: %d\n",
1547                          (hcchar & HCCHAR_MULTICNT_MASK) >>
1548                          HCCHAR_MULTICNT_SHIFT);
1549
1550         dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1551         if (dbg_hc(chan))
1552                 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,
1553                          chan->hc_num);
1554
1555         chan->xfer_started = 1;
1556         chan->requests++;
1557
1558         if (!hsotg->params.host_dma &&
1559             !chan->ep_is_in && chan->xfer_len > 0)
1560                 /* Load OUT packet into the appropriate Tx FIFO */
1561                 dwc2_hc_write_packet(hsotg, chan);
1562 }
1563
1564 /**
1565  * dwc2_hc_start_transfer_ddma() - Does the setup for a data transfer for a
1566  * host channel and starts the transfer in Descriptor DMA mode
1567  *
1568  * @hsotg: Programming view of DWC_otg controller
1569  * @chan:  Information needed to initialize the host channel
1570  *
1571  * Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set.
1572  * Sets PID and NTD values. For periodic transfers initializes SCHED_INFO field
1573  * with micro-frame bitmap.
1574  *
1575  * Initializes HCDMA register with descriptor list address and CTD value then
1576  * starts the transfer via enabling the channel.
1577  */
1578 void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg,
1579                                  struct dwc2_host_chan *chan)
1580 {
1581         u32 hcchar;
1582         u32 hctsiz = 0;
1583
1584         if (chan->do_ping)
1585                 hctsiz |= TSIZ_DOPNG;
1586
1587         if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1588                 dwc2_set_pid_isoc(chan);
1589
1590         /* Packet Count and Xfer Size are not used in Descriptor DMA mode */
1591         hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT &
1592                   TSIZ_SC_MC_PID_MASK;
1593
1594         /* 0 - 1 descriptor, 1 - 2 descriptors, etc */
1595         hctsiz |= (chan->ntd - 1) << TSIZ_NTD_SHIFT & TSIZ_NTD_MASK;
1596
1597         /* Non-zero only for high-speed interrupt endpoints */
1598         hctsiz |= chan->schinfo << TSIZ_SCHINFO_SHIFT & TSIZ_SCHINFO_MASK;
1599
1600         if (dbg_hc(chan)) {
1601                 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1602                          chan->hc_num);
1603                 dev_vdbg(hsotg->dev, "   Start PID: %d\n",
1604                          chan->data_pid_start);
1605                 dev_vdbg(hsotg->dev, "   NTD: %d\n", chan->ntd - 1);
1606         }
1607
1608         dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
1609
1610         dma_sync_single_for_device(hsotg->dev, chan->desc_list_addr,
1611                                    chan->desc_list_sz, DMA_TO_DEVICE);
1612
1613         dwc2_writel(chan->desc_list_addr, hsotg->regs + HCDMA(chan->hc_num));
1614
1615         if (dbg_hc(chan))
1616                 dev_vdbg(hsotg->dev, "Wrote %pad to HCDMA(%d)\n",
1617                          &chan->desc_list_addr, chan->hc_num);
1618
1619         hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1620         hcchar &= ~HCCHAR_MULTICNT_MASK;
1621         hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT &
1622                   HCCHAR_MULTICNT_MASK;
1623
1624         if (hcchar & HCCHAR_CHDIS)
1625                 dev_warn(hsotg->dev,
1626                          "%s: chdis set, channel %d, hcchar 0x%08x\n",
1627                          __func__, chan->hc_num, hcchar);
1628
1629         /* Set host channel enable after all other setup is complete */
1630         hcchar |= HCCHAR_CHENA;
1631         hcchar &= ~HCCHAR_CHDIS;
1632
1633         if (dbg_hc(chan))
1634                 dev_vdbg(hsotg->dev, "   Multi Cnt: %d\n",
1635                          (hcchar & HCCHAR_MULTICNT_MASK) >>
1636                          HCCHAR_MULTICNT_SHIFT);
1637
1638         dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1639         if (dbg_hc(chan))
1640                 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,
1641                          chan->hc_num);
1642
1643         chan->xfer_started = 1;
1644         chan->requests++;
1645 }
1646
1647 /**
1648  * dwc2_hc_continue_transfer() - Continues a data transfer that was started by
1649  * a previous call to dwc2_hc_start_transfer()
1650  *
1651  * @hsotg: Programming view of DWC_otg controller
1652  * @chan:  Information needed to initialize the host channel
1653  *
1654  * The caller must ensure there is sufficient space in the request queue and Tx
1655  * Data FIFO. This function should only be called in Slave mode. In DMA mode,
1656  * the controller acts autonomously to complete transfers programmed to a host
1657  * channel.
1658  *
1659  * For an OUT transfer, a new data packet is loaded into the appropriate FIFO
1660  * if there is any data remaining to be queued. For an IN transfer, another
1661  * data packet is always requested. For the SETUP phase of a control transfer,
1662  * this function does nothing.
1663  *
1664  * Return: 1 if a new request is queued, 0 if no more requests are required
1665  * for this transfer
1666  */
1667 static int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg,
1668                                      struct dwc2_host_chan *chan)
1669 {
1670         if (dbg_hc(chan))
1671                 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1672                          chan->hc_num);
1673
1674         if (chan->do_split)
1675                 /* SPLITs always queue just once per channel */
1676                 return 0;
1677
1678         if (chan->data_pid_start == DWC2_HC_PID_SETUP)
1679                 /* SETUPs are queued only once since they can't be NAK'd */
1680                 return 0;
1681
1682         if (chan->ep_is_in) {
1683                 /*
1684                  * Always queue another request for other IN transfers. If
1685                  * back-to-back INs are issued and NAKs are received for both,
1686                  * the driver may still be processing the first NAK when the
1687                  * second NAK is received. When the interrupt handler clears
1688                  * the NAK interrupt for the first NAK, the second NAK will
1689                  * not be seen. So we can't depend on the NAK interrupt
1690                  * handler to requeue a NAK'd request. Instead, IN requests
1691                  * are issued each time this function is called. When the
1692                  * transfer completes, the extra requests for the channel will
1693                  * be flushed.
1694                  */
1695                 u32 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1696
1697                 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar);
1698                 hcchar |= HCCHAR_CHENA;
1699                 hcchar &= ~HCCHAR_CHDIS;
1700                 if (dbg_hc(chan))
1701                         dev_vdbg(hsotg->dev, "   IN xfer: hcchar = 0x%08x\n",
1702                                  hcchar);
1703                 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1704                 chan->requests++;
1705                 return 1;
1706         }
1707
1708         /* OUT transfers */
1709
1710         if (chan->xfer_count < chan->xfer_len) {
1711                 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1712                     chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1713                         u32 hcchar = dwc2_readl(hsotg->regs +
1714                                                 HCCHAR(chan->hc_num));
1715
1716                         dwc2_hc_set_even_odd_frame(hsotg, chan,
1717                                                    &hcchar);
1718                 }
1719
1720                 /* Load OUT packet into the appropriate Tx FIFO */
1721                 dwc2_hc_write_packet(hsotg, chan);
1722                 chan->requests++;
1723                 return 1;
1724         }
1725
1726         return 0;
1727 }
1728
1729 /*
1730  * =========================================================================
1731  *  HCD
1732  * =========================================================================
1733  */
1734
1735 /*
1736  * Processes all the URBs in a single list of QHs. Completes them with
1737  * -ETIMEDOUT and frees the QTD.
1738  *
1739  * Must be called with interrupt disabled and spinlock held
1740  */
1741 static void dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg *hsotg,
1742                                       struct list_head *qh_list)
1743 {
1744         struct dwc2_qh *qh, *qh_tmp;
1745         struct dwc2_qtd *qtd, *qtd_tmp;
1746
1747         list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) {
1748                 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list,
1749                                          qtd_list_entry) {
1750                         dwc2_host_complete(hsotg, qtd, -ECONNRESET);
1751                         dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
1752                 }
1753         }
1754 }
1755
1756 static void dwc2_qh_list_free(struct dwc2_hsotg *hsotg,
1757                               struct list_head *qh_list)
1758 {
1759         struct dwc2_qtd *qtd, *qtd_tmp;
1760         struct dwc2_qh *qh, *qh_tmp;
1761         unsigned long flags;
1762
1763         if (!qh_list->next)
1764                 /* The list hasn't been initialized yet */
1765                 return;
1766
1767         spin_lock_irqsave(&hsotg->lock, flags);
1768
1769         /* Ensure there are no QTDs or URBs left */
1770         dwc2_kill_urbs_in_qh_list(hsotg, qh_list);
1771
1772         list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) {
1773                 dwc2_hcd_qh_unlink(hsotg, qh);
1774
1775                 /* Free each QTD in the QH's QTD list */
1776                 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list,
1777                                          qtd_list_entry)
1778                         dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
1779
1780                 if (qh->channel && qh->channel->qh == qh)
1781                         qh->channel->qh = NULL;
1782
1783                 spin_unlock_irqrestore(&hsotg->lock, flags);
1784                 dwc2_hcd_qh_free(hsotg, qh);
1785                 spin_lock_irqsave(&hsotg->lock, flags);
1786         }
1787
1788         spin_unlock_irqrestore(&hsotg->lock, flags);
1789 }
1790
1791 /*
1792  * Responds with an error status of -ETIMEDOUT to all URBs in the non-periodic
1793  * and periodic schedules. The QTD associated with each URB is removed from
1794  * the schedule and freed. This function may be called when a disconnect is
1795  * detected or when the HCD is being stopped.
1796  *
1797  * Must be called with interrupt disabled and spinlock held
1798  */
1799 static void dwc2_kill_all_urbs(struct dwc2_hsotg *hsotg)
1800 {
1801         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_inactive);
1802         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_active);
1803         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_inactive);
1804         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_ready);
1805         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_assigned);
1806         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_queued);
1807 }
1808
1809 /**
1810  * dwc2_hcd_start() - Starts the HCD when switching to Host mode
1811  *
1812  * @hsotg: Pointer to struct dwc2_hsotg
1813  */
1814 void dwc2_hcd_start(struct dwc2_hsotg *hsotg)
1815 {
1816         u32 hprt0;
1817
1818         if (hsotg->op_state == OTG_STATE_B_HOST) {
1819                 /*
1820                  * Reset the port. During a HNP mode switch the reset
1821                  * needs to occur within 1ms and have a duration of at
1822                  * least 50ms.
1823                  */
1824                 hprt0 = dwc2_read_hprt0(hsotg);
1825                 hprt0 |= HPRT0_RST;
1826                 dwc2_writel(hprt0, hsotg->regs + HPRT0);
1827         }
1828
1829         queue_delayed_work(hsotg->wq_otg, &hsotg->start_work,
1830                            msecs_to_jiffies(50));
1831 }
1832
1833 /* Must be called with interrupt disabled and spinlock held */
1834 static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg)
1835 {
1836         int num_channels = hsotg->params.host_channels;
1837         struct dwc2_host_chan *channel;
1838         u32 hcchar;
1839         int i;
1840
1841         if (!hsotg->params.host_dma) {
1842                 /* Flush out any channel requests in slave mode */
1843                 for (i = 0; i < num_channels; i++) {
1844                         channel = hsotg->hc_ptr_array[i];
1845                         if (!list_empty(&channel->hc_list_entry))
1846                                 continue;
1847                         hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
1848                         if (hcchar & HCCHAR_CHENA) {
1849                                 hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR);
1850                                 hcchar |= HCCHAR_CHDIS;
1851                                 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
1852                         }
1853                 }
1854         }
1855
1856         for (i = 0; i < num_channels; i++) {
1857                 channel = hsotg->hc_ptr_array[i];
1858                 if (!list_empty(&channel->hc_list_entry))
1859                         continue;
1860                 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
1861                 if (hcchar & HCCHAR_CHENA) {
1862                         /* Halt the channel */
1863                         hcchar |= HCCHAR_CHDIS;
1864                         dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
1865                 }
1866
1867                 dwc2_hc_cleanup(hsotg, channel);
1868                 list_add_tail(&channel->hc_list_entry, &hsotg->free_hc_list);
1869                 /*
1870                  * Added for Descriptor DMA to prevent channel double cleanup in
1871                  * release_channel_ddma(), which is called from ep_disable when
1872                  * device disconnects
1873                  */
1874                 channel->qh = NULL;
1875         }
1876         /* All channels have been freed, mark them available */
1877         if (hsotg->params.uframe_sched) {
1878                 hsotg->available_host_channels =
1879                         hsotg->params.host_channels;
1880         } else {
1881                 hsotg->non_periodic_channels = 0;
1882                 hsotg->periodic_channels = 0;
1883         }
1884 }
1885
1886 /**
1887  * dwc2_hcd_connect() - Handles connect of the HCD
1888  *
1889  * @hsotg: Pointer to struct dwc2_hsotg
1890  *
1891  * Must be called with interrupt disabled and spinlock held
1892  */
1893 void dwc2_hcd_connect(struct dwc2_hsotg *hsotg)
1894 {
1895         if (hsotg->lx_state != DWC2_L0)
1896                 usb_hcd_resume_root_hub(hsotg->priv);
1897
1898         hsotg->flags.b.port_connect_status_change = 1;
1899         hsotg->flags.b.port_connect_status = 1;
1900 }
1901
1902 /**
1903  * dwc2_hcd_disconnect() - Handles disconnect of the HCD
1904  *
1905  * @hsotg: Pointer to struct dwc2_hsotg
1906  * @force: If true, we won't try to reconnect even if we see device connected.
1907  *
1908  * Must be called with interrupt disabled and spinlock held
1909  */
1910 void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force)
1911 {
1912         u32 intr;
1913         u32 hprt0;
1914
1915         /* Set status flags for the hub driver */
1916         hsotg->flags.b.port_connect_status_change = 1;
1917         hsotg->flags.b.port_connect_status = 0;
1918
1919         /*
1920          * Shutdown any transfers in process by clearing the Tx FIFO Empty
1921          * interrupt mask and status bits and disabling subsequent host
1922          * channel interrupts.
1923          */
1924         intr = dwc2_readl(hsotg->regs + GINTMSK);
1925         intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT);
1926         dwc2_writel(intr, hsotg->regs + GINTMSK);
1927         intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT;
1928         dwc2_writel(intr, hsotg->regs + GINTSTS);
1929
1930         /*
1931          * Turn off the vbus power only if the core has transitioned to device
1932          * mode. If still in host mode, need to keep power on to detect a
1933          * reconnection.
1934          */
1935         if (dwc2_is_device_mode(hsotg)) {
1936                 if (hsotg->op_state != OTG_STATE_A_SUSPEND) {
1937                         dev_dbg(hsotg->dev, "Disconnect: PortPower off\n");
1938                         dwc2_writel(0, hsotg->regs + HPRT0);
1939                 }
1940
1941                 dwc2_disable_host_interrupts(hsotg);
1942         }
1943
1944         /* Respond with an error status to all URBs in the schedule */
1945         dwc2_kill_all_urbs(hsotg);
1946
1947         if (dwc2_is_host_mode(hsotg))
1948                 /* Clean up any host channels that were in use */
1949                 dwc2_hcd_cleanup_channels(hsotg);
1950
1951         dwc2_host_disconnect(hsotg);
1952
1953         /*
1954          * Add an extra check here to see if we're actually connected but
1955          * we don't have a detection interrupt pending.  This can happen if:
1956          *   1. hardware sees connect
1957          *   2. hardware sees disconnect
1958          *   3. hardware sees connect
1959          *   4. dwc2_port_intr() - clears connect interrupt
1960          *   5. dwc2_handle_common_intr() - calls here
1961          *
1962          * Without the extra check here we will end calling disconnect
1963          * and won't get any future interrupts to handle the connect.
1964          */
1965         if (!force) {
1966                 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
1967                 if (!(hprt0 & HPRT0_CONNDET) && (hprt0 & HPRT0_CONNSTS))
1968                         dwc2_hcd_connect(hsotg);
1969         }
1970 }
1971
1972 /**
1973  * dwc2_hcd_rem_wakeup() - Handles Remote Wakeup
1974  *
1975  * @hsotg: Pointer to struct dwc2_hsotg
1976  */
1977 static void dwc2_hcd_rem_wakeup(struct dwc2_hsotg *hsotg)
1978 {
1979         if (hsotg->bus_suspended) {
1980                 hsotg->flags.b.port_suspend_change = 1;
1981                 usb_hcd_resume_root_hub(hsotg->priv);
1982         }
1983
1984         if (hsotg->lx_state == DWC2_L1)
1985                 hsotg->flags.b.port_l1_change = 1;
1986 }
1987
1988 /**
1989  * dwc2_hcd_stop() - Halts the DWC_otg host mode operations in a clean manner
1990  *
1991  * @hsotg: Pointer to struct dwc2_hsotg
1992  *
1993  * Must be called with interrupt disabled and spinlock held
1994  */
1995 void dwc2_hcd_stop(struct dwc2_hsotg *hsotg)
1996 {
1997         dev_dbg(hsotg->dev, "DWC OTG HCD STOP\n");
1998
1999         /*
2000          * The root hub should be disconnected before this function is called.
2001          * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
2002          * and the QH lists (via ..._hcd_endpoint_disable).
2003          */
2004
2005         /* Turn off all host-specific interrupts */
2006         dwc2_disable_host_interrupts(hsotg);
2007
2008         /* Turn off the vbus power */
2009         dev_dbg(hsotg->dev, "PortPower off\n");
2010         dwc2_writel(0, hsotg->regs + HPRT0);
2011 }
2012
2013 /* Caller must hold driver lock */
2014 static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg,
2015                                 struct dwc2_hcd_urb *urb, struct dwc2_qh *qh,
2016                                 struct dwc2_qtd *qtd)
2017 {
2018         u32 intr_mask;
2019         int retval;
2020         int dev_speed;
2021
2022         if (!hsotg->flags.b.port_connect_status) {
2023                 /* No longer connected */
2024                 dev_err(hsotg->dev, "Not connected\n");
2025                 return -ENODEV;
2026         }
2027
2028         dev_speed = dwc2_host_get_speed(hsotg, urb->priv);
2029
2030         /* Some configurations cannot support LS traffic on a FS root port */
2031         if ((dev_speed == USB_SPEED_LOW) &&
2032             (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) &&
2033             (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) {
2034                 u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
2035                 u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
2036
2037                 if (prtspd == HPRT0_SPD_FULL_SPEED)
2038                         return -ENODEV;
2039         }
2040
2041         if (!qtd)
2042                 return -EINVAL;
2043
2044         dwc2_hcd_qtd_init(qtd, urb);
2045         retval = dwc2_hcd_qtd_add(hsotg, qtd, qh);
2046         if (retval) {
2047                 dev_err(hsotg->dev,
2048                         "DWC OTG HCD URB Enqueue failed adding QTD. Error status %d\n",
2049                         retval);
2050                 return retval;
2051         }
2052
2053         intr_mask = dwc2_readl(hsotg->regs + GINTMSK);
2054         if (!(intr_mask & GINTSTS_SOF)) {
2055                 enum dwc2_transaction_type tr_type;
2056
2057                 if (qtd->qh->ep_type == USB_ENDPOINT_XFER_BULK &&
2058                     !(qtd->urb->flags & URB_GIVEBACK_ASAP))
2059                         /*
2060                          * Do not schedule SG transactions until qtd has
2061                          * URB_GIVEBACK_ASAP set
2062                          */
2063                         return 0;
2064
2065                 tr_type = dwc2_hcd_select_transactions(hsotg);
2066                 if (tr_type != DWC2_TRANSACTION_NONE)
2067                         dwc2_hcd_queue_transactions(hsotg, tr_type);
2068         }
2069
2070         return 0;
2071 }
2072
2073 /* Must be called with interrupt disabled and spinlock held */
2074 static int dwc2_hcd_urb_dequeue(struct dwc2_hsotg *hsotg,
2075                                 struct dwc2_hcd_urb *urb)
2076 {
2077         struct dwc2_qh *qh;
2078         struct dwc2_qtd *urb_qtd;
2079
2080         urb_qtd = urb->qtd;
2081         if (!urb_qtd) {
2082                 dev_dbg(hsotg->dev, "## Urb QTD is NULL ##\n");
2083                 return -EINVAL;
2084         }
2085
2086         qh = urb_qtd->qh;
2087         if (!qh) {
2088                 dev_dbg(hsotg->dev, "## Urb QTD QH is NULL ##\n");
2089                 return -EINVAL;
2090         }
2091
2092         urb->priv = NULL;
2093
2094         if (urb_qtd->in_process && qh->channel) {
2095                 dwc2_dump_channel_info(hsotg, qh->channel);
2096
2097                 /* The QTD is in process (it has been assigned to a channel) */
2098                 if (hsotg->flags.b.port_connect_status)
2099                         /*
2100                          * If still connected (i.e. in host mode), halt the
2101                          * channel so it can be used for other transfers. If
2102                          * no longer connected, the host registers can't be
2103                          * written to halt the channel since the core is in
2104                          * device mode.
2105                          */
2106                         dwc2_hc_halt(hsotg, qh->channel,
2107                                      DWC2_HC_XFER_URB_DEQUEUE);
2108         }
2109
2110         /*
2111          * Free the QTD and clean up the associated QH. Leave the QH in the
2112          * schedule if it has any remaining QTDs.
2113          */
2114         if (!hsotg->params.dma_desc_enable) {
2115                 u8 in_process = urb_qtd->in_process;
2116
2117                 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
2118                 if (in_process) {
2119                         dwc2_hcd_qh_deactivate(hsotg, qh, 0);
2120                         qh->channel = NULL;
2121                 } else if (list_empty(&qh->qtd_list)) {
2122                         dwc2_hcd_qh_unlink(hsotg, qh);
2123                 }
2124         } else {
2125                 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
2126         }
2127
2128         return 0;
2129 }
2130
2131 /* Must NOT be called with interrupt disabled or spinlock held */
2132 static int dwc2_hcd_endpoint_disable(struct dwc2_hsotg *hsotg,
2133                                      struct usb_host_endpoint *ep, int retry)
2134 {
2135         struct dwc2_qtd *qtd, *qtd_tmp;
2136         struct dwc2_qh *qh;
2137         unsigned long flags;
2138         int rc;
2139
2140         spin_lock_irqsave(&hsotg->lock, flags);
2141
2142         qh = ep->hcpriv;
2143         if (!qh) {
2144                 rc = -EINVAL;
2145                 goto err;
2146         }
2147
2148         while (!list_empty(&qh->qtd_list) && retry--) {
2149                 if (retry == 0) {
2150                         dev_err(hsotg->dev,
2151                                 "## timeout in dwc2_hcd_endpoint_disable() ##\n");
2152                         rc = -EBUSY;
2153                         goto err;
2154                 }
2155
2156                 spin_unlock_irqrestore(&hsotg->lock, flags);
2157                 msleep(20);
2158                 spin_lock_irqsave(&hsotg->lock, flags);
2159                 qh = ep->hcpriv;
2160                 if (!qh) {
2161                         rc = -EINVAL;
2162                         goto err;
2163                 }
2164         }
2165
2166         dwc2_hcd_qh_unlink(hsotg, qh);
2167
2168         /* Free each QTD in the QH's QTD list */
2169         list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry)
2170                 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
2171
2172         ep->hcpriv = NULL;
2173
2174         if (qh->channel && qh->channel->qh == qh)
2175                 qh->channel->qh = NULL;
2176
2177         spin_unlock_irqrestore(&hsotg->lock, flags);
2178
2179         dwc2_hcd_qh_free(hsotg, qh);
2180
2181         return 0;
2182
2183 err:
2184         ep->hcpriv = NULL;
2185         spin_unlock_irqrestore(&hsotg->lock, flags);
2186
2187         return rc;
2188 }
2189
2190 /* Must be called with interrupt disabled and spinlock held */
2191 static int dwc2_hcd_endpoint_reset(struct dwc2_hsotg *hsotg,
2192                                    struct usb_host_endpoint *ep)
2193 {
2194         struct dwc2_qh *qh = ep->hcpriv;
2195
2196         if (!qh)
2197                 return -EINVAL;
2198
2199         qh->data_toggle = DWC2_HC_PID_DATA0;
2200
2201         return 0;
2202 }
2203
2204 /**
2205  * dwc2_core_init() - Initializes the DWC_otg controller registers and
2206  * prepares the core for device mode or host mode operation
2207  *
2208  * @hsotg:         Programming view of the DWC_otg controller
2209  * @initial_setup: If true then this is the first init for this instance.
2210  */
2211 static int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup)
2212 {
2213         u32 usbcfg, otgctl;
2214         int retval;
2215
2216         dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
2217
2218         usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
2219
2220         /* Set ULPI External VBUS bit if needed */
2221         usbcfg &= ~GUSBCFG_ULPI_EXT_VBUS_DRV;
2222         if (hsotg->params.phy_ulpi_ext_vbus)
2223                 usbcfg |= GUSBCFG_ULPI_EXT_VBUS_DRV;
2224
2225         /* Set external TS Dline pulsing bit if needed */
2226         usbcfg &= ~GUSBCFG_TERMSELDLPULSE;
2227         if (hsotg->params.ts_dline)
2228                 usbcfg |= GUSBCFG_TERMSELDLPULSE;
2229
2230         dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
2231
2232         /*
2233          * Reset the Controller
2234          *
2235          * We only need to reset the controller if this is a re-init.
2236          * For the first init we know for sure that earlier code reset us (it
2237          * needed to in order to properly detect various parameters).
2238          */
2239         if (!initial_setup) {
2240                 retval = dwc2_core_reset_and_force_dr_mode(hsotg);
2241                 if (retval) {
2242                         dev_err(hsotg->dev, "%s(): Reset failed, aborting\n",
2243                                 __func__);
2244                         return retval;
2245                 }
2246         }
2247
2248         /*
2249          * This needs to happen in FS mode before any other programming occurs
2250          */
2251         retval = dwc2_phy_init(hsotg, initial_setup);
2252         if (retval)
2253                 return retval;
2254
2255         /* Program the GAHBCFG Register */
2256         retval = dwc2_gahbcfg_init(hsotg);
2257         if (retval)
2258                 return retval;
2259
2260         /* Program the GUSBCFG register */
2261         dwc2_gusbcfg_init(hsotg);
2262
2263         /* Program the GOTGCTL register */
2264         otgctl = dwc2_readl(hsotg->regs + GOTGCTL);
2265         otgctl &= ~GOTGCTL_OTGVER;
2266         dwc2_writel(otgctl, hsotg->regs + GOTGCTL);
2267
2268         /* Clear the SRP success bit for FS-I2c */
2269         hsotg->srp_success = 0;
2270
2271         /* Enable common interrupts */
2272         dwc2_enable_common_interrupts(hsotg);
2273
2274         /*
2275          * Do device or host initialization based on mode during PCD and
2276          * HCD initialization
2277          */
2278         if (dwc2_is_host_mode(hsotg)) {
2279                 dev_dbg(hsotg->dev, "Host Mode\n");
2280                 hsotg->op_state = OTG_STATE_A_HOST;
2281         } else {
2282                 dev_dbg(hsotg->dev, "Device Mode\n");
2283                 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
2284         }
2285
2286         return 0;
2287 }
2288
2289 /**
2290  * dwc2_core_host_init() - Initializes the DWC_otg controller registers for
2291  * Host mode
2292  *
2293  * @hsotg: Programming view of DWC_otg controller
2294  *
2295  * This function flushes the Tx and Rx FIFOs and flushes any entries in the
2296  * request queues. Host channels are reset to ensure that they are ready for
2297  * performing transfers.
2298  */
2299 static void dwc2_core_host_init(struct dwc2_hsotg *hsotg)
2300 {
2301         u32 hcfg, hfir, otgctl;
2302
2303         dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
2304
2305         /* Restart the Phy Clock */
2306         dwc2_writel(0, hsotg->regs + PCGCTL);
2307
2308         /* Initialize Host Configuration Register */
2309         dwc2_init_fs_ls_pclk_sel(hsotg);
2310         if (hsotg->params.speed == DWC2_SPEED_PARAM_FULL ||
2311             hsotg->params.speed == DWC2_SPEED_PARAM_LOW) {
2312                 hcfg = dwc2_readl(hsotg->regs + HCFG);
2313                 hcfg |= HCFG_FSLSSUPP;
2314                 dwc2_writel(hcfg, hsotg->regs + HCFG);
2315         }
2316
2317         /*
2318          * This bit allows dynamic reloading of the HFIR register during
2319          * runtime. This bit needs to be programmed during initial configuration
2320          * and its value must not be changed during runtime.
2321          */
2322         if (hsotg->params.reload_ctl) {
2323                 hfir = dwc2_readl(hsotg->regs + HFIR);
2324                 hfir |= HFIR_RLDCTRL;
2325                 dwc2_writel(hfir, hsotg->regs + HFIR);
2326         }
2327
2328         if (hsotg->params.dma_desc_enable) {
2329                 u32 op_mode = hsotg->hw_params.op_mode;
2330
2331                 if (hsotg->hw_params.snpsid < DWC2_CORE_REV_2_90a ||
2332                     !hsotg->hw_params.dma_desc_enable ||
2333                     op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE ||
2334                     op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE ||
2335                     op_mode == GHWCFG2_OP_MODE_UNDEFINED) {
2336                         dev_err(hsotg->dev,
2337                                 "Hardware does not support descriptor DMA mode -\n");
2338                         dev_err(hsotg->dev,
2339                                 "falling back to buffer DMA mode.\n");
2340                         hsotg->params.dma_desc_enable = false;
2341                 } else {
2342                         hcfg = dwc2_readl(hsotg->regs + HCFG);
2343                         hcfg |= HCFG_DESCDMA;
2344                         dwc2_writel(hcfg, hsotg->regs + HCFG);
2345                 }
2346         }
2347
2348         /* Configure data FIFO sizes */
2349         dwc2_config_fifos(hsotg);
2350
2351         /* TODO - check this */
2352         /* Clear Host Set HNP Enable in the OTG Control Register */
2353         otgctl = dwc2_readl(hsotg->regs + GOTGCTL);
2354         otgctl &= ~GOTGCTL_HSTSETHNPEN;
2355         dwc2_writel(otgctl, hsotg->regs + GOTGCTL);
2356
2357         /* Make sure the FIFOs are flushed */
2358         dwc2_flush_tx_fifo(hsotg, 0x10 /* all TX FIFOs */);
2359         dwc2_flush_rx_fifo(hsotg);
2360
2361         /* Clear Host Set HNP Enable in the OTG Control Register */
2362         otgctl = dwc2_readl(hsotg->regs + GOTGCTL);
2363         otgctl &= ~GOTGCTL_HSTSETHNPEN;
2364         dwc2_writel(otgctl, hsotg->regs + GOTGCTL);
2365
2366         if (!hsotg->params.dma_desc_enable) {
2367                 int num_channels, i;
2368                 u32 hcchar;
2369
2370                 /* Flush out any leftover queued requests */
2371                 num_channels = hsotg->params.host_channels;
2372                 for (i = 0; i < num_channels; i++) {
2373                         hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
2374                         hcchar &= ~HCCHAR_CHENA;
2375                         hcchar |= HCCHAR_CHDIS;
2376                         hcchar &= ~HCCHAR_EPDIR;
2377                         dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
2378                 }
2379
2380                 /* Halt all channels to put them into a known state */
2381                 for (i = 0; i < num_channels; i++) {
2382                         int count = 0;
2383
2384                         hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
2385                         hcchar |= HCCHAR_CHENA | HCCHAR_CHDIS;
2386                         hcchar &= ~HCCHAR_EPDIR;
2387                         dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
2388                         dev_dbg(hsotg->dev, "%s: Halt channel %d\n",
2389                                 __func__, i);
2390                         do {
2391                                 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
2392                                 if (++count > 1000) {
2393                                         dev_err(hsotg->dev,
2394                                                 "Unable to clear enable on channel %d\n",
2395                                                 i);
2396                                         break;
2397                                 }
2398                                 udelay(1);
2399                         } while (hcchar & HCCHAR_CHENA);
2400                 }
2401         }
2402
2403         /* Turn on the vbus power */
2404         dev_dbg(hsotg->dev, "Init: Port Power? op_state=%d\n", hsotg->op_state);
2405         if (hsotg->op_state == OTG_STATE_A_HOST) {
2406                 u32 hprt0 = dwc2_read_hprt0(hsotg);
2407
2408                 dev_dbg(hsotg->dev, "Init: Power Port (%d)\n",
2409                         !!(hprt0 & HPRT0_PWR));
2410                 if (!(hprt0 & HPRT0_PWR)) {
2411                         hprt0 |= HPRT0_PWR;
2412                         dwc2_writel(hprt0, hsotg->regs + HPRT0);
2413                 }
2414         }
2415
2416         dwc2_enable_host_interrupts(hsotg);
2417 }
2418
2419 /*
2420  * Initializes dynamic portions of the DWC_otg HCD state
2421  *
2422  * Must be called with interrupt disabled and spinlock held
2423  */
2424 static void dwc2_hcd_reinit(struct dwc2_hsotg *hsotg)
2425 {
2426         struct dwc2_host_chan *chan, *chan_tmp;
2427         int num_channels;
2428         int i;
2429
2430         hsotg->flags.d32 = 0;
2431         hsotg->non_periodic_qh_ptr = &hsotg->non_periodic_sched_active;
2432
2433         if (hsotg->params.uframe_sched) {
2434                 hsotg->available_host_channels =
2435                         hsotg->params.host_channels;
2436         } else {
2437                 hsotg->non_periodic_channels = 0;
2438                 hsotg->periodic_channels = 0;
2439         }
2440
2441         /*
2442          * Put all channels in the free channel list and clean up channel
2443          * states
2444          */
2445         list_for_each_entry_safe(chan, chan_tmp, &hsotg->free_hc_list,
2446                                  hc_list_entry)
2447                 list_del_init(&chan->hc_list_entry);
2448
2449         num_channels = hsotg->params.host_channels;
2450         for (i = 0; i < num_channels; i++) {
2451                 chan = hsotg->hc_ptr_array[i];
2452                 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list);
2453                 dwc2_hc_cleanup(hsotg, chan);
2454         }
2455
2456         /* Initialize the DWC core for host mode operation */
2457         dwc2_core_host_init(hsotg);
2458 }
2459
2460 static void dwc2_hc_init_split(struct dwc2_hsotg *hsotg,
2461                                struct dwc2_host_chan *chan,
2462                                struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb)
2463 {
2464         int hub_addr, hub_port;
2465
2466         chan->do_split = 1;
2467         chan->xact_pos = qtd->isoc_split_pos;
2468         chan->complete_split = qtd->complete_split;
2469         dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port);
2470         chan->hub_addr = (u8)hub_addr;
2471         chan->hub_port = (u8)hub_port;
2472 }
2473
2474 static void dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg,
2475                               struct dwc2_host_chan *chan,
2476                               struct dwc2_qtd *qtd)
2477 {
2478         struct dwc2_hcd_urb *urb = qtd->urb;
2479         struct dwc2_hcd_iso_packet_desc *frame_desc;
2480
2481         switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) {
2482         case USB_ENDPOINT_XFER_CONTROL:
2483                 chan->ep_type = USB_ENDPOINT_XFER_CONTROL;
2484
2485                 switch (qtd->control_phase) {
2486                 case DWC2_CONTROL_SETUP:
2487                         dev_vdbg(hsotg->dev, "  Control setup transaction\n");
2488                         chan->do_ping = 0;
2489                         chan->ep_is_in = 0;
2490                         chan->data_pid_start = DWC2_HC_PID_SETUP;
2491                         if (hsotg->params.host_dma)
2492                                 chan->xfer_dma = urb->setup_dma;
2493                         else
2494                                 chan->xfer_buf = urb->setup_packet;
2495                         chan->xfer_len = 8;
2496                         break;
2497
2498                 case DWC2_CONTROL_DATA:
2499                         dev_vdbg(hsotg->dev, "  Control data transaction\n");
2500                         chan->data_pid_start = qtd->data_toggle;
2501                         break;
2502
2503                 case DWC2_CONTROL_STATUS:
2504                         /*
2505                          * Direction is opposite of data direction or IN if no
2506                          * data
2507                          */
2508                         dev_vdbg(hsotg->dev, "  Control status transaction\n");
2509                         if (urb->length == 0)
2510                                 chan->ep_is_in = 1;
2511                         else
2512                                 chan->ep_is_in =
2513                                         dwc2_hcd_is_pipe_out(&urb->pipe_info);
2514                         if (chan->ep_is_in)
2515                                 chan->do_ping = 0;
2516                         chan->data_pid_start = DWC2_HC_PID_DATA1;
2517                         chan->xfer_len = 0;
2518                         if (hsotg->params.host_dma)
2519                                 chan->xfer_dma = hsotg->status_buf_dma;
2520                         else
2521                                 chan->xfer_buf = hsotg->status_buf;
2522                         break;
2523                 }
2524                 break;
2525
2526         case USB_ENDPOINT_XFER_BULK:
2527                 chan->ep_type = USB_ENDPOINT_XFER_BULK;
2528                 break;
2529
2530         case USB_ENDPOINT_XFER_INT:
2531                 chan->ep_type = USB_ENDPOINT_XFER_INT;
2532                 break;
2533
2534         case USB_ENDPOINT_XFER_ISOC:
2535                 chan->ep_type = USB_ENDPOINT_XFER_ISOC;
2536                 if (hsotg->params.dma_desc_enable)
2537                         break;
2538
2539                 frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
2540                 frame_desc->status = 0;
2541
2542                 if (hsotg->params.host_dma) {
2543                         chan->xfer_dma = urb->dma;
2544                         chan->xfer_dma += frame_desc->offset +
2545                                         qtd->isoc_split_offset;
2546                 } else {
2547                         chan->xfer_buf = urb->buf;
2548                         chan->xfer_buf += frame_desc->offset +
2549                                         qtd->isoc_split_offset;
2550                 }
2551
2552                 chan->xfer_len = frame_desc->length - qtd->isoc_split_offset;
2553
2554                 if (chan->xact_pos == DWC2_HCSPLT_XACTPOS_ALL) {
2555                         if (chan->xfer_len <= 188)
2556                                 chan->xact_pos = DWC2_HCSPLT_XACTPOS_ALL;
2557                         else
2558                                 chan->xact_pos = DWC2_HCSPLT_XACTPOS_BEGIN;
2559                 }
2560                 break;
2561         }
2562 }
2563
2564 #define DWC2_USB_DMA_ALIGN 4
2565
2566 struct dma_aligned_buffer {
2567         void *kmalloc_ptr;
2568         void *old_xfer_buffer;
2569         u8 data[0];
2570 };
2571
2572 static void dwc2_free_dma_aligned_buffer(struct urb *urb)
2573 {
2574         struct dma_aligned_buffer *temp;
2575
2576         if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER))
2577                 return;
2578
2579         temp = container_of(urb->transfer_buffer,
2580                             struct dma_aligned_buffer, data);
2581
2582         if (usb_urb_dir_in(urb))
2583                 memcpy(temp->old_xfer_buffer, temp->data,
2584                        urb->transfer_buffer_length);
2585         urb->transfer_buffer = temp->old_xfer_buffer;
2586         kfree(temp->kmalloc_ptr);
2587
2588         urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER;
2589 }
2590
2591 static int dwc2_alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags)
2592 {
2593         struct dma_aligned_buffer *temp, *kmalloc_ptr;
2594         size_t kmalloc_size;
2595
2596         if (urb->num_sgs || urb->sg ||
2597             urb->transfer_buffer_length == 0 ||
2598             !((uintptr_t)urb->transfer_buffer & (DWC2_USB_DMA_ALIGN - 1)))
2599                 return 0;
2600
2601         /* Allocate a buffer with enough padding for alignment */
2602         kmalloc_size = urb->transfer_buffer_length +
2603                 sizeof(struct dma_aligned_buffer) + DWC2_USB_DMA_ALIGN - 1;
2604
2605         kmalloc_ptr = kmalloc(kmalloc_size, mem_flags);
2606         if (!kmalloc_ptr)
2607                 return -ENOMEM;
2608
2609         /* Position our struct dma_aligned_buffer such that data is aligned */
2610         temp = PTR_ALIGN(kmalloc_ptr + 1, DWC2_USB_DMA_ALIGN) - 1;
2611         temp->kmalloc_ptr = kmalloc_ptr;
2612         temp->old_xfer_buffer = urb->transfer_buffer;
2613         if (usb_urb_dir_out(urb))
2614                 memcpy(temp->data, urb->transfer_buffer,
2615                        urb->transfer_buffer_length);
2616         urb->transfer_buffer = temp->data;
2617
2618         urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER;
2619
2620         return 0;
2621 }
2622
2623 static int dwc2_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
2624                                 gfp_t mem_flags)
2625 {
2626         int ret;
2627
2628         /* We assume setup_dma is always aligned; warn if not */
2629         WARN_ON_ONCE(urb->setup_dma &&
2630                      (urb->setup_dma & (DWC2_USB_DMA_ALIGN - 1)));
2631
2632         ret = dwc2_alloc_dma_aligned_buffer(urb, mem_flags);
2633         if (ret)
2634                 return ret;
2635
2636         ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
2637         if (ret)
2638                 dwc2_free_dma_aligned_buffer(urb);
2639
2640         return ret;
2641 }
2642
2643 static void dwc2_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
2644 {
2645         usb_hcd_unmap_urb_for_dma(hcd, urb);
2646         dwc2_free_dma_aligned_buffer(urb);
2647 }
2648
2649 /**
2650  * dwc2_assign_and_init_hc() - Assigns transactions from a QTD to a free host
2651  * channel and initializes the host channel to perform the transactions. The
2652  * host channel is removed from the free list.
2653  *
2654  * @hsotg: The HCD state structure
2655  * @qh:    Transactions from the first QTD for this QH are selected and assigned
2656  *         to a free host channel
2657  */
2658 static int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
2659 {
2660         struct dwc2_host_chan *chan;
2661         struct dwc2_hcd_urb *urb;
2662         struct dwc2_qtd *qtd;
2663
2664         if (dbg_qh(qh))
2665                 dev_vdbg(hsotg->dev, "%s(%p,%p)\n", __func__, hsotg, qh);
2666
2667         if (list_empty(&qh->qtd_list)) {
2668                 dev_dbg(hsotg->dev, "No QTDs in QH list\n");
2669                 return -ENOMEM;
2670         }
2671
2672         if (list_empty(&hsotg->free_hc_list)) {
2673                 dev_dbg(hsotg->dev, "No free channel to assign\n");
2674                 return -ENOMEM;
2675         }
2676
2677         chan = list_first_entry(&hsotg->free_hc_list, struct dwc2_host_chan,
2678                                 hc_list_entry);
2679
2680         /* Remove host channel from free list */
2681         list_del_init(&chan->hc_list_entry);
2682
2683         qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry);
2684         urb = qtd->urb;
2685         qh->channel = chan;
2686         qtd->in_process = 1;
2687
2688         /*
2689          * Use usb_pipedevice to determine device address. This address is
2690          * 0 before the SET_ADDRESS command and the correct address afterward.
2691          */
2692         chan->dev_addr = dwc2_hcd_get_dev_addr(&urb->pipe_info);
2693         chan->ep_num = dwc2_hcd_get_ep_num(&urb->pipe_info);
2694         chan->speed = qh->dev_speed;
2695         chan->max_packet = dwc2_max_packet(qh->maxp);
2696
2697         chan->xfer_started = 0;
2698         chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS;
2699         chan->error_state = (qtd->error_count > 0);
2700         chan->halt_on_queue = 0;
2701         chan->halt_pending = 0;
2702         chan->requests = 0;
2703
2704         /*
2705          * The following values may be modified in the transfer type section
2706          * below. The xfer_len value may be reduced when the transfer is
2707          * started to accommodate the max widths of the XferSize and PktCnt
2708          * fields in the HCTSIZn register.
2709          */
2710
2711         chan->ep_is_in = (dwc2_hcd_is_pipe_in(&urb->pipe_info) != 0);
2712         if (chan->ep_is_in)
2713                 chan->do_ping = 0;
2714         else
2715                 chan->do_ping = qh->ping_state;
2716
2717         chan->data_pid_start = qh->data_toggle;
2718         chan->multi_count = 1;
2719
2720         if (urb->actual_length > urb->length &&
2721             !dwc2_hcd_is_pipe_in(&urb->pipe_info))
2722                 urb->actual_length = urb->length;
2723
2724         if (hsotg->params.host_dma)
2725                 chan->xfer_dma = urb->dma + urb->actual_length;
2726         else
2727                 chan->xfer_buf = (u8 *)urb->buf + urb->actual_length;
2728
2729         chan->xfer_len = urb->length - urb->actual_length;
2730         chan->xfer_count = 0;
2731
2732         /* Set the split attributes if required */
2733         if (qh->do_split)
2734                 dwc2_hc_init_split(hsotg, chan, qtd, urb);
2735         else
2736                 chan->do_split = 0;
2737
2738         /* Set the transfer attributes */
2739         dwc2_hc_init_xfer(hsotg, chan, qtd);
2740
2741         if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
2742             chan->ep_type == USB_ENDPOINT_XFER_ISOC)
2743                 /*
2744                  * This value may be modified when the transfer is started
2745                  * to reflect the actual transfer length
2746                  */
2747                 chan->multi_count = dwc2_hb_mult(qh->maxp);
2748
2749         if (hsotg->params.dma_desc_enable) {
2750                 chan->desc_list_addr = qh->desc_list_dma;
2751                 chan->desc_list_sz = qh->desc_list_sz;
2752         }
2753
2754         dwc2_hc_init(hsotg, chan);
2755         chan->qh = qh;
2756
2757         return 0;
2758 }
2759
2760 /**
2761  * dwc2_hcd_select_transactions() - Selects transactions from the HCD transfer
2762  * schedule and assigns them to available host channels. Called from the HCD
2763  * interrupt handler functions.
2764  *
2765  * @hsotg: The HCD state structure
2766  *
2767  * Return: The types of new transactions that were assigned to host channels
2768  */
2769 enum dwc2_transaction_type dwc2_hcd_select_transactions(
2770                 struct dwc2_hsotg *hsotg)
2771 {
2772         enum dwc2_transaction_type ret_val = DWC2_TRANSACTION_NONE;
2773         struct list_head *qh_ptr;
2774         struct dwc2_qh *qh;
2775         int num_channels;
2776
2777 #ifdef DWC2_DEBUG_SOF
2778         dev_vdbg(hsotg->dev, "  Select Transactions\n");
2779 #endif
2780
2781         /* Process entries in the periodic ready list */
2782         qh_ptr = hsotg->periodic_sched_ready.next;
2783         while (qh_ptr != &hsotg->periodic_sched_ready) {
2784                 if (list_empty(&hsotg->free_hc_list))
2785                         break;
2786                 if (hsotg->params.uframe_sched) {
2787                         if (hsotg->available_host_channels <= 1)
2788                                 break;
2789                         hsotg->available_host_channels--;
2790                 }
2791                 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
2792                 if (dwc2_assign_and_init_hc(hsotg, qh))
2793                         break;
2794
2795                 /*
2796                  * Move the QH from the periodic ready schedule to the
2797                  * periodic assigned schedule
2798                  */
2799                 qh_ptr = qh_ptr->next;
2800                 list_move_tail(&qh->qh_list_entry,
2801                                &hsotg->periodic_sched_assigned);
2802                 ret_val = DWC2_TRANSACTION_PERIODIC;
2803         }
2804
2805         /*
2806          * Process entries in the inactive portion of the non-periodic
2807          * schedule. Some free host channels may not be used if they are
2808          * reserved for periodic transfers.
2809          */
2810         num_channels = hsotg->params.host_channels;
2811         qh_ptr = hsotg->non_periodic_sched_inactive.next;
2812         while (qh_ptr != &hsotg->non_periodic_sched_inactive) {
2813                 if (!hsotg->params.uframe_sched &&
2814                     hsotg->non_periodic_channels >= num_channels -
2815                                                 hsotg->periodic_channels)
2816                         break;
2817                 if (list_empty(&hsotg->free_hc_list))
2818                         break;
2819                 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
2820                 if (hsotg->params.uframe_sched) {
2821                         if (hsotg->available_host_channels < 1)
2822                                 break;
2823                         hsotg->available_host_channels--;
2824                 }
2825
2826                 if (dwc2_assign_and_init_hc(hsotg, qh))
2827                         break;
2828
2829                 /*
2830                  * Move the QH from the non-periodic inactive schedule to the
2831                  * non-periodic active schedule
2832                  */
2833                 qh_ptr = qh_ptr->next;
2834                 list_move_tail(&qh->qh_list_entry,
2835                                &hsotg->non_periodic_sched_active);
2836
2837                 if (ret_val == DWC2_TRANSACTION_NONE)
2838                         ret_val = DWC2_TRANSACTION_NON_PERIODIC;
2839                 else
2840                         ret_val = DWC2_TRANSACTION_ALL;
2841
2842                 if (!hsotg->params.uframe_sched)
2843                         hsotg->non_periodic_channels++;
2844         }
2845
2846         return ret_val;
2847 }
2848
2849 /**
2850  * dwc2_queue_transaction() - Attempts to queue a single transaction request for
2851  * a host channel associated with either a periodic or non-periodic transfer
2852  *
2853  * @hsotg: The HCD state structure
2854  * @chan:  Host channel descriptor associated with either a periodic or
2855  *         non-periodic transfer
2856  * @fifo_dwords_avail: Number of DWORDs available in the periodic Tx FIFO
2857  *                     for periodic transfers or the non-periodic Tx FIFO
2858  *                     for non-periodic transfers
2859  *
2860  * Return: 1 if a request is queued and more requests may be needed to
2861  * complete the transfer, 0 if no more requests are required for this
2862  * transfer, -1 if there is insufficient space in the Tx FIFO
2863  *
2864  * This function assumes that there is space available in the appropriate
2865  * request queue. For an OUT transfer or SETUP transaction in Slave mode,
2866  * it checks whether space is available in the appropriate Tx FIFO.
2867  *
2868  * Must be called with interrupt disabled and spinlock held
2869  */
2870 static int dwc2_queue_transaction(struct dwc2_hsotg *hsotg,
2871                                   struct dwc2_host_chan *chan,
2872                                   u16 fifo_dwords_avail)
2873 {
2874         int retval = 0;
2875
2876         if (chan->do_split)
2877                 /* Put ourselves on the list to keep order straight */
2878                 list_move_tail(&chan->split_order_list_entry,
2879                                &hsotg->split_order);
2880
2881         if (hsotg->params.host_dma) {
2882                 if (hsotg->params.dma_desc_enable) {
2883                         if (!chan->xfer_started ||
2884                             chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
2885                                 dwc2_hcd_start_xfer_ddma(hsotg, chan->qh);
2886                                 chan->qh->ping_state = 0;
2887                         }
2888                 } else if (!chan->xfer_started) {
2889                         dwc2_hc_start_transfer(hsotg, chan);
2890                         chan->qh->ping_state = 0;
2891                 }
2892         } else if (chan->halt_pending) {
2893                 /* Don't queue a request if the channel has been halted */
2894         } else if (chan->halt_on_queue) {
2895                 dwc2_hc_halt(hsotg, chan, chan->halt_status);
2896         } else if (chan->do_ping) {
2897                 if (!chan->xfer_started)
2898                         dwc2_hc_start_transfer(hsotg, chan);
2899         } else if (!chan->ep_is_in ||
2900                    chan->data_pid_start == DWC2_HC_PID_SETUP) {
2901                 if ((fifo_dwords_avail * 4) >= chan->max_packet) {
2902                         if (!chan->xfer_started) {
2903                                 dwc2_hc_start_transfer(hsotg, chan);
2904                                 retval = 1;
2905                         } else {
2906                                 retval = dwc2_hc_continue_transfer(hsotg, chan);
2907                         }
2908                 } else {
2909                         retval = -1;
2910                 }
2911         } else {
2912                 if (!chan->xfer_started) {
2913                         dwc2_hc_start_transfer(hsotg, chan);
2914                         retval = 1;
2915                 } else {
2916                         retval = dwc2_hc_continue_transfer(hsotg, chan);
2917                 }
2918         }
2919
2920         return retval;
2921 }
2922
2923 /*
2924  * Processes periodic channels for the next frame and queues transactions for
2925  * these channels to the DWC_otg controller. After queueing transactions, the
2926  * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
2927  * to queue as Periodic Tx FIFO or request queue space becomes available.
2928  * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
2929  *
2930  * Must be called with interrupt disabled and spinlock held
2931  */
2932 static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg)
2933 {
2934         struct list_head *qh_ptr;
2935         struct dwc2_qh *qh;
2936         u32 tx_status;
2937         u32 fspcavail;
2938         u32 gintmsk;
2939         int status;
2940         bool no_queue_space = false;
2941         bool no_fifo_space = false;
2942         u32 qspcavail;
2943
2944         /* If empty list then just adjust interrupt enables */
2945         if (list_empty(&hsotg->periodic_sched_assigned))
2946                 goto exit;
2947
2948         if (dbg_perio())
2949                 dev_vdbg(hsotg->dev, "Queue periodic transactions\n");
2950
2951         tx_status = dwc2_readl(hsotg->regs + HPTXSTS);
2952         qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
2953                     TXSTS_QSPCAVAIL_SHIFT;
2954         fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
2955                     TXSTS_FSPCAVAIL_SHIFT;
2956
2957         if (dbg_perio()) {
2958                 dev_vdbg(hsotg->dev, "  P Tx Req Queue Space Avail (before queue): %d\n",
2959                          qspcavail);
2960                 dev_vdbg(hsotg->dev, "  P Tx FIFO Space Avail (before queue): %d\n",
2961                          fspcavail);
2962         }
2963
2964         qh_ptr = hsotg->periodic_sched_assigned.next;
2965         while (qh_ptr != &hsotg->periodic_sched_assigned) {
2966                 tx_status = dwc2_readl(hsotg->regs + HPTXSTS);
2967                 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
2968                             TXSTS_QSPCAVAIL_SHIFT;
2969                 if (qspcavail == 0) {
2970                         no_queue_space = true;
2971                         break;
2972                 }
2973
2974                 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
2975                 if (!qh->channel) {
2976                         qh_ptr = qh_ptr->next;
2977                         continue;
2978                 }
2979
2980                 /* Make sure EP's TT buffer is clean before queueing qtds */
2981                 if (qh->tt_buffer_dirty) {
2982                         qh_ptr = qh_ptr->next;
2983                         continue;
2984                 }
2985
2986                 /*
2987                  * Set a flag if we're queuing high-bandwidth in slave mode.
2988                  * The flag prevents any halts to get into the request queue in
2989                  * the middle of multiple high-bandwidth packets getting queued.
2990                  */
2991                 if (!hsotg->params.host_dma &&
2992                     qh->channel->multi_count > 1)
2993                         hsotg->queuing_high_bandwidth = 1;
2994
2995                 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
2996                             TXSTS_FSPCAVAIL_SHIFT;
2997                 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
2998                 if (status < 0) {
2999                         no_fifo_space = true;
3000                         break;
3001                 }
3002
3003                 /*
3004                  * In Slave mode, stay on the current transfer until there is
3005                  * nothing more to do or the high-bandwidth request count is
3006                  * reached. In DMA mode, only need to queue one request. The
3007                  * controller automatically handles multiple packets for
3008                  * high-bandwidth transfers.
3009                  */
3010                 if (hsotg->params.host_dma || status == 0 ||
3011                     qh->channel->requests == qh->channel->multi_count) {
3012                         qh_ptr = qh_ptr->next;
3013                         /*
3014                          * Move the QH from the periodic assigned schedule to
3015                          * the periodic queued schedule
3016                          */
3017                         list_move_tail(&qh->qh_list_entry,
3018                                        &hsotg->periodic_sched_queued);
3019
3020                         /* done queuing high bandwidth */
3021                         hsotg->queuing_high_bandwidth = 0;
3022                 }
3023         }
3024
3025 exit:
3026         if (no_queue_space || no_fifo_space ||
3027             (!hsotg->params.host_dma &&
3028              !list_empty(&hsotg->periodic_sched_assigned))) {
3029                 /*
3030                  * May need to queue more transactions as the request
3031                  * queue or Tx FIFO empties. Enable the periodic Tx
3032                  * FIFO empty interrupt. (Always use the half-empty
3033                  * level to ensure that new requests are loaded as
3034                  * soon as possible.)
3035                  */
3036                 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3037                 if (!(gintmsk & GINTSTS_PTXFEMP)) {
3038                         gintmsk |= GINTSTS_PTXFEMP;
3039                         dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
3040                 }
3041         } else {
3042                 /*
3043                  * Disable the Tx FIFO empty interrupt since there are
3044                  * no more transactions that need to be queued right
3045                  * now. This function is called from interrupt
3046                  * handlers to queue more transactions as transfer
3047                  * states change.
3048                  */
3049                 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3050                 if (gintmsk & GINTSTS_PTXFEMP) {
3051                         gintmsk &= ~GINTSTS_PTXFEMP;
3052                         dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
3053                 }
3054         }
3055 }
3056
3057 /*
3058  * Processes active non-periodic channels and queues transactions for these
3059  * channels to the DWC_otg controller. After queueing transactions, the NP Tx
3060  * FIFO Empty interrupt is enabled if there are more transactions to queue as
3061  * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
3062  * FIFO Empty interrupt is disabled.
3063  *
3064  * Must be called with interrupt disabled and spinlock held
3065  */
3066 static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg)
3067 {
3068         struct list_head *orig_qh_ptr;
3069         struct dwc2_qh *qh;
3070         u32 tx_status;
3071         u32 qspcavail;
3072         u32 fspcavail;
3073         u32 gintmsk;
3074         int status;
3075         int no_queue_space = 0;
3076         int no_fifo_space = 0;
3077         int more_to_do = 0;
3078
3079         dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n");
3080
3081         tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
3082         qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3083                     TXSTS_QSPCAVAIL_SHIFT;
3084         fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
3085                     TXSTS_FSPCAVAIL_SHIFT;
3086         dev_vdbg(hsotg->dev, "  NP Tx Req Queue Space Avail (before queue): %d\n",
3087                  qspcavail);
3088         dev_vdbg(hsotg->dev, "  NP Tx FIFO Space Avail (before queue): %d\n",
3089                  fspcavail);
3090
3091         /*
3092          * Keep track of the starting point. Skip over the start-of-list
3093          * entry.
3094          */
3095         if (hsotg->non_periodic_qh_ptr == &hsotg->non_periodic_sched_active)
3096                 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
3097         orig_qh_ptr = hsotg->non_periodic_qh_ptr;
3098
3099         /*
3100          * Process once through the active list or until no more space is
3101          * available in the request queue or the Tx FIFO
3102          */
3103         do {
3104                 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
3105                 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3106                             TXSTS_QSPCAVAIL_SHIFT;
3107                 if (!hsotg->params.host_dma && qspcavail == 0) {
3108                         no_queue_space = 1;
3109                         break;
3110                 }
3111
3112                 qh = list_entry(hsotg->non_periodic_qh_ptr, struct dwc2_qh,
3113                                 qh_list_entry);
3114                 if (!qh->channel)
3115                         goto next;
3116
3117                 /* Make sure EP's TT buffer is clean before queueing qtds */
3118                 if (qh->tt_buffer_dirty)
3119                         goto next;
3120
3121                 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
3122                             TXSTS_FSPCAVAIL_SHIFT;
3123                 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
3124
3125                 if (status > 0) {
3126                         more_to_do = 1;
3127                 } else if (status < 0) {
3128                         no_fifo_space = 1;
3129                         break;
3130                 }
3131 next:
3132                 /* Advance to next QH, skipping start-of-list entry */
3133                 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
3134                 if (hsotg->non_periodic_qh_ptr ==
3135                                 &hsotg->non_periodic_sched_active)
3136                         hsotg->non_periodic_qh_ptr =
3137                                         hsotg->non_periodic_qh_ptr->next;
3138         } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr);
3139
3140         if (!hsotg->params.host_dma) {
3141                 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
3142                 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3143                             TXSTS_QSPCAVAIL_SHIFT;
3144                 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
3145                             TXSTS_FSPCAVAIL_SHIFT;
3146                 dev_vdbg(hsotg->dev,
3147                          "  NP Tx Req Queue Space Avail (after queue): %d\n",
3148                          qspcavail);
3149                 dev_vdbg(hsotg->dev,
3150                          "  NP Tx FIFO Space Avail (after queue): %d\n",
3151                          fspcavail);
3152
3153                 if (more_to_do || no_queue_space || no_fifo_space) {
3154                         /*
3155                          * May need to queue more transactions as the request
3156                          * queue or Tx FIFO empties. Enable the non-periodic
3157                          * Tx FIFO empty interrupt. (Always use the half-empty
3158                          * level to ensure that new requests are loaded as
3159                          * soon as possible.)
3160                          */
3161                         gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3162                         gintmsk |= GINTSTS_NPTXFEMP;
3163                         dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
3164                 } else {
3165                         /*
3166                          * Disable the Tx FIFO empty interrupt since there are
3167                          * no more transactions that need to be queued right
3168                          * now. This function is called from interrupt
3169                          * handlers to queue more transactions as transfer
3170                          * states change.
3171                          */
3172                         gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3173                         gintmsk &= ~GINTSTS_NPTXFEMP;
3174                         dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
3175                 }
3176         }
3177 }
3178
3179 /**
3180  * dwc2_hcd_queue_transactions() - Processes the currently active host channels
3181  * and queues transactions for these channels to the DWC_otg controller. Called
3182  * from the HCD interrupt handler functions.
3183  *
3184  * @hsotg:   The HCD state structure
3185  * @tr_type: The type(s) of transactions to queue (non-periodic, periodic,
3186  *           or both)
3187  *
3188  * Must be called with interrupt disabled and spinlock held
3189  */
3190 void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg,
3191                                  enum dwc2_transaction_type tr_type)
3192 {
3193 #ifdef DWC2_DEBUG_SOF
3194         dev_vdbg(hsotg->dev, "Queue Transactions\n");
3195 #endif
3196         /* Process host channels associated with periodic transfers */
3197         if (tr_type == DWC2_TRANSACTION_PERIODIC ||
3198             tr_type == DWC2_TRANSACTION_ALL)
3199                 dwc2_process_periodic_channels(hsotg);
3200
3201         /* Process host channels associated with non-periodic transfers */
3202         if (tr_type == DWC2_TRANSACTION_NON_PERIODIC ||
3203             tr_type == DWC2_TRANSACTION_ALL) {
3204                 if (!list_empty(&hsotg->non_periodic_sched_active)) {
3205                         dwc2_process_non_periodic_channels(hsotg);
3206                 } else {
3207                         /*
3208                          * Ensure NP Tx FIFO empty interrupt is disabled when
3209                          * there are no non-periodic transfers to process
3210                          */
3211                         u32 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3212
3213                         gintmsk &= ~GINTSTS_NPTXFEMP;
3214                         dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
3215                 }
3216         }
3217 }
3218
3219 static void dwc2_conn_id_status_change(struct work_struct *work)
3220 {
3221         struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
3222                                                 wf_otg);
3223         u32 count = 0;
3224         u32 gotgctl;
3225         unsigned long flags;
3226
3227         dev_dbg(hsotg->dev, "%s()\n", __func__);
3228
3229         gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
3230         dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl);
3231         dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n",
3232                 !!(gotgctl & GOTGCTL_CONID_B));
3233
3234         /* B-Device connector (Device Mode) */
3235         if (gotgctl & GOTGCTL_CONID_B) {
3236                 /* Wait for switch to device mode */
3237                 dev_dbg(hsotg->dev, "connId B\n");
3238                 if (hsotg->bus_suspended) {
3239                         dev_info(hsotg->dev,
3240                                  "Do port resume before switching to device mode\n");
3241                         dwc2_port_resume(hsotg);
3242                 }
3243                 while (!dwc2_is_device_mode(hsotg)) {
3244                         dev_info(hsotg->dev,
3245                                  "Waiting for Peripheral Mode, Mode=%s\n",
3246                                  dwc2_is_host_mode(hsotg) ? "Host" :
3247                                  "Peripheral");
3248                         msleep(20);
3249                         /*
3250                          * Sometimes the initial GOTGCTRL read is wrong, so
3251                          * check it again and jump to host mode if that was
3252                          * the case.
3253                          */
3254                         gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
3255                         if (!(gotgctl & GOTGCTL_CONID_B))
3256                                 goto host;
3257                         if (++count > 250)
3258                                 break;
3259                 }
3260                 if (count > 250)
3261                         dev_err(hsotg->dev,
3262                                 "Connection id status change timed out\n");
3263                 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
3264                 dwc2_core_init(hsotg, false);
3265                 dwc2_enable_global_interrupts(hsotg);
3266                 spin_lock_irqsave(&hsotg->lock, flags);
3267                 dwc2_hsotg_core_init_disconnected(hsotg, false);
3268                 spin_unlock_irqrestore(&hsotg->lock, flags);
3269                 dwc2_hsotg_core_connect(hsotg);
3270         } else {
3271 host:
3272                 /* A-Device connector (Host Mode) */
3273                 dev_dbg(hsotg->dev, "connId A\n");
3274                 while (!dwc2_is_host_mode(hsotg)) {
3275                         dev_info(hsotg->dev, "Waiting for Host Mode, Mode=%s\n",
3276                                  dwc2_is_host_mode(hsotg) ?
3277                                  "Host" : "Peripheral");
3278                         msleep(20);
3279                         if (++count > 250)
3280                                 break;
3281                 }
3282                 if (count > 250)
3283                         dev_err(hsotg->dev,
3284                                 "Connection id status change timed out\n");
3285                 hsotg->op_state = OTG_STATE_A_HOST;
3286
3287                 /* Initialize the Core for Host mode */
3288                 dwc2_core_init(hsotg, false);
3289                 dwc2_enable_global_interrupts(hsotg);
3290                 dwc2_hcd_start(hsotg);
3291         }
3292 }
3293
3294 static void dwc2_wakeup_detected(unsigned long data)
3295 {
3296         struct dwc2_hsotg *hsotg = (struct dwc2_hsotg *)data;
3297         u32 hprt0;
3298
3299         dev_dbg(hsotg->dev, "%s()\n", __func__);
3300
3301         /*
3302          * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
3303          * so that OPT tests pass with all PHYs.)
3304          */
3305         hprt0 = dwc2_read_hprt0(hsotg);
3306         dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0);
3307         hprt0 &= ~HPRT0_RES;
3308         dwc2_writel(hprt0, hsotg->regs + HPRT0);
3309         dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n",
3310                 dwc2_readl(hsotg->regs + HPRT0));
3311
3312         dwc2_hcd_rem_wakeup(hsotg);
3313         hsotg->bus_suspended = false;
3314
3315         /* Change to L0 state */
3316         hsotg->lx_state = DWC2_L0;
3317 }
3318
3319 static int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg)
3320 {
3321         struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
3322
3323         return hcd->self.b_hnp_enable;
3324 }
3325
3326 /* Must NOT be called with interrupt disabled or spinlock held */
3327 static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex)
3328 {
3329         unsigned long flags;
3330         u32 hprt0;
3331         u32 pcgctl;
3332         u32 gotgctl;
3333
3334         dev_dbg(hsotg->dev, "%s()\n", __func__);
3335
3336         spin_lock_irqsave(&hsotg->lock, flags);
3337
3338         if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) {
3339                 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
3340                 gotgctl |= GOTGCTL_HSTSETHNPEN;
3341                 dwc2_writel(gotgctl, hsotg->regs + GOTGCTL);
3342                 hsotg->op_state = OTG_STATE_A_SUSPEND;
3343         }
3344
3345         hprt0 = dwc2_read_hprt0(hsotg);
3346         hprt0 |= HPRT0_SUSP;
3347         dwc2_writel(hprt0, hsotg->regs + HPRT0);
3348
3349         hsotg->bus_suspended = true;
3350
3351         /*
3352          * If hibernation is supported, Phy clock will be suspended
3353          * after registers are backuped.
3354          */
3355         if (!hsotg->params.hibernation) {
3356                 /* Suspend the Phy Clock */
3357                 pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
3358                 pcgctl |= PCGCTL_STOPPCLK;
3359                 dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
3360                 udelay(10);
3361         }
3362
3363         /* For HNP the bus must be suspended for at least 200ms */
3364         if (dwc2_host_is_b_hnp_enabled(hsotg)) {
3365                 pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
3366                 pcgctl &= ~PCGCTL_STOPPCLK;
3367                 dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
3368
3369                 spin_unlock_irqrestore(&hsotg->lock, flags);
3370
3371                 msleep(200);
3372         } else {
3373                 spin_unlock_irqrestore(&hsotg->lock, flags);
3374         }
3375 }
3376
3377 /* Must NOT be called with interrupt disabled or spinlock held */
3378 static void dwc2_port_resume(struct dwc2_hsotg *hsotg)
3379 {
3380         unsigned long flags;
3381         u32 hprt0;
3382         u32 pcgctl;
3383
3384         spin_lock_irqsave(&hsotg->lock, flags);
3385
3386         /*
3387          * If hibernation is supported, Phy clock is already resumed
3388          * after registers restore.
3389          */
3390         if (!hsotg->params.hibernation) {
3391                 pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
3392                 pcgctl &= ~PCGCTL_STOPPCLK;
3393                 dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
3394                 spin_unlock_irqrestore(&hsotg->lock, flags);
3395                 msleep(20);
3396                 spin_lock_irqsave(&hsotg->lock, flags);
3397         }
3398
3399         hprt0 = dwc2_read_hprt0(hsotg);
3400         hprt0 |= HPRT0_RES;
3401         hprt0 &= ~HPRT0_SUSP;
3402         dwc2_writel(hprt0, hsotg->regs + HPRT0);
3403         spin_unlock_irqrestore(&hsotg->lock, flags);
3404
3405         msleep(USB_RESUME_TIMEOUT);
3406
3407         spin_lock_irqsave(&hsotg->lock, flags);
3408         hprt0 = dwc2_read_hprt0(hsotg);
3409         hprt0 &= ~(HPRT0_RES | HPRT0_SUSP);
3410         dwc2_writel(hprt0, hsotg->regs + HPRT0);
3411         hsotg->bus_suspended = false;
3412         spin_unlock_irqrestore(&hsotg->lock, flags);
3413 }
3414
3415 /* Handles hub class-specific requests */
3416 static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
3417                                 u16 wvalue, u16 windex, char *buf, u16 wlength)
3418 {
3419         struct usb_hub_descriptor *hub_desc;
3420         int retval = 0;
3421         u32 hprt0;
3422         u32 port_status;
3423         u32 speed;
3424         u32 pcgctl;
3425
3426         switch (typereq) {
3427         case ClearHubFeature:
3428                 dev_dbg(hsotg->dev, "ClearHubFeature %1xh\n", wvalue);
3429
3430                 switch (wvalue) {
3431                 case C_HUB_LOCAL_POWER:
3432                 case C_HUB_OVER_CURRENT:
3433                         /* Nothing required here */
3434                         break;
3435
3436                 default:
3437                         retval = -EINVAL;
3438                         dev_err(hsotg->dev,
3439                                 "ClearHubFeature request %1xh unknown\n",
3440                                 wvalue);
3441                 }
3442                 break;
3443
3444         case ClearPortFeature:
3445                 if (wvalue != USB_PORT_FEAT_L1)
3446                         if (!windex || windex > 1)
3447                                 goto error;
3448                 switch (wvalue) {
3449                 case USB_PORT_FEAT_ENABLE:
3450                         dev_dbg(hsotg->dev,
3451                                 "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
3452                         hprt0 = dwc2_read_hprt0(hsotg);
3453                         hprt0 |= HPRT0_ENA;
3454                         dwc2_writel(hprt0, hsotg->regs + HPRT0);
3455                         break;
3456
3457                 case USB_PORT_FEAT_SUSPEND:
3458                         dev_dbg(hsotg->dev,
3459                                 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
3460
3461                         if (hsotg->bus_suspended)
3462                                 dwc2_port_resume(hsotg);
3463                         break;
3464
3465                 case USB_PORT_FEAT_POWER:
3466                         dev_dbg(hsotg->dev,
3467                                 "ClearPortFeature USB_PORT_FEAT_POWER\n");
3468                         hprt0 = dwc2_read_hprt0(hsotg);
3469                         hprt0 &= ~HPRT0_PWR;
3470                         dwc2_writel(hprt0, hsotg->regs + HPRT0);
3471                         break;
3472
3473                 case USB_PORT_FEAT_INDICATOR:
3474                         dev_dbg(hsotg->dev,
3475                                 "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
3476                         /* Port indicator not supported */
3477                         break;
3478
3479                 case USB_PORT_FEAT_C_CONNECTION:
3480                         /*
3481                          * Clears driver's internal Connect Status Change flag
3482                          */
3483                         dev_dbg(hsotg->dev,
3484                                 "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
3485                         hsotg->flags.b.port_connect_status_change = 0;
3486                         break;
3487
3488                 case USB_PORT_FEAT_C_RESET:
3489                         /* Clears driver's internal Port Reset Change flag */
3490                         dev_dbg(hsotg->dev,
3491                                 "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
3492                         hsotg->flags.b.port_reset_change = 0;
3493                         break;
3494
3495                 case USB_PORT_FEAT_C_ENABLE:
3496                         /*
3497                          * Clears the driver's internal Port Enable/Disable
3498                          * Change flag
3499                          */
3500                         dev_dbg(hsotg->dev,
3501                                 "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
3502                         hsotg->flags.b.port_enable_change = 0;
3503                         break;
3504
3505                 case USB_PORT_FEAT_C_SUSPEND:
3506                         /*
3507                          * Clears the driver's internal Port Suspend Change
3508                          * flag, which is set when resume signaling on the host
3509                          * port is complete
3510                          */
3511                         dev_dbg(hsotg->dev,
3512                                 "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
3513                         hsotg->flags.b.port_suspend_change = 0;
3514                         break;
3515
3516                 case USB_PORT_FEAT_C_PORT_L1:
3517                         dev_dbg(hsotg->dev,
3518                                 "ClearPortFeature USB_PORT_FEAT_C_PORT_L1\n");
3519                         hsotg->flags.b.port_l1_change = 0;
3520                         break;
3521
3522                 case USB_PORT_FEAT_C_OVER_CURRENT:
3523                         dev_dbg(hsotg->dev,
3524                                 "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
3525                         hsotg->flags.b.port_over_current_change = 0;
3526                         break;
3527
3528                 default:
3529                         retval = -EINVAL;
3530                         dev_err(hsotg->dev,
3531                                 "ClearPortFeature request %1xh unknown or unsupported\n",
3532                                 wvalue);
3533                 }
3534                 break;
3535
3536         case GetHubDescriptor:
3537                 dev_dbg(hsotg->dev, "GetHubDescriptor\n");
3538                 hub_desc = (struct usb_hub_descriptor *)buf;
3539                 hub_desc->bDescLength = 9;
3540                 hub_desc->bDescriptorType = USB_DT_HUB;
3541                 hub_desc->bNbrPorts = 1;
3542                 hub_desc->wHubCharacteristics =
3543                         cpu_to_le16(HUB_CHAR_COMMON_LPSM |
3544                                     HUB_CHAR_INDV_PORT_OCPM);
3545                 hub_desc->bPwrOn2PwrGood = 1;
3546                 hub_desc->bHubContrCurrent = 0;
3547                 hub_desc->u.hs.DeviceRemovable[0] = 0;
3548                 hub_desc->u.hs.DeviceRemovable[1] = 0xff;
3549                 break;
3550
3551         case GetHubStatus:
3552                 dev_dbg(hsotg->dev, "GetHubStatus\n");
3553                 memset(buf, 0, 4);
3554                 break;
3555
3556         case GetPortStatus:
3557                 dev_vdbg(hsotg->dev,
3558                          "GetPortStatus wIndex=0x%04x flags=0x%08x\n", windex,
3559                          hsotg->flags.d32);
3560                 if (!windex || windex > 1)
3561                         goto error;
3562
3563                 port_status = 0;
3564                 if (hsotg->flags.b.port_connect_status_change)
3565                         port_status |= USB_PORT_STAT_C_CONNECTION << 16;
3566                 if (hsotg->flags.b.port_enable_change)
3567                         port_status |= USB_PORT_STAT_C_ENABLE << 16;
3568                 if (hsotg->flags.b.port_suspend_change)
3569                         port_status |= USB_PORT_STAT_C_SUSPEND << 16;
3570                 if (hsotg->flags.b.port_l1_change)
3571                         port_status |= USB_PORT_STAT_C_L1 << 16;
3572                 if (hsotg->flags.b.port_reset_change)
3573                         port_status |= USB_PORT_STAT_C_RESET << 16;
3574                 if (hsotg->flags.b.port_over_current_change) {
3575                         dev_warn(hsotg->dev, "Overcurrent change detected\n");
3576                         port_status |= USB_PORT_STAT_C_OVERCURRENT << 16;
3577                 }
3578
3579                 if (!hsotg->flags.b.port_connect_status) {
3580                         /*
3581                          * The port is disconnected, which means the core is
3582                          * either in device mode or it soon will be. Just
3583                          * return 0's for the remainder of the port status
3584                          * since the port register can't be read if the core
3585                          * is in device mode.
3586                          */
3587                         *(__le32 *)buf = cpu_to_le32(port_status);
3588                         break;
3589                 }
3590
3591                 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
3592                 dev_vdbg(hsotg->dev, "  HPRT0: 0x%08x\n", hprt0);
3593
3594                 if (hprt0 & HPRT0_CONNSTS)
3595                         port_status |= USB_PORT_STAT_CONNECTION;
3596                 if (hprt0 & HPRT0_ENA)
3597                         port_status |= USB_PORT_STAT_ENABLE;
3598                 if (hprt0 & HPRT0_SUSP)
3599                         port_status |= USB_PORT_STAT_SUSPEND;
3600                 if (hprt0 & HPRT0_OVRCURRACT)
3601                         port_status |= USB_PORT_STAT_OVERCURRENT;
3602                 if (hprt0 & HPRT0_RST)
3603                         port_status |= USB_PORT_STAT_RESET;
3604                 if (hprt0 & HPRT0_PWR)
3605                         port_status |= USB_PORT_STAT_POWER;
3606
3607                 speed = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
3608                 if (speed == HPRT0_SPD_HIGH_SPEED)
3609                         port_status |= USB_PORT_STAT_HIGH_SPEED;
3610                 else if (speed == HPRT0_SPD_LOW_SPEED)
3611                         port_status |= USB_PORT_STAT_LOW_SPEED;
3612
3613                 if (hprt0 & HPRT0_TSTCTL_MASK)
3614                         port_status |= USB_PORT_STAT_TEST;
3615                 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
3616
3617                 if (hsotg->params.dma_desc_fs_enable) {
3618                         /*
3619                          * Enable descriptor DMA only if a full speed
3620                          * device is connected.
3621                          */
3622                         if (hsotg->new_connection &&
3623                             ((port_status &
3624                               (USB_PORT_STAT_CONNECTION |
3625                                USB_PORT_STAT_HIGH_SPEED |
3626                                USB_PORT_STAT_LOW_SPEED)) ==
3627                                USB_PORT_STAT_CONNECTION)) {
3628                                 u32 hcfg;
3629
3630                                 dev_info(hsotg->dev, "Enabling descriptor DMA mode\n");
3631                                 hsotg->params.dma_desc_enable = true;
3632                                 hcfg = dwc2_readl(hsotg->regs + HCFG);
3633                                 hcfg |= HCFG_DESCDMA;
3634                                 dwc2_writel(hcfg, hsotg->regs + HCFG);
3635                                 hsotg->new_connection = false;
3636                         }
3637                 }
3638
3639                 dev_vdbg(hsotg->dev, "port_status=%08x\n", port_status);
3640                 *(__le32 *)buf = cpu_to_le32(port_status);
3641                 break;
3642
3643         case SetHubFeature:
3644                 dev_dbg(hsotg->dev, "SetHubFeature\n");
3645                 /* No HUB features supported */
3646                 break;
3647
3648         case SetPortFeature:
3649                 dev_dbg(hsotg->dev, "SetPortFeature\n");
3650                 if (wvalue != USB_PORT_FEAT_TEST && (!windex || windex > 1))
3651                         goto error;
3652
3653                 if (!hsotg->flags.b.port_connect_status) {
3654                         /*
3655                          * The port is disconnected, which means the core is
3656                          * either in device mode or it soon will be. Just
3657                          * return without doing anything since the port
3658                          * register can't be written if the core is in device
3659                          * mode.
3660                          */
3661                         break;
3662                 }
3663
3664                 switch (wvalue) {
3665                 case USB_PORT_FEAT_SUSPEND:
3666                         dev_dbg(hsotg->dev,
3667                                 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
3668                         if (windex != hsotg->otg_port)
3669                                 goto error;
3670                         dwc2_port_suspend(hsotg, windex);
3671                         break;
3672
3673                 case USB_PORT_FEAT_POWER:
3674                         dev_dbg(hsotg->dev,
3675                                 "SetPortFeature - USB_PORT_FEAT_POWER\n");
3676                         hprt0 = dwc2_read_hprt0(hsotg);
3677                         hprt0 |= HPRT0_PWR;
3678                         dwc2_writel(hprt0, hsotg->regs + HPRT0);
3679                         break;
3680
3681                 case USB_PORT_FEAT_RESET:
3682                         hprt0 = dwc2_read_hprt0(hsotg);
3683                         dev_dbg(hsotg->dev,
3684                                 "SetPortFeature - USB_PORT_FEAT_RESET\n");
3685                         pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
3686                         pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK);
3687                         dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
3688                         /* ??? Original driver does this */
3689                         dwc2_writel(0, hsotg->regs + PCGCTL);
3690
3691                         hprt0 = dwc2_read_hprt0(hsotg);
3692                         /* Clear suspend bit if resetting from suspend state */
3693                         hprt0 &= ~HPRT0_SUSP;
3694
3695                         /*
3696                          * When B-Host the Port reset bit is set in the Start
3697                          * HCD Callback function, so that the reset is started
3698                          * within 1ms of the HNP success interrupt
3699                          */
3700                         if (!dwc2_hcd_is_b_host(hsotg)) {
3701                                 hprt0 |= HPRT0_PWR | HPRT0_RST;
3702                                 dev_dbg(hsotg->dev,
3703                                         "In host mode, hprt0=%08x\n", hprt0);
3704                                 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3705                         }
3706
3707                         /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
3708                         msleep(50);
3709                         hprt0 &= ~HPRT0_RST;
3710                         dwc2_writel(hprt0, hsotg->regs + HPRT0);
3711                         hsotg->lx_state = DWC2_L0; /* Now back to On state */
3712                         break;
3713
3714                 case USB_PORT_FEAT_INDICATOR:
3715                         dev_dbg(hsotg->dev,
3716                                 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
3717                         /* Not supported */
3718                         break;
3719
3720                 case USB_PORT_FEAT_TEST:
3721                         hprt0 = dwc2_read_hprt0(hsotg);
3722                         dev_dbg(hsotg->dev,
3723                                 "SetPortFeature - USB_PORT_FEAT_TEST\n");
3724                         hprt0 &= ~HPRT0_TSTCTL_MASK;
3725                         hprt0 |= (windex >> 8) << HPRT0_TSTCTL_SHIFT;
3726                         dwc2_writel(hprt0, hsotg->regs + HPRT0);
3727                         break;
3728
3729                 default:
3730                         retval = -EINVAL;
3731                         dev_err(hsotg->dev,
3732                                 "SetPortFeature %1xh unknown or unsupported\n",
3733                                 wvalue);
3734                         break;
3735                 }
3736                 break;
3737
3738         default:
3739 error:
3740                 retval = -EINVAL;
3741                 dev_dbg(hsotg->dev,
3742                         "Unknown hub control request: %1xh wIndex: %1xh wValue: %1xh\n",
3743                         typereq, windex, wvalue);
3744                 break;
3745         }
3746
3747         return retval;
3748 }
3749
3750 static int dwc2_hcd_is_status_changed(struct dwc2_hsotg *hsotg, int port)
3751 {
3752         int retval;
3753
3754         if (port != 1)
3755                 return -EINVAL;
3756
3757         retval = (hsotg->flags.b.port_connect_status_change ||
3758                   hsotg->flags.b.port_reset_change ||
3759                   hsotg->flags.b.port_enable_change ||
3760                   hsotg->flags.b.port_suspend_change ||
3761                   hsotg->flags.b.port_over_current_change);
3762
3763         if (retval) {
3764                 dev_dbg(hsotg->dev,
3765                         "DWC OTG HCD HUB STATUS DATA: Root port status changed\n");
3766                 dev_dbg(hsotg->dev, "  port_connect_status_change: %d\n",
3767                         hsotg->flags.b.port_connect_status_change);
3768                 dev_dbg(hsotg->dev, "  port_reset_change: %d\n",
3769                         hsotg->flags.b.port_reset_change);
3770                 dev_dbg(hsotg->dev, "  port_enable_change: %d\n",
3771                         hsotg->flags.b.port_enable_change);
3772                 dev_dbg(hsotg->dev, "  port_suspend_change: %d\n",
3773                         hsotg->flags.b.port_suspend_change);
3774                 dev_dbg(hsotg->dev, "  port_over_current_change: %d\n",
3775                         hsotg->flags.b.port_over_current_change);
3776         }
3777
3778         return retval;
3779 }
3780
3781 int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
3782 {
3783         u32 hfnum = dwc2_readl(hsotg->regs + HFNUM);
3784
3785 #ifdef DWC2_DEBUG_SOF
3786         dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n",
3787                  (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT);
3788 #endif
3789         return (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT;
3790 }
3791
3792 int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us)
3793 {
3794         u32 hprt = dwc2_readl(hsotg->regs + HPRT0);
3795         u32 hfir = dwc2_readl(hsotg->regs + HFIR);
3796         u32 hfnum = dwc2_readl(hsotg->regs + HFNUM);
3797         unsigned int us_per_frame;
3798         unsigned int frame_number;
3799         unsigned int remaining;
3800         unsigned int interval;
3801         unsigned int phy_clks;
3802
3803         /* High speed has 125 us per (micro) frame; others are 1 ms per */
3804         us_per_frame = (hprt & HPRT0_SPD_MASK) ? 1000 : 125;
3805
3806         /* Extract fields */
3807         frame_number = (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT;
3808         remaining = (hfnum & HFNUM_FRREM_MASK) >> HFNUM_FRREM_SHIFT;
3809         interval = (hfir & HFIR_FRINT_MASK) >> HFIR_FRINT_SHIFT;
3810
3811         /*
3812          * Number of phy clocks since the last tick of the frame number after
3813          * "us" has passed.
3814          */
3815         phy_clks = (interval - remaining) +
3816                    DIV_ROUND_UP(interval * us, us_per_frame);
3817
3818         return dwc2_frame_num_inc(frame_number, phy_clks / interval);
3819 }
3820
3821 int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg)
3822 {
3823         return hsotg->op_state == OTG_STATE_B_HOST;
3824 }
3825
3826 static struct dwc2_hcd_urb *dwc2_hcd_urb_alloc(struct dwc2_hsotg *hsotg,
3827                                                int iso_desc_count,
3828                                                gfp_t mem_flags)
3829 {
3830         struct dwc2_hcd_urb *urb;
3831         u32 size = sizeof(*urb) + iso_desc_count *
3832                    sizeof(struct dwc2_hcd_iso_packet_desc);
3833
3834         urb = kzalloc(size, mem_flags);
3835         if (urb)
3836                 urb->packet_count = iso_desc_count;
3837         return urb;
3838 }
3839
3840 static void dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *hsotg,
3841                                       struct dwc2_hcd_urb *urb, u8 dev_addr,
3842                                       u8 ep_num, u8 ep_type, u8 ep_dir, u16 mps)
3843 {
3844         if (dbg_perio() ||
3845             ep_type == USB_ENDPOINT_XFER_BULK ||
3846             ep_type == USB_ENDPOINT_XFER_CONTROL)
3847                 dev_vdbg(hsotg->dev,
3848                          "addr=%d, ep_num=%d, ep_dir=%1x, ep_type=%1x, mps=%d\n",
3849                          dev_addr, ep_num, ep_dir, ep_type, mps);
3850         urb->pipe_info.dev_addr = dev_addr;
3851         urb->pipe_info.ep_num = ep_num;
3852         urb->pipe_info.pipe_type = ep_type;
3853         urb->pipe_info.pipe_dir = ep_dir;
3854         urb->pipe_info.mps = mps;
3855 }
3856
3857 /*
3858  * NOTE: This function will be removed once the peripheral controller code
3859  * is integrated and the driver is stable
3860  */
3861 void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg)
3862 {
3863 #ifdef DEBUG
3864         struct dwc2_host_chan *chan;
3865         struct dwc2_hcd_urb *urb;
3866         struct dwc2_qtd *qtd;
3867         int num_channels;
3868         u32 np_tx_status;
3869         u32 p_tx_status;
3870         int i;
3871
3872         num_channels = hsotg->params.host_channels;
3873         dev_dbg(hsotg->dev, "\n");
3874         dev_dbg(hsotg->dev,
3875                 "************************************************************\n");
3876         dev_dbg(hsotg->dev, "HCD State:\n");
3877         dev_dbg(hsotg->dev, "  Num channels: %d\n", num_channels);
3878
3879         for (i = 0; i < num_channels; i++) {
3880                 chan = hsotg->hc_ptr_array[i];
3881                 dev_dbg(hsotg->dev, "  Channel %d:\n", i);
3882                 dev_dbg(hsotg->dev,
3883                         "    dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
3884                         chan->dev_addr, chan->ep_num, chan->ep_is_in);
3885                 dev_dbg(hsotg->dev, "    speed: %d\n", chan->speed);
3886                 dev_dbg(hsotg->dev, "    ep_type: %d\n", chan->ep_type);
3887                 dev_dbg(hsotg->dev, "    max_packet: %d\n", chan->max_packet);
3888                 dev_dbg(hsotg->dev, "    data_pid_start: %d\n",
3889                         chan->data_pid_start);
3890                 dev_dbg(hsotg->dev, "    multi_count: %d\n", chan->multi_count);
3891                 dev_dbg(hsotg->dev, "    xfer_started: %d\n",
3892                         chan->xfer_started);
3893                 dev_dbg(hsotg->dev, "    xfer_buf: %p\n", chan->xfer_buf);
3894                 dev_dbg(hsotg->dev, "    xfer_dma: %08lx\n",
3895                         (unsigned long)chan->xfer_dma);
3896                 dev_dbg(hsotg->dev, "    xfer_len: %d\n", chan->xfer_len);
3897                 dev_dbg(hsotg->dev, "    xfer_count: %d\n", chan->xfer_count);
3898                 dev_dbg(hsotg->dev, "    halt_on_queue: %d\n",
3899                         chan->halt_on_queue);
3900                 dev_dbg(hsotg->dev, "    halt_pending: %d\n",
3901                         chan->halt_pending);
3902                 dev_dbg(hsotg->dev, "    halt_status: %d\n", chan->halt_status);
3903                 dev_dbg(hsotg->dev, "    do_split: %d\n", chan->do_split);
3904                 dev_dbg(hsotg->dev, "    complete_split: %d\n",
3905                         chan->complete_split);
3906                 dev_dbg(hsotg->dev, "    hub_addr: %d\n", chan->hub_addr);
3907                 dev_dbg(hsotg->dev, "    hub_port: %d\n", chan->hub_port);
3908                 dev_dbg(hsotg->dev, "    xact_pos: %d\n", chan->xact_pos);
3909                 dev_dbg(hsotg->dev, "    requests: %d\n", chan->requests);
3910                 dev_dbg(hsotg->dev, "    qh: %p\n", chan->qh);
3911
3912                 if (chan->xfer_started) {
3913                         u32 hfnum, hcchar, hctsiz, hcint, hcintmsk;
3914
3915                         hfnum = dwc2_readl(hsotg->regs + HFNUM);
3916                         hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
3917                         hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(i));
3918                         hcint = dwc2_readl(hsotg->regs + HCINT(i));
3919                         hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(i));
3920                         dev_dbg(hsotg->dev, "    hfnum: 0x%08x\n", hfnum);
3921                         dev_dbg(hsotg->dev, "    hcchar: 0x%08x\n", hcchar);
3922                         dev_dbg(hsotg->dev, "    hctsiz: 0x%08x\n", hctsiz);
3923                         dev_dbg(hsotg->dev, "    hcint: 0x%08x\n", hcint);
3924                         dev_dbg(hsotg->dev, "    hcintmsk: 0x%08x\n", hcintmsk);
3925                 }
3926
3927                 if (!(chan->xfer_started && chan->qh))
3928                         continue;
3929
3930                 list_for_each_entry(qtd, &chan->qh->qtd_list, qtd_list_entry) {
3931                         if (!qtd->in_process)
3932                                 break;
3933                         urb = qtd->urb;
3934                         dev_dbg(hsotg->dev, "    URB Info:\n");
3935                         dev_dbg(hsotg->dev, "      qtd: %p, urb: %p\n",
3936                                 qtd, urb);
3937                         if (urb) {
3938                                 dev_dbg(hsotg->dev,
3939                                         "      Dev: %d, EP: %d %s\n",
3940                                         dwc2_hcd_get_dev_addr(&urb->pipe_info),
3941                                         dwc2_hcd_get_ep_num(&urb->pipe_info),
3942                                         dwc2_hcd_is_pipe_in(&urb->pipe_info) ?
3943                                         "IN" : "OUT");
3944                                 dev_dbg(hsotg->dev,
3945                                         "      Max packet size: %d\n",
3946                                         dwc2_hcd_get_mps(&urb->pipe_info));
3947                                 dev_dbg(hsotg->dev,
3948                                         "      transfer_buffer: %p\n",
3949                                         urb->buf);
3950                                 dev_dbg(hsotg->dev,
3951                                         "      transfer_dma: %08lx\n",
3952                                         (unsigned long)urb->dma);
3953                                 dev_dbg(hsotg->dev,
3954                                         "      transfer_buffer_length: %d\n",
3955                                         urb->length);
3956                                 dev_dbg(hsotg->dev, "      actual_length: %d\n",
3957                                         urb->actual_length);
3958                         }
3959                 }
3960         }
3961
3962         dev_dbg(hsotg->dev, "  non_periodic_channels: %d\n",
3963                 hsotg->non_periodic_channels);
3964         dev_dbg(hsotg->dev, "  periodic_channels: %d\n",
3965                 hsotg->periodic_channels);
3966         dev_dbg(hsotg->dev, "  periodic_usecs: %d\n", hsotg->periodic_usecs);
3967         np_tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
3968         dev_dbg(hsotg->dev, "  NP Tx Req Queue Space Avail: %d\n",
3969                 (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
3970         dev_dbg(hsotg->dev, "  NP Tx FIFO Space Avail: %d\n",
3971                 (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
3972         p_tx_status = dwc2_readl(hsotg->regs + HPTXSTS);
3973         dev_dbg(hsotg->dev, "  P Tx Req Queue Space Avail: %d\n",
3974                 (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
3975         dev_dbg(hsotg->dev, "  P Tx FIFO Space Avail: %d\n",
3976                 (p_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
3977         dwc2_hcd_dump_frrem(hsotg);
3978         dwc2_dump_global_registers(hsotg);
3979         dwc2_dump_host_registers(hsotg);
3980         dev_dbg(hsotg->dev,
3981                 "************************************************************\n");
3982         dev_dbg(hsotg->dev, "\n");
3983 #endif
3984 }
3985
3986 /*
3987  * NOTE: This function will be removed once the peripheral controller code
3988  * is integrated and the driver is stable
3989  */
3990 void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg)
3991 {
3992 #ifdef DWC2_DUMP_FRREM
3993         dev_dbg(hsotg->dev, "Frame remaining at SOF:\n");
3994         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
3995                 hsotg->frrem_samples, hsotg->frrem_accum,
3996                 hsotg->frrem_samples > 0 ?
3997                 hsotg->frrem_accum / hsotg->frrem_samples : 0);
3998         dev_dbg(hsotg->dev, "\n");
3999         dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 7):\n");
4000         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
4001                 hsotg->hfnum_7_samples,
4002                 hsotg->hfnum_7_frrem_accum,
4003                 hsotg->hfnum_7_samples > 0 ?
4004                 hsotg->hfnum_7_frrem_accum / hsotg->hfnum_7_samples : 0);
4005         dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 0):\n");
4006         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
4007                 hsotg->hfnum_0_samples,
4008                 hsotg->hfnum_0_frrem_accum,
4009                 hsotg->hfnum_0_samples > 0 ?
4010                 hsotg->hfnum_0_frrem_accum / hsotg->hfnum_0_samples : 0);
4011         dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 1-6):\n");
4012         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
4013                 hsotg->hfnum_other_samples,
4014                 hsotg->hfnum_other_frrem_accum,
4015                 hsotg->hfnum_other_samples > 0 ?
4016                 hsotg->hfnum_other_frrem_accum / hsotg->hfnum_other_samples :
4017                 0);
4018         dev_dbg(hsotg->dev, "\n");
4019         dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 7):\n");
4020         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
4021                 hsotg->hfnum_7_samples_a, hsotg->hfnum_7_frrem_accum_a,
4022                 hsotg->hfnum_7_samples_a > 0 ?
4023                 hsotg->hfnum_7_frrem_accum_a / hsotg->hfnum_7_samples_a : 0);
4024         dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 0):\n");
4025         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
4026                 hsotg->hfnum_0_samples_a, hsotg->hfnum_0_frrem_accum_a,
4027                 hsotg->hfnum_0_samples_a > 0 ?
4028                 hsotg->hfnum_0_frrem_accum_a / hsotg->hfnum_0_samples_a : 0);
4029         dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 1-6):\n");
4030         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
4031                 hsotg->hfnum_other_samples_a, hsotg->hfnum_other_frrem_accum_a,
4032                 hsotg->hfnum_other_samples_a > 0 ?
4033                 hsotg->hfnum_other_frrem_accum_a / hsotg->hfnum_other_samples_a
4034                 : 0);
4035         dev_dbg(hsotg->dev, "\n");
4036         dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 7):\n");
4037         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
4038                 hsotg->hfnum_7_samples_b, hsotg->hfnum_7_frrem_accum_b,
4039                 hsotg->hfnum_7_samples_b > 0 ?
4040                 hsotg->hfnum_7_frrem_accum_b / hsotg->hfnum_7_samples_b : 0);
4041         dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 0):\n");
4042         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
4043                 hsotg->hfnum_0_samples_b, hsotg->hfnum_0_frrem_accum_b,
4044                 (hsotg->hfnum_0_samples_b > 0) ?
4045                 hsotg->hfnum_0_frrem_accum_b / hsotg->hfnum_0_samples_b : 0);
4046         dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 1-6):\n");
4047         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
4048                 hsotg->hfnum_other_samples_b, hsotg->hfnum_other_frrem_accum_b,
4049                 (hsotg->hfnum_other_samples_b > 0) ?
4050                 hsotg->hfnum_other_frrem_accum_b / hsotg->hfnum_other_samples_b
4051                 : 0);
4052 #endif
4053 }
4054
4055 struct wrapper_priv_data {
4056         struct dwc2_hsotg *hsotg;
4057 };
4058
4059 /* Gets the dwc2_hsotg from a usb_hcd */
4060 static struct dwc2_hsotg *dwc2_hcd_to_hsotg(struct usb_hcd *hcd)
4061 {
4062         struct wrapper_priv_data *p;
4063
4064         p = (struct wrapper_priv_data *)&hcd->hcd_priv;
4065         return p->hsotg;
4066 }
4067
4068 /**
4069  * dwc2_host_get_tt_info() - Get the dwc2_tt associated with context
4070  *
4071  * This will get the dwc2_tt structure (and ttport) associated with the given
4072  * context (which is really just a struct urb pointer).
4073  *
4074  * The first time this is called for a given TT we allocate memory for our
4075  * structure.  When everyone is done and has called dwc2_host_put_tt_info()
4076  * then the refcount for the structure will go to 0 and we'll free it.
4077  *
4078  * @hsotg:     The HCD state structure for the DWC OTG controller.
4079  * @qh:        The QH structure.
4080  * @context:   The priv pointer from a struct dwc2_hcd_urb.
4081  * @mem_flags: Flags for allocating memory.
4082  * @ttport:    We'll return this device's port number here.  That's used to
4083  *             reference into the bitmap if we're on a multi_tt hub.
4084  *
4085  * Return: a pointer to a struct dwc2_tt.  Don't forget to call
4086  *         dwc2_host_put_tt_info()!  Returns NULL upon memory alloc failure.
4087  */
4088
4089 struct dwc2_tt *dwc2_host_get_tt_info(struct dwc2_hsotg *hsotg, void *context,
4090                                       gfp_t mem_flags, int *ttport)
4091 {
4092         struct urb *urb = context;
4093         struct dwc2_tt *dwc_tt = NULL;
4094
4095         if (urb->dev->tt) {
4096                 *ttport = urb->dev->ttport;
4097
4098                 dwc_tt = urb->dev->tt->hcpriv;
4099                 if (!dwc_tt) {
4100                         size_t bitmap_size;
4101
4102                         /*
4103                          * For single_tt we need one schedule.  For multi_tt
4104                          * we need one per port.
4105                          */
4106                         bitmap_size = DWC2_ELEMENTS_PER_LS_BITMAP *
4107                                       sizeof(dwc_tt->periodic_bitmaps[0]);
4108                         if (urb->dev->tt->multi)
4109                                 bitmap_size *= urb->dev->tt->hub->maxchild;
4110
4111                         dwc_tt = kzalloc(sizeof(*dwc_tt) + bitmap_size,
4112                                          mem_flags);
4113                         if (!dwc_tt)
4114                                 return NULL;
4115
4116                         dwc_tt->usb_tt = urb->dev->tt;
4117                         dwc_tt->usb_tt->hcpriv = dwc_tt;
4118                 }
4119
4120                 dwc_tt->refcount++;
4121         }
4122
4123         return dwc_tt;
4124 }
4125
4126 /**
4127  * dwc2_host_put_tt_info() - Put the dwc2_tt from dwc2_host_get_tt_info()
4128  *
4129  * Frees resources allocated by dwc2_host_get_tt_info() if all current holders
4130  * of the structure are done.
4131  *
4132  * It's OK to call this with NULL.
4133  *
4134  * @hsotg:     The HCD state structure for the DWC OTG controller.
4135  * @dwc_tt:    The pointer returned by dwc2_host_get_tt_info.
4136  */
4137 void dwc2_host_put_tt_info(struct dwc2_hsotg *hsotg, struct dwc2_tt *dwc_tt)
4138 {
4139         /* Model kfree and make put of NULL a no-op */
4140         if (!dwc_tt)
4141                 return;
4142
4143         WARN_ON(dwc_tt->refcount < 1);
4144
4145         dwc_tt->refcount--;
4146         if (!dwc_tt->refcount) {
4147                 dwc_tt->usb_tt->hcpriv = NULL;
4148                 kfree(dwc_tt);
4149         }
4150 }
4151
4152 int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context)
4153 {
4154         struct urb *urb = context;
4155
4156         return urb->dev->speed;
4157 }
4158
4159 static void dwc2_allocate_bus_bandwidth(struct usb_hcd *hcd, u16 bw,
4160                                         struct urb *urb)
4161 {
4162         struct usb_bus *bus = hcd_to_bus(hcd);
4163
4164         if (urb->interval)
4165                 bus->bandwidth_allocated += bw / urb->interval;
4166         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
4167                 bus->bandwidth_isoc_reqs++;
4168         else
4169                 bus->bandwidth_int_reqs++;
4170 }
4171
4172 static void dwc2_free_bus_bandwidth(struct usb_hcd *hcd, u16 bw,
4173                                     struct urb *urb)
4174 {
4175         struct usb_bus *bus = hcd_to_bus(hcd);
4176
4177         if (urb->interval)
4178                 bus->bandwidth_allocated -= bw / urb->interval;
4179         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
4180                 bus->bandwidth_isoc_reqs--;
4181         else
4182                 bus->bandwidth_int_reqs--;
4183 }
4184
4185 /*
4186  * Sets the final status of an URB and returns it to the upper layer. Any
4187  * required cleanup of the URB is performed.
4188  *
4189  * Must be called with interrupt disabled and spinlock held
4190  */
4191 void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
4192                         int status)
4193 {
4194         struct urb *urb;
4195         int i;
4196
4197         if (!qtd) {
4198                 dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__);
4199                 return;
4200         }
4201
4202         if (!qtd->urb) {
4203                 dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__);
4204                 return;
4205         }
4206
4207         urb = qtd->urb->priv;
4208         if (!urb) {
4209                 dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__);
4210                 return;
4211         }
4212
4213         urb->actual_length = dwc2_hcd_urb_get_actual_length(qtd->urb);
4214
4215         if (dbg_urb(urb))
4216                 dev_vdbg(hsotg->dev,
4217                          "%s: urb %p device %d ep %d-%s status %d actual %d\n",
4218                          __func__, urb, usb_pipedevice(urb->pipe),
4219                          usb_pipeendpoint(urb->pipe),
4220                          usb_pipein(urb->pipe) ? "IN" : "OUT", status,
4221                          urb->actual_length);
4222
4223         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
4224                 urb->error_count = dwc2_hcd_urb_get_error_count(qtd->urb);
4225                 for (i = 0; i < urb->number_of_packets; ++i) {
4226                         urb->iso_frame_desc[i].actual_length =
4227                                 dwc2_hcd_urb_get_iso_desc_actual_length(
4228                                                 qtd->urb, i);
4229                         urb->iso_frame_desc[i].status =
4230                                 dwc2_hcd_urb_get_iso_desc_status(qtd->urb, i);
4231                 }
4232         }
4233
4234         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS && dbg_perio()) {
4235                 for (i = 0; i < urb->number_of_packets; i++)
4236                         dev_vdbg(hsotg->dev, " ISO Desc %d status %d\n",
4237                                  i, urb->iso_frame_desc[i].status);
4238         }
4239
4240         urb->status = status;
4241         if (!status) {
4242                 if ((urb->transfer_flags & URB_SHORT_NOT_OK) &&
4243                     urb->actual_length < urb->transfer_buffer_length)
4244                         urb->status = -EREMOTEIO;
4245         }
4246
4247         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
4248             usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
4249                 struct usb_host_endpoint *ep = urb->ep;
4250
4251                 if (ep)
4252                         dwc2_free_bus_bandwidth(dwc2_hsotg_to_hcd(hsotg),
4253                                         dwc2_hcd_get_ep_bandwidth(hsotg, ep),
4254                                         urb);
4255         }
4256
4257         usb_hcd_unlink_urb_from_ep(dwc2_hsotg_to_hcd(hsotg), urb);
4258         urb->hcpriv = NULL;
4259         kfree(qtd->urb);
4260         qtd->urb = NULL;
4261
4262         usb_hcd_giveback_urb(dwc2_hsotg_to_hcd(hsotg), urb, status);
4263 }
4264
4265 /*
4266  * Work queue function for starting the HCD when A-Cable is connected
4267  */
4268 static void dwc2_hcd_start_func(struct work_struct *work)
4269 {
4270         struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
4271                                                 start_work.work);
4272
4273         dev_dbg(hsotg->dev, "%s() %p\n", __func__, hsotg);
4274         dwc2_host_start(hsotg);
4275 }
4276
4277 /*
4278  * Reset work queue function
4279  */
4280 static void dwc2_hcd_reset_func(struct work_struct *work)
4281 {
4282         struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
4283                                                 reset_work.work);
4284         unsigned long flags;
4285         u32 hprt0;
4286
4287         dev_dbg(hsotg->dev, "USB RESET function called\n");
4288
4289         spin_lock_irqsave(&hsotg->lock, flags);
4290
4291         hprt0 = dwc2_read_hprt0(hsotg);
4292         hprt0 &= ~HPRT0_RST;
4293         dwc2_writel(hprt0, hsotg->regs + HPRT0);
4294         hsotg->flags.b.port_reset_change = 1;
4295
4296         spin_unlock_irqrestore(&hsotg->lock, flags);
4297 }
4298
4299 /*
4300  * =========================================================================
4301  *  Linux HC Driver Functions
4302  * =========================================================================
4303  */
4304
4305 /*
4306  * Initializes the DWC_otg controller and its root hub and prepares it for host
4307  * mode operation. Activates the root port. Returns 0 on success and a negative
4308  * error code on failure.
4309  */
4310 static int _dwc2_hcd_start(struct usb_hcd *hcd)
4311 {
4312         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4313         struct usb_bus *bus = hcd_to_bus(hcd);
4314         unsigned long flags;
4315
4316         dev_dbg(hsotg->dev, "DWC OTG HCD START\n");
4317
4318         spin_lock_irqsave(&hsotg->lock, flags);
4319         hsotg->lx_state = DWC2_L0;
4320         hcd->state = HC_STATE_RUNNING;
4321         set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4322
4323         if (dwc2_is_device_mode(hsotg)) {
4324                 spin_unlock_irqrestore(&hsotg->lock, flags);
4325                 return 0;       /* why 0 ?? */
4326         }
4327
4328         dwc2_hcd_reinit(hsotg);
4329
4330         /* Initialize and connect root hub if one is not already attached */
4331         if (bus->root_hub) {
4332                 dev_dbg(hsotg->dev, "DWC OTG HCD Has Root Hub\n");
4333                 /* Inform the HUB driver to resume */
4334                 usb_hcd_resume_root_hub(hcd);
4335         }
4336
4337         spin_unlock_irqrestore(&hsotg->lock, flags);
4338         return 0;
4339 }
4340
4341 /*
4342  * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
4343  * stopped.
4344  */
4345 static void _dwc2_hcd_stop(struct usb_hcd *hcd)
4346 {
4347         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4348         unsigned long flags;
4349
4350         /* Turn off all host-specific interrupts */
4351         dwc2_disable_host_interrupts(hsotg);
4352
4353         /* Wait for interrupt processing to finish */
4354         synchronize_irq(hcd->irq);
4355
4356         spin_lock_irqsave(&hsotg->lock, flags);
4357         /* Ensure hcd is disconnected */
4358         dwc2_hcd_disconnect(hsotg, true);
4359         dwc2_hcd_stop(hsotg);
4360         hsotg->lx_state = DWC2_L3;
4361         hcd->state = HC_STATE_HALT;
4362         clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4363         spin_unlock_irqrestore(&hsotg->lock, flags);
4364
4365         usleep_range(1000, 3000);
4366 }
4367
4368 static int _dwc2_hcd_suspend(struct usb_hcd *hcd)
4369 {
4370         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4371         unsigned long flags;
4372         int ret = 0;
4373         u32 hprt0;
4374
4375         spin_lock_irqsave(&hsotg->lock, flags);
4376
4377         if (hsotg->lx_state != DWC2_L0)
4378                 goto unlock;
4379
4380         if (!HCD_HW_ACCESSIBLE(hcd))
4381                 goto unlock;
4382
4383         if (!hsotg->params.hibernation)
4384                 goto skip_power_saving;
4385
4386         /*
4387          * Drive USB suspend and disable port Power
4388          * if usb bus is not suspended.
4389          */
4390         if (!hsotg->bus_suspended) {
4391                 hprt0 = dwc2_read_hprt0(hsotg);
4392                 hprt0 |= HPRT0_SUSP;
4393                 hprt0 &= ~HPRT0_PWR;
4394                 dwc2_writel(hprt0, hsotg->regs + HPRT0);
4395         }
4396
4397         /* Enter hibernation */
4398         ret = dwc2_enter_hibernation(hsotg);
4399         if (ret) {
4400                 if (ret != -ENOTSUPP)
4401                         dev_err(hsotg->dev,
4402                                 "enter hibernation failed\n");
4403                 goto skip_power_saving;
4404         }
4405
4406         /* Ask phy to be suspended */
4407         if (!IS_ERR_OR_NULL(hsotg->uphy)) {
4408                 spin_unlock_irqrestore(&hsotg->lock, flags);
4409                 usb_phy_set_suspend(hsotg->uphy, true);
4410                 spin_lock_irqsave(&hsotg->lock, flags);
4411         }
4412
4413         /* After entering hibernation, hardware is no more accessible */
4414         clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4415
4416 skip_power_saving:
4417         hsotg->lx_state = DWC2_L2;
4418 unlock:
4419         spin_unlock_irqrestore(&hsotg->lock, flags);
4420
4421         return ret;
4422 }
4423
4424 static int _dwc2_hcd_resume(struct usb_hcd *hcd)
4425 {
4426         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4427         unsigned long flags;
4428         int ret = 0;
4429
4430         spin_lock_irqsave(&hsotg->lock, flags);
4431
4432         if (hsotg->lx_state != DWC2_L2)
4433                 goto unlock;
4434
4435         if (!hsotg->params.hibernation) {
4436                 hsotg->lx_state = DWC2_L0;
4437                 goto unlock;
4438         }
4439
4440         /*
4441          * Set HW accessible bit before powering on the controller
4442          * since an interrupt may rise.
4443          */
4444         set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4445
4446         /*
4447          * Enable power if not already done.
4448          * This must not be spinlocked since duration
4449          * of this call is unknown.
4450          */
4451         if (!IS_ERR_OR_NULL(hsotg->uphy)) {
4452                 spin_unlock_irqrestore(&hsotg->lock, flags);
4453                 usb_phy_set_suspend(hsotg->uphy, false);
4454                 spin_lock_irqsave(&hsotg->lock, flags);
4455         }
4456
4457         /* Exit hibernation */
4458         ret = dwc2_exit_hibernation(hsotg, true);
4459         if (ret && (ret != -ENOTSUPP))
4460                 dev_err(hsotg->dev, "exit hibernation failed\n");
4461
4462         hsotg->lx_state = DWC2_L0;
4463
4464         spin_unlock_irqrestore(&hsotg->lock, flags);
4465
4466         if (hsotg->bus_suspended) {
4467                 spin_lock_irqsave(&hsotg->lock, flags);
4468                 hsotg->flags.b.port_suspend_change = 1;
4469                 spin_unlock_irqrestore(&hsotg->lock, flags);
4470                 dwc2_port_resume(hsotg);
4471         } else {
4472                 /* Wait for controller to correctly update D+/D- level */
4473                 usleep_range(3000, 5000);
4474
4475                 /*
4476                  * Clear Port Enable and Port Status changes.
4477                  * Enable Port Power.
4478                  */
4479                 dwc2_writel(HPRT0_PWR | HPRT0_CONNDET |
4480                                 HPRT0_ENACHG, hsotg->regs + HPRT0);
4481                 /* Wait for controller to detect Port Connect */
4482                 usleep_range(5000, 7000);
4483         }
4484
4485         return ret;
4486 unlock:
4487         spin_unlock_irqrestore(&hsotg->lock, flags);
4488
4489         return ret;
4490 }
4491
4492 /* Returns the current frame number */
4493 static int _dwc2_hcd_get_frame_number(struct usb_hcd *hcd)
4494 {
4495         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4496
4497         return dwc2_hcd_get_frame_number(hsotg);
4498 }
4499
4500 static void dwc2_dump_urb_info(struct usb_hcd *hcd, struct urb *urb,
4501                                char *fn_name)
4502 {
4503 #ifdef VERBOSE_DEBUG
4504         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4505         char *pipetype;
4506         char *speed;
4507
4508         dev_vdbg(hsotg->dev, "%s, urb %p\n", fn_name, urb);
4509         dev_vdbg(hsotg->dev, "  Device address: %d\n",
4510                  usb_pipedevice(urb->pipe));
4511         dev_vdbg(hsotg->dev, "  Endpoint: %d, %s\n",
4512                  usb_pipeendpoint(urb->pipe),
4513                  usb_pipein(urb->pipe) ? "IN" : "OUT");
4514
4515         switch (usb_pipetype(urb->pipe)) {
4516         case PIPE_CONTROL:
4517                 pipetype = "CONTROL";
4518                 break;
4519         case PIPE_BULK:
4520                 pipetype = "BULK";
4521                 break;
4522         case PIPE_INTERRUPT:
4523                 pipetype = "INTERRUPT";
4524                 break;
4525         case PIPE_ISOCHRONOUS:
4526                 pipetype = "ISOCHRONOUS";
4527                 break;
4528         }
4529
4530         dev_vdbg(hsotg->dev, "  Endpoint type: %s %s (%s)\n", pipetype,
4531                  usb_urb_dir_in(urb) ? "IN" : "OUT", usb_pipein(urb->pipe) ?
4532                  "IN" : "OUT");
4533
4534         switch (urb->dev->speed) {
4535         case USB_SPEED_HIGH:
4536                 speed = "HIGH";
4537                 break;
4538         case USB_SPEED_FULL:
4539                 speed = "FULL";
4540                 break;
4541         case USB_SPEED_LOW:
4542                 speed = "LOW";
4543                 break;
4544         default:
4545                 speed = "UNKNOWN";
4546                 break;
4547         }
4548
4549         dev_vdbg(hsotg->dev, "  Speed: %s\n", speed);
4550         dev_vdbg(hsotg->dev, "  Max packet size: %d\n",
4551                  usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
4552         dev_vdbg(hsotg->dev, "  Data buffer length: %d\n",
4553                  urb->transfer_buffer_length);
4554         dev_vdbg(hsotg->dev, "  Transfer buffer: %p, Transfer DMA: %08lx\n",
4555                  urb->transfer_buffer, (unsigned long)urb->transfer_dma);
4556         dev_vdbg(hsotg->dev, "  Setup buffer: %p, Setup DMA: %08lx\n",
4557                  urb->setup_packet, (unsigned long)urb->setup_dma);
4558         dev_vdbg(hsotg->dev, "  Interval: %d\n", urb->interval);
4559
4560         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
4561                 int i;
4562
4563                 for (i = 0; i < urb->number_of_packets; i++) {
4564                         dev_vdbg(hsotg->dev, "  ISO Desc %d:\n", i);
4565                         dev_vdbg(hsotg->dev, "    offset: %d, length %d\n",
4566                                  urb->iso_frame_desc[i].offset,
4567                                  urb->iso_frame_desc[i].length);
4568                 }
4569         }
4570 #endif
4571 }
4572
4573 /*
4574  * Starts processing a USB transfer request specified by a USB Request Block
4575  * (URB). mem_flags indicates the type of memory allocation to use while
4576  * processing this URB.
4577  */
4578 static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
4579                                  gfp_t mem_flags)
4580 {
4581         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4582         struct usb_host_endpoint *ep = urb->ep;
4583         struct dwc2_hcd_urb *dwc2_urb;
4584         int i;
4585         int retval;
4586         int alloc_bandwidth = 0;
4587         u8 ep_type = 0;
4588         u32 tflags = 0;
4589         void *buf;
4590         unsigned long flags;
4591         struct dwc2_qh *qh;
4592         bool qh_allocated = false;
4593         struct dwc2_qtd *qtd;
4594
4595         if (dbg_urb(urb)) {
4596                 dev_vdbg(hsotg->dev, "DWC OTG HCD URB Enqueue\n");
4597                 dwc2_dump_urb_info(hcd, urb, "urb_enqueue");
4598         }
4599
4600         if (!ep)
4601                 return -EINVAL;
4602
4603         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
4604             usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
4605                 spin_lock_irqsave(&hsotg->lock, flags);
4606                 if (!dwc2_hcd_is_bandwidth_allocated(hsotg, ep))
4607                         alloc_bandwidth = 1;
4608                 spin_unlock_irqrestore(&hsotg->lock, flags);
4609         }
4610
4611         switch (usb_pipetype(urb->pipe)) {
4612         case PIPE_CONTROL:
4613                 ep_type = USB_ENDPOINT_XFER_CONTROL;
4614                 break;
4615         case PIPE_ISOCHRONOUS:
4616                 ep_type = USB_ENDPOINT_XFER_ISOC;
4617                 break;
4618         case PIPE_BULK:
4619                 ep_type = USB_ENDPOINT_XFER_BULK;
4620                 break;
4621         case PIPE_INTERRUPT:
4622                 ep_type = USB_ENDPOINT_XFER_INT;
4623                 break;
4624         }
4625
4626         dwc2_urb = dwc2_hcd_urb_alloc(hsotg, urb->number_of_packets,
4627                                       mem_flags);
4628         if (!dwc2_urb)
4629                 return -ENOMEM;
4630
4631         dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, usb_pipedevice(urb->pipe),
4632                                   usb_pipeendpoint(urb->pipe), ep_type,
4633                                   usb_pipein(urb->pipe),
4634                                   usb_maxpacket(urb->dev, urb->pipe,
4635                                                 !(usb_pipein(urb->pipe))));
4636
4637         buf = urb->transfer_buffer;
4638
4639         if (hcd->self.uses_dma) {
4640                 if (!buf && (urb->transfer_dma & 3)) {
4641                         dev_err(hsotg->dev,
4642                                 "%s: unaligned transfer with no transfer_buffer",
4643                                 __func__);
4644                         retval = -EINVAL;
4645                         goto fail0;
4646                 }
4647         }
4648
4649         if (!(urb->transfer_flags & URB_NO_INTERRUPT))
4650                 tflags |= URB_GIVEBACK_ASAP;
4651         if (urb->transfer_flags & URB_ZERO_PACKET)
4652                 tflags |= URB_SEND_ZERO_PACKET;
4653
4654         dwc2_urb->priv = urb;
4655         dwc2_urb->buf = buf;
4656         dwc2_urb->dma = urb->transfer_dma;
4657         dwc2_urb->length = urb->transfer_buffer_length;
4658         dwc2_urb->setup_packet = urb->setup_packet;
4659         dwc2_urb->setup_dma = urb->setup_dma;
4660         dwc2_urb->flags = tflags;
4661         dwc2_urb->interval = urb->interval;
4662         dwc2_urb->status = -EINPROGRESS;
4663
4664         for (i = 0; i < urb->number_of_packets; ++i)
4665                 dwc2_hcd_urb_set_iso_desc_params(dwc2_urb, i,
4666                                                  urb->iso_frame_desc[i].offset,
4667                                                  urb->iso_frame_desc[i].length);
4668
4669         urb->hcpriv = dwc2_urb;
4670         qh = (struct dwc2_qh *)ep->hcpriv;
4671         /* Create QH for the endpoint if it doesn't exist */
4672         if (!qh) {
4673                 qh = dwc2_hcd_qh_create(hsotg, dwc2_urb, mem_flags);
4674                 if (!qh) {
4675                         retval = -ENOMEM;
4676                         goto fail0;
4677                 }
4678                 ep->hcpriv = qh;
4679                 qh_allocated = true;
4680         }
4681
4682         qtd = kzalloc(sizeof(*qtd), mem_flags);
4683         if (!qtd) {
4684                 retval = -ENOMEM;
4685                 goto fail1;
4686         }
4687
4688         spin_lock_irqsave(&hsotg->lock, flags);
4689         retval = usb_hcd_link_urb_to_ep(hcd, urb);
4690         if (retval)
4691                 goto fail2;
4692
4693         retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, qh, qtd);
4694         if (retval)
4695                 goto fail3;
4696
4697         if (alloc_bandwidth) {
4698                 dwc2_allocate_bus_bandwidth(hcd,
4699                                 dwc2_hcd_get_ep_bandwidth(hsotg, ep),
4700                                 urb);
4701         }
4702
4703         spin_unlock_irqrestore(&hsotg->lock, flags);
4704
4705         return 0;
4706
4707 fail3:
4708         dwc2_urb->priv = NULL;
4709         usb_hcd_unlink_urb_from_ep(hcd, urb);
4710         if (qh_allocated && qh->channel && qh->channel->qh == qh)
4711                 qh->channel->qh = NULL;
4712 fail2:
4713         spin_unlock_irqrestore(&hsotg->lock, flags);
4714         urb->hcpriv = NULL;
4715         kfree(qtd);
4716         qtd = NULL;
4717 fail1:
4718         if (qh_allocated) {
4719                 struct dwc2_qtd *qtd2, *qtd2_tmp;
4720
4721                 ep->hcpriv = NULL;
4722                 dwc2_hcd_qh_unlink(hsotg, qh);
4723                 /* Free each QTD in the QH's QTD list */
4724                 list_for_each_entry_safe(qtd2, qtd2_tmp, &qh->qtd_list,
4725                                          qtd_list_entry)
4726                         dwc2_hcd_qtd_unlink_and_free(hsotg, qtd2, qh);
4727                 dwc2_hcd_qh_free(hsotg, qh);
4728         }
4729 fail0:
4730         kfree(dwc2_urb);
4731
4732         return retval;
4733 }
4734
4735 /*
4736  * Aborts/cancels a USB transfer request. Always returns 0 to indicate success.
4737  */
4738 static int _dwc2_hcd_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
4739                                  int status)
4740 {
4741         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4742         int rc;
4743         unsigned long flags;
4744
4745         dev_dbg(hsotg->dev, "DWC OTG HCD URB Dequeue\n");
4746         dwc2_dump_urb_info(hcd, urb, "urb_dequeue");
4747
4748         spin_lock_irqsave(&hsotg->lock, flags);
4749
4750         rc = usb_hcd_check_unlink_urb(hcd, urb, status);
4751         if (rc)
4752                 goto out;
4753
4754         if (!urb->hcpriv) {
4755                 dev_dbg(hsotg->dev, "## urb->hcpriv is NULL ##\n");
4756                 goto out;
4757         }
4758
4759         rc = dwc2_hcd_urb_dequeue(hsotg, urb->hcpriv);
4760
4761         usb_hcd_unlink_urb_from_ep(hcd, urb);
4762
4763         kfree(urb->hcpriv);
4764         urb->hcpriv = NULL;
4765
4766         /* Higher layer software sets URB status */
4767         spin_unlock(&hsotg->lock);
4768         usb_hcd_giveback_urb(hcd, urb, status);
4769         spin_lock(&hsotg->lock);
4770
4771         dev_dbg(hsotg->dev, "Called usb_hcd_giveback_urb()\n");
4772         dev_dbg(hsotg->dev, "  urb->status = %d\n", urb->status);
4773 out:
4774         spin_unlock_irqrestore(&hsotg->lock, flags);
4775
4776         return rc;
4777 }
4778
4779 /*
4780  * Frees resources in the DWC_otg controller related to a given endpoint. Also
4781  * clears state in the HCD related to the endpoint. Any URBs for the endpoint
4782  * must already be dequeued.
4783  */
4784 static void _dwc2_hcd_endpoint_disable(struct usb_hcd *hcd,
4785                                        struct usb_host_endpoint *ep)
4786 {
4787         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4788
4789         dev_dbg(hsotg->dev,
4790                 "DWC OTG HCD EP DISABLE: bEndpointAddress=0x%02x, ep->hcpriv=%p\n",
4791                 ep->desc.bEndpointAddress, ep->hcpriv);
4792         dwc2_hcd_endpoint_disable(hsotg, ep, 250);
4793 }
4794
4795 /*
4796  * Resets endpoint specific parameter values, in current version used to reset
4797  * the data toggle (as a WA). This function can be called from usb_clear_halt
4798  * routine.
4799  */
4800 static void _dwc2_hcd_endpoint_reset(struct usb_hcd *hcd,
4801                                      struct usb_host_endpoint *ep)
4802 {
4803         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4804         unsigned long flags;
4805
4806         dev_dbg(hsotg->dev,
4807                 "DWC OTG HCD EP RESET: bEndpointAddress=0x%02x\n",
4808                 ep->desc.bEndpointAddress);
4809
4810         spin_lock_irqsave(&hsotg->lock, flags);
4811         dwc2_hcd_endpoint_reset(hsotg, ep);
4812         spin_unlock_irqrestore(&hsotg->lock, flags);
4813 }
4814
4815 /*
4816  * Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if
4817  * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid
4818  * interrupt.
4819  *
4820  * This function is called by the USB core when an interrupt occurs
4821  */
4822 static irqreturn_t _dwc2_hcd_irq(struct usb_hcd *hcd)
4823 {
4824         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4825
4826         return dwc2_handle_hcd_intr(hsotg);
4827 }
4828
4829 /*
4830  * Creates Status Change bitmap for the root hub and root port. The bitmap is
4831  * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1
4832  * is the status change indicator for the single root port. Returns 1 if either
4833  * change indicator is 1, otherwise returns 0.
4834  */
4835 static int _dwc2_hcd_hub_status_data(struct usb_hcd *hcd, char *buf)
4836 {
4837         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4838
4839         buf[0] = dwc2_hcd_is_status_changed(hsotg, 1) << 1;
4840         return buf[0] != 0;
4841 }
4842
4843 /* Handles hub class-specific requests */
4844 static int _dwc2_hcd_hub_control(struct usb_hcd *hcd, u16 typereq, u16 wvalue,
4845                                  u16 windex, char *buf, u16 wlength)
4846 {
4847         int retval = dwc2_hcd_hub_control(dwc2_hcd_to_hsotg(hcd), typereq,
4848                                           wvalue, windex, buf, wlength);
4849         return retval;
4850 }
4851
4852 /* Handles hub TT buffer clear completions */
4853 static void _dwc2_hcd_clear_tt_buffer_complete(struct usb_hcd *hcd,
4854                                                struct usb_host_endpoint *ep)
4855 {
4856         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4857         struct dwc2_qh *qh;
4858         unsigned long flags;
4859
4860         qh = ep->hcpriv;
4861         if (!qh)
4862                 return;
4863
4864         spin_lock_irqsave(&hsotg->lock, flags);
4865         qh->tt_buffer_dirty = 0;
4866
4867         if (hsotg->flags.b.port_connect_status)
4868                 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_ALL);
4869
4870         spin_unlock_irqrestore(&hsotg->lock, flags);
4871 }
4872
4873 /*
4874  * HPRT0_SPD_HIGH_SPEED: high speed
4875  * HPRT0_SPD_FULL_SPEED: full speed
4876  */
4877 static void dwc2_change_bus_speed(struct usb_hcd *hcd, int speed)
4878 {
4879         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4880
4881         if (hsotg->params.speed == speed)
4882                 return;
4883
4884         hsotg->params.speed = speed;
4885         queue_work(hsotg->wq_otg, &hsotg->wf_otg);
4886 }
4887
4888 static void dwc2_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
4889 {
4890         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4891
4892         if (!hsotg->params.change_speed_quirk)
4893                 return;
4894
4895         /*
4896          * On removal, set speed to default high-speed.
4897          */
4898         if (udev->parent && udev->parent->speed > USB_SPEED_UNKNOWN &&
4899             udev->parent->speed < USB_SPEED_HIGH) {
4900                 dev_info(hsotg->dev, "Set speed to default high-speed\n");
4901                 dwc2_change_bus_speed(hcd, HPRT0_SPD_HIGH_SPEED);
4902         }
4903 }
4904
4905 static int dwc2_reset_device(struct usb_hcd *hcd, struct usb_device *udev)
4906 {
4907         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4908
4909         if (!hsotg->params.change_speed_quirk)
4910                 return 0;
4911
4912         if (udev->speed == USB_SPEED_HIGH) {
4913                 dev_info(hsotg->dev, "Set speed to high-speed\n");
4914                 dwc2_change_bus_speed(hcd, HPRT0_SPD_HIGH_SPEED);
4915         } else if ((udev->speed == USB_SPEED_FULL ||
4916                                 udev->speed == USB_SPEED_LOW)) {
4917                 /*
4918                  * Change speed setting to full-speed if there's
4919                  * a full-speed or low-speed device plugged in.
4920                  */
4921                 dev_info(hsotg->dev, "Set speed to full-speed\n");
4922                 dwc2_change_bus_speed(hcd, HPRT0_SPD_FULL_SPEED);
4923         }
4924
4925         return 0;
4926 }
4927
4928 static struct hc_driver dwc2_hc_driver = {
4929         .description = "dwc2_hsotg",
4930         .product_desc = "DWC OTG Controller",
4931         .hcd_priv_size = sizeof(struct wrapper_priv_data),
4932
4933         .irq = _dwc2_hcd_irq,
4934         .flags = HCD_MEMORY | HCD_USB2 | HCD_BH,
4935
4936         .start = _dwc2_hcd_start,
4937         .stop = _dwc2_hcd_stop,
4938         .urb_enqueue = _dwc2_hcd_urb_enqueue,
4939         .urb_dequeue = _dwc2_hcd_urb_dequeue,
4940         .endpoint_disable = _dwc2_hcd_endpoint_disable,
4941         .endpoint_reset = _dwc2_hcd_endpoint_reset,
4942         .get_frame_number = _dwc2_hcd_get_frame_number,
4943
4944         .hub_status_data = _dwc2_hcd_hub_status_data,
4945         .hub_control = _dwc2_hcd_hub_control,
4946         .clear_tt_buffer_complete = _dwc2_hcd_clear_tt_buffer_complete,
4947
4948         .bus_suspend = _dwc2_hcd_suspend,
4949         .bus_resume = _dwc2_hcd_resume,
4950
4951         .map_urb_for_dma        = dwc2_map_urb_for_dma,
4952         .unmap_urb_for_dma      = dwc2_unmap_urb_for_dma,
4953 };
4954
4955 /*
4956  * Frees secondary storage associated with the dwc2_hsotg structure contained
4957  * in the struct usb_hcd field
4958  */
4959 static void dwc2_hcd_free(struct dwc2_hsotg *hsotg)
4960 {
4961         u32 ahbcfg;
4962         u32 dctl;
4963         int i;
4964
4965         dev_dbg(hsotg->dev, "DWC OTG HCD FREE\n");
4966
4967         /* Free memory for QH/QTD lists */
4968         dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_inactive);
4969         dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_active);
4970         dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_inactive);
4971         dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_ready);
4972         dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_assigned);
4973         dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_queued);
4974
4975         /* Free memory for the host channels */
4976         for (i = 0; i < MAX_EPS_CHANNELS; i++) {
4977                 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
4978
4979                 if (chan) {
4980                         dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n",
4981                                 i, chan);
4982                         hsotg->hc_ptr_array[i] = NULL;
4983                         kfree(chan);
4984                 }
4985         }
4986
4987         if (hsotg->params.host_dma) {
4988                 if (hsotg->status_buf) {
4989                         dma_free_coherent(hsotg->dev, DWC2_HCD_STATUS_BUF_SIZE,
4990                                           hsotg->status_buf,
4991                                           hsotg->status_buf_dma);
4992                         hsotg->status_buf = NULL;
4993                 }
4994         } else {
4995                 kfree(hsotg->status_buf);
4996                 hsotg->status_buf = NULL;
4997         }
4998
4999         ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
5000
5001         /* Disable all interrupts */
5002         ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
5003         dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
5004         dwc2_writel(0, hsotg->regs + GINTMSK);
5005
5006         if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) {
5007                 dctl = dwc2_readl(hsotg->regs + DCTL);
5008                 dctl |= DCTL_SFTDISCON;
5009                 dwc2_writel(dctl, hsotg->regs + DCTL);
5010         }
5011
5012         if (hsotg->wq_otg) {
5013                 if (!cancel_work_sync(&hsotg->wf_otg))
5014                         flush_workqueue(hsotg->wq_otg);
5015                 destroy_workqueue(hsotg->wq_otg);
5016         }
5017
5018         del_timer(&hsotg->wkp_timer);
5019 }
5020
5021 static void dwc2_hcd_release(struct dwc2_hsotg *hsotg)
5022 {
5023         /* Turn off all host-specific interrupts */
5024         dwc2_disable_host_interrupts(hsotg);
5025
5026         dwc2_hcd_free(hsotg);
5027 }
5028
5029 /*
5030  * Initializes the HCD. This function allocates memory for and initializes the
5031  * static parts of the usb_hcd and dwc2_hsotg structures. It also registers the
5032  * USB bus with the core and calls the hc_driver->start() function. It returns
5033  * a negative error on failure.
5034  */
5035 int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq)
5036 {
5037         struct platform_device *pdev = to_platform_device(hsotg->dev);
5038         struct resource *res;
5039         struct usb_hcd *hcd;
5040         struct dwc2_host_chan *channel;
5041         u32 hcfg;
5042         int i, num_channels;
5043         int retval;
5044
5045         if (usb_disabled())
5046                 return -ENODEV;
5047
5048         dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n");
5049
5050         retval = -ENOMEM;
5051
5052         hcfg = dwc2_readl(hsotg->regs + HCFG);
5053         dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg);
5054
5055 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
5056         hsotg->frame_num_array = kzalloc(sizeof(*hsotg->frame_num_array) *
5057                                          FRAME_NUM_ARRAY_SIZE, GFP_KERNEL);
5058         if (!hsotg->frame_num_array)
5059                 goto error1;
5060         hsotg->last_frame_num_array = kzalloc(
5061                         sizeof(*hsotg->last_frame_num_array) *
5062                         FRAME_NUM_ARRAY_SIZE, GFP_KERNEL);
5063         if (!hsotg->last_frame_num_array)
5064                 goto error1;
5065 #endif
5066         hsotg->last_frame_num = HFNUM_MAX_FRNUM;
5067
5068         /* Check if the bus driver or platform code has setup a dma_mask */
5069         if (hsotg->params.host_dma &&
5070             !hsotg->dev->dma_mask) {
5071                 dev_warn(hsotg->dev,
5072                          "dma_mask not set, disabling DMA\n");
5073                 hsotg->params.host_dma = false;
5074                 hsotg->params.dma_desc_enable = false;
5075         }
5076
5077         /* Set device flags indicating whether the HCD supports DMA */
5078         if (hsotg->params.host_dma) {
5079                 if (dma_set_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
5080                         dev_warn(hsotg->dev, "can't set DMA mask\n");
5081                 if (dma_set_coherent_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
5082                         dev_warn(hsotg->dev, "can't set coherent DMA mask\n");
5083         }
5084
5085         if (hsotg->params.change_speed_quirk) {
5086                 dwc2_hc_driver.free_dev = dwc2_free_dev;
5087                 dwc2_hc_driver.reset_device = dwc2_reset_device;
5088         }
5089
5090         hcd = usb_create_hcd(&dwc2_hc_driver, hsotg->dev, dev_name(hsotg->dev));
5091         if (!hcd)
5092                 goto error1;
5093
5094         if (!hsotg->params.host_dma)
5095                 hcd->self.uses_dma = 0;
5096
5097         hcd->has_tt = 1;
5098
5099         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
5100         hcd->rsrc_start = res->start;
5101         hcd->rsrc_len = resource_size(res);
5102
5103         ((struct wrapper_priv_data *)&hcd->hcd_priv)->hsotg = hsotg;
5104         hsotg->priv = hcd;
5105
5106         /*
5107          * Disable the global interrupt until all the interrupt handlers are
5108          * installed
5109          */
5110         dwc2_disable_global_interrupts(hsotg);
5111
5112         /* Initialize the DWC_otg core, and select the Phy type */
5113         retval = dwc2_core_init(hsotg, true);
5114         if (retval)
5115                 goto error2;
5116
5117         /* Create new workqueue and init work */
5118         retval = -ENOMEM;
5119         hsotg->wq_otg = alloc_ordered_workqueue("dwc2", 0);
5120         if (!hsotg->wq_otg) {
5121                 dev_err(hsotg->dev, "Failed to create workqueue\n");
5122                 goto error2;
5123         }
5124         INIT_WORK(&hsotg->wf_otg, dwc2_conn_id_status_change);
5125
5126         setup_timer(&hsotg->wkp_timer, dwc2_wakeup_detected,
5127                     (unsigned long)hsotg);
5128
5129         /* Initialize the non-periodic schedule */
5130         INIT_LIST_HEAD(&hsotg->non_periodic_sched_inactive);
5131         INIT_LIST_HEAD(&hsotg->non_periodic_sched_active);
5132
5133         /* Initialize the periodic schedule */
5134         INIT_LIST_HEAD(&hsotg->periodic_sched_inactive);
5135         INIT_LIST_HEAD(&hsotg->periodic_sched_ready);
5136         INIT_LIST_HEAD(&hsotg->periodic_sched_assigned);
5137         INIT_LIST_HEAD(&hsotg->periodic_sched_queued);
5138
5139         INIT_LIST_HEAD(&hsotg->split_order);
5140
5141         /*
5142          * Create a host channel descriptor for each host channel implemented
5143          * in the controller. Initialize the channel descriptor array.
5144          */
5145         INIT_LIST_HEAD(&hsotg->free_hc_list);
5146         num_channels = hsotg->params.host_channels;
5147         memset(&hsotg->hc_ptr_array[0], 0, sizeof(hsotg->hc_ptr_array));
5148
5149         for (i = 0; i < num_channels; i++) {
5150                 channel = kzalloc(sizeof(*channel), GFP_KERNEL);
5151                 if (!channel)
5152                         goto error3;
5153                 channel->hc_num = i;
5154                 INIT_LIST_HEAD(&channel->split_order_list_entry);
5155                 hsotg->hc_ptr_array[i] = channel;
5156         }
5157
5158         /* Initialize hsotg start work */
5159         INIT_DELAYED_WORK(&hsotg->start_work, dwc2_hcd_start_func);
5160
5161         /* Initialize port reset work */
5162         INIT_DELAYED_WORK(&hsotg->reset_work, dwc2_hcd_reset_func);
5163
5164         /*
5165          * Allocate space for storing data on status transactions. Normally no
5166          * data is sent, but this space acts as a bit bucket. This must be
5167          * done after usb_add_hcd since that function allocates the DMA buffer
5168          * pool.
5169          */
5170         if (hsotg->params.host_dma)
5171                 hsotg->status_buf = dma_alloc_coherent(hsotg->dev,
5172                                         DWC2_HCD_STATUS_BUF_SIZE,
5173                                         &hsotg->status_buf_dma, GFP_KERNEL);
5174         else
5175                 hsotg->status_buf = kzalloc(DWC2_HCD_STATUS_BUF_SIZE,
5176                                           GFP_KERNEL);
5177
5178         if (!hsotg->status_buf)
5179                 goto error3;
5180
5181         /*
5182          * Create kmem caches to handle descriptor buffers in descriptor
5183          * DMA mode.
5184          * Alignment must be set to 512 bytes.
5185          */
5186         if (hsotg->params.dma_desc_enable ||
5187             hsotg->params.dma_desc_fs_enable) {
5188                 hsotg->desc_gen_cache = kmem_cache_create("dwc2-gen-desc",
5189                                 sizeof(struct dwc2_dma_desc) *
5190                                 MAX_DMA_DESC_NUM_GENERIC, 512, SLAB_CACHE_DMA,
5191                                 NULL);
5192                 if (!hsotg->desc_gen_cache) {
5193                         dev_err(hsotg->dev,
5194                                 "unable to create dwc2 generic desc cache\n");
5195
5196                         /*
5197                          * Disable descriptor dma mode since it will not be
5198                          * usable.
5199                          */
5200                         hsotg->params.dma_desc_enable = false;
5201                         hsotg->params.dma_desc_fs_enable = false;
5202                 }
5203
5204                 hsotg->desc_hsisoc_cache = kmem_cache_create("dwc2-hsisoc-desc",
5205                                 sizeof(struct dwc2_dma_desc) *
5206                                 MAX_DMA_DESC_NUM_HS_ISOC, 512, 0, NULL);
5207                 if (!hsotg->desc_hsisoc_cache) {
5208                         dev_err(hsotg->dev,
5209                                 "unable to create dwc2 hs isoc desc cache\n");
5210
5211                         kmem_cache_destroy(hsotg->desc_gen_cache);
5212
5213                         /*
5214                          * Disable descriptor dma mode since it will not be
5215                          * usable.
5216                          */
5217                         hsotg->params.dma_desc_enable = false;
5218                         hsotg->params.dma_desc_fs_enable = false;
5219                 }
5220         }
5221
5222         hsotg->otg_port = 1;
5223         hsotg->frame_list = NULL;
5224         hsotg->frame_list_dma = 0;
5225         hsotg->periodic_qh_count = 0;
5226
5227         /* Initiate lx_state to L3 disconnected state */
5228         hsotg->lx_state = DWC2_L3;
5229
5230         hcd->self.otg_port = hsotg->otg_port;
5231
5232         /* Don't support SG list at this point */
5233         hcd->self.sg_tablesize = 0;
5234
5235         if (!IS_ERR_OR_NULL(hsotg->uphy))
5236                 otg_set_host(hsotg->uphy->otg, &hcd->self);
5237
5238         /*
5239          * Finish generic HCD initialization and start the HCD. This function
5240          * allocates the DMA buffer pool, registers the USB bus, requests the
5241          * IRQ line, and calls hcd_start method.
5242          */
5243         retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
5244         if (retval < 0)
5245                 goto error4;
5246
5247         device_wakeup_enable(hcd->self.controller);
5248
5249         dwc2_hcd_dump_state(hsotg);
5250
5251         dwc2_enable_global_interrupts(hsotg);
5252
5253         return 0;
5254
5255 error4:
5256         kmem_cache_destroy(hsotg->desc_gen_cache);
5257         kmem_cache_destroy(hsotg->desc_hsisoc_cache);
5258 error3:
5259         dwc2_hcd_release(hsotg);
5260 error2:
5261         usb_put_hcd(hcd);
5262 error1:
5263
5264 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
5265         kfree(hsotg->last_frame_num_array);
5266         kfree(hsotg->frame_num_array);
5267 #endif
5268
5269         dev_err(hsotg->dev, "%s() FAILED, returning %d\n", __func__, retval);
5270         return retval;
5271 }
5272
5273 /*
5274  * Removes the HCD.
5275  * Frees memory and resources associated with the HCD and deregisters the bus.
5276  */
5277 void dwc2_hcd_remove(struct dwc2_hsotg *hsotg)
5278 {
5279         struct usb_hcd *hcd;
5280
5281         dev_dbg(hsotg->dev, "DWC OTG HCD REMOVE\n");
5282
5283         hcd = dwc2_hsotg_to_hcd(hsotg);
5284         dev_dbg(hsotg->dev, "hsotg->hcd = %p\n", hcd);
5285
5286         if (!hcd) {
5287                 dev_dbg(hsotg->dev, "%s: dwc2_hsotg_to_hcd(hsotg) NULL!\n",
5288                         __func__);
5289                 return;
5290         }
5291
5292         if (!IS_ERR_OR_NULL(hsotg->uphy))
5293                 otg_set_host(hsotg->uphy->otg, NULL);
5294
5295         usb_remove_hcd(hcd);
5296         hsotg->priv = NULL;
5297
5298         kmem_cache_destroy(hsotg->desc_gen_cache);
5299         kmem_cache_destroy(hsotg->desc_hsisoc_cache);
5300
5301         dwc2_hcd_release(hsotg);
5302         usb_put_hcd(hcd);
5303
5304 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
5305         kfree(hsotg->last_frame_num_array);
5306         kfree(hsotg->frame_num_array);
5307 #endif
5308 }
5309
5310 /**
5311  * dwc2_backup_host_registers() - Backup controller host registers.
5312  * When suspending usb bus, registers needs to be backuped
5313  * if controller power is disabled once suspended.
5314  *
5315  * @hsotg: Programming view of the DWC_otg controller
5316  */
5317 int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg)
5318 {
5319         struct dwc2_hregs_backup *hr;
5320         int i;
5321
5322         dev_dbg(hsotg->dev, "%s\n", __func__);
5323
5324         /* Backup Host regs */
5325         hr = &hsotg->hr_backup;
5326         hr->hcfg = dwc2_readl(hsotg->regs + HCFG);
5327         hr->haintmsk = dwc2_readl(hsotg->regs + HAINTMSK);
5328         for (i = 0; i < hsotg->params.host_channels; ++i)
5329                 hr->hcintmsk[i] = dwc2_readl(hsotg->regs + HCINTMSK(i));
5330
5331         hr->hprt0 = dwc2_read_hprt0(hsotg);
5332         hr->hfir = dwc2_readl(hsotg->regs + HFIR);
5333         hr->valid = true;
5334
5335         return 0;
5336 }
5337
5338 /**
5339  * dwc2_restore_host_registers() - Restore controller host registers.
5340  * When resuming usb bus, device registers needs to be restored
5341  * if controller power were disabled.
5342  *
5343  * @hsotg: Programming view of the DWC_otg controller
5344  */
5345 int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg)
5346 {
5347         struct dwc2_hregs_backup *hr;
5348         int i;
5349
5350         dev_dbg(hsotg->dev, "%s\n", __func__);
5351
5352         /* Restore host regs */
5353         hr = &hsotg->hr_backup;
5354         if (!hr->valid) {
5355                 dev_err(hsotg->dev, "%s: no host registers to restore\n",
5356                         __func__);
5357                 return -EINVAL;
5358         }
5359         hr->valid = false;
5360
5361         dwc2_writel(hr->hcfg, hsotg->regs + HCFG);
5362         dwc2_writel(hr->haintmsk, hsotg->regs + HAINTMSK);
5363
5364         for (i = 0; i < hsotg->params.host_channels; ++i)
5365                 dwc2_writel(hr->hcintmsk[i], hsotg->regs + HCINTMSK(i));
5366
5367         dwc2_writel(hr->hprt0, hsotg->regs + HPRT0);
5368         dwc2_writel(hr->hfir, hsotg->regs + HFIR);
5369         hsotg->frame_number = 0;
5370
5371         return 0;
5372 }