2 * core.c - DesignWare USB3 DRD Controller Core file
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/slab.h>
25 #include <linux/spinlock.h>
26 #include <linux/platform_device.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/interrupt.h>
29 #include <linux/ioport.h>
31 #include <linux/list.h>
32 #include <linux/delay.h>
33 #include <linux/dma-mapping.h>
36 #include <linux/usb/otg.h>
37 #include <linux/usb/ch9.h>
38 #include <linux/usb/gadget.h>
39 #include <linux/usb/of.h>
40 #include <linux/usb/otg.h>
42 #include "platform_data.h"
49 /* -------------------------------------------------------------------------- */
51 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
55 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
56 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
57 reg |= DWC3_GCTL_PRTCAPDIR(mode);
58 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
62 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
63 * @dwc: pointer to our context structure
65 static void dwc3_core_soft_reset(struct dwc3 *dwc)
69 /* Before Resetting PHY, put Core in Reset */
70 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
71 reg |= DWC3_GCTL_CORESOFTRESET;
72 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
74 /* Assert USB3 PHY reset */
75 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
76 reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
77 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
79 /* Assert USB2 PHY reset */
80 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
81 reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
82 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
84 usb_phy_init(dwc->usb2_phy);
85 usb_phy_init(dwc->usb3_phy);
88 /* Clear USB3 PHY reset */
89 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
90 reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
91 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
93 /* Clear USB2 PHY reset */
94 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
95 reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
96 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
100 /* After PHYs are stable we can take Core out of reset state */
101 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
102 reg &= ~DWC3_GCTL_CORESOFTRESET;
103 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
107 * dwc3_free_one_event_buffer - Frees one event buffer
108 * @dwc: Pointer to our controller context structure
109 * @evt: Pointer to event buffer to be freed
111 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
112 struct dwc3_event_buffer *evt)
114 dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
118 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
119 * @dwc: Pointer to our controller context structure
120 * @length: size of the event buffer
122 * Returns a pointer to the allocated event buffer structure on success
123 * otherwise ERR_PTR(errno).
125 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
128 struct dwc3_event_buffer *evt;
130 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
132 return ERR_PTR(-ENOMEM);
135 evt->length = length;
136 evt->buf = dma_alloc_coherent(dwc->dev, length,
137 &evt->dma, GFP_KERNEL);
139 return ERR_PTR(-ENOMEM);
145 * dwc3_free_event_buffers - frees all allocated event buffers
146 * @dwc: Pointer to our controller context structure
148 static void dwc3_free_event_buffers(struct dwc3 *dwc)
150 struct dwc3_event_buffer *evt;
153 for (i = 0; i < dwc->num_event_buffers; i++) {
154 evt = dwc->ev_buffs[i];
156 dwc3_free_one_event_buffer(dwc, evt);
161 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
162 * @dwc: pointer to our controller context structure
163 * @length: size of event buffer
165 * Returns 0 on success otherwise negative errno. In the error case, dwc
166 * may contain some buffers allocated but not all which were requested.
168 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
173 num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
174 dwc->num_event_buffers = num;
176 dwc->ev_buffs = devm_kzalloc(dwc->dev, sizeof(*dwc->ev_buffs) * num,
178 if (!dwc->ev_buffs) {
179 dev_err(dwc->dev, "can't allocate event buffers array\n");
183 for (i = 0; i < num; i++) {
184 struct dwc3_event_buffer *evt;
186 evt = dwc3_alloc_one_event_buffer(dwc, length);
188 dev_err(dwc->dev, "can't allocate event buffer\n");
191 dwc->ev_buffs[i] = evt;
198 * dwc3_event_buffers_setup - setup our allocated event buffers
199 * @dwc: pointer to our controller context structure
201 * Returns 0 on success otherwise negative errno.
203 static int dwc3_event_buffers_setup(struct dwc3 *dwc)
205 struct dwc3_event_buffer *evt;
208 for (n = 0; n < dwc->num_event_buffers; n++) {
209 evt = dwc->ev_buffs[n];
210 dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",
211 evt->buf, (unsigned long long) evt->dma,
216 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
217 lower_32_bits(evt->dma));
218 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
219 upper_32_bits(evt->dma));
220 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
221 DWC3_GEVNTSIZ_SIZE(evt->length));
222 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
228 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
230 struct dwc3_event_buffer *evt;
233 for (n = 0; n < dwc->num_event_buffers; n++) {
234 evt = dwc->ev_buffs[n];
238 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
239 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
240 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK
241 | DWC3_GEVNTSIZ_SIZE(0));
242 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
246 static void dwc3_core_num_eps(struct dwc3 *dwc)
248 struct dwc3_hwparams *parms = &dwc->hwparams;
250 dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
251 dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
253 dev_vdbg(dwc->dev, "found %d IN and %d OUT endpoints\n",
254 dwc->num_in_eps, dwc->num_out_eps);
257 static void dwc3_cache_hwparams(struct dwc3 *dwc)
259 struct dwc3_hwparams *parms = &dwc->hwparams;
261 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
262 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
263 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
264 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
265 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
266 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
267 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
268 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
269 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
273 * dwc3_core_init - Low-level initialization of DWC3 Core
274 * @dwc: Pointer to our controller context structure
276 * Returns 0 on success otherwise negative errno.
278 static int dwc3_core_init(struct dwc3 *dwc)
280 unsigned long timeout;
284 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
285 /* This should read as U3 followed by revision number */
286 if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
287 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
293 /* issue device SoftReset too */
294 timeout = jiffies + msecs_to_jiffies(500);
295 dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
297 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
298 if (!(reg & DWC3_DCTL_CSFTRST))
301 if (time_after(jiffies, timeout)) {
302 dev_err(dwc->dev, "Reset Timed Out\n");
310 dwc3_core_soft_reset(dwc);
312 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
313 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
314 reg &= ~DWC3_GCTL_DISSCRAMBLE;
316 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
317 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
318 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
321 dev_dbg(dwc->dev, "No power optimization available\n");
325 * WORKAROUND: DWC3 revisions <1.90a have a bug
326 * where the device can fail to connect at SuperSpeed
327 * and falls back to high-speed mode which causes
328 * the device to enter a Connect/Disconnect loop
330 if (dwc->revision < DWC3_REVISION_190A)
331 reg |= DWC3_GCTL_U2RSTECN;
333 dwc3_core_num_eps(dwc);
335 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
343 static void dwc3_core_exit(struct dwc3 *dwc)
345 usb_phy_shutdown(dwc->usb2_phy);
346 usb_phy_shutdown(dwc->usb3_phy);
349 #define DWC3_ALIGN_MASK (16 - 1)
351 static int dwc3_probe(struct platform_device *pdev)
353 struct device *dev = &pdev->dev;
354 struct dwc3_platform_data *pdata = dev_get_platdata(dev);
355 struct device_node *node = dev->of_node;
356 struct resource *res;
364 mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
366 dev_err(dev, "not enough memory\n");
369 dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
372 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
374 dev_err(dev, "missing IRQ\n");
377 dwc->xhci_resources[1].start = res->start;
378 dwc->xhci_resources[1].end = res->end;
379 dwc->xhci_resources[1].flags = res->flags;
380 dwc->xhci_resources[1].name = res->name;
382 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
384 dev_err(dev, "missing memory resource\n");
389 dwc->maximum_speed = of_usb_get_maximum_speed(node);
391 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
392 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
394 dwc->needs_fifo_resize = of_property_read_bool(node, "tx-fifo-resize");
395 dwc->dr_mode = of_usb_get_dr_mode(node);
397 dwc->maximum_speed = pdata->maximum_speed;
399 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
400 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
402 dwc->needs_fifo_resize = pdata->tx_fifo_resize;
403 dwc->dr_mode = pdata->dr_mode;
405 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
406 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
409 /* default to superspeed if no maximum_speed passed */
410 if (dwc->maximum_speed == USB_SPEED_UNKNOWN)
411 dwc->maximum_speed = USB_SPEED_SUPER;
413 if (IS_ERR(dwc->usb2_phy)) {
414 ret = PTR_ERR(dwc->usb2_phy);
417 * if -ENXIO is returned, it means PHY layer wasn't
418 * enabled, so it makes no sense to return -EPROBE_DEFER
419 * in that case, since no PHY driver will ever probe.
424 dev_err(dev, "no usb2 phy configured\n");
425 return -EPROBE_DEFER;
428 if (IS_ERR(dwc->usb3_phy)) {
429 ret = PTR_ERR(dwc->usb3_phy);
432 * if -ENXIO is returned, it means PHY layer wasn't
433 * enabled, so it makes no sense to return -EPROBE_DEFER
434 * in that case, since no PHY driver will ever probe.
439 dev_err(dev, "no usb3 phy configured\n");
440 return -EPROBE_DEFER;
443 dwc->xhci_resources[0].start = res->start;
444 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
446 dwc->xhci_resources[0].flags = res->flags;
447 dwc->xhci_resources[0].name = res->name;
449 res->start += DWC3_GLOBALS_REGS_START;
452 * Request memory region but exclude xHCI regs,
453 * since it will be requested by the xhci-plat driver.
455 regs = devm_ioremap_resource(dev, res);
457 return PTR_ERR(regs);
459 usb_phy_set_suspend(dwc->usb2_phy, 0);
460 usb_phy_set_suspend(dwc->usb3_phy, 0);
462 spin_lock_init(&dwc->lock);
463 platform_set_drvdata(pdev, dwc);
466 dwc->regs_size = resource_size(res);
469 dev->dma_mask = dev->parent->dma_mask;
470 dev->dma_parms = dev->parent->dma_parms;
471 dma_set_coherent_mask(dev, dev->parent->coherent_dma_mask);
473 pm_runtime_enable(dev);
474 pm_runtime_get_sync(dev);
475 pm_runtime_forbid(dev);
477 dwc3_cache_hwparams(dwc);
479 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
481 dev_err(dwc->dev, "failed to allocate event buffers\n");
486 ret = dwc3_core_init(dwc);
488 dev_err(dev, "failed to initialize core\n");
492 ret = dwc3_event_buffers_setup(dwc);
494 dev_err(dwc->dev, "failed to setup event buffers\n");
498 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
499 dwc->dr_mode = USB_DR_MODE_HOST;
500 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
501 dwc->dr_mode = USB_DR_MODE_PERIPHERAL;
503 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
504 dwc->dr_mode = USB_DR_MODE_OTG;
506 switch (dwc->dr_mode) {
507 case USB_DR_MODE_PERIPHERAL:
508 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
509 ret = dwc3_gadget_init(dwc);
511 dev_err(dev, "failed to initialize gadget\n");
515 case USB_DR_MODE_HOST:
516 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
517 ret = dwc3_host_init(dwc);
519 dev_err(dev, "failed to initialize host\n");
523 case USB_DR_MODE_OTG:
524 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
525 ret = dwc3_host_init(dwc);
527 dev_err(dev, "failed to initialize host\n");
531 ret = dwc3_gadget_init(dwc);
533 dev_err(dev, "failed to initialize gadget\n");
538 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
542 ret = dwc3_debugfs_init(dwc);
544 dev_err(dev, "failed to initialize debugfs\n");
548 pm_runtime_allow(dev);
553 switch (dwc->dr_mode) {
554 case USB_DR_MODE_PERIPHERAL:
555 dwc3_gadget_exit(dwc);
557 case USB_DR_MODE_HOST:
560 case USB_DR_MODE_OTG:
562 dwc3_gadget_exit(dwc);
570 dwc3_event_buffers_cleanup(dwc);
576 dwc3_free_event_buffers(dwc);
581 static int dwc3_remove(struct platform_device *pdev)
583 struct dwc3 *dwc = platform_get_drvdata(pdev);
585 usb_phy_set_suspend(dwc->usb2_phy, 1);
586 usb_phy_set_suspend(dwc->usb3_phy, 1);
588 pm_runtime_put(&pdev->dev);
589 pm_runtime_disable(&pdev->dev);
591 dwc3_debugfs_exit(dwc);
593 switch (dwc->dr_mode) {
594 case USB_DR_MODE_PERIPHERAL:
595 dwc3_gadget_exit(dwc);
597 case USB_DR_MODE_HOST:
600 case USB_DR_MODE_OTG:
602 dwc3_gadget_exit(dwc);
609 dwc3_event_buffers_cleanup(dwc);
610 dwc3_free_event_buffers(dwc);
616 #ifdef CONFIG_PM_SLEEP
617 static int dwc3_prepare(struct device *dev)
619 struct dwc3 *dwc = dev_get_drvdata(dev);
622 spin_lock_irqsave(&dwc->lock, flags);
624 switch (dwc->dr_mode) {
625 case USB_DR_MODE_PERIPHERAL:
626 case USB_DR_MODE_OTG:
627 dwc3_gadget_prepare(dwc);
629 case USB_DR_MODE_HOST:
631 dwc3_event_buffers_cleanup(dwc);
635 spin_unlock_irqrestore(&dwc->lock, flags);
640 static void dwc3_complete(struct device *dev)
642 struct dwc3 *dwc = dev_get_drvdata(dev);
645 spin_lock_irqsave(&dwc->lock, flags);
647 switch (dwc->dr_mode) {
648 case USB_DR_MODE_PERIPHERAL:
649 case USB_DR_MODE_OTG:
650 dwc3_gadget_complete(dwc);
652 case USB_DR_MODE_HOST:
654 dwc3_event_buffers_setup(dwc);
658 spin_unlock_irqrestore(&dwc->lock, flags);
661 static int dwc3_suspend(struct device *dev)
663 struct dwc3 *dwc = dev_get_drvdata(dev);
666 spin_lock_irqsave(&dwc->lock, flags);
668 switch (dwc->dr_mode) {
669 case USB_DR_MODE_PERIPHERAL:
670 case USB_DR_MODE_OTG:
671 dwc3_gadget_suspend(dwc);
673 case USB_DR_MODE_HOST:
679 dwc->gctl = dwc3_readl(dwc->regs, DWC3_GCTL);
680 spin_unlock_irqrestore(&dwc->lock, flags);
682 usb_phy_shutdown(dwc->usb3_phy);
683 usb_phy_shutdown(dwc->usb2_phy);
688 static int dwc3_resume(struct device *dev)
690 struct dwc3 *dwc = dev_get_drvdata(dev);
693 usb_phy_init(dwc->usb3_phy);
694 usb_phy_init(dwc->usb2_phy);
697 spin_lock_irqsave(&dwc->lock, flags);
699 dwc3_writel(dwc->regs, DWC3_GCTL, dwc->gctl);
701 switch (dwc->dr_mode) {
702 case USB_DR_MODE_PERIPHERAL:
703 case USB_DR_MODE_OTG:
704 dwc3_gadget_resume(dwc);
706 case USB_DR_MODE_HOST:
712 spin_unlock_irqrestore(&dwc->lock, flags);
714 pm_runtime_disable(dev);
715 pm_runtime_set_active(dev);
716 pm_runtime_enable(dev);
721 static const struct dev_pm_ops dwc3_dev_pm_ops = {
722 .prepare = dwc3_prepare,
723 .complete = dwc3_complete,
725 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
728 #define DWC3_PM_OPS &(dwc3_dev_pm_ops)
730 #define DWC3_PM_OPS NULL
734 static const struct of_device_id of_dwc3_match[] = {
736 .compatible = "snps,dwc3"
739 .compatible = "synopsys,dwc3"
743 MODULE_DEVICE_TABLE(of, of_dwc3_match);
746 static struct platform_driver dwc3_driver = {
748 .remove = dwc3_remove,
751 .of_match_table = of_match_ptr(of_dwc3_match),
756 module_platform_driver(dwc3_driver);
758 MODULE_ALIAS("platform:dwc3");
759 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
760 MODULE_LICENSE("GPL v2");
761 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");