drivers/usb/dwc3/core.c

   1 /**
   2  * core.c - DesignWare USB3 DRD Controller Core file
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * This program is free software: you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2  of
  11  * the License as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/slab.h>
  25 #include <linux/spinlock.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/ioport.h>
  30 #include <linux/io.h>
  31 #include <linux/list.h>
  32 #include <linux/delay.h>
  33 #include <linux/dma-mapping.h>
  34 #include <linux/of.h>
  35
  36 #include <linux/usb/otg.h>
  37 #include <linux/usb/ch9.h>
  38 #include <linux/usb/gadget.h>
  39 #include <linux/usb/of.h>
  40 #include <linux/usb/otg.h>
  41
  42 #include "platform_data.h"
  43 #include "core.h"
  44 #include "gadget.h"
  45 #include "io.h"
  46
  47 #include "debug.h"
  48
  49 /* -------------------------------------------------------------------------- */
  50
  51 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
  52 {
  53         u32 reg;
  54
  55         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  56         reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
  57         reg |= DWC3_GCTL_PRTCAPDIR(mode);
  58         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  59 }
  60
  61 /**
  62  * dwc3_core_soft_reset - Issues core soft reset and PHY reset
  63  * @dwc: pointer to our context structure
  64  */
  65 static void dwc3_core_soft_reset(struct dwc3 *dwc)
  66 {
  67         u32             reg;
  68
  69         /* Before Resetting PHY, put Core in Reset */
  70         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  71         reg |= DWC3_GCTL_CORESOFTRESET;
  72         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  73
  74         /* Assert USB3 PHY reset */
  75         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
  76         reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
  77         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
  78
  79         /* Assert USB2 PHY reset */
  80         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
  81         reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
  82         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
  83
  84         usb_phy_init(dwc->usb2_phy);
  85         usb_phy_init(dwc->usb3_phy);
  86         mdelay(100);
  87
  88         /* Clear USB3 PHY reset */
  89         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
  90         reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
  91         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
  92
  93         /* Clear USB2 PHY reset */
  94         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
  95         reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
  96         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
  97
  98         mdelay(100);
  99
 100         /* After PHYs are stable we can take Core out of reset state */
 101         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 102         reg &= ~DWC3_GCTL_CORESOFTRESET;
 103         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 104 }
 105
 106 /**
 107  * dwc3_free_one_event_buffer - Frees one event buffer
 108  * @dwc: Pointer to our controller context structure
 109  * @evt: Pointer to event buffer to be freed
 110  */
 111 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
 112                 struct dwc3_event_buffer *evt)
 113 {
 114         dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
 115 }
 116
 117 /**
 118  * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
 119  * @dwc: Pointer to our controller context structure
 120  * @length: size of the event buffer
 121  *
 122  * Returns a pointer to the allocated event buffer structure on success
 123  * otherwise ERR_PTR(errno).
 124  */
 125 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
 126                 unsigned length)
 127 {
 128         struct dwc3_event_buffer        *evt;
 129
 130         evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
 131         if (!evt)
 132                 return ERR_PTR(-ENOMEM);
 133
 134         evt->dwc        = dwc;
 135         evt->length     = length;
 136         evt->buf        = dma_alloc_coherent(dwc->dev, length,
 137                         &evt->dma, GFP_KERNEL);
 138         if (!evt->buf)
 139                 return ERR_PTR(-ENOMEM);
 140
 141         return evt;
 142 }
 143
 144 /**
 145  * dwc3_free_event_buffers - frees all allocated event buffers
 146  * @dwc: Pointer to our controller context structure
 147  */
 148 static void dwc3_free_event_buffers(struct dwc3 *dwc)
 149 {
 150         struct dwc3_event_buffer        *evt;
 151         int i;
 152
 153         for (i = 0; i < dwc->num_event_buffers; i++) {
 154                 evt = dwc->ev_buffs[i];
 155                 if (evt)
 156                         dwc3_free_one_event_buffer(dwc, evt);
 157         }
 158 }
 159
 160 /**
 161  * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
 162  * @dwc: pointer to our controller context structure
 163  * @length: size of event buffer
 164  *
 165  * Returns 0 on success otherwise negative errno. In the error case, dwc
 166  * may contain some buffers allocated but not all which were requested.
 167  */
 168 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
 169 {
 170         int                     num;
 171         int                     i;
 172
 173         num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
 174         dwc->num_event_buffers = num;
 175
 176         dwc->ev_buffs = devm_kzalloc(dwc->dev, sizeof(*dwc->ev_buffs) * num,
 177                         GFP_KERNEL);
 178         if (!dwc->ev_buffs) {
 179                 dev_err(dwc->dev, "can't allocate event buffers array\n");
 180                 return -ENOMEM;
 181         }
 182
 183         for (i = 0; i < num; i++) {
 184                 struct dwc3_event_buffer        *evt;
 185
 186                 evt = dwc3_alloc_one_event_buffer(dwc, length);
 187                 if (IS_ERR(evt)) {
 188                         dev_err(dwc->dev, "can't allocate event buffer\n");
 189                         return PTR_ERR(evt);
 190                 }
 191                 dwc->ev_buffs[i] = evt;
 192         }
 193
 194         return 0;
 195 }
 196
 197 /**
 198  * dwc3_event_buffers_setup - setup our allocated event buffers
 199  * @dwc: pointer to our controller context structure
 200  *
 201  * Returns 0 on success otherwise negative errno.
 202  */
 203 static int dwc3_event_buffers_setup(struct dwc3 *dwc)
 204 {
 205         struct dwc3_event_buffer        *evt;
 206         int                             n;
 207
 208         for (n = 0; n < dwc->num_event_buffers; n++) {
 209                 evt = dwc->ev_buffs[n];
 210                 dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",
 211                                 evt->buf, (unsigned long long) evt->dma,
 212                                 evt->length);
 213
 214                 evt->lpos = 0;
 215
 216                 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
 217                                 lower_32_bits(evt->dma));
 218                 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
 219                                 upper_32_bits(evt->dma));
 220                 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
 221                                 DWC3_GEVNTSIZ_SIZE(evt->length));
 222                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
 223         }
 224
 225         return 0;
 226 }
 227
 228 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
 229 {
 230         struct dwc3_event_buffer        *evt;
 231         int                             n;
 232
 233         for (n = 0; n < dwc->num_event_buffers; n++) {
 234                 evt = dwc->ev_buffs[n];
 235
 236                 evt->lpos = 0;
 237
 238                 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
 239                 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
 240                 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK
 241                                 | DWC3_GEVNTSIZ_SIZE(0));
 242                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
 243         }
 244 }
 245
 246 static void dwc3_core_num_eps(struct dwc3 *dwc)
 247 {
 248         struct dwc3_hwparams    *parms = &dwc->hwparams;
 249
 250         dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
 251         dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
 252
 253         dev_vdbg(dwc->dev, "found %d IN and %d OUT endpoints\n",
 254                         dwc->num_in_eps, dwc->num_out_eps);
 255 }
 256
 257 static void dwc3_cache_hwparams(struct dwc3 *dwc)
 258 {
 259         struct dwc3_hwparams    *parms = &dwc->hwparams;
 260
 261         parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
 262         parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
 263         parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
 264         parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
 265         parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
 266         parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
 267         parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
 268         parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
 269         parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
 270 }
 271
 272 /**
 273  * dwc3_core_init - Low-level initialization of DWC3 Core
 274  * @dwc: Pointer to our controller context structure
 275  *
 276  * Returns 0 on success otherwise negative errno.
 277  */
 278 static int dwc3_core_init(struct dwc3 *dwc)
 279 {
 280         unsigned long           timeout;
 281         u32                     reg;
 282         int                     ret;
 283
 284         reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
 285         /* This should read as U3 followed by revision number */
 286         if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
 287                 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
 288                 ret = -ENODEV;
 289                 goto err0;
 290         }
 291         dwc->revision = reg;
 292
 293         /* issue device SoftReset too */
 294         timeout = jiffies + msecs_to_jiffies(500);
 295         dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
 296         do {
 297                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 298                 if (!(reg & DWC3_DCTL_CSFTRST))
 299                         break;
 300
 301                 if (time_after(jiffies, timeout)) {
 302                         dev_err(dwc->dev, "Reset Timed Out\n");
 303                         ret = -ETIMEDOUT;
 304                         goto err0;
 305                 }
 306
 307                 cpu_relax();
 308         } while (true);
 309
 310         dwc3_core_soft_reset(dwc);
 311
 312         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 313         reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
 314         reg &= ~DWC3_GCTL_DISSCRAMBLE;
 315
 316         switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
 317         case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
 318                 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
 319                 break;
 320         default:
 321                 dev_dbg(dwc->dev, "No power optimization available\n");
 322         }
 323
 324         /*
 325          * WORKAROUND: DWC3 revisions <1.90a have a bug
 326          * where the device can fail to connect at SuperSpeed
 327          * and falls back to high-speed mode which causes
 328          * the device to enter a Connect/Disconnect loop
 329          */
 330         if (dwc->revision < DWC3_REVISION_190A)
 331                 reg |= DWC3_GCTL_U2RSTECN;
 332
 333         dwc3_core_num_eps(dwc);
 334
 335         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 336
 337         return 0;
 338
 339 err0:
 340         return ret;
 341 }
 342
 343 static void dwc3_core_exit(struct dwc3 *dwc)
 344 {
 345         usb_phy_shutdown(dwc->usb2_phy);
 346         usb_phy_shutdown(dwc->usb3_phy);
 347 }
 348
 349 #define DWC3_ALIGN_MASK         (16 - 1)
 350
 351 static int dwc3_probe(struct platform_device *pdev)
 352 {
 353         struct device           *dev = &pdev->dev;
 354         struct dwc3_platform_data *pdata = dev_get_platdata(dev);
 355         struct device_node      *node = dev->of_node;
 356         struct resource         *res;
 357         struct dwc3             *dwc;
 358
 359         int                     ret = -ENOMEM;
 360
 361         void __iomem            *regs;
 362         void                    *mem;
 363
 364         mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
 365         if (!mem) {
 366                 dev_err(dev, "not enough memory\n");
 367                 return -ENOMEM;
 368         }
 369         dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
 370         dwc->mem = mem;
 371
 372         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 373         if (!res) {
 374                 dev_err(dev, "missing IRQ\n");
 375                 return -ENODEV;
 376         }
 377         dwc->xhci_resources[1].start = res->start;
 378         dwc->xhci_resources[1].end = res->end;
 379         dwc->xhci_resources[1].flags = res->flags;
 380         dwc->xhci_resources[1].name = res->name;
 381
 382         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 383         if (!res) {
 384                 dev_err(dev, "missing memory resource\n");
 385                 return -ENODEV;
 386         }
 387
 388         if (node) {
 389                 dwc->maximum_speed = of_usb_get_maximum_speed(node);
 390
 391                 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
 392                 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
 393
 394                 dwc->needs_fifo_resize = of_property_read_bool(node, "tx-fifo-resize");
 395                 dwc->dr_mode = of_usb_get_dr_mode(node);
 396         } else if (pdata) {
 397                 dwc->maximum_speed = pdata->maximum_speed;
 398
 399                 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
 400                 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
 401
 402                 dwc->needs_fifo_resize = pdata->tx_fifo_resize;
 403                 dwc->dr_mode = pdata->dr_mode;
 404         } else {
 405                 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
 406                 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
 407         }
 408
 409         /* default to superspeed if no maximum_speed passed */
 410         if (dwc->maximum_speed == USB_SPEED_UNKNOWN)
 411                 dwc->maximum_speed = USB_SPEED_SUPER;
 412
 413         if (IS_ERR(dwc->usb2_phy)) {
 414                 ret = PTR_ERR(dwc->usb2_phy);
 415
 416                 /*
 417                  * if -ENXIO is returned, it means PHY layer wasn't
 418                  * enabled, so it makes no sense to return -EPROBE_DEFER
 419                  * in that case, since no PHY driver will ever probe.
 420                  */
 421                 if (ret == -ENXIO)
 422                         return ret;
 423
 424                 dev_err(dev, "no usb2 phy configured\n");
 425                 return -EPROBE_DEFER;
 426         }
 427
 428         if (IS_ERR(dwc->usb3_phy)) {
 429                 ret = PTR_ERR(dwc->usb3_phy);
 430
 431                 /*
 432                  * if -ENXIO is returned, it means PHY layer wasn't
 433                  * enabled, so it makes no sense to return -EPROBE_DEFER
 434                  * in that case, since no PHY driver will ever probe.
 435                  */
 436                 if (ret == -ENXIO)
 437                         return ret;
 438
 439                 dev_err(dev, "no usb3 phy configured\n");
 440                 return -EPROBE_DEFER;
 441         }
 442
 443         dwc->xhci_resources[0].start = res->start;
 444         dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
 445                                         DWC3_XHCI_REGS_END;
 446         dwc->xhci_resources[0].flags = res->flags;
 447         dwc->xhci_resources[0].name = res->name;
 448
 449         res->start += DWC3_GLOBALS_REGS_START;
 450
 451         /*
 452          * Request memory region but exclude xHCI regs,
 453          * since it will be requested by the xhci-plat driver.
 454          */
 455         regs = devm_ioremap_resource(dev, res);
 456         if (IS_ERR(regs))
 457                 return PTR_ERR(regs);
 458
 459         usb_phy_set_suspend(dwc->usb2_phy, 0);
 460         usb_phy_set_suspend(dwc->usb3_phy, 0);
 461
 462         spin_lock_init(&dwc->lock);
 463         platform_set_drvdata(pdev, dwc);
 464
 465         dwc->regs       = regs;
 466         dwc->regs_size  = resource_size(res);
 467         dwc->dev        = dev;
 468
 469         dev->dma_mask   = dev->parent->dma_mask;
 470         dev->dma_parms  = dev->parent->dma_parms;
 471         dma_set_coherent_mask(dev, dev->parent->coherent_dma_mask);
 472
 473         pm_runtime_enable(dev);
 474         pm_runtime_get_sync(dev);
 475         pm_runtime_forbid(dev);
 476
 477         dwc3_cache_hwparams(dwc);
 478
 479         ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
 480         if (ret) {
 481                 dev_err(dwc->dev, "failed to allocate event buffers\n");
 482                 ret = -ENOMEM;
 483                 goto err0;
 484         }
 485
 486         ret = dwc3_core_init(dwc);
 487         if (ret) {
 488                 dev_err(dev, "failed to initialize core\n");
 489                 goto err0;
 490         }
 491
 492         ret = dwc3_event_buffers_setup(dwc);
 493         if (ret) {
 494                 dev_err(dwc->dev, "failed to setup event buffers\n");
 495                 goto err1;
 496         }
 497
 498         if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
 499                 dwc->dr_mode = USB_DR_MODE_HOST;
 500         else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
 501                 dwc->dr_mode = USB_DR_MODE_PERIPHERAL;
 502
 503         if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
 504                 dwc->dr_mode = USB_DR_MODE_OTG;
 505
 506         switch (dwc->dr_mode) {
 507         case USB_DR_MODE_PERIPHERAL:
 508                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
 509                 ret = dwc3_gadget_init(dwc);
 510                 if (ret) {
 511                         dev_err(dev, "failed to initialize gadget\n");
 512                         goto err2;
 513                 }
 514                 break;
 515         case USB_DR_MODE_HOST:
 516                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
 517                 ret = dwc3_host_init(dwc);
 518                 if (ret) {
 519                         dev_err(dev, "failed to initialize host\n");
 520                         goto err2;
 521                 }
 522                 break;
 523         case USB_DR_MODE_OTG:
 524                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
 525                 ret = dwc3_host_init(dwc);
 526                 if (ret) {
 527                         dev_err(dev, "failed to initialize host\n");
 528                         goto err2;
 529                 }
 530
 531                 ret = dwc3_gadget_init(dwc);
 532                 if (ret) {
 533                         dev_err(dev, "failed to initialize gadget\n");
 534                         goto err2;
 535                 }
 536                 break;
 537         default:
 538                 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
 539                 goto err2;
 540         }
 541
 542         ret = dwc3_debugfs_init(dwc);
 543         if (ret) {
 544                 dev_err(dev, "failed to initialize debugfs\n");
 545                 goto err3;
 546         }
 547
 548         pm_runtime_allow(dev);
 549
 550         return 0;
 551
 552 err3:
 553         switch (dwc->dr_mode) {
 554         case USB_DR_MODE_PERIPHERAL:
 555                 dwc3_gadget_exit(dwc);
 556                 break;
 557         case USB_DR_MODE_HOST:
 558                 dwc3_host_exit(dwc);
 559                 break;
 560         case USB_DR_MODE_OTG:
 561                 dwc3_host_exit(dwc);
 562                 dwc3_gadget_exit(dwc);
 563                 break;
 564         default:
 565                 /* do nothing */
 566                 break;
 567         }
 568
 569 err2:
 570         dwc3_event_buffers_cleanup(dwc);
 571
 572 err1:
 573         dwc3_core_exit(dwc);
 574
 575 err0:
 576         dwc3_free_event_buffers(dwc);
 577
 578         return ret;
 579 }
 580
 581 static int dwc3_remove(struct platform_device *pdev)
 582 {
 583         struct dwc3     *dwc = platform_get_drvdata(pdev);
 584
 585         usb_phy_set_suspend(dwc->usb2_phy, 1);
 586         usb_phy_set_suspend(dwc->usb3_phy, 1);
 587
 588         pm_runtime_put(&pdev->dev);
 589         pm_runtime_disable(&pdev->dev);
 590
 591         dwc3_debugfs_exit(dwc);
 592
 593         switch (dwc->dr_mode) {
 594         case USB_DR_MODE_PERIPHERAL:
 595                 dwc3_gadget_exit(dwc);
 596                 break;
 597         case USB_DR_MODE_HOST:
 598                 dwc3_host_exit(dwc);
 599                 break;
 600         case USB_DR_MODE_OTG:
 601                 dwc3_host_exit(dwc);
 602                 dwc3_gadget_exit(dwc);
 603                 break;
 604         default:
 605                 /* do nothing */
 606                 break;
 607         }
 608
 609         dwc3_event_buffers_cleanup(dwc);
 610         dwc3_free_event_buffers(dwc);
 611         dwc3_core_exit(dwc);
 612
 613         return 0;
 614 }
 615
 616 #ifdef CONFIG_PM_SLEEP
 617 static int dwc3_prepare(struct device *dev)
 618 {
 619         struct dwc3     *dwc = dev_get_drvdata(dev);
 620         unsigned long   flags;
 621
 622         spin_lock_irqsave(&dwc->lock, flags);
 623
 624         switch (dwc->dr_mode) {
 625         case USB_DR_MODE_PERIPHERAL:
 626         case USB_DR_MODE_OTG:
 627                 dwc3_gadget_prepare(dwc);
 628                 /* FALLTHROUGH */
 629         case USB_DR_MODE_HOST:
 630         default:
 631                 dwc3_event_buffers_cleanup(dwc);
 632                 break;
 633         }
 634
 635         spin_unlock_irqrestore(&dwc->lock, flags);
 636
 637         return 0;
 638 }
 639
 640 static void dwc3_complete(struct device *dev)
 641 {
 642         struct dwc3     *dwc = dev_get_drvdata(dev);
 643         unsigned long   flags;
 644
 645         spin_lock_irqsave(&dwc->lock, flags);
 646
 647         switch (dwc->dr_mode) {
 648         case USB_DR_MODE_PERIPHERAL:
 649         case USB_DR_MODE_OTG:
 650                 dwc3_gadget_complete(dwc);
 651                 /* FALLTHROUGH */
 652         case USB_DR_MODE_HOST:
 653         default:
 654                 dwc3_event_buffers_setup(dwc);
 655                 break;
 656         }
 657
 658         spin_unlock_irqrestore(&dwc->lock, flags);
 659 }
 660
 661 static int dwc3_suspend(struct device *dev)
 662 {
 663         struct dwc3     *dwc = dev_get_drvdata(dev);
 664         unsigned long   flags;
 665
 666         spin_lock_irqsave(&dwc->lock, flags);
 667
 668         switch (dwc->dr_mode) {
 669         case USB_DR_MODE_PERIPHERAL:
 670         case USB_DR_MODE_OTG:
 671                 dwc3_gadget_suspend(dwc);
 672                 /* FALLTHROUGH */
 673         case USB_DR_MODE_HOST:
 674         default:
 675                 /* do nothing */
 676                 break;
 677         }
 678
 679         dwc->gctl = dwc3_readl(dwc->regs, DWC3_GCTL);
 680         spin_unlock_irqrestore(&dwc->lock, flags);
 681
 682         usb_phy_shutdown(dwc->usb3_phy);
 683         usb_phy_shutdown(dwc->usb2_phy);
 684
 685         return 0;
 686 }
 687
 688 static int dwc3_resume(struct device *dev)
 689 {
 690         struct dwc3     *dwc = dev_get_drvdata(dev);
 691         unsigned long   flags;
 692
 693         usb_phy_init(dwc->usb3_phy);
 694         usb_phy_init(dwc->usb2_phy);
 695         msleep(100);
 696
 697         spin_lock_irqsave(&dwc->lock, flags);
 698
 699         dwc3_writel(dwc->regs, DWC3_GCTL, dwc->gctl);
 700
 701         switch (dwc->dr_mode) {
 702         case USB_DR_MODE_PERIPHERAL:
 703         case USB_DR_MODE_OTG:
 704                 dwc3_gadget_resume(dwc);
 705                 /* FALLTHROUGH */
 706         case USB_DR_MODE_HOST:
 707         default:
 708                 /* do nothing */
 709                 break;
 710         }
 711
 712         spin_unlock_irqrestore(&dwc->lock, flags);
 713
 714         pm_runtime_disable(dev);
 715         pm_runtime_set_active(dev);
 716         pm_runtime_enable(dev);
 717
 718         return 0;
 719 }
 720
 721 static const struct dev_pm_ops dwc3_dev_pm_ops = {
 722         .prepare        = dwc3_prepare,
 723         .complete       = dwc3_complete,
 724
 725         SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
 726 };
 727
 728 #define DWC3_PM_OPS     &(dwc3_dev_pm_ops)
 729 #else
 730 #define DWC3_PM_OPS     NULL
 731 #endif
 732
 733 #ifdef CONFIG_OF
 734 static const struct of_device_id of_dwc3_match[] = {
 735         {
 736                 .compatible = "snps,dwc3"
 737         },
 738         {
 739                 .compatible = "synopsys,dwc3"
 740         },
 741         { },
 742 };
 743 MODULE_DEVICE_TABLE(of, of_dwc3_match);
 744 #endif
 745
 746 static struct platform_driver dwc3_driver = {
 747         .probe          = dwc3_probe,
 748         .remove         = dwc3_remove,
 749         .driver         = {
 750                 .name   = "dwc3",
 751                 .of_match_table = of_match_ptr(of_dwc3_match),
 752                 .pm     = DWC3_PM_OPS,
 753         },
 754 };
 755
 756 module_platform_driver(dwc3_driver);
 757
 758 MODULE_ALIAS("platform:dwc3");
 759 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
 760 MODULE_LICENSE("GPL v2");
 761 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");