2 * core.c - DesignWare USB3 DRD Controller Core file
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. The names of the above-listed copyright holders may not be used
19 * to endorse or promote products derived from this software without
20 * specific prior written permission.
22 * ALTERNATIVELY, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2, as published by the Free
24 * Software Foundation.
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 #include <linux/module.h>
40 #include <linux/kernel.h>
41 #include <linux/slab.h>
42 #include <linux/spinlock.h>
43 #include <linux/platform_device.h>
44 #include <linux/pm_runtime.h>
45 #include <linux/interrupt.h>
46 #include <linux/ioport.h>
48 #include <linux/list.h>
49 #include <linux/delay.h>
50 #include <linux/dma-mapping.h>
53 #include <linux/usb/otg.h>
54 #include <linux/usb/ch9.h>
55 #include <linux/usb/gadget.h>
63 static char *maximum_speed = "super";
64 module_param(maximum_speed, charp, 0);
65 MODULE_PARM_DESC(maximum_speed, "Maximum supported speed.");
67 /* -------------------------------------------------------------------------- */
69 #define DWC3_DEVS_POSSIBLE 32
71 static DECLARE_BITMAP(dwc3_devs, DWC3_DEVS_POSSIBLE);
73 int dwc3_get_device_id(void)
78 id = find_first_zero_bit(dwc3_devs, DWC3_DEVS_POSSIBLE);
79 if (id < DWC3_DEVS_POSSIBLE) {
82 old = test_and_set_bit(id, dwc3_devs);
86 pr_err("dwc3: no space for new device\n");
92 EXPORT_SYMBOL_GPL(dwc3_get_device_id);
94 void dwc3_put_device_id(int id)
101 ret = test_bit(id, dwc3_devs);
102 WARN(!ret, "dwc3: ID %d not in use\n", id);
103 smp_mb__before_clear_bit();
104 clear_bit(id, dwc3_devs);
106 EXPORT_SYMBOL_GPL(dwc3_put_device_id);
108 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
112 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
113 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
114 reg |= DWC3_GCTL_PRTCAPDIR(mode);
115 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
119 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
120 * @dwc: pointer to our context structure
122 static void dwc3_core_soft_reset(struct dwc3 *dwc)
126 /* Before Resetting PHY, put Core in Reset */
127 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
128 reg |= DWC3_GCTL_CORESOFTRESET;
129 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
131 /* Assert USB3 PHY reset */
132 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
133 reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
134 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
136 /* Assert USB2 PHY reset */
137 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
138 reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
139 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
141 usb_phy_init(dwc->usb2_phy);
142 usb_phy_init(dwc->usb3_phy);
145 /* Clear USB3 PHY reset */
146 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
147 reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
148 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
150 /* Clear USB2 PHY reset */
151 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
152 reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
153 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
157 /* After PHYs are stable we can take Core out of reset state */
158 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
159 reg &= ~DWC3_GCTL_CORESOFTRESET;
160 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
164 * dwc3_free_one_event_buffer - Frees one event buffer
165 * @dwc: Pointer to our controller context structure
166 * @evt: Pointer to event buffer to be freed
168 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
169 struct dwc3_event_buffer *evt)
171 dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
176 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
177 * @dwc: Pointer to our controller context structure
178 * @length: size of the event buffer
180 * Returns a pointer to the allocated event buffer structure on success
181 * otherwise ERR_PTR(errno).
183 static struct dwc3_event_buffer *__devinit
184 dwc3_alloc_one_event_buffer(struct dwc3 *dwc, unsigned length)
186 struct dwc3_event_buffer *evt;
188 evt = kzalloc(sizeof(*evt), GFP_KERNEL);
190 return ERR_PTR(-ENOMEM);
193 evt->length = length;
194 evt->buf = dma_alloc_coherent(dwc->dev, length,
195 &evt->dma, GFP_KERNEL);
198 return ERR_PTR(-ENOMEM);
205 * dwc3_free_event_buffers - frees all allocated event buffers
206 * @dwc: Pointer to our controller context structure
208 static void dwc3_free_event_buffers(struct dwc3 *dwc)
210 struct dwc3_event_buffer *evt;
213 for (i = 0; i < dwc->num_event_buffers; i++) {
214 evt = dwc->ev_buffs[i];
216 dwc3_free_one_event_buffer(dwc, evt);
219 kfree(dwc->ev_buffs);
223 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
224 * @dwc: pointer to our controller context structure
225 * @length: size of event buffer
227 * Returns 0 on success otherwise negative errno. In the error case, dwc
228 * may contain some buffers allocated but not all which were requested.
230 static int __devinit dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
235 num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
236 dwc->num_event_buffers = num;
238 dwc->ev_buffs = kzalloc(sizeof(*dwc->ev_buffs) * num, GFP_KERNEL);
239 if (!dwc->ev_buffs) {
240 dev_err(dwc->dev, "can't allocate event buffers array\n");
244 for (i = 0; i < num; i++) {
245 struct dwc3_event_buffer *evt;
247 evt = dwc3_alloc_one_event_buffer(dwc, length);
249 dev_err(dwc->dev, "can't allocate event buffer\n");
252 dwc->ev_buffs[i] = evt;
259 * dwc3_event_buffers_setup - setup our allocated event buffers
260 * @dwc: pointer to our controller context structure
262 * Returns 0 on success otherwise negative errno.
264 static int dwc3_event_buffers_setup(struct dwc3 *dwc)
266 struct dwc3_event_buffer *evt;
269 for (n = 0; n < dwc->num_event_buffers; n++) {
270 evt = dwc->ev_buffs[n];
271 dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",
272 evt->buf, (unsigned long long) evt->dma,
277 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
278 lower_32_bits(evt->dma));
279 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
280 upper_32_bits(evt->dma));
281 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
282 evt->length & 0xffff);
283 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
289 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
291 struct dwc3_event_buffer *evt;
294 for (n = 0; n < dwc->num_event_buffers; n++) {
295 evt = dwc->ev_buffs[n];
299 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
300 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
301 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), 0);
302 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
306 static void __devinit dwc3_cache_hwparams(struct dwc3 *dwc)
308 struct dwc3_hwparams *parms = &dwc->hwparams;
310 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
311 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
312 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
313 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
314 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
315 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
316 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
317 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
318 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
322 * dwc3_core_init - Low-level initialization of DWC3 Core
323 * @dwc: Pointer to our controller context structure
325 * Returns 0 on success otherwise negative errno.
327 static int __devinit dwc3_core_init(struct dwc3 *dwc)
329 unsigned long timeout;
333 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
334 /* This should read as U3 followed by revision number */
335 if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
336 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
342 /* issue device SoftReset too */
343 timeout = jiffies + msecs_to_jiffies(500);
344 dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
346 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
347 if (!(reg & DWC3_DCTL_CSFTRST))
350 if (time_after(jiffies, timeout)) {
351 dev_err(dwc->dev, "Reset Timed Out\n");
359 dwc3_core_soft_reset(dwc);
361 dwc3_cache_hwparams(dwc);
363 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
364 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
365 reg &= ~DWC3_GCTL_DISSCRAMBLE;
367 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
368 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
369 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
372 dev_dbg(dwc->dev, "No power optimization available\n");
376 * WORKAROUND: DWC3 revisions <1.90a have a bug
377 * where the device can fail to connect at SuperSpeed
378 * and falls back to high-speed mode which causes
379 * the device to enter a Connect/Disconnect loop
381 if (dwc->revision < DWC3_REVISION_190A)
382 reg |= DWC3_GCTL_U2RSTECN;
384 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
386 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
388 dev_err(dwc->dev, "failed to allocate event buffers\n");
393 ret = dwc3_event_buffers_setup(dwc);
395 dev_err(dwc->dev, "failed to setup event buffers\n");
402 dwc3_free_event_buffers(dwc);
408 static void dwc3_core_exit(struct dwc3 *dwc)
410 dwc3_event_buffers_cleanup(dwc);
411 dwc3_free_event_buffers(dwc);
414 #define DWC3_ALIGN_MASK (16 - 1)
416 static int __devinit dwc3_probe(struct platform_device *pdev)
418 struct device_node *node = pdev->dev.of_node;
419 struct resource *res;
421 struct device *dev = &pdev->dev;
430 mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
432 dev_err(dev, "not enough memory\n");
435 dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
438 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
440 dev_err(dev, "missing IRQ\n");
443 dwc->xhci_resources[1].start = res->start;
444 dwc->xhci_resources[1].end = res->end;
445 dwc->xhci_resources[1].flags = res->flags;
446 dwc->xhci_resources[1].name = res->name;
448 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
450 dev_err(dev, "missing memory resource\n");
453 dwc->xhci_resources[0].start = res->start;
454 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
456 dwc->xhci_resources[0].flags = res->flags;
457 dwc->xhci_resources[0].name = res->name;
460 * Request memory region but exclude xHCI regs,
461 * since it will be requested by the xhci-plat driver.
463 res = devm_request_mem_region(dev, res->start + DWC3_GLOBALS_REGS_START,
464 resource_size(res) - DWC3_GLOBALS_REGS_START,
467 dev_err(dev, "can't request mem region\n");
471 regs = devm_ioremap_nocache(dev, res->start, resource_size(res));
473 dev_err(dev, "ioremap failed\n");
477 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
478 if (IS_ERR_OR_NULL(dwc->usb2_phy)) {
479 dev_err(dev, "no usb2 phy configured\n");
480 return -EPROBE_DEFER;
483 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
484 if (IS_ERR_OR_NULL(dwc->usb3_phy)) {
485 dev_err(dev, "no usb3 phy configured\n");
486 return -EPROBE_DEFER;
489 spin_lock_init(&dwc->lock);
490 platform_set_drvdata(pdev, dwc);
493 dwc->regs_size = resource_size(res);
496 if (!strncmp("super", maximum_speed, 5))
497 dwc->maximum_speed = DWC3_DCFG_SUPERSPEED;
498 else if (!strncmp("high", maximum_speed, 4))
499 dwc->maximum_speed = DWC3_DCFG_HIGHSPEED;
500 else if (!strncmp("full", maximum_speed, 4))
501 dwc->maximum_speed = DWC3_DCFG_FULLSPEED1;
502 else if (!strncmp("low", maximum_speed, 3))
503 dwc->maximum_speed = DWC3_DCFG_LOWSPEED;
505 dwc->maximum_speed = DWC3_DCFG_SUPERSPEED;
507 if (of_get_property(node, "tx-fifo-resize", NULL))
508 dwc->needs_fifo_resize = true;
510 pm_runtime_enable(dev);
511 pm_runtime_get_sync(dev);
512 pm_runtime_forbid(dev);
514 ret = dwc3_core_init(dwc);
516 dev_err(dev, "failed to initialize core\n");
520 mode = DWC3_MODE(dwc->hwparams.hwparams0);
523 case DWC3_MODE_DEVICE:
524 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
525 ret = dwc3_gadget_init(dwc);
527 dev_err(dev, "failed to initialize gadget\n");
532 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
533 ret = dwc3_host_init(dwc);
535 dev_err(dev, "failed to initialize host\n");
540 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
541 ret = dwc3_host_init(dwc);
543 dev_err(dev, "failed to initialize host\n");
547 ret = dwc3_gadget_init(dwc);
549 dev_err(dev, "failed to initialize gadget\n");
554 dev_err(dev, "Unsupported mode of operation %d\n", mode);
559 ret = dwc3_debugfs_init(dwc);
561 dev_err(dev, "failed to initialize debugfs\n");
565 pm_runtime_allow(dev);
571 case DWC3_MODE_DEVICE:
572 dwc3_gadget_exit(dwc);
579 dwc3_gadget_exit(dwc);
592 static int __devexit dwc3_remove(struct platform_device *pdev)
594 struct dwc3 *dwc = platform_get_drvdata(pdev);
595 struct resource *res;
597 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
599 pm_runtime_put(&pdev->dev);
600 pm_runtime_disable(&pdev->dev);
602 dwc3_debugfs_exit(dwc);
605 case DWC3_MODE_DEVICE:
606 dwc3_gadget_exit(dwc);
613 dwc3_gadget_exit(dwc);
625 static struct platform_driver dwc3_driver = {
627 .remove = __devexit_p(dwc3_remove),
633 module_platform_driver(dwc3_driver);
635 MODULE_ALIAS("platform:dwc3");
636 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
637 MODULE_LICENSE("Dual BSD/GPL");
638 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");