2 * core.c - DesignWare USB3 DRD Controller Core file
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
22 #include <linux/version.h>
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/slab.h>
26 #include <linux/spinlock.h>
27 #include <linux/platform_device.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/interrupt.h>
30 #include <linux/ioport.h>
32 #include <linux/list.h>
33 #include <linux/delay.h>
34 #include <linux/dma-mapping.h>
36 #include <linux/acpi.h>
37 #include <linux/pinctrl/consumer.h>
39 #include <linux/usb/ch9.h>
40 #include <linux/usb/gadget.h>
41 #include <linux/usb/of.h>
42 #include <linux/usb/otg.h>
44 #include "platform_data.h"
51 /* -------------------------------------------------------------------------- */
53 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
57 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
58 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
59 reg |= DWC3_GCTL_PRTCAPDIR(mode);
60 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
63 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
65 struct dwc3 *dwc = dep->dwc;
68 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
69 DWC3_GDBGFIFOSPACE_NUM(dep->number) |
70 DWC3_GDBGFIFOSPACE_TYPE(type));
72 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
74 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
78 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
79 * @dwc: pointer to our context structure
81 static int dwc3_core_soft_reset(struct dwc3 *dwc)
87 usb_phy_init(dwc->usb2_phy);
88 usb_phy_init(dwc->usb3_phy);
89 ret = phy_init(dwc->usb2_generic_phy);
93 ret = phy_init(dwc->usb3_generic_phy);
95 phy_exit(dwc->usb2_generic_phy);
100 * We're resetting only the device side because, if we're in host mode,
101 * XHCI driver will reset the host block. If dwc3 was configured for
102 * host-only mode, then we can return early.
104 if (dwc->dr_mode == USB_DR_MODE_HOST)
107 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
108 reg |= DWC3_DCTL_CSFTRST;
109 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
112 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
113 if (!(reg & DWC3_DCTL_CSFTRST))
123 * dwc3_soft_reset - Issue soft reset
124 * @dwc: Pointer to our controller context structure
126 static int dwc3_soft_reset(struct dwc3 *dwc)
128 unsigned long timeout;
131 timeout = jiffies + msecs_to_jiffies(500);
132 dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
134 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
135 if (!(reg & DWC3_DCTL_CSFTRST))
138 if (time_after(jiffies, timeout)) {
139 dev_err(dwc->dev, "Reset Timed Out\n");
150 * dwc3_frame_length_adjustment - Adjusts frame length if required
151 * @dwc3: Pointer to our controller context structure
153 static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
158 if (dwc->revision < DWC3_REVISION_250A)
164 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
165 dft = reg & DWC3_GFLADJ_30MHZ_MASK;
166 if (!dev_WARN_ONCE(dwc->dev, dft == dwc->fladj,
167 "request value same as default, ignoring\n")) {
168 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
169 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
170 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
175 * dwc3_free_one_event_buffer - Frees one event buffer
176 * @dwc: Pointer to our controller context structure
177 * @evt: Pointer to event buffer to be freed
179 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
180 struct dwc3_event_buffer *evt)
182 dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
186 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
187 * @dwc: Pointer to our controller context structure
188 * @length: size of the event buffer
190 * Returns a pointer to the allocated event buffer structure on success
191 * otherwise ERR_PTR(errno).
193 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
196 struct dwc3_event_buffer *evt;
198 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
200 return ERR_PTR(-ENOMEM);
203 evt->length = length;
204 evt->buf = dma_alloc_coherent(dwc->dev, length,
205 &evt->dma, GFP_KERNEL);
207 return ERR_PTR(-ENOMEM);
213 * dwc3_free_event_buffers - frees all allocated event buffers
214 * @dwc: Pointer to our controller context structure
216 static void dwc3_free_event_buffers(struct dwc3 *dwc)
218 struct dwc3_event_buffer *evt;
222 dwc3_free_one_event_buffer(dwc, evt);
226 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
227 * @dwc: pointer to our controller context structure
228 * @length: size of event buffer
230 * Returns 0 on success otherwise negative errno. In the error case, dwc
231 * may contain some buffers allocated but not all which were requested.
233 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
235 struct dwc3_event_buffer *evt;
237 evt = dwc3_alloc_one_event_buffer(dwc, length);
239 dev_err(dwc->dev, "can't allocate event buffer\n");
248 * dwc3_event_buffers_setup - setup our allocated event buffers
249 * @dwc: pointer to our controller context structure
251 * Returns 0 on success otherwise negative errno.
253 static int dwc3_event_buffers_setup(struct dwc3 *dwc)
255 struct dwc3_event_buffer *evt;
258 dwc3_trace(trace_dwc3_core,
259 "Event buf %p dma %08llx length %d\n",
260 evt->buf, (unsigned long long) evt->dma,
265 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
266 lower_32_bits(evt->dma));
267 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
268 upper_32_bits(evt->dma));
269 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
270 DWC3_GEVNTSIZ_SIZE(evt->length));
271 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
276 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
278 struct dwc3_event_buffer *evt;
284 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
285 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
286 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
287 | DWC3_GEVNTSIZ_SIZE(0));
288 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
291 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
293 if (!dwc->has_hibernation)
296 if (!dwc->nr_scratch)
299 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
300 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
301 if (!dwc->scratchbuf)
307 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
309 dma_addr_t scratch_addr;
313 if (!dwc->has_hibernation)
316 if (!dwc->nr_scratch)
319 /* should never fall here */
320 if (!WARN_ON(dwc->scratchbuf))
323 scratch_addr = dma_map_single(dwc->dev, dwc->scratchbuf,
324 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
326 if (dma_mapping_error(dwc->dev, scratch_addr)) {
327 dev_err(dwc->dev, "failed to map scratch buffer\n");
332 dwc->scratch_addr = scratch_addr;
334 param = lower_32_bits(scratch_addr);
336 ret = dwc3_send_gadget_generic_command(dwc,
337 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
341 param = upper_32_bits(scratch_addr);
343 ret = dwc3_send_gadget_generic_command(dwc,
344 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
351 dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
352 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
358 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
360 if (!dwc->has_hibernation)
363 if (!dwc->nr_scratch)
366 /* should never fall here */
367 if (!WARN_ON(dwc->scratchbuf))
370 dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
371 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
372 kfree(dwc->scratchbuf);
375 static void dwc3_core_num_eps(struct dwc3 *dwc)
377 struct dwc3_hwparams *parms = &dwc->hwparams;
379 dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
380 dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
382 dwc3_trace(trace_dwc3_core, "found %d IN and %d OUT endpoints",
383 dwc->num_in_eps, dwc->num_out_eps);
386 static void dwc3_cache_hwparams(struct dwc3 *dwc)
388 struct dwc3_hwparams *parms = &dwc->hwparams;
390 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
391 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
392 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
393 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
394 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
395 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
396 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
397 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
398 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
402 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
403 * @dwc: Pointer to our controller context structure
405 * Returns 0 on success. The USB PHY interfaces are configured but not
406 * initialized. The PHY interfaces and the PHYs get initialized together with
407 * the core in dwc3_core_init.
409 static int dwc3_phy_setup(struct dwc3 *dwc)
414 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
417 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
418 * to '0' during coreConsultant configuration. So default value
419 * will be '0' when the core is reset. Application needs to set it
420 * to '1' after the core initialization is completed.
422 if (dwc->revision > DWC3_REVISION_194A)
423 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
425 if (dwc->u2ss_inp3_quirk)
426 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
428 if (dwc->dis_rxdet_inp3_quirk)
429 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
431 if (dwc->req_p1p2p3_quirk)
432 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
434 if (dwc->del_p1p2p3_quirk)
435 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
437 if (dwc->del_phy_power_chg_quirk)
438 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
440 if (dwc->lfps_filter_quirk)
441 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
443 if (dwc->rx_detect_poll_quirk)
444 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
446 if (dwc->tx_de_emphasis_quirk)
447 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
449 if (dwc->dis_u3_susphy_quirk)
450 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
452 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
454 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
456 /* Select the HS PHY interface */
457 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
458 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
459 if (dwc->hsphy_interface &&
460 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
461 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
463 } else if (dwc->hsphy_interface &&
464 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
465 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
466 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
468 /* Relying on default value. */
469 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
473 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
474 /* Making sure the interface and PHY are operational */
475 ret = dwc3_soft_reset(dwc);
481 ret = dwc3_ulpi_init(dwc);
490 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
491 * '0' during coreConsultant configuration. So default value will
492 * be '0' when the core is reset. Application needs to set it to
493 * '1' after the core initialization is completed.
495 if (dwc->revision > DWC3_REVISION_194A)
496 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
498 if (dwc->dis_u2_susphy_quirk)
499 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
501 if (dwc->dis_enblslpm_quirk)
502 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
504 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
510 * dwc3_core_init - Low-level initialization of DWC3 Core
511 * @dwc: Pointer to our controller context structure
513 * Returns 0 on success otherwise negative errno.
515 static int dwc3_core_init(struct dwc3 *dwc)
517 u32 hwparams4 = dwc->hwparams.hwparams4;
521 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
522 /* This should read as U3 followed by revision number */
523 if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) {
524 /* Detected DWC_usb3 IP */
526 } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) {
527 /* Detected DWC_usb31 IP */
528 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
529 dwc->revision |= DWC3_REVISION_IS_DWC31;
531 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
537 * Write Linux Version Code to our GUID register so it's easy to figure
538 * out which kernel version a bug was found.
540 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
542 /* Handle USB2.0-only core configuration */
543 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
544 DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
545 if (dwc->maximum_speed == USB_SPEED_SUPER)
546 dwc->maximum_speed = USB_SPEED_HIGH;
549 /* issue device SoftReset too */
550 ret = dwc3_soft_reset(dwc);
554 ret = dwc3_core_soft_reset(dwc);
558 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
559 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
561 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
562 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
564 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
565 * issue which would cause xHCI compliance tests to fail.
567 * Because of that we cannot enable clock gating on such
572 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
575 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
576 dwc->dr_mode == USB_DR_MODE_OTG) &&
577 (dwc->revision >= DWC3_REVISION_210A &&
578 dwc->revision <= DWC3_REVISION_250A))
579 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
581 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
583 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
584 /* enable hibernation here */
585 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
588 * REVISIT Enabling this bit so that host-mode hibernation
589 * will work. Device-mode hibernation is not yet implemented.
591 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
594 dwc3_trace(trace_dwc3_core, "No power optimization available\n");
597 /* check if current dwc3 is on simulation board */
598 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
599 dwc3_trace(trace_dwc3_core,
600 "running on FPGA platform\n");
604 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
605 "disable_scramble cannot be used on non-FPGA builds\n");
607 if (dwc->disable_scramble_quirk && dwc->is_fpga)
608 reg |= DWC3_GCTL_DISSCRAMBLE;
610 reg &= ~DWC3_GCTL_DISSCRAMBLE;
612 if (dwc->u2exit_lfps_quirk)
613 reg |= DWC3_GCTL_U2EXIT_LFPS;
616 * WORKAROUND: DWC3 revisions <1.90a have a bug
617 * where the device can fail to connect at SuperSpeed
618 * and falls back to high-speed mode which causes
619 * the device to enter a Connect/Disconnect loop
621 if (dwc->revision < DWC3_REVISION_190A)
622 reg |= DWC3_GCTL_U2RSTECN;
624 dwc3_core_num_eps(dwc);
626 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
628 ret = dwc3_alloc_scratch_buffers(dwc);
632 ret = dwc3_setup_scratch_buffers(dwc);
639 dwc3_free_scratch_buffers(dwc);
642 usb_phy_shutdown(dwc->usb2_phy);
643 usb_phy_shutdown(dwc->usb3_phy);
644 phy_exit(dwc->usb2_generic_phy);
645 phy_exit(dwc->usb3_generic_phy);
651 static void dwc3_core_exit(struct dwc3 *dwc)
653 dwc3_free_scratch_buffers(dwc);
654 usb_phy_shutdown(dwc->usb2_phy);
655 usb_phy_shutdown(dwc->usb3_phy);
656 phy_exit(dwc->usb2_generic_phy);
657 phy_exit(dwc->usb3_generic_phy);
660 static int dwc3_core_get_phy(struct dwc3 *dwc)
662 struct device *dev = dwc->dev;
663 struct device_node *node = dev->of_node;
667 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
668 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
670 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
671 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
674 if (IS_ERR(dwc->usb2_phy)) {
675 ret = PTR_ERR(dwc->usb2_phy);
676 if (ret == -ENXIO || ret == -ENODEV) {
677 dwc->usb2_phy = NULL;
678 } else if (ret == -EPROBE_DEFER) {
681 dev_err(dev, "no usb2 phy configured\n");
686 if (IS_ERR(dwc->usb3_phy)) {
687 ret = PTR_ERR(dwc->usb3_phy);
688 if (ret == -ENXIO || ret == -ENODEV) {
689 dwc->usb3_phy = NULL;
690 } else if (ret == -EPROBE_DEFER) {
693 dev_err(dev, "no usb3 phy configured\n");
698 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
699 if (IS_ERR(dwc->usb2_generic_phy)) {
700 ret = PTR_ERR(dwc->usb2_generic_phy);
701 if (ret == -ENOSYS || ret == -ENODEV) {
702 dwc->usb2_generic_phy = NULL;
703 } else if (ret == -EPROBE_DEFER) {
706 dev_err(dev, "no usb2 phy configured\n");
711 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
712 if (IS_ERR(dwc->usb3_generic_phy)) {
713 ret = PTR_ERR(dwc->usb3_generic_phy);
714 if (ret == -ENOSYS || ret == -ENODEV) {
715 dwc->usb3_generic_phy = NULL;
716 } else if (ret == -EPROBE_DEFER) {
719 dev_err(dev, "no usb3 phy configured\n");
727 static int dwc3_core_init_mode(struct dwc3 *dwc)
729 struct device *dev = dwc->dev;
732 switch (dwc->dr_mode) {
733 case USB_DR_MODE_PERIPHERAL:
734 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
735 ret = dwc3_gadget_init(dwc);
737 dev_err(dev, "failed to initialize gadget\n");
741 case USB_DR_MODE_HOST:
742 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
743 ret = dwc3_host_init(dwc);
745 dev_err(dev, "failed to initialize host\n");
749 case USB_DR_MODE_OTG:
750 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
751 ret = dwc3_host_init(dwc);
753 dev_err(dev, "failed to initialize host\n");
757 ret = dwc3_gadget_init(dwc);
759 dev_err(dev, "failed to initialize gadget\n");
764 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
771 static void dwc3_core_exit_mode(struct dwc3 *dwc)
773 switch (dwc->dr_mode) {
774 case USB_DR_MODE_PERIPHERAL:
775 dwc3_gadget_exit(dwc);
777 case USB_DR_MODE_HOST:
780 case USB_DR_MODE_OTG:
782 dwc3_gadget_exit(dwc);
790 #define DWC3_ALIGN_MASK (16 - 1)
792 static int dwc3_probe(struct platform_device *pdev)
794 struct device *dev = &pdev->dev;
795 struct dwc3_platform_data *pdata = dev_get_platdata(dev);
796 struct resource *res;
798 u8 lpm_nyet_threshold;
807 mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
811 dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
815 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
817 dev_err(dev, "missing IRQ\n");
820 dwc->xhci_resources[1].start = res->start;
821 dwc->xhci_resources[1].end = res->end;
822 dwc->xhci_resources[1].flags = res->flags;
823 dwc->xhci_resources[1].name = res->name;
825 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
827 dev_err(dev, "missing memory resource\n");
831 dwc->xhci_resources[0].start = res->start;
832 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
834 dwc->xhci_resources[0].flags = res->flags;
835 dwc->xhci_resources[0].name = res->name;
837 res->start += DWC3_GLOBALS_REGS_START;
840 * Request memory region but exclude xHCI regs,
841 * since it will be requested by the xhci-plat driver.
843 regs = devm_ioremap_resource(dev, res);
850 dwc->regs_size = resource_size(res);
852 /* default to highest possible threshold */
853 lpm_nyet_threshold = 0xff;
855 /* default to -3.5dB de-emphasis */
859 * default to assert utmi_sleep_n and use maximum allowed HIRD
860 * threshold value of 0b1100
864 dwc->maximum_speed = usb_get_maximum_speed(dev);
865 dwc->dr_mode = usb_get_dr_mode(dev);
867 dwc->has_lpm_erratum = device_property_read_bool(dev,
868 "snps,has-lpm-erratum");
869 device_property_read_u8(dev, "snps,lpm-nyet-threshold",
870 &lpm_nyet_threshold);
871 dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
872 "snps,is-utmi-l1-suspend");
873 device_property_read_u8(dev, "snps,hird-threshold",
875 dwc->usb3_lpm_capable = device_property_read_bool(dev,
876 "snps,usb3_lpm_capable");
878 dwc->disable_scramble_quirk = device_property_read_bool(dev,
879 "snps,disable_scramble_quirk");
880 dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
881 "snps,u2exit_lfps_quirk");
882 dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
883 "snps,u2ss_inp3_quirk");
884 dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
885 "snps,req_p1p2p3_quirk");
886 dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
887 "snps,del_p1p2p3_quirk");
888 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
889 "snps,del_phy_power_chg_quirk");
890 dwc->lfps_filter_quirk = device_property_read_bool(dev,
891 "snps,lfps_filter_quirk");
892 dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
893 "snps,rx_detect_poll_quirk");
894 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
895 "snps,dis_u3_susphy_quirk");
896 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
897 "snps,dis_u2_susphy_quirk");
898 dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
899 "snps,dis_enblslpm_quirk");
900 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
901 "snps,dis_rxdet_inp3_quirk");
903 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
904 "snps,tx_de_emphasis_quirk");
905 device_property_read_u8(dev, "snps,tx_de_emphasis",
907 device_property_read_string(dev, "snps,hsphy_interface",
908 &dwc->hsphy_interface);
909 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
913 dwc->maximum_speed = pdata->maximum_speed;
914 dwc->has_lpm_erratum = pdata->has_lpm_erratum;
915 if (pdata->lpm_nyet_threshold)
916 lpm_nyet_threshold = pdata->lpm_nyet_threshold;
917 dwc->is_utmi_l1_suspend = pdata->is_utmi_l1_suspend;
918 if (pdata->hird_threshold)
919 hird_threshold = pdata->hird_threshold;
921 dwc->usb3_lpm_capable = pdata->usb3_lpm_capable;
922 dwc->dr_mode = pdata->dr_mode;
924 dwc->disable_scramble_quirk = pdata->disable_scramble_quirk;
925 dwc->u2exit_lfps_quirk = pdata->u2exit_lfps_quirk;
926 dwc->u2ss_inp3_quirk = pdata->u2ss_inp3_quirk;
927 dwc->req_p1p2p3_quirk = pdata->req_p1p2p3_quirk;
928 dwc->del_p1p2p3_quirk = pdata->del_p1p2p3_quirk;
929 dwc->del_phy_power_chg_quirk = pdata->del_phy_power_chg_quirk;
930 dwc->lfps_filter_quirk = pdata->lfps_filter_quirk;
931 dwc->rx_detect_poll_quirk = pdata->rx_detect_poll_quirk;
932 dwc->dis_u3_susphy_quirk = pdata->dis_u3_susphy_quirk;
933 dwc->dis_u2_susphy_quirk = pdata->dis_u2_susphy_quirk;
934 dwc->dis_enblslpm_quirk = pdata->dis_enblslpm_quirk;
935 dwc->dis_rxdet_inp3_quirk = pdata->dis_rxdet_inp3_quirk;
937 dwc->tx_de_emphasis_quirk = pdata->tx_de_emphasis_quirk;
938 if (pdata->tx_de_emphasis)
939 tx_de_emphasis = pdata->tx_de_emphasis;
941 dwc->hsphy_interface = pdata->hsphy_interface;
942 dwc->fladj = pdata->fladj_value;
945 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
946 dwc->tx_de_emphasis = tx_de_emphasis;
948 dwc->hird_threshold = hird_threshold
949 | (dwc->is_utmi_l1_suspend << 4);
951 platform_set_drvdata(pdev, dwc);
952 dwc3_cache_hwparams(dwc);
954 ret = dwc3_phy_setup(dwc);
958 ret = dwc3_core_get_phy(dwc);
962 spin_lock_init(&dwc->lock);
964 if (!dev->dma_mask) {
965 dev->dma_mask = dev->parent->dma_mask;
966 dev->dma_parms = dev->parent->dma_parms;
967 dma_set_coherent_mask(dev, dev->parent->coherent_dma_mask);
970 pm_runtime_enable(dev);
971 pm_runtime_get_sync(dev);
972 pm_runtime_forbid(dev);
974 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
976 dev_err(dwc->dev, "failed to allocate event buffers\n");
981 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
982 dwc->dr_mode = USB_DR_MODE_HOST;
983 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
984 dwc->dr_mode = USB_DR_MODE_PERIPHERAL;
986 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
987 dwc->dr_mode = USB_DR_MODE_OTG;
989 ret = dwc3_core_init(dwc);
991 dev_err(dev, "failed to initialize core\n");
995 /* Check the maximum_speed parameter */
996 switch (dwc->maximum_speed) {
1000 case USB_SPEED_SUPER:
1001 case USB_SPEED_SUPER_PLUS:
1004 dev_err(dev, "invalid maximum_speed parameter %d\n",
1005 dwc->maximum_speed);
1007 case USB_SPEED_UNKNOWN:
1008 /* default to superspeed */
1009 dwc->maximum_speed = USB_SPEED_SUPER;
1012 * default to superspeed plus if we are capable.
1014 if (dwc3_is_usb31(dwc) &&
1015 (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
1016 DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1017 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1022 /* Adjust Frame Length */
1023 dwc3_frame_length_adjustment(dwc);
1025 usb_phy_set_suspend(dwc->usb2_phy, 0);
1026 usb_phy_set_suspend(dwc->usb3_phy, 0);
1027 ret = phy_power_on(dwc->usb2_generic_phy);
1031 ret = phy_power_on(dwc->usb3_generic_phy);
1035 ret = dwc3_event_buffers_setup(dwc);
1037 dev_err(dwc->dev, "failed to setup event buffers\n");
1041 ret = dwc3_core_init_mode(dwc);
1045 dwc3_debugfs_init(dwc);
1046 pm_runtime_allow(dev);
1051 dwc3_event_buffers_cleanup(dwc);
1054 phy_power_off(dwc->usb3_generic_phy);
1057 phy_power_off(dwc->usb2_generic_phy);
1060 usb_phy_set_suspend(dwc->usb2_phy, 1);
1061 usb_phy_set_suspend(dwc->usb3_phy, 1);
1062 dwc3_core_exit(dwc);
1065 dwc3_free_event_buffers(dwc);
1066 dwc3_ulpi_exit(dwc);
1070 * restore res->start back to its original value so that, in case the
1071 * probe is deferred, we don't end up getting error in request the
1072 * memory region the next time probe is called.
1074 res->start -= DWC3_GLOBALS_REGS_START;
1079 static int dwc3_remove(struct platform_device *pdev)
1081 struct dwc3 *dwc = platform_get_drvdata(pdev);
1082 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1085 * restore res->start back to its original value so that, in case the
1086 * probe is deferred, we don't end up getting error in request the
1087 * memory region the next time probe is called.
1089 res->start -= DWC3_GLOBALS_REGS_START;
1091 dwc3_debugfs_exit(dwc);
1092 dwc3_core_exit_mode(dwc);
1093 dwc3_event_buffers_cleanup(dwc);
1094 dwc3_free_event_buffers(dwc);
1096 usb_phy_set_suspend(dwc->usb2_phy, 1);
1097 usb_phy_set_suspend(dwc->usb3_phy, 1);
1098 phy_power_off(dwc->usb2_generic_phy);
1099 phy_power_off(dwc->usb3_generic_phy);
1101 dwc3_core_exit(dwc);
1102 dwc3_ulpi_exit(dwc);
1104 pm_runtime_put_sync(&pdev->dev);
1105 pm_runtime_disable(&pdev->dev);
1110 #ifdef CONFIG_PM_SLEEP
1111 static int dwc3_suspend(struct device *dev)
1113 struct dwc3 *dwc = dev_get_drvdata(dev);
1114 unsigned long flags;
1116 spin_lock_irqsave(&dwc->lock, flags);
1118 switch (dwc->dr_mode) {
1119 case USB_DR_MODE_PERIPHERAL:
1120 case USB_DR_MODE_OTG:
1121 dwc3_gadget_suspend(dwc);
1123 case USB_DR_MODE_HOST:
1125 dwc3_event_buffers_cleanup(dwc);
1129 dwc->gctl = dwc3_readl(dwc->regs, DWC3_GCTL);
1130 spin_unlock_irqrestore(&dwc->lock, flags);
1132 usb_phy_shutdown(dwc->usb3_phy);
1133 usb_phy_shutdown(dwc->usb2_phy);
1134 phy_exit(dwc->usb2_generic_phy);
1135 phy_exit(dwc->usb3_generic_phy);
1137 usb_phy_set_suspend(dwc->usb2_phy, 1);
1138 usb_phy_set_suspend(dwc->usb3_phy, 1);
1139 WARN_ON(phy_power_off(dwc->usb2_generic_phy) < 0);
1140 WARN_ON(phy_power_off(dwc->usb3_generic_phy) < 0);
1142 pinctrl_pm_select_sleep_state(dev);
1147 static int dwc3_resume(struct device *dev)
1149 struct dwc3 *dwc = dev_get_drvdata(dev);
1150 unsigned long flags;
1153 pinctrl_pm_select_default_state(dev);
1155 usb_phy_set_suspend(dwc->usb2_phy, 0);
1156 usb_phy_set_suspend(dwc->usb3_phy, 0);
1157 ret = phy_power_on(dwc->usb2_generic_phy);
1161 ret = phy_power_on(dwc->usb3_generic_phy);
1163 goto err_usb2phy_power;
1165 usb_phy_init(dwc->usb3_phy);
1166 usb_phy_init(dwc->usb2_phy);
1167 ret = phy_init(dwc->usb2_generic_phy);
1169 goto err_usb3phy_power;
1171 ret = phy_init(dwc->usb3_generic_phy);
1173 goto err_usb2phy_init;
1175 spin_lock_irqsave(&dwc->lock, flags);
1177 dwc3_event_buffers_setup(dwc);
1178 dwc3_writel(dwc->regs, DWC3_GCTL, dwc->gctl);
1180 switch (dwc->dr_mode) {
1181 case USB_DR_MODE_PERIPHERAL:
1182 case USB_DR_MODE_OTG:
1183 dwc3_gadget_resume(dwc);
1185 case USB_DR_MODE_HOST:
1191 spin_unlock_irqrestore(&dwc->lock, flags);
1193 pm_runtime_disable(dev);
1194 pm_runtime_set_active(dev);
1195 pm_runtime_enable(dev);
1200 phy_exit(dwc->usb2_generic_phy);
1203 phy_power_off(dwc->usb3_generic_phy);
1206 phy_power_off(dwc->usb2_generic_phy);
1210 #endif /* CONFIG_PM_SLEEP */
1212 static const struct dev_pm_ops dwc3_dev_pm_ops = {
1213 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
1217 static const struct of_device_id of_dwc3_match[] = {
1219 .compatible = "snps,dwc3"
1222 .compatible = "synopsys,dwc3"
1226 MODULE_DEVICE_TABLE(of, of_dwc3_match);
1231 #define ACPI_ID_INTEL_BSW "808622B7"
1233 static const struct acpi_device_id dwc3_acpi_match[] = {
1234 { ACPI_ID_INTEL_BSW, 0 },
1237 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
1240 static struct platform_driver dwc3_driver = {
1241 .probe = dwc3_probe,
1242 .remove = dwc3_remove,
1245 .of_match_table = of_match_ptr(of_dwc3_match),
1246 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
1247 .pm = &dwc3_dev_pm_ops,
1251 module_platform_driver(dwc3_driver);
1253 MODULE_ALIAS("platform:dwc3");
1254 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1255 MODULE_LICENSE("GPL v2");
1256 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");