2 * core.c - DesignWare USB3 DRD Controller Core file
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/slab.h>
25 #include <linux/spinlock.h>
26 #include <linux/platform_device.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/interrupt.h>
29 #include <linux/ioport.h>
31 #include <linux/list.h>
32 #include <linux/delay.h>
33 #include <linux/dma-mapping.h>
36 #include <linux/usb/ch9.h>
37 #include <linux/usb/gadget.h>
38 #include <linux/usb/of.h>
39 #include <linux/usb/otg.h>
41 #include "platform_data.h"
48 /* -------------------------------------------------------------------------- */
50 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
54 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
55 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
56 reg |= DWC3_GCTL_PRTCAPDIR(mode);
57 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
61 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
62 * @dwc: pointer to our context structure
64 static int dwc3_core_soft_reset(struct dwc3 *dwc)
69 /* Before Resetting PHY, put Core in Reset */
70 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
71 reg |= DWC3_GCTL_CORESOFTRESET;
72 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
74 /* Assert USB3 PHY reset */
75 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
76 reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
77 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
79 /* Assert USB2 PHY reset */
80 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
81 reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
82 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
84 usb_phy_init(dwc->usb2_phy);
85 usb_phy_init(dwc->usb3_phy);
86 ret = phy_init(dwc->usb2_generic_phy);
90 ret = phy_init(dwc->usb3_generic_phy);
92 phy_exit(dwc->usb2_generic_phy);
97 /* Clear USB3 PHY reset */
98 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
99 reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
100 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
102 /* Clear USB2 PHY reset */
103 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
104 reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
105 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
109 /* After PHYs are stable we can take Core out of reset state */
110 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
111 reg &= ~DWC3_GCTL_CORESOFTRESET;
112 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
118 * dwc3_free_one_event_buffer - Frees one event buffer
119 * @dwc: Pointer to our controller context structure
120 * @evt: Pointer to event buffer to be freed
122 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
123 struct dwc3_event_buffer *evt)
125 dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
129 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
130 * @dwc: Pointer to our controller context structure
131 * @length: size of the event buffer
133 * Returns a pointer to the allocated event buffer structure on success
134 * otherwise ERR_PTR(errno).
136 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
139 struct dwc3_event_buffer *evt;
141 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
143 return ERR_PTR(-ENOMEM);
146 evt->length = length;
147 evt->buf = dma_alloc_coherent(dwc->dev, length,
148 &evt->dma, GFP_KERNEL);
150 return ERR_PTR(-ENOMEM);
156 * dwc3_free_event_buffers - frees all allocated event buffers
157 * @dwc: Pointer to our controller context structure
159 static void dwc3_free_event_buffers(struct dwc3 *dwc)
161 struct dwc3_event_buffer *evt;
164 for (i = 0; i < dwc->num_event_buffers; i++) {
165 evt = dwc->ev_buffs[i];
167 dwc3_free_one_event_buffer(dwc, evt);
172 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
173 * @dwc: pointer to our controller context structure
174 * @length: size of event buffer
176 * Returns 0 on success otherwise negative errno. In the error case, dwc
177 * may contain some buffers allocated but not all which were requested.
179 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
184 num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
185 dwc->num_event_buffers = num;
187 dwc->ev_buffs = devm_kzalloc(dwc->dev, sizeof(*dwc->ev_buffs) * num,
189 if (!dwc->ev_buffs) {
190 dev_err(dwc->dev, "can't allocate event buffers array\n");
194 for (i = 0; i < num; i++) {
195 struct dwc3_event_buffer *evt;
197 evt = dwc3_alloc_one_event_buffer(dwc, length);
199 dev_err(dwc->dev, "can't allocate event buffer\n");
202 dwc->ev_buffs[i] = evt;
209 * dwc3_event_buffers_setup - setup our allocated event buffers
210 * @dwc: pointer to our controller context structure
212 * Returns 0 on success otherwise negative errno.
214 static int dwc3_event_buffers_setup(struct dwc3 *dwc)
216 struct dwc3_event_buffer *evt;
219 for (n = 0; n < dwc->num_event_buffers; n++) {
220 evt = dwc->ev_buffs[n];
221 dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",
222 evt->buf, (unsigned long long) evt->dma,
227 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
228 lower_32_bits(evt->dma));
229 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
230 upper_32_bits(evt->dma));
231 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
232 DWC3_GEVNTSIZ_SIZE(evt->length));
233 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
239 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
241 struct dwc3_event_buffer *evt;
244 for (n = 0; n < dwc->num_event_buffers; n++) {
245 evt = dwc->ev_buffs[n];
249 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
250 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
251 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK
252 | DWC3_GEVNTSIZ_SIZE(0));
253 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
257 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
259 if (!dwc->has_hibernation)
262 if (!dwc->nr_scratch)
265 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
266 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
267 if (!dwc->scratchbuf)
273 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
275 dma_addr_t scratch_addr;
279 if (!dwc->has_hibernation)
282 if (!dwc->nr_scratch)
285 /* should never fall here */
286 if (!WARN_ON(dwc->scratchbuf))
289 scratch_addr = dma_map_single(dwc->dev, dwc->scratchbuf,
290 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
292 if (dma_mapping_error(dwc->dev, scratch_addr)) {
293 dev_err(dwc->dev, "failed to map scratch buffer\n");
298 dwc->scratch_addr = scratch_addr;
300 param = lower_32_bits(scratch_addr);
302 ret = dwc3_send_gadget_generic_command(dwc,
303 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
307 param = upper_32_bits(scratch_addr);
309 ret = dwc3_send_gadget_generic_command(dwc,
310 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
317 dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
318 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
324 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
326 if (!dwc->has_hibernation)
329 if (!dwc->nr_scratch)
332 /* should never fall here */
333 if (!WARN_ON(dwc->scratchbuf))
336 dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
337 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
338 kfree(dwc->scratchbuf);
341 static void dwc3_core_num_eps(struct dwc3 *dwc)
343 struct dwc3_hwparams *parms = &dwc->hwparams;
345 dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
346 dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
348 dev_vdbg(dwc->dev, "found %d IN and %d OUT endpoints\n",
349 dwc->num_in_eps, dwc->num_out_eps);
352 static void dwc3_cache_hwparams(struct dwc3 *dwc)
354 struct dwc3_hwparams *parms = &dwc->hwparams;
356 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
357 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
358 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
359 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
360 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
361 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
362 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
363 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
364 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
368 * dwc3_core_init - Low-level initialization of DWC3 Core
369 * @dwc: Pointer to our controller context structure
371 * Returns 0 on success otherwise negative errno.
373 static int dwc3_core_init(struct dwc3 *dwc)
375 unsigned long timeout;
376 u32 hwparams4 = dwc->hwparams.hwparams4;
380 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
381 /* This should read as U3 followed by revision number */
382 if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
383 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
389 /* issue device SoftReset too */
390 timeout = jiffies + msecs_to_jiffies(500);
391 dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
393 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
394 if (!(reg & DWC3_DCTL_CSFTRST))
397 if (time_after(jiffies, timeout)) {
398 dev_err(dwc->dev, "Reset Timed Out\n");
406 ret = dwc3_core_soft_reset(dwc);
410 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
411 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
412 reg &= ~DWC3_GCTL_DISSCRAMBLE;
414 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
415 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
417 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
418 * issue which would cause xHCI compliance tests to fail.
420 * Because of that we cannot enable clock gating on such
425 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
428 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
429 dwc->dr_mode == USB_DR_MODE_OTG) &&
430 (dwc->revision >= DWC3_REVISION_210A &&
431 dwc->revision <= DWC3_REVISION_250A))
432 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
434 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
436 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
437 /* enable hibernation here */
438 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
441 dev_dbg(dwc->dev, "No power optimization available\n");
445 * WORKAROUND: DWC3 revisions <1.90a have a bug
446 * where the device can fail to connect at SuperSpeed
447 * and falls back to high-speed mode which causes
448 * the device to enter a Connect/Disconnect loop
450 if (dwc->revision < DWC3_REVISION_190A)
451 reg |= DWC3_GCTL_U2RSTECN;
453 dwc3_core_num_eps(dwc);
455 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
457 ret = dwc3_alloc_scratch_buffers(dwc);
461 ret = dwc3_setup_scratch_buffers(dwc);
468 dwc3_free_scratch_buffers(dwc);
471 usb_phy_shutdown(dwc->usb2_phy);
472 usb_phy_shutdown(dwc->usb3_phy);
473 phy_exit(dwc->usb2_generic_phy);
474 phy_exit(dwc->usb3_generic_phy);
480 static void dwc3_core_exit(struct dwc3 *dwc)
482 dwc3_free_scratch_buffers(dwc);
483 usb_phy_shutdown(dwc->usb2_phy);
484 usb_phy_shutdown(dwc->usb3_phy);
485 phy_exit(dwc->usb2_generic_phy);
486 phy_exit(dwc->usb3_generic_phy);
489 #define DWC3_ALIGN_MASK (16 - 1)
491 static int dwc3_probe(struct platform_device *pdev)
493 struct device *dev = &pdev->dev;
494 struct dwc3_platform_data *pdata = dev_get_platdata(dev);
495 struct device_node *node = dev->of_node;
496 struct resource *res;
504 mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
506 dev_err(dev, "not enough memory\n");
509 dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
512 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
514 dev_err(dev, "missing IRQ\n");
517 dwc->xhci_resources[1].start = res->start;
518 dwc->xhci_resources[1].end = res->end;
519 dwc->xhci_resources[1].flags = res->flags;
520 dwc->xhci_resources[1].name = res->name;
522 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
524 dev_err(dev, "missing memory resource\n");
529 dwc->maximum_speed = of_usb_get_maximum_speed(node);
531 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
532 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
534 dwc->needs_fifo_resize = of_property_read_bool(node, "tx-fifo-resize");
535 dwc->dr_mode = of_usb_get_dr_mode(node);
537 dwc->maximum_speed = pdata->maximum_speed;
539 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
540 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
542 dwc->needs_fifo_resize = pdata->tx_fifo_resize;
543 dwc->dr_mode = pdata->dr_mode;
545 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
546 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
549 /* default to superspeed if no maximum_speed passed */
550 if (dwc->maximum_speed == USB_SPEED_UNKNOWN)
551 dwc->maximum_speed = USB_SPEED_SUPER;
553 if (IS_ERR(dwc->usb2_phy)) {
554 ret = PTR_ERR(dwc->usb2_phy);
555 if (ret == -ENXIO || ret == -ENODEV) {
556 dwc->usb2_phy = NULL;
557 } else if (ret == -EPROBE_DEFER) {
560 dev_err(dev, "no usb2 phy configured\n");
565 if (IS_ERR(dwc->usb3_phy)) {
566 ret = PTR_ERR(dwc->usb3_phy);
567 if (ret == -ENXIO || ret == -ENODEV) {
568 dwc->usb3_phy = NULL;
569 } else if (ret == -EPROBE_DEFER) {
572 dev_err(dev, "no usb3 phy configured\n");
577 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
578 if (IS_ERR(dwc->usb2_generic_phy)) {
579 ret = PTR_ERR(dwc->usb2_generic_phy);
580 if (ret == -ENOSYS || ret == -ENODEV) {
581 dwc->usb2_generic_phy = NULL;
582 } else if (ret == -EPROBE_DEFER) {
585 dev_err(dev, "no usb2 phy configured\n");
590 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
591 if (IS_ERR(dwc->usb3_generic_phy)) {
592 ret = PTR_ERR(dwc->usb3_generic_phy);
593 if (ret == -ENOSYS || ret == -ENODEV) {
594 dwc->usb3_generic_phy = NULL;
595 } else if (ret == -EPROBE_DEFER) {
598 dev_err(dev, "no usb3 phy configured\n");
603 dwc->xhci_resources[0].start = res->start;
604 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
606 dwc->xhci_resources[0].flags = res->flags;
607 dwc->xhci_resources[0].name = res->name;
609 res->start += DWC3_GLOBALS_REGS_START;
612 * Request memory region but exclude xHCI regs,
613 * since it will be requested by the xhci-plat driver.
615 regs = devm_ioremap_resource(dev, res);
617 return PTR_ERR(regs);
619 spin_lock_init(&dwc->lock);
620 platform_set_drvdata(pdev, dwc);
623 dwc->regs_size = resource_size(res);
626 dev->dma_mask = dev->parent->dma_mask;
627 dev->dma_parms = dev->parent->dma_parms;
628 dma_set_coherent_mask(dev, dev->parent->coherent_dma_mask);
630 pm_runtime_enable(dev);
631 pm_runtime_get_sync(dev);
632 pm_runtime_forbid(dev);
634 dwc3_cache_hwparams(dwc);
636 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
638 dev_err(dwc->dev, "failed to allocate event buffers\n");
643 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
644 dwc->dr_mode = USB_DR_MODE_HOST;
645 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
646 dwc->dr_mode = USB_DR_MODE_PERIPHERAL;
648 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
649 dwc->dr_mode = USB_DR_MODE_OTG;
651 ret = dwc3_core_init(dwc);
653 dev_err(dev, "failed to initialize core\n");
657 usb_phy_set_suspend(dwc->usb2_phy, 0);
658 usb_phy_set_suspend(dwc->usb3_phy, 0);
659 ret = phy_power_on(dwc->usb2_generic_phy);
663 ret = phy_power_on(dwc->usb3_generic_phy);
665 goto err_usb2phy_power;
667 ret = dwc3_event_buffers_setup(dwc);
669 dev_err(dwc->dev, "failed to setup event buffers\n");
670 goto err_usb3phy_power;
673 switch (dwc->dr_mode) {
674 case USB_DR_MODE_PERIPHERAL:
675 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
676 ret = dwc3_gadget_init(dwc);
678 dev_err(dev, "failed to initialize gadget\n");
682 case USB_DR_MODE_HOST:
683 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
684 ret = dwc3_host_init(dwc);
686 dev_err(dev, "failed to initialize host\n");
690 case USB_DR_MODE_OTG:
691 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
692 ret = dwc3_host_init(dwc);
694 dev_err(dev, "failed to initialize host\n");
698 ret = dwc3_gadget_init(dwc);
700 dev_err(dev, "failed to initialize gadget\n");
705 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
709 ret = dwc3_debugfs_init(dwc);
711 dev_err(dev, "failed to initialize debugfs\n");
715 pm_runtime_allow(dev);
720 switch (dwc->dr_mode) {
721 case USB_DR_MODE_PERIPHERAL:
722 dwc3_gadget_exit(dwc);
724 case USB_DR_MODE_HOST:
727 case USB_DR_MODE_OTG:
729 dwc3_gadget_exit(dwc);
737 dwc3_event_buffers_cleanup(dwc);
740 phy_power_off(dwc->usb3_generic_phy);
743 phy_power_off(dwc->usb2_generic_phy);
746 usb_phy_set_suspend(dwc->usb2_phy, 1);
747 usb_phy_set_suspend(dwc->usb3_phy, 1);
751 dwc3_free_event_buffers(dwc);
756 static int dwc3_remove(struct platform_device *pdev)
758 struct dwc3 *dwc = platform_get_drvdata(pdev);
760 usb_phy_set_suspend(dwc->usb2_phy, 1);
761 usb_phy_set_suspend(dwc->usb3_phy, 1);
762 phy_power_off(dwc->usb2_generic_phy);
763 phy_power_off(dwc->usb3_generic_phy);
765 pm_runtime_put_sync(&pdev->dev);
766 pm_runtime_disable(&pdev->dev);
768 dwc3_debugfs_exit(dwc);
770 switch (dwc->dr_mode) {
771 case USB_DR_MODE_PERIPHERAL:
772 dwc3_gadget_exit(dwc);
774 case USB_DR_MODE_HOST:
777 case USB_DR_MODE_OTG:
779 dwc3_gadget_exit(dwc);
786 dwc3_event_buffers_cleanup(dwc);
787 dwc3_free_event_buffers(dwc);
793 #ifdef CONFIG_PM_SLEEP
794 static int dwc3_prepare(struct device *dev)
796 struct dwc3 *dwc = dev_get_drvdata(dev);
799 spin_lock_irqsave(&dwc->lock, flags);
801 switch (dwc->dr_mode) {
802 case USB_DR_MODE_PERIPHERAL:
803 case USB_DR_MODE_OTG:
804 dwc3_gadget_prepare(dwc);
806 case USB_DR_MODE_HOST:
808 dwc3_event_buffers_cleanup(dwc);
812 spin_unlock_irqrestore(&dwc->lock, flags);
817 static void dwc3_complete(struct device *dev)
819 struct dwc3 *dwc = dev_get_drvdata(dev);
822 spin_lock_irqsave(&dwc->lock, flags);
824 dwc3_event_buffers_setup(dwc);
825 switch (dwc->dr_mode) {
826 case USB_DR_MODE_PERIPHERAL:
827 case USB_DR_MODE_OTG:
828 dwc3_gadget_complete(dwc);
830 case USB_DR_MODE_HOST:
835 spin_unlock_irqrestore(&dwc->lock, flags);
838 static int dwc3_suspend(struct device *dev)
840 struct dwc3 *dwc = dev_get_drvdata(dev);
843 spin_lock_irqsave(&dwc->lock, flags);
845 switch (dwc->dr_mode) {
846 case USB_DR_MODE_PERIPHERAL:
847 case USB_DR_MODE_OTG:
848 dwc3_gadget_suspend(dwc);
850 case USB_DR_MODE_HOST:
856 dwc->gctl = dwc3_readl(dwc->regs, DWC3_GCTL);
857 spin_unlock_irqrestore(&dwc->lock, flags);
859 usb_phy_shutdown(dwc->usb3_phy);
860 usb_phy_shutdown(dwc->usb2_phy);
861 phy_exit(dwc->usb2_generic_phy);
862 phy_exit(dwc->usb3_generic_phy);
867 static int dwc3_resume(struct device *dev)
869 struct dwc3 *dwc = dev_get_drvdata(dev);
873 usb_phy_init(dwc->usb3_phy);
874 usb_phy_init(dwc->usb2_phy);
875 ret = phy_init(dwc->usb2_generic_phy);
879 ret = phy_init(dwc->usb3_generic_phy);
881 goto err_usb2phy_init;
883 spin_lock_irqsave(&dwc->lock, flags);
885 dwc3_writel(dwc->regs, DWC3_GCTL, dwc->gctl);
887 switch (dwc->dr_mode) {
888 case USB_DR_MODE_PERIPHERAL:
889 case USB_DR_MODE_OTG:
890 dwc3_gadget_resume(dwc);
892 case USB_DR_MODE_HOST:
898 spin_unlock_irqrestore(&dwc->lock, flags);
900 pm_runtime_disable(dev);
901 pm_runtime_set_active(dev);
902 pm_runtime_enable(dev);
907 phy_exit(dwc->usb2_generic_phy);
912 static const struct dev_pm_ops dwc3_dev_pm_ops = {
913 .prepare = dwc3_prepare,
914 .complete = dwc3_complete,
916 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
919 #define DWC3_PM_OPS &(dwc3_dev_pm_ops)
921 #define DWC3_PM_OPS NULL
925 static const struct of_device_id of_dwc3_match[] = {
927 .compatible = "snps,dwc3"
930 .compatible = "synopsys,dwc3"
934 MODULE_DEVICE_TABLE(of, of_dwc3_match);
937 static struct platform_driver dwc3_driver = {
939 .remove = dwc3_remove,
942 .of_match_table = of_match_ptr(of_dwc3_match),
947 module_platform_driver(dwc3_driver);
949 MODULE_ALIAS("platform:dwc3");
950 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
951 MODULE_LICENSE("GPL v2");
952 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");