drivers/usb/dwc3/dwc3-omap.c

   1 /**
   2  * dwc3-omap.c - OMAP Specific Glue layer
   3  *
   4  * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/dwc3-omap.c) and ported
  10  * to uboot.
  11  *
  12  * commit 7ee2566ff5 : usb: dwc3: dwc3-omap: get rid of ->prepare()/->complete()
  13  *
  14  * SPDX-License-Identifier:     GPL-2.0
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/kernel.h>
  19 #include <linux/slab.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/platform_data/dwc3-omap.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/ioport.h>
  25 #include <linux/io.h>
  26 #include <linux/of.h>
  27 #include <linux/of_platform.h>
  28 #include <linux/extcon.h>
  29 #include <linux/regulator/consumer.h>
  30
  31 #include <linux/usb/otg.h>
  32
  33 /*
  34  * All these registers belong to OMAP's Wrapper around the
  35  * DesignWare USB3 Core.
  36  */
  37
  38 #define USBOTGSS_REVISION                       0x0000
  39 #define USBOTGSS_SYSCONFIG                      0x0010
  40 #define USBOTGSS_IRQ_EOI                        0x0020
  41 #define USBOTGSS_EOI_OFFSET                     0x0008
  42 #define USBOTGSS_IRQSTATUS_RAW_0                0x0024
  43 #define USBOTGSS_IRQSTATUS_0                    0x0028
  44 #define USBOTGSS_IRQENABLE_SET_0                0x002c
  45 #define USBOTGSS_IRQENABLE_CLR_0                0x0030
  46 #define USBOTGSS_IRQ0_OFFSET                    0x0004
  47 #define USBOTGSS_IRQSTATUS_RAW_1                0x0030
  48 #define USBOTGSS_IRQSTATUS_1                    0x0034
  49 #define USBOTGSS_IRQENABLE_SET_1                0x0038
  50 #define USBOTGSS_IRQENABLE_CLR_1                0x003c
  51 #define USBOTGSS_IRQSTATUS_RAW_2                0x0040
  52 #define USBOTGSS_IRQSTATUS_2                    0x0044
  53 #define USBOTGSS_IRQENABLE_SET_2                0x0048
  54 #define USBOTGSS_IRQENABLE_CLR_2                0x004c
  55 #define USBOTGSS_IRQSTATUS_RAW_3                0x0050
  56 #define USBOTGSS_IRQSTATUS_3                    0x0054
  57 #define USBOTGSS_IRQENABLE_SET_3                0x0058
  58 #define USBOTGSS_IRQENABLE_CLR_3                0x005c
  59 #define USBOTGSS_IRQSTATUS_EOI_MISC             0x0030
  60 #define USBOTGSS_IRQSTATUS_RAW_MISC             0x0034
  61 #define USBOTGSS_IRQSTATUS_MISC                 0x0038
  62 #define USBOTGSS_IRQENABLE_SET_MISC             0x003c
  63 #define USBOTGSS_IRQENABLE_CLR_MISC             0x0040
  64 #define USBOTGSS_IRQMISC_OFFSET                 0x03fc
  65 #define USBOTGSS_UTMI_OTG_CTRL                  0x0080
  66 #define USBOTGSS_UTMI_OTG_STATUS                0x0084
  67 #define USBOTGSS_UTMI_OTG_OFFSET                0x0480
  68 #define USBOTGSS_TXFIFO_DEPTH                   0x0508
  69 #define USBOTGSS_RXFIFO_DEPTH                   0x050c
  70 #define USBOTGSS_MMRAM_OFFSET                   0x0100
  71 #define USBOTGSS_FLADJ                          0x0104
  72 #define USBOTGSS_DEBUG_CFG                      0x0108
  73 #define USBOTGSS_DEBUG_DATA                     0x010c
  74 #define USBOTGSS_DEV_EBC_EN                     0x0110
  75 #define USBOTGSS_DEBUG_OFFSET                   0x0600
  76
  77 /* SYSCONFIG REGISTER */
  78 #define USBOTGSS_SYSCONFIG_DMADISABLE           (1 << 16)
  79
  80 /* IRQ_EOI REGISTER */
  81 #define USBOTGSS_IRQ_EOI_LINE_NUMBER            (1 << 0)
  82
  83 /* IRQS0 BITS */
  84 #define USBOTGSS_IRQO_COREIRQ_ST                (1 << 0)
  85
  86 /* IRQMISC BITS */
  87 #define USBOTGSS_IRQMISC_DMADISABLECLR          (1 << 17)
  88 #define USBOTGSS_IRQMISC_OEVT                   (1 << 16)
  89 #define USBOTGSS_IRQMISC_DRVVBUS_RISE           (1 << 13)
  90 #define USBOTGSS_IRQMISC_CHRGVBUS_RISE          (1 << 12)
  91 #define USBOTGSS_IRQMISC_DISCHRGVBUS_RISE       (1 << 11)
  92 #define USBOTGSS_IRQMISC_IDPULLUP_RISE          (1 << 8)
  93 #define USBOTGSS_IRQMISC_DRVVBUS_FALL           (1 << 5)
  94 #define USBOTGSS_IRQMISC_CHRGVBUS_FALL          (1 << 4)
  95 #define USBOTGSS_IRQMISC_DISCHRGVBUS_FALL               (1 << 3)
  96 #define USBOTGSS_IRQMISC_IDPULLUP_FALL          (1 << 0)
  97
  98 /* UTMI_OTG_CTRL REGISTER */
  99 #define USBOTGSS_UTMI_OTG_CTRL_DRVVBUS          (1 << 5)
 100 #define USBOTGSS_UTMI_OTG_CTRL_CHRGVBUS         (1 << 4)
 101 #define USBOTGSS_UTMI_OTG_CTRL_DISCHRGVBUS      (1 << 3)
 102 #define USBOTGSS_UTMI_OTG_CTRL_IDPULLUP         (1 << 0)
 103
 104 /* UTMI_OTG_STATUS REGISTER */
 105 #define USBOTGSS_UTMI_OTG_STATUS_SW_MODE        (1 << 31)
 106 #define USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT   (1 << 9)
 107 #define USBOTGSS_UTMI_OTG_STATUS_TXBITSTUFFENABLE (1 << 8)
 108 #define USBOTGSS_UTMI_OTG_STATUS_IDDIG          (1 << 4)
 109 #define USBOTGSS_UTMI_OTG_STATUS_SESSEND        (1 << 3)
 110 #define USBOTGSS_UTMI_OTG_STATUS_SESSVALID      (1 << 2)
 111 #define USBOTGSS_UTMI_OTG_STATUS_VBUSVALID      (1 << 1)
 112
 113 struct dwc3_omap {
 114         struct device           *dev;
 115
 116         int                     irq;
 117         void __iomem            *base;
 118
 119         u32                     utmi_otg_status;
 120         u32                     utmi_otg_offset;
 121         u32                     irqmisc_offset;
 122         u32                     irq_eoi_offset;
 123         u32                     debug_offset;
 124         u32                     irq0_offset;
 125
 126         u32                     dma_status:1;
 127
 128         struct extcon_specific_cable_nb extcon_vbus_dev;
 129         struct extcon_specific_cable_nb extcon_id_dev;
 130         struct notifier_block   vbus_nb;
 131         struct notifier_block   id_nb;
 132
 133         struct regulator        *vbus_reg;
 134 };
 135
 136 enum omap_dwc3_vbus_id_status {
 137         OMAP_DWC3_ID_FLOAT,
 138         OMAP_DWC3_ID_GROUND,
 139         OMAP_DWC3_VBUS_OFF,
 140         OMAP_DWC3_VBUS_VALID,
 141 };
 142
 143 static inline u32 dwc3_omap_readl(void __iomem *base, u32 offset)
 144 {
 145         return readl(base + offset);
 146 }
 147
 148 static inline void dwc3_omap_writel(void __iomem *base, u32 offset, u32 value)
 149 {
 150         writel(value, base + offset);
 151 }
 152
 153 static u32 dwc3_omap_read_utmi_status(struct dwc3_omap *omap)
 154 {
 155         return dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS +
 156                                                         omap->utmi_otg_offset);
 157 }
 158
 159 static void dwc3_omap_write_utmi_status(struct dwc3_omap *omap, u32 value)
 160 {
 161         dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS +
 162                                         omap->utmi_otg_offset, value);
 163
 164 }
 165
 166 static u32 dwc3_omap_read_irq0_status(struct dwc3_omap *omap)
 167 {
 168         return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_0 -
 169                                                 omap->irq0_offset);
 170 }
 171
 172 static void dwc3_omap_write_irq0_status(struct dwc3_omap *omap, u32 value)
 173 {
 174         dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_0 -
 175                                                 omap->irq0_offset, value);
 176
 177 }
 178
 179 static u32 dwc3_omap_read_irqmisc_status(struct dwc3_omap *omap)
 180 {
 181         return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_MISC +
 182                                                 omap->irqmisc_offset);
 183 }
 184
 185 static void dwc3_omap_write_irqmisc_status(struct dwc3_omap *omap, u32 value)
 186 {
 187         dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_MISC +
 188                                         omap->irqmisc_offset, value);
 189
 190 }
 191
 192 static void dwc3_omap_write_irqmisc_set(struct dwc3_omap *omap, u32 value)
 193 {
 194         dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_MISC +
 195                                                 omap->irqmisc_offset, value);
 196
 197 }
 198
 199 static void dwc3_omap_write_irq0_set(struct dwc3_omap *omap, u32 value)
 200 {
 201         dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_0 -
 202                                                 omap->irq0_offset, value);
 203 }
 204
 205 static void dwc3_omap_set_mailbox(struct dwc3_omap *omap,
 206         enum omap_dwc3_vbus_id_status status)
 207 {
 208         int     ret;
 209         u32     val;
 210
 211         switch (status) {
 212         case OMAP_DWC3_ID_GROUND:
 213                 dev_dbg(omap->dev, "ID GND\n");
 214
 215                 if (omap->vbus_reg) {
 216                         ret = regulator_enable(omap->vbus_reg);
 217                         if (ret) {
 218                                 dev_dbg(omap->dev, "regulator enable failed\n");
 219                                 return;
 220                         }
 221                 }
 222
 223                 val = dwc3_omap_read_utmi_status(omap);
 224                 val &= ~(USBOTGSS_UTMI_OTG_STATUS_IDDIG
 225                                 | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID
 226                                 | USBOTGSS_UTMI_OTG_STATUS_SESSEND);
 227                 val |= USBOTGSS_UTMI_OTG_STATUS_SESSVALID
 228                                 | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT;
 229                 dwc3_omap_write_utmi_status(omap, val);
 230                 break;
 231
 232         case OMAP_DWC3_VBUS_VALID:
 233                 dev_dbg(omap->dev, "VBUS Connect\n");
 234
 235                 val = dwc3_omap_read_utmi_status(omap);
 236                 val &= ~USBOTGSS_UTMI_OTG_STATUS_SESSEND;
 237                 val |= USBOTGSS_UTMI_OTG_STATUS_IDDIG
 238                                 | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID
 239                                 | USBOTGSS_UTMI_OTG_STATUS_SESSVALID
 240                                 | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT;
 241                 dwc3_omap_write_utmi_status(omap, val);
 242                 break;
 243
 244         case OMAP_DWC3_ID_FLOAT:
 245                 if (omap->vbus_reg)
 246                         regulator_disable(omap->vbus_reg);
 247
 248         case OMAP_DWC3_VBUS_OFF:
 249                 dev_dbg(omap->dev, "VBUS Disconnect\n");
 250
 251                 val = dwc3_omap_read_utmi_status(omap);
 252                 val &= ~(USBOTGSS_UTMI_OTG_STATUS_SESSVALID
 253                                 | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID
 254                                 | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT);
 255                 val |= USBOTGSS_UTMI_OTG_STATUS_SESSEND
 256                                 | USBOTGSS_UTMI_OTG_STATUS_IDDIG;
 257                 dwc3_omap_write_utmi_status(omap, val);
 258                 break;
 259
 260         default:
 261                 dev_dbg(omap->dev, "invalid state\n");
 262         }
 263 }
 264
 265 static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap)
 266 {
 267         struct dwc3_omap        *omap = _omap;
 268         u32                     reg;
 269
 270         reg = dwc3_omap_read_irqmisc_status(omap);
 271
 272         if (reg & USBOTGSS_IRQMISC_DMADISABLECLR) {
 273                 dev_dbg(omap->dev, "DMA Disable was Cleared\n");
 274                 omap->dma_status = false;
 275         }
 276
 277         if (reg & USBOTGSS_IRQMISC_OEVT)
 278                 dev_dbg(omap->dev, "OTG Event\n");
 279
 280         if (reg & USBOTGSS_IRQMISC_DRVVBUS_RISE)
 281                 dev_dbg(omap->dev, "DRVVBUS Rise\n");
 282
 283         if (reg & USBOTGSS_IRQMISC_CHRGVBUS_RISE)
 284                 dev_dbg(omap->dev, "CHRGVBUS Rise\n");
 285
 286         if (reg & USBOTGSS_IRQMISC_DISCHRGVBUS_RISE)
 287                 dev_dbg(omap->dev, "DISCHRGVBUS Rise\n");
 288
 289         if (reg & USBOTGSS_IRQMISC_IDPULLUP_RISE)
 290                 dev_dbg(omap->dev, "IDPULLUP Rise\n");
 291
 292         if (reg & USBOTGSS_IRQMISC_DRVVBUS_FALL)
 293                 dev_dbg(omap->dev, "DRVVBUS Fall\n");
 294
 295         if (reg & USBOTGSS_IRQMISC_CHRGVBUS_FALL)
 296                 dev_dbg(omap->dev, "CHRGVBUS Fall\n");
 297
 298         if (reg & USBOTGSS_IRQMISC_DISCHRGVBUS_FALL)
 299                 dev_dbg(omap->dev, "DISCHRGVBUS Fall\n");
 300
 301         if (reg & USBOTGSS_IRQMISC_IDPULLUP_FALL)
 302                 dev_dbg(omap->dev, "IDPULLUP Fall\n");
 303
 304         dwc3_omap_write_irqmisc_status(omap, reg);
 305
 306         reg = dwc3_omap_read_irq0_status(omap);
 307
 308         dwc3_omap_write_irq0_status(omap, reg);
 309
 310         return IRQ_HANDLED;
 311 }
 312
 313 static int dwc3_omap_remove_core(struct device *dev, void *c)
 314 {
 315         struct platform_device *pdev = to_platform_device(dev);
 316
 317         of_device_unregister(pdev);
 318
 319         return 0;
 320 }
 321
 322 static void dwc3_omap_enable_irqs(struct dwc3_omap *omap)
 323 {
 324         u32                     reg;
 325
 326         /* enable all IRQs */
 327         reg = USBOTGSS_IRQO_COREIRQ_ST;
 328         dwc3_omap_write_irq0_set(omap, reg);
 329
 330         reg = (USBOTGSS_IRQMISC_OEVT |
 331                         USBOTGSS_IRQMISC_DRVVBUS_RISE |
 332                         USBOTGSS_IRQMISC_CHRGVBUS_RISE |
 333                         USBOTGSS_IRQMISC_DISCHRGVBUS_RISE |
 334                         USBOTGSS_IRQMISC_IDPULLUP_RISE |
 335                         USBOTGSS_IRQMISC_DRVVBUS_FALL |
 336                         USBOTGSS_IRQMISC_CHRGVBUS_FALL |
 337                         USBOTGSS_IRQMISC_DISCHRGVBUS_FALL |
 338                         USBOTGSS_IRQMISC_IDPULLUP_FALL);
 339
 340         dwc3_omap_write_irqmisc_set(omap, reg);
 341 }
 342
 343 static void dwc3_omap_disable_irqs(struct dwc3_omap *omap)
 344 {
 345         /* disable all IRQs */
 346         dwc3_omap_write_irqmisc_set(omap, 0x00);
 347         dwc3_omap_write_irq0_set(omap, 0x00);
 348 }
 349
 350 static u64 dwc3_omap_dma_mask = DMA_BIT_MASK(32);
 351
 352 static int dwc3_omap_id_notifier(struct notifier_block *nb,
 353         unsigned long event, void *ptr)
 354 {
 355         struct dwc3_omap *omap = container_of(nb, struct dwc3_omap, id_nb);
 356
 357         if (event)
 358                 dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND);
 359         else
 360                 dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_FLOAT);
 361
 362         return NOTIFY_DONE;
 363 }
 364
 365 static int dwc3_omap_vbus_notifier(struct notifier_block *nb,
 366         unsigned long event, void *ptr)
 367 {
 368         struct dwc3_omap *omap = container_of(nb, struct dwc3_omap, vbus_nb);
 369
 370         if (event)
 371                 dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID);
 372         else
 373                 dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_OFF);
 374
 375         return NOTIFY_DONE;
 376 }
 377
 378 static void dwc3_omap_map_offset(struct dwc3_omap *omap)
 379 {
 380         struct device_node      *node = omap->dev->of_node;
 381
 382         /*
 383          * Differentiate between OMAP5 and AM437x.
 384          *
 385          * For OMAP5(ES2.0) and AM437x wrapper revision is same, even
 386          * though there are changes in wrapper register offsets.
 387          *
 388          * Using dt compatible to differentiate AM437x.
 389          */
 390         if (of_device_is_compatible(node, "ti,am437x-dwc3")) {
 391                 omap->irq_eoi_offset = USBOTGSS_EOI_OFFSET;
 392                 omap->irq0_offset = USBOTGSS_IRQ0_OFFSET;
 393                 omap->irqmisc_offset = USBOTGSS_IRQMISC_OFFSET;
 394                 omap->utmi_otg_offset = USBOTGSS_UTMI_OTG_OFFSET;
 395                 omap->debug_offset = USBOTGSS_DEBUG_OFFSET;
 396         }
 397 }
 398
 399 static void dwc3_omap_set_utmi_mode(struct dwc3_omap *omap)
 400 {
 401         u32                     reg;
 402         struct device_node      *node = omap->dev->of_node;
 403         int                     utmi_mode = 0;
 404
 405         reg = dwc3_omap_read_utmi_status(omap);
 406
 407         of_property_read_u32(node, "utmi-mode", &utmi_mode);
 408
 409         switch (utmi_mode) {
 410         case DWC3_OMAP_UTMI_MODE_SW:
 411                 reg |= USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
 412                 break;
 413         case DWC3_OMAP_UTMI_MODE_HW:
 414                 reg &= ~USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
 415                 break;
 416         default:
 417                 dev_dbg(omap->dev, "UNKNOWN utmi mode %d\n", utmi_mode);
 418         }
 419
 420         dwc3_omap_write_utmi_status(omap, reg);
 421 }
 422
 423 static int dwc3_omap_extcon_register(struct dwc3_omap *omap)
 424 {
 425         int                     ret;
 426         struct device_node      *node = omap->dev->of_node;
 427         struct extcon_dev       *edev;
 428
 429         if (of_property_read_bool(node, "extcon")) {
 430                 edev = extcon_get_edev_by_phandle(omap->dev, 0);
 431                 if (IS_ERR(edev)) {
 432                         dev_vdbg(omap->dev, "couldn't get extcon device\n");
 433                         return -EPROBE_DEFER;
 434                 }
 435
 436                 omap->vbus_nb.notifier_call = dwc3_omap_vbus_notifier;
 437                 ret = extcon_register_interest(&omap->extcon_vbus_dev,
 438                                                edev->name, "USB",
 439                                                &omap->vbus_nb);
 440                 if (ret < 0)
 441                         dev_vdbg(omap->dev, "failed to register notifier for USB\n");
 442
 443                 omap->id_nb.notifier_call = dwc3_omap_id_notifier;
 444                 ret = extcon_register_interest(&omap->extcon_id_dev,
 445                                                edev->name, "USB-HOST",
 446                                                &omap->id_nb);
 447                 if (ret < 0)
 448                         dev_vdbg(omap->dev, "failed to register notifier for USB-HOST\n");
 449
 450                 if (extcon_get_cable_state(edev, "USB") == true)
 451                         dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID);
 452                 if (extcon_get_cable_state(edev, "USB-HOST") == true)
 453                         dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND);
 454         }
 455
 456         return 0;
 457 }
 458
 459 static int dwc3_omap_probe(struct platform_device *pdev)
 460 {
 461         struct device_node      *node = pdev->dev.of_node;
 462
 463         struct dwc3_omap        *omap;
 464         struct resource         *res;
 465         struct device           *dev = &pdev->dev;
 466         struct regulator        *vbus_reg = NULL;
 467
 468         int                     ret;
 469         int                     irq;
 470
 471         u32                     reg;
 472
 473         void __iomem            *base;
 474
 475         if (!node) {
 476                 dev_err(dev, "device node not found\n");
 477                 return -EINVAL;
 478         }
 479
 480         omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL);
 481         if (!omap)
 482                 return -ENOMEM;
 483
 484         platform_set_drvdata(pdev, omap);
 485
 486         irq = platform_get_irq(pdev, 0);
 487         if (irq < 0) {
 488                 dev_err(dev, "missing IRQ resource\n");
 489                 return -EINVAL;
 490         }
 491
 492         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 493         base = devm_ioremap_resource(dev, res);
 494         if (IS_ERR(base))
 495                 return PTR_ERR(base);
 496
 497         if (of_property_read_bool(node, "vbus-supply")) {
 498                 vbus_reg = devm_regulator_get(dev, "vbus");
 499                 if (IS_ERR(vbus_reg)) {
 500                         dev_err(dev, "vbus init failed\n");
 501                         return PTR_ERR(vbus_reg);
 502                 }
 503         }
 504
 505         omap->dev       = dev;
 506         omap->irq       = irq;
 507         omap->base      = base;
 508         omap->vbus_reg  = vbus_reg;
 509         dev->dma_mask   = &dwc3_omap_dma_mask;
 510
 511         dwc3_omap_map_offset(omap);
 512         dwc3_omap_set_utmi_mode(omap);
 513
 514         /* check the DMA Status */
 515         reg = dwc3_omap_readl(omap->base, USBOTGSS_SYSCONFIG);
 516         omap->dma_status = !!(reg & USBOTGSS_SYSCONFIG_DMADISABLE);
 517
 518         ret = devm_request_irq(dev, omap->irq, dwc3_omap_interrupt, 0,
 519                         "dwc3-omap", omap);
 520         if (ret) {
 521                 dev_err(dev, "failed to request IRQ #%d --> %d\n",
 522                                 omap->irq, ret);
 523                 goto err0;
 524         }
 525
 526         dwc3_omap_enable_irqs(omap);
 527
 528         ret = dwc3_omap_extcon_register(omap);
 529         if (ret < 0)
 530                 goto err1;
 531
 532         ret = of_platform_populate(node, NULL, NULL, dev);
 533         if (ret) {
 534                 dev_err(&pdev->dev, "failed to create dwc3 core\n");
 535                 goto err2;
 536         }
 537
 538         return 0;
 539
 540 err2:
 541         if (omap->extcon_vbus_dev.edev)
 542                 extcon_unregister_interest(&omap->extcon_vbus_dev);
 543         if (omap->extcon_id_dev.edev)
 544                 extcon_unregister_interest(&omap->extcon_id_dev);
 545
 546 err1:
 547         dwc3_omap_disable_irqs(omap);
 548
 549 err0:
 550         return ret;
 551 }
 552
 553 static int dwc3_omap_remove(struct platform_device *pdev)
 554 {
 555         struct dwc3_omap        *omap = platform_get_drvdata(pdev);
 556
 557         if (omap->extcon_vbus_dev.edev)
 558                 extcon_unregister_interest(&omap->extcon_vbus_dev);
 559         if (omap->extcon_id_dev.edev)
 560                 extcon_unregister_interest(&omap->extcon_id_dev);
 561         dwc3_omap_disable_irqs(omap);
 562         device_for_each_child(&pdev->dev, NULL, dwc3_omap_remove_core);
 563
 564         return 0;
 565 }
 566
 567 static const struct of_device_id of_dwc3_match[] = {
 568         {
 569                 .compatible =   "ti,dwc3"
 570         },
 571         {
 572                 .compatible =   "ti,am437x-dwc3"
 573         },
 574         { },
 575 };
 576 MODULE_DEVICE_TABLE(of, of_dwc3_match);
 577
 578 static struct platform_driver dwc3_omap_driver = {
 579         .probe          = dwc3_omap_probe,
 580         .remove         = dwc3_omap_remove,
 581         .driver         = {
 582                 .name   = "omap-dwc3",
 583                 .of_match_table = of_dwc3_match,
 584         },
 585 };
 586
 587 module_platform_driver(dwc3_omap_driver);
 588
 589 MODULE_ALIAS("platform:omap-dwc3");
 590 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
 591 MODULE_LICENSE("GPL v2");
 592 MODULE_DESCRIPTION("DesignWare USB3 OMAP Glue Layer");