drivers/usb/dwc3/dwc3-omap.c

   1 /**
   2  * dwc3-omap.c - OMAP Specific Glue layer
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * This program is free software: you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2  of
  11  * the License as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/module.h>
  20 #include <linux/kernel.h>
  21 #include <linux/slab.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/platform_data/dwc3-omap.h>
  25 #include <linux/pm_runtime.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/ioport.h>
  28 #include <linux/io.h>
  29 #include <linux/of.h>
  30 #include <linux/of_platform.h>
  31 #include <linux/extcon.h>
  32 #include <linux/regulator/consumer.h>
  33
  34 #include <linux/usb/otg.h>
  35
  36 /*
  37  * All these registers belong to OMAP's Wrapper around the
  38  * DesignWare USB3 Core.
  39  */
  40
  41 #define USBOTGSS_REVISION                       0x0000
  42 #define USBOTGSS_SYSCONFIG                      0x0010
  43 #define USBOTGSS_IRQ_EOI                        0x0020
  44 #define USBOTGSS_EOI_OFFSET                     0x0008
  45 #define USBOTGSS_IRQSTATUS_RAW_0                0x0024
  46 #define USBOTGSS_IRQSTATUS_0                    0x0028
  47 #define USBOTGSS_IRQENABLE_SET_0                0x002c
  48 #define USBOTGSS_IRQENABLE_CLR_0                0x0030
  49 #define USBOTGSS_IRQ0_OFFSET                    0x0004
  50 #define USBOTGSS_IRQSTATUS_RAW_1                0x0030
  51 #define USBOTGSS_IRQSTATUS_1                    0x0034
  52 #define USBOTGSS_IRQENABLE_SET_1                0x0038
  53 #define USBOTGSS_IRQENABLE_CLR_1                0x003c
  54 #define USBOTGSS_IRQSTATUS_RAW_2                0x0040
  55 #define USBOTGSS_IRQSTATUS_2                    0x0044
  56 #define USBOTGSS_IRQENABLE_SET_2                0x0048
  57 #define USBOTGSS_IRQENABLE_CLR_2                0x004c
  58 #define USBOTGSS_IRQSTATUS_RAW_3                0x0050
  59 #define USBOTGSS_IRQSTATUS_3                    0x0054
  60 #define USBOTGSS_IRQENABLE_SET_3                0x0058
  61 #define USBOTGSS_IRQENABLE_CLR_3                0x005c
  62 #define USBOTGSS_IRQSTATUS_EOI_MISC             0x0030
  63 #define USBOTGSS_IRQSTATUS_RAW_MISC             0x0034
  64 #define USBOTGSS_IRQSTATUS_MISC                 0x0038
  65 #define USBOTGSS_IRQENABLE_SET_MISC             0x003c
  66 #define USBOTGSS_IRQENABLE_CLR_MISC             0x0040
  67 #define USBOTGSS_IRQMISC_OFFSET                 0x03fc
  68 #define USBOTGSS_UTMI_OTG_STATUS                0x0080
  69 #define USBOTGSS_UTMI_OTG_CTRL                  0x0084
  70 #define USBOTGSS_UTMI_OTG_OFFSET                0x0480
  71 #define USBOTGSS_TXFIFO_DEPTH                   0x0508
  72 #define USBOTGSS_RXFIFO_DEPTH                   0x050c
  73 #define USBOTGSS_MMRAM_OFFSET                   0x0100
  74 #define USBOTGSS_FLADJ                          0x0104
  75 #define USBOTGSS_DEBUG_CFG                      0x0108
  76 #define USBOTGSS_DEBUG_DATA                     0x010c
  77 #define USBOTGSS_DEV_EBC_EN                     0x0110
  78 #define USBOTGSS_DEBUG_OFFSET                   0x0600
  79
  80 /* SYSCONFIG REGISTER */
  81 #define USBOTGSS_SYSCONFIG_DMADISABLE           (1 << 16)
  82
  83 /* IRQ_EOI REGISTER */
  84 #define USBOTGSS_IRQ_EOI_LINE_NUMBER            (1 << 0)
  85
  86 /* IRQS0 BITS */
  87 #define USBOTGSS_IRQO_COREIRQ_ST                (1 << 0)
  88
  89 /* IRQMISC BITS */
  90 #define USBOTGSS_IRQMISC_DMADISABLECLR          (1 << 17)
  91 #define USBOTGSS_IRQMISC_OEVT                   (1 << 16)
  92 #define USBOTGSS_IRQMISC_DRVVBUS_RISE           (1 << 13)
  93 #define USBOTGSS_IRQMISC_CHRGVBUS_RISE          (1 << 12)
  94 #define USBOTGSS_IRQMISC_DISCHRGVBUS_RISE       (1 << 11)
  95 #define USBOTGSS_IRQMISC_IDPULLUP_RISE          (1 << 8)
  96 #define USBOTGSS_IRQMISC_DRVVBUS_FALL           (1 << 5)
  97 #define USBOTGSS_IRQMISC_CHRGVBUS_FALL          (1 << 4)
  98 #define USBOTGSS_IRQMISC_DISCHRGVBUS_FALL               (1 << 3)
  99 #define USBOTGSS_IRQMISC_IDPULLUP_FALL          (1 << 0)
 100
 101 /* UTMI_OTG_STATUS REGISTER */
 102 #define USBOTGSS_UTMI_OTG_STATUS_DRVVBUS        (1 << 5)
 103 #define USBOTGSS_UTMI_OTG_STATUS_CHRGVBUS       (1 << 4)
 104 #define USBOTGSS_UTMI_OTG_STATUS_DISCHRGVBUS    (1 << 3)
 105 #define USBOTGSS_UTMI_OTG_STATUS_IDPULLUP       (1 << 0)
 106
 107 /* UTMI_OTG_CTRL REGISTER */
 108 #define USBOTGSS_UTMI_OTG_CTRL_SW_MODE          (1 << 31)
 109 #define USBOTGSS_UTMI_OTG_CTRL_POWERPRESENT     (1 << 9)
 110 #define USBOTGSS_UTMI_OTG_CTRL_TXBITSTUFFENABLE (1 << 8)
 111 #define USBOTGSS_UTMI_OTG_CTRL_IDDIG            (1 << 4)
 112 #define USBOTGSS_UTMI_OTG_CTRL_SESSEND          (1 << 3)
 113 #define USBOTGSS_UTMI_OTG_CTRL_SESSVALID        (1 << 2)
 114 #define USBOTGSS_UTMI_OTG_CTRL_VBUSVALID        (1 << 1)
 115
 116 struct dwc3_omap {
 117         struct device           *dev;
 118
 119         int                     irq;
 120         void __iomem            *base;
 121
 122         u32                     utmi_otg_ctrl;
 123         u32                     utmi_otg_offset;
 124         u32                     irqmisc_offset;
 125         u32                     irq_eoi_offset;
 126         u32                     debug_offset;
 127         u32                     irq0_offset;
 128
 129         u32                     dma_status:1;
 130
 131         struct extcon_specific_cable_nb extcon_vbus_dev;
 132         struct extcon_specific_cable_nb extcon_id_dev;
 133         struct notifier_block   vbus_nb;
 134         struct notifier_block   id_nb;
 135
 136         struct regulator        *vbus_reg;
 137 };
 138
 139 enum omap_dwc3_vbus_id_status {
 140         OMAP_DWC3_ID_FLOAT,
 141         OMAP_DWC3_ID_GROUND,
 142         OMAP_DWC3_VBUS_OFF,
 143         OMAP_DWC3_VBUS_VALID,
 144 };
 145
 146 static inline u32 dwc3_omap_readl(void __iomem *base, u32 offset)
 147 {
 148         return readl(base + offset);
 149 }
 150
 151 static inline void dwc3_omap_writel(void __iomem *base, u32 offset, u32 value)
 152 {
 153         writel(value, base + offset);
 154 }
 155
 156 static u32 dwc3_omap_read_utmi_ctrl(struct dwc3_omap *omap)
 157 {
 158         return dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_CTRL +
 159                                                         omap->utmi_otg_offset);
 160 }
 161
 162 static void dwc3_omap_write_utmi_ctrl(struct dwc3_omap *omap, u32 value)
 163 {
 164         dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_CTRL +
 165                                         omap->utmi_otg_offset, value);
 166
 167 }
 168
 169 static u32 dwc3_omap_read_irq0_status(struct dwc3_omap *omap)
 170 {
 171         return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_0 -
 172                                                 omap->irq0_offset);
 173 }
 174
 175 static void dwc3_omap_write_irq0_status(struct dwc3_omap *omap, u32 value)
 176 {
 177         dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_0 -
 178                                                 omap->irq0_offset, value);
 179
 180 }
 181
 182 static u32 dwc3_omap_read_irqmisc_status(struct dwc3_omap *omap)
 183 {
 184         return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_MISC +
 185                                                 omap->irqmisc_offset);
 186 }
 187
 188 static void dwc3_omap_write_irqmisc_status(struct dwc3_omap *omap, u32 value)
 189 {
 190         dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_MISC +
 191                                         omap->irqmisc_offset, value);
 192
 193 }
 194
 195 static void dwc3_omap_write_irqmisc_set(struct dwc3_omap *omap, u32 value)
 196 {
 197         dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_MISC +
 198                                                 omap->irqmisc_offset, value);
 199
 200 }
 201
 202 static void dwc3_omap_write_irq0_set(struct dwc3_omap *omap, u32 value)
 203 {
 204         dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_0 -
 205                                                 omap->irq0_offset, value);
 206 }
 207
 208 static void dwc3_omap_write_irqmisc_clr(struct dwc3_omap *omap, u32 value)
 209 {
 210         dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_MISC +
 211                                                 omap->irqmisc_offset, value);
 212 }
 213
 214 static void dwc3_omap_write_irq0_clr(struct dwc3_omap *omap, u32 value)
 215 {
 216         dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_0 -
 217                                                 omap->irq0_offset, value);
 218 }
 219
 220 static void dwc3_omap_set_mailbox(struct dwc3_omap *omap,
 221         enum omap_dwc3_vbus_id_status status)
 222 {
 223         int     ret;
 224         u32     val;
 225
 226         switch (status) {
 227         case OMAP_DWC3_ID_GROUND:
 228                 if (omap->vbus_reg) {
 229                         ret = regulator_enable(omap->vbus_reg);
 230                         if (ret) {
 231                                 dev_err(omap->dev, "regulator enable failed\n");
 232                                 return;
 233                         }
 234                 }
 235
 236                 val = dwc3_omap_read_utmi_ctrl(omap);
 237                 val &= ~(USBOTGSS_UTMI_OTG_CTRL_IDDIG
 238                                 | USBOTGSS_UTMI_OTG_CTRL_VBUSVALID
 239                                 | USBOTGSS_UTMI_OTG_CTRL_SESSEND);
 240                 val |= USBOTGSS_UTMI_OTG_CTRL_SESSVALID
 241                                 | USBOTGSS_UTMI_OTG_CTRL_POWERPRESENT;
 242                 dwc3_omap_write_utmi_ctrl(omap, val);
 243                 break;
 244
 245         case OMAP_DWC3_VBUS_VALID:
 246                 val = dwc3_omap_read_utmi_ctrl(omap);
 247                 val &= ~USBOTGSS_UTMI_OTG_CTRL_SESSEND;
 248                 val |= USBOTGSS_UTMI_OTG_CTRL_IDDIG
 249                                 | USBOTGSS_UTMI_OTG_CTRL_VBUSVALID
 250                                 | USBOTGSS_UTMI_OTG_CTRL_SESSVALID
 251                                 | USBOTGSS_UTMI_OTG_CTRL_POWERPRESENT;
 252                 dwc3_omap_write_utmi_ctrl(omap, val);
 253                 break;
 254
 255         case OMAP_DWC3_ID_FLOAT:
 256                 if (omap->vbus_reg)
 257                         regulator_disable(omap->vbus_reg);
 258
 259         case OMAP_DWC3_VBUS_OFF:
 260                 val = dwc3_omap_read_utmi_ctrl(omap);
 261                 val &= ~(USBOTGSS_UTMI_OTG_CTRL_SESSVALID
 262                                 | USBOTGSS_UTMI_OTG_CTRL_VBUSVALID
 263                                 | USBOTGSS_UTMI_OTG_CTRL_POWERPRESENT);
 264                 val |= USBOTGSS_UTMI_OTG_CTRL_SESSEND
 265                                 | USBOTGSS_UTMI_OTG_CTRL_IDDIG;
 266                 dwc3_omap_write_utmi_ctrl(omap, val);
 267                 break;
 268
 269         default:
 270                 dev_WARN(omap->dev, "invalid state\n");
 271         }
 272 }
 273
 274 static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap)
 275 {
 276         struct dwc3_omap        *omap = _omap;
 277         u32                     reg;
 278
 279         reg = dwc3_omap_read_irqmisc_status(omap);
 280
 281         if (reg & USBOTGSS_IRQMISC_DMADISABLECLR)
 282                 omap->dma_status = false;
 283
 284         dwc3_omap_write_irqmisc_status(omap, reg);
 285
 286         reg = dwc3_omap_read_irq0_status(omap);
 287
 288         dwc3_omap_write_irq0_status(omap, reg);
 289
 290         return IRQ_HANDLED;
 291 }
 292
 293 static void dwc3_omap_enable_irqs(struct dwc3_omap *omap)
 294 {
 295         u32                     reg;
 296
 297         /* enable all IRQs */
 298         reg = USBOTGSS_IRQO_COREIRQ_ST;
 299         dwc3_omap_write_irq0_set(omap, reg);
 300
 301         reg = (USBOTGSS_IRQMISC_OEVT |
 302                         USBOTGSS_IRQMISC_DRVVBUS_RISE |
 303                         USBOTGSS_IRQMISC_CHRGVBUS_RISE |
 304                         USBOTGSS_IRQMISC_DISCHRGVBUS_RISE |
 305                         USBOTGSS_IRQMISC_IDPULLUP_RISE |
 306                         USBOTGSS_IRQMISC_DRVVBUS_FALL |
 307                         USBOTGSS_IRQMISC_CHRGVBUS_FALL |
 308                         USBOTGSS_IRQMISC_DISCHRGVBUS_FALL |
 309                         USBOTGSS_IRQMISC_IDPULLUP_FALL);
 310
 311         dwc3_omap_write_irqmisc_set(omap, reg);
 312 }
 313
 314 static void dwc3_omap_disable_irqs(struct dwc3_omap *omap)
 315 {
 316         u32                     reg;
 317
 318         /* disable all IRQs */
 319         reg = USBOTGSS_IRQO_COREIRQ_ST;
 320         dwc3_omap_write_irq0_clr(omap, reg);
 321
 322         reg = (USBOTGSS_IRQMISC_OEVT |
 323                         USBOTGSS_IRQMISC_DRVVBUS_RISE |
 324                         USBOTGSS_IRQMISC_CHRGVBUS_RISE |
 325                         USBOTGSS_IRQMISC_DISCHRGVBUS_RISE |
 326                         USBOTGSS_IRQMISC_IDPULLUP_RISE |
 327                         USBOTGSS_IRQMISC_DRVVBUS_FALL |
 328                         USBOTGSS_IRQMISC_CHRGVBUS_FALL |
 329                         USBOTGSS_IRQMISC_DISCHRGVBUS_FALL |
 330                         USBOTGSS_IRQMISC_IDPULLUP_FALL);
 331
 332         dwc3_omap_write_irqmisc_clr(omap, reg);
 333 }
 334
 335 static u64 dwc3_omap_dma_mask = DMA_BIT_MASK(32);
 336
 337 static int dwc3_omap_id_notifier(struct notifier_block *nb,
 338         unsigned long event, void *ptr)
 339 {
 340         struct dwc3_omap *omap = container_of(nb, struct dwc3_omap, id_nb);
 341
 342         if (event)
 343                 dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND);
 344         else
 345                 dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_FLOAT);
 346
 347         return NOTIFY_DONE;
 348 }
 349
 350 static int dwc3_omap_vbus_notifier(struct notifier_block *nb,
 351         unsigned long event, void *ptr)
 352 {
 353         struct dwc3_omap *omap = container_of(nb, struct dwc3_omap, vbus_nb);
 354
 355         if (event)
 356                 dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID);
 357         else
 358                 dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_OFF);
 359
 360         return NOTIFY_DONE;
 361 }
 362
 363 static void dwc3_omap_map_offset(struct dwc3_omap *omap)
 364 {
 365         struct device_node      *node = omap->dev->of_node;
 366
 367         /*
 368          * Differentiate between OMAP5 and AM437x.
 369          *
 370          * For OMAP5(ES2.0) and AM437x wrapper revision is same, even
 371          * though there are changes in wrapper register offsets.
 372          *
 373          * Using dt compatible to differentiate AM437x.
 374          */
 375         if (of_device_is_compatible(node, "ti,am437x-dwc3")) {
 376                 omap->irq_eoi_offset = USBOTGSS_EOI_OFFSET;
 377                 omap->irq0_offset = USBOTGSS_IRQ0_OFFSET;
 378                 omap->irqmisc_offset = USBOTGSS_IRQMISC_OFFSET;
 379                 omap->utmi_otg_offset = USBOTGSS_UTMI_OTG_OFFSET;
 380                 omap->debug_offset = USBOTGSS_DEBUG_OFFSET;
 381         }
 382 }
 383
 384 static void dwc3_omap_set_utmi_mode(struct dwc3_omap *omap)
 385 {
 386         u32                     reg;
 387         struct device_node      *node = omap->dev->of_node;
 388         int                     utmi_mode = 0;
 389
 390         reg = dwc3_omap_read_utmi_ctrl(omap);
 391
 392         of_property_read_u32(node, "utmi-mode", &utmi_mode);
 393
 394         switch (utmi_mode) {
 395         case DWC3_OMAP_UTMI_MODE_SW:
 396                 reg |= USBOTGSS_UTMI_OTG_CTRL_SW_MODE;
 397                 break;
 398         case DWC3_OMAP_UTMI_MODE_HW:
 399                 reg &= ~USBOTGSS_UTMI_OTG_CTRL_SW_MODE;
 400                 break;
 401         default:
 402                 dev_WARN(omap->dev, "UNKNOWN utmi mode %d\n", utmi_mode);
 403         }
 404
 405         dwc3_omap_write_utmi_ctrl(omap, reg);
 406 }
 407
 408 static int dwc3_omap_extcon_register(struct dwc3_omap *omap)
 409 {
 410         int                     ret;
 411         struct device_node      *node = omap->dev->of_node;
 412         struct extcon_dev       *edev;
 413
 414         if (of_property_read_bool(node, "extcon")) {
 415                 edev = extcon_get_edev_by_phandle(omap->dev, 0);
 416                 if (IS_ERR(edev)) {
 417                         dev_vdbg(omap->dev, "couldn't get extcon device\n");
 418                         return -EPROBE_DEFER;
 419                 }
 420
 421                 omap->vbus_nb.notifier_call = dwc3_omap_vbus_notifier;
 422                 ret = extcon_register_interest(&omap->extcon_vbus_dev,
 423                                                edev->name, "USB",
 424                                                &omap->vbus_nb);
 425                 if (ret < 0)
 426                         dev_vdbg(omap->dev, "failed to register notifier for USB\n");
 427
 428                 omap->id_nb.notifier_call = dwc3_omap_id_notifier;
 429                 ret = extcon_register_interest(&omap->extcon_id_dev,
 430                                                edev->name, "USB-HOST",
 431                                                &omap->id_nb);
 432                 if (ret < 0)
 433                         dev_vdbg(omap->dev, "failed to register notifier for USB-HOST\n");
 434
 435                 if (extcon_get_cable_state(edev, "USB") == true)
 436                         dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID);
 437                 if (extcon_get_cable_state(edev, "USB-HOST") == true)
 438                         dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND);
 439         }
 440
 441         return 0;
 442 }
 443
 444 static int dwc3_omap_probe(struct platform_device *pdev)
 445 {
 446         struct device_node      *node = pdev->dev.of_node;
 447
 448         struct dwc3_omap        *omap;
 449         struct resource         *res;
 450         struct device           *dev = &pdev->dev;
 451         struct regulator        *vbus_reg = NULL;
 452
 453         int                     ret;
 454         int                     irq;
 455
 456         u32                     reg;
 457
 458         void __iomem            *base;
 459
 460         if (!node) {
 461                 dev_err(dev, "device node not found\n");
 462                 return -EINVAL;
 463         }
 464
 465         omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL);
 466         if (!omap)
 467                 return -ENOMEM;
 468
 469         platform_set_drvdata(pdev, omap);
 470
 471         irq = platform_get_irq(pdev, 0);
 472         if (irq < 0) {
 473                 dev_err(dev, "missing IRQ resource\n");
 474                 return -EINVAL;
 475         }
 476
 477         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 478         base = devm_ioremap_resource(dev, res);
 479         if (IS_ERR(base))
 480                 return PTR_ERR(base);
 481
 482         if (of_property_read_bool(node, "vbus-supply")) {
 483                 vbus_reg = devm_regulator_get(dev, "vbus");
 484                 if (IS_ERR(vbus_reg)) {
 485                         dev_err(dev, "vbus init failed\n");
 486                         return PTR_ERR(vbus_reg);
 487                 }
 488         }
 489
 490         omap->dev       = dev;
 491         omap->irq       = irq;
 492         omap->base      = base;
 493         omap->vbus_reg  = vbus_reg;
 494         dev->dma_mask   = &dwc3_omap_dma_mask;
 495
 496         pm_runtime_enable(dev);
 497         ret = pm_runtime_get_sync(dev);
 498         if (ret < 0) {
 499                 dev_err(dev, "get_sync failed with err %d\n", ret);
 500                 goto err0;
 501         }
 502
 503         dwc3_omap_map_offset(omap);
 504         dwc3_omap_set_utmi_mode(omap);
 505
 506         /* check the DMA Status */
 507         reg = dwc3_omap_readl(omap->base, USBOTGSS_SYSCONFIG);
 508         omap->dma_status = !!(reg & USBOTGSS_SYSCONFIG_DMADISABLE);
 509
 510         ret = devm_request_irq(dev, omap->irq, dwc3_omap_interrupt, 0,
 511                         "dwc3-omap", omap);
 512         if (ret) {
 513                 dev_err(dev, "failed to request IRQ #%d --> %d\n",
 514                                 omap->irq, ret);
 515                 goto err1;
 516         }
 517
 518         dwc3_omap_enable_irqs(omap);
 519
 520         ret = dwc3_omap_extcon_register(omap);
 521         if (ret < 0)
 522                 goto err2;
 523
 524         ret = of_platform_populate(node, NULL, NULL, dev);
 525         if (ret) {
 526                 dev_err(&pdev->dev, "failed to create dwc3 core\n");
 527                 goto err3;
 528         }
 529
 530         return 0;
 531
 532 err3:
 533         if (omap->extcon_vbus_dev.edev)
 534                 extcon_unregister_interest(&omap->extcon_vbus_dev);
 535         if (omap->extcon_id_dev.edev)
 536                 extcon_unregister_interest(&omap->extcon_id_dev);
 537
 538 err2:
 539         dwc3_omap_disable_irqs(omap);
 540
 541 err1:
 542         pm_runtime_put_sync(dev);
 543
 544 err0:
 545         pm_runtime_disable(dev);
 546
 547         return ret;
 548 }
 549
 550 static int dwc3_omap_remove(struct platform_device *pdev)
 551 {
 552         struct dwc3_omap        *omap = platform_get_drvdata(pdev);
 553
 554         if (omap->extcon_vbus_dev.edev)
 555                 extcon_unregister_interest(&omap->extcon_vbus_dev);
 556         if (omap->extcon_id_dev.edev)
 557                 extcon_unregister_interest(&omap->extcon_id_dev);
 558         dwc3_omap_disable_irqs(omap);
 559         of_platform_depopulate(omap->dev);
 560         pm_runtime_put_sync(&pdev->dev);
 561         pm_runtime_disable(&pdev->dev);
 562
 563         return 0;
 564 }
 565
 566 static const struct of_device_id of_dwc3_match[] = {
 567         {
 568                 .compatible =   "ti,dwc3"
 569         },
 570         {
 571                 .compatible =   "ti,am437x-dwc3"
 572         },
 573         { },
 574 };
 575 MODULE_DEVICE_TABLE(of, of_dwc3_match);
 576
 577 #ifdef CONFIG_PM_SLEEP
 578 static int dwc3_omap_suspend(struct device *dev)
 579 {
 580         struct dwc3_omap        *omap = dev_get_drvdata(dev);
 581
 582         omap->utmi_otg_ctrl = dwc3_omap_read_utmi_ctrl(omap);
 583         dwc3_omap_disable_irqs(omap);
 584
 585         return 0;
 586 }
 587
 588 static int dwc3_omap_resume(struct device *dev)
 589 {
 590         struct dwc3_omap        *omap = dev_get_drvdata(dev);
 591
 592         dwc3_omap_write_utmi_ctrl(omap, omap->utmi_otg_ctrl);
 593         dwc3_omap_enable_irqs(omap);
 594
 595         pm_runtime_disable(dev);
 596         pm_runtime_set_active(dev);
 597         pm_runtime_enable(dev);
 598
 599         return 0;
 600 }
 601
 602 static const struct dev_pm_ops dwc3_omap_dev_pm_ops = {
 603
 604         SET_SYSTEM_SLEEP_PM_OPS(dwc3_omap_suspend, dwc3_omap_resume)
 605 };
 606
 607 #define DEV_PM_OPS      (&dwc3_omap_dev_pm_ops)
 608 #else
 609 #define DEV_PM_OPS      NULL
 610 #endif /* CONFIG_PM_SLEEP */
 611
 612 static struct platform_driver dwc3_omap_driver = {
 613         .probe          = dwc3_omap_probe,
 614         .remove         = dwc3_omap_remove,
 615         .driver         = {
 616                 .name   = "omap-dwc3",
 617                 .of_match_table = of_dwc3_match,
 618                 .pm     = DEV_PM_OPS,
 619         },
 620 };
 621
 622 module_platform_driver(dwc3_omap_driver);
 623
 624 MODULE_ALIAS("platform:omap-dwc3");
 625 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
 626 MODULE_LICENSE("GPL v2");
 627 MODULE_DESCRIPTION("DesignWare USB3 OMAP Glue Layer");