2 * dwc3-omap.c - OMAP Specific Glue layer
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/module.h>
20 #include <linux/kernel.h>
21 #include <linux/slab.h>
22 #include <linux/irq.h>
23 #include <linux/interrupt.h>
24 #include <linux/platform_device.h>
25 #include <linux/platform_data/dwc3-omap.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/ioport.h>
31 #include <linux/of_platform.h>
32 #include <linux/extcon.h>
33 #include <linux/regulator/consumer.h>
35 #include <linux/usb/otg.h>
38 * All these registers belong to OMAP's Wrapper around the
39 * DesignWare USB3 Core.
42 #define USBOTGSS_REVISION 0x0000
43 #define USBOTGSS_SYSCONFIG 0x0010
44 #define USBOTGSS_IRQ_EOI 0x0020
45 #define USBOTGSS_EOI_OFFSET 0x0008
46 #define USBOTGSS_IRQSTATUS_RAW_0 0x0024
47 #define USBOTGSS_IRQSTATUS_0 0x0028
48 #define USBOTGSS_IRQENABLE_SET_0 0x002c
49 #define USBOTGSS_IRQENABLE_CLR_0 0x0030
50 #define USBOTGSS_IRQ0_OFFSET 0x0004
51 #define USBOTGSS_IRQSTATUS_RAW_1 0x0030
52 #define USBOTGSS_IRQSTATUS_1 0x0034
53 #define USBOTGSS_IRQENABLE_SET_1 0x0038
54 #define USBOTGSS_IRQENABLE_CLR_1 0x003c
55 #define USBOTGSS_IRQSTATUS_RAW_2 0x0040
56 #define USBOTGSS_IRQSTATUS_2 0x0044
57 #define USBOTGSS_IRQENABLE_SET_2 0x0048
58 #define USBOTGSS_IRQENABLE_CLR_2 0x004c
59 #define USBOTGSS_IRQSTATUS_RAW_3 0x0050
60 #define USBOTGSS_IRQSTATUS_3 0x0054
61 #define USBOTGSS_IRQENABLE_SET_3 0x0058
62 #define USBOTGSS_IRQENABLE_CLR_3 0x005c
63 #define USBOTGSS_IRQSTATUS_EOI_MISC 0x0030
64 #define USBOTGSS_IRQSTATUS_RAW_MISC 0x0034
65 #define USBOTGSS_IRQSTATUS_MISC 0x0038
66 #define USBOTGSS_IRQENABLE_SET_MISC 0x003c
67 #define USBOTGSS_IRQENABLE_CLR_MISC 0x0040
68 #define USBOTGSS_IRQMISC_OFFSET 0x03fc
69 #define USBOTGSS_UTMI_OTG_STATUS 0x0080
70 #define USBOTGSS_UTMI_OTG_CTRL 0x0084
71 #define USBOTGSS_UTMI_OTG_OFFSET 0x0480
72 #define USBOTGSS_TXFIFO_DEPTH 0x0508
73 #define USBOTGSS_RXFIFO_DEPTH 0x050c
74 #define USBOTGSS_MMRAM_OFFSET 0x0100
75 #define USBOTGSS_FLADJ 0x0104
76 #define USBOTGSS_DEBUG_CFG 0x0108
77 #define USBOTGSS_DEBUG_DATA 0x010c
78 #define USBOTGSS_DEV_EBC_EN 0x0110
79 #define USBOTGSS_DEBUG_OFFSET 0x0600
81 /* SYSCONFIG REGISTER */
82 #define USBOTGSS_SYSCONFIG_DMADISABLE (1 << 16)
84 /* IRQ_EOI REGISTER */
85 #define USBOTGSS_IRQ_EOI_LINE_NUMBER (1 << 0)
88 #define USBOTGSS_IRQO_COREIRQ_ST (1 << 0)
91 #define USBOTGSS_IRQMISC_DMADISABLECLR (1 << 17)
92 #define USBOTGSS_IRQMISC_OEVT (1 << 16)
93 #define USBOTGSS_IRQMISC_DRVVBUS_RISE (1 << 13)
94 #define USBOTGSS_IRQMISC_CHRGVBUS_RISE (1 << 12)
95 #define USBOTGSS_IRQMISC_DISCHRGVBUS_RISE (1 << 11)
96 #define USBOTGSS_IRQMISC_IDPULLUP_RISE (1 << 8)
97 #define USBOTGSS_IRQMISC_DRVVBUS_FALL (1 << 5)
98 #define USBOTGSS_IRQMISC_CHRGVBUS_FALL (1 << 4)
99 #define USBOTGSS_IRQMISC_DISCHRGVBUS_FALL (1 << 3)
100 #define USBOTGSS_IRQMISC_IDPULLUP_FALL (1 << 0)
102 /* UTMI_OTG_STATUS REGISTER */
103 #define USBOTGSS_UTMI_OTG_STATUS_DRVVBUS (1 << 5)
104 #define USBOTGSS_UTMI_OTG_STATUS_CHRGVBUS (1 << 4)
105 #define USBOTGSS_UTMI_OTG_STATUS_DISCHRGVBUS (1 << 3)
106 #define USBOTGSS_UTMI_OTG_STATUS_IDPULLUP (1 << 0)
108 /* UTMI_OTG_CTRL REGISTER */
109 #define USBOTGSS_UTMI_OTG_CTRL_SW_MODE (1 << 31)
110 #define USBOTGSS_UTMI_OTG_CTRL_POWERPRESENT (1 << 9)
111 #define USBOTGSS_UTMI_OTG_CTRL_TXBITSTUFFENABLE (1 << 8)
112 #define USBOTGSS_UTMI_OTG_CTRL_IDDIG (1 << 4)
113 #define USBOTGSS_UTMI_OTG_CTRL_SESSEND (1 << 3)
114 #define USBOTGSS_UTMI_OTG_CTRL_SESSVALID (1 << 2)
115 #define USBOTGSS_UTMI_OTG_CTRL_VBUSVALID (1 << 1)
130 struct extcon_dev *edev;
131 struct notifier_block vbus_nb;
132 struct notifier_block id_nb;
134 struct regulator *vbus_reg;
137 enum omap_dwc3_vbus_id_status {
141 OMAP_DWC3_VBUS_VALID,
144 static inline u32 dwc3_omap_readl(void __iomem *base, u32 offset)
146 return readl(base + offset);
149 static inline void dwc3_omap_writel(void __iomem *base, u32 offset, u32 value)
151 writel(value, base + offset);
154 static u32 dwc3_omap_read_utmi_ctrl(struct dwc3_omap *omap)
156 return dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_CTRL +
157 omap->utmi_otg_offset);
160 static void dwc3_omap_write_utmi_ctrl(struct dwc3_omap *omap, u32 value)
162 dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_CTRL +
163 omap->utmi_otg_offset, value);
167 static u32 dwc3_omap_read_irq0_status(struct dwc3_omap *omap)
169 return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_RAW_0 -
173 static void dwc3_omap_write_irq0_status(struct dwc3_omap *omap, u32 value)
175 dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_0 -
176 omap->irq0_offset, value);
180 static u32 dwc3_omap_read_irqmisc_status(struct dwc3_omap *omap)
182 return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_RAW_MISC +
183 omap->irqmisc_offset);
186 static void dwc3_omap_write_irqmisc_status(struct dwc3_omap *omap, u32 value)
188 dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_MISC +
189 omap->irqmisc_offset, value);
193 static void dwc3_omap_write_irqmisc_set(struct dwc3_omap *omap, u32 value)
195 dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_MISC +
196 omap->irqmisc_offset, value);
200 static void dwc3_omap_write_irq0_set(struct dwc3_omap *omap, u32 value)
202 dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_0 -
203 omap->irq0_offset, value);
206 static void dwc3_omap_write_irqmisc_clr(struct dwc3_omap *omap, u32 value)
208 dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_MISC +
209 omap->irqmisc_offset, value);
212 static void dwc3_omap_write_irq0_clr(struct dwc3_omap *omap, u32 value)
214 dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_0 -
215 omap->irq0_offset, value);
218 static void dwc3_omap_set_mailbox(struct dwc3_omap *omap,
219 enum omap_dwc3_vbus_id_status status)
225 case OMAP_DWC3_ID_GROUND:
226 if (omap->vbus_reg) {
227 ret = regulator_enable(omap->vbus_reg);
229 dev_err(omap->dev, "regulator enable failed\n");
234 val = dwc3_omap_read_utmi_ctrl(omap);
235 val &= ~USBOTGSS_UTMI_OTG_CTRL_IDDIG;
236 dwc3_omap_write_utmi_ctrl(omap, val);
239 case OMAP_DWC3_VBUS_VALID:
240 val = dwc3_omap_read_utmi_ctrl(omap);
241 val &= ~USBOTGSS_UTMI_OTG_CTRL_SESSEND;
242 val |= USBOTGSS_UTMI_OTG_CTRL_VBUSVALID
243 | USBOTGSS_UTMI_OTG_CTRL_SESSVALID;
244 dwc3_omap_write_utmi_ctrl(omap, val);
247 case OMAP_DWC3_ID_FLOAT:
249 regulator_disable(omap->vbus_reg);
250 val = dwc3_omap_read_utmi_ctrl(omap);
251 val |= USBOTGSS_UTMI_OTG_CTRL_IDDIG;
252 dwc3_omap_write_utmi_ctrl(omap, val);
254 case OMAP_DWC3_VBUS_OFF:
255 val = dwc3_omap_read_utmi_ctrl(omap);
256 val &= ~(USBOTGSS_UTMI_OTG_CTRL_SESSVALID
257 | USBOTGSS_UTMI_OTG_CTRL_VBUSVALID);
258 val |= USBOTGSS_UTMI_OTG_CTRL_SESSEND;
259 dwc3_omap_write_utmi_ctrl(omap, val);
263 dev_WARN(omap->dev, "invalid state\n");
267 static void dwc3_omap_enable_irqs(struct dwc3_omap *omap);
268 static void dwc3_omap_disable_irqs(struct dwc3_omap *omap);
270 static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap)
272 struct dwc3_omap *omap = _omap;
274 if (dwc3_omap_read_irqmisc_status(omap) ||
275 dwc3_omap_read_irq0_status(omap)) {
277 dwc3_omap_disable_irqs(omap);
278 return IRQ_WAKE_THREAD;
284 static irqreturn_t dwc3_omap_interrupt_thread(int irq, void *_omap)
286 struct dwc3_omap *omap = _omap;
289 /* clear irq status flags */
290 reg = dwc3_omap_read_irqmisc_status(omap);
291 dwc3_omap_write_irqmisc_status(omap, reg);
293 reg = dwc3_omap_read_irq0_status(omap);
294 dwc3_omap_write_irq0_status(omap, reg);
297 dwc3_omap_enable_irqs(omap);
302 static void dwc3_omap_enable_irqs(struct dwc3_omap *omap)
306 /* enable all IRQs */
307 reg = USBOTGSS_IRQO_COREIRQ_ST;
308 dwc3_omap_write_irq0_set(omap, reg);
310 reg = (USBOTGSS_IRQMISC_OEVT |
311 USBOTGSS_IRQMISC_DRVVBUS_RISE |
312 USBOTGSS_IRQMISC_CHRGVBUS_RISE |
313 USBOTGSS_IRQMISC_DISCHRGVBUS_RISE |
314 USBOTGSS_IRQMISC_IDPULLUP_RISE |
315 USBOTGSS_IRQMISC_DRVVBUS_FALL |
316 USBOTGSS_IRQMISC_CHRGVBUS_FALL |
317 USBOTGSS_IRQMISC_DISCHRGVBUS_FALL |
318 USBOTGSS_IRQMISC_IDPULLUP_FALL);
320 dwc3_omap_write_irqmisc_set(omap, reg);
323 static void dwc3_omap_disable_irqs(struct dwc3_omap *omap)
327 /* disable all IRQs */
328 reg = USBOTGSS_IRQO_COREIRQ_ST;
329 dwc3_omap_write_irq0_clr(omap, reg);
331 reg = (USBOTGSS_IRQMISC_OEVT |
332 USBOTGSS_IRQMISC_DRVVBUS_RISE |
333 USBOTGSS_IRQMISC_CHRGVBUS_RISE |
334 USBOTGSS_IRQMISC_DISCHRGVBUS_RISE |
335 USBOTGSS_IRQMISC_IDPULLUP_RISE |
336 USBOTGSS_IRQMISC_DRVVBUS_FALL |
337 USBOTGSS_IRQMISC_CHRGVBUS_FALL |
338 USBOTGSS_IRQMISC_DISCHRGVBUS_FALL |
339 USBOTGSS_IRQMISC_IDPULLUP_FALL);
341 dwc3_omap_write_irqmisc_clr(omap, reg);
344 static int dwc3_omap_id_notifier(struct notifier_block *nb,
345 unsigned long event, void *ptr)
347 struct dwc3_omap *omap = container_of(nb, struct dwc3_omap, id_nb);
350 dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND);
352 dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_FLOAT);
357 static int dwc3_omap_vbus_notifier(struct notifier_block *nb,
358 unsigned long event, void *ptr)
360 struct dwc3_omap *omap = container_of(nb, struct dwc3_omap, vbus_nb);
363 dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID);
365 dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_OFF);
370 static void dwc3_omap_map_offset(struct dwc3_omap *omap)
372 struct device_node *node = omap->dev->of_node;
375 * Differentiate between OMAP5 and AM437x.
377 * For OMAP5(ES2.0) and AM437x wrapper revision is same, even
378 * though there are changes in wrapper register offsets.
380 * Using dt compatible to differentiate AM437x.
382 if (of_device_is_compatible(node, "ti,am437x-dwc3")) {
383 omap->irq_eoi_offset = USBOTGSS_EOI_OFFSET;
384 omap->irq0_offset = USBOTGSS_IRQ0_OFFSET;
385 omap->irqmisc_offset = USBOTGSS_IRQMISC_OFFSET;
386 omap->utmi_otg_offset = USBOTGSS_UTMI_OTG_OFFSET;
387 omap->debug_offset = USBOTGSS_DEBUG_OFFSET;
391 static void dwc3_omap_set_utmi_mode(struct dwc3_omap *omap)
394 struct device_node *node = omap->dev->of_node;
397 reg = dwc3_omap_read_utmi_ctrl(omap);
399 of_property_read_u32(node, "utmi-mode", &utmi_mode);
402 case DWC3_OMAP_UTMI_MODE_SW:
403 reg |= USBOTGSS_UTMI_OTG_CTRL_SW_MODE;
405 case DWC3_OMAP_UTMI_MODE_HW:
406 reg &= ~USBOTGSS_UTMI_OTG_CTRL_SW_MODE;
409 dev_WARN(omap->dev, "UNKNOWN utmi mode %d\n", utmi_mode);
412 dwc3_omap_write_utmi_ctrl(omap, reg);
415 static int dwc3_omap_extcon_register(struct dwc3_omap *omap)
418 struct device_node *node = omap->dev->of_node;
419 struct extcon_dev *edev;
421 if (of_property_read_bool(node, "extcon")) {
422 edev = extcon_get_edev_by_phandle(omap->dev, 0);
424 dev_vdbg(omap->dev, "couldn't get extcon device\n");
425 return -EPROBE_DEFER;
428 omap->vbus_nb.notifier_call = dwc3_omap_vbus_notifier;
429 ret = devm_extcon_register_notifier(omap->dev, edev,
430 EXTCON_USB, &omap->vbus_nb);
432 dev_vdbg(omap->dev, "failed to register notifier for USB\n");
434 omap->id_nb.notifier_call = dwc3_omap_id_notifier;
435 ret = devm_extcon_register_notifier(omap->dev, edev,
436 EXTCON_USB_HOST, &omap->id_nb);
438 dev_vdbg(omap->dev, "failed to register notifier for USB-HOST\n");
440 if (extcon_get_state(edev, EXTCON_USB) == true)
441 dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID);
442 if (extcon_get_state(edev, EXTCON_USB_HOST) == true)
443 dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND);
451 static int dwc3_omap_probe(struct platform_device *pdev)
453 struct device_node *node = pdev->dev.of_node;
455 struct dwc3_omap *omap;
456 struct resource *res;
457 struct device *dev = &pdev->dev;
458 struct regulator *vbus_reg = NULL;
468 dev_err(dev, "device node not found\n");
472 omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL);
476 platform_set_drvdata(pdev, omap);
478 irq = platform_get_irq(pdev, 0);
480 dev_err(dev, "missing IRQ resource\n");
484 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
485 base = devm_ioremap_resource(dev, res);
487 return PTR_ERR(base);
489 if (of_property_read_bool(node, "vbus-supply")) {
490 vbus_reg = devm_regulator_get(dev, "vbus");
491 if (IS_ERR(vbus_reg)) {
492 dev_err(dev, "vbus init failed\n");
493 return PTR_ERR(vbus_reg);
500 omap->vbus_reg = vbus_reg;
502 pm_runtime_enable(dev);
503 ret = pm_runtime_get_sync(dev);
505 dev_err(dev, "get_sync failed with err %d\n", ret);
509 dwc3_omap_map_offset(omap);
510 dwc3_omap_set_utmi_mode(omap);
512 /* check the DMA Status */
513 reg = dwc3_omap_readl(omap->base, USBOTGSS_SYSCONFIG);
514 irq_set_status_flags(omap->irq, IRQ_NOAUTOEN);
515 ret = devm_request_threaded_irq(dev, omap->irq, dwc3_omap_interrupt,
516 dwc3_omap_interrupt_thread, IRQF_SHARED,
519 dev_err(dev, "failed to request IRQ #%d --> %d\n",
524 ret = dwc3_omap_extcon_register(omap);
528 ret = of_platform_populate(node, NULL, NULL, dev);
530 dev_err(&pdev->dev, "failed to create dwc3 core\n");
534 dwc3_omap_enable_irqs(omap);
535 enable_irq(omap->irq);
539 pm_runtime_put_sync(dev);
540 pm_runtime_disable(dev);
545 static int dwc3_omap_remove(struct platform_device *pdev)
547 struct dwc3_omap *omap = platform_get_drvdata(pdev);
549 dwc3_omap_disable_irqs(omap);
550 disable_irq(omap->irq);
551 of_platform_depopulate(omap->dev);
552 pm_runtime_put_sync(&pdev->dev);
553 pm_runtime_disable(&pdev->dev);
558 static const struct of_device_id of_dwc3_match[] = {
560 .compatible = "ti,dwc3"
563 .compatible = "ti,am437x-dwc3"
567 MODULE_DEVICE_TABLE(of, of_dwc3_match);
569 #ifdef CONFIG_PM_SLEEP
570 static int dwc3_omap_suspend(struct device *dev)
572 struct dwc3_omap *omap = dev_get_drvdata(dev);
574 omap->utmi_otg_ctrl = dwc3_omap_read_utmi_ctrl(omap);
575 dwc3_omap_disable_irqs(omap);
580 static int dwc3_omap_resume(struct device *dev)
582 struct dwc3_omap *omap = dev_get_drvdata(dev);
584 dwc3_omap_write_utmi_ctrl(omap, omap->utmi_otg_ctrl);
585 dwc3_omap_enable_irqs(omap);
587 pm_runtime_disable(dev);
588 pm_runtime_set_active(dev);
589 pm_runtime_enable(dev);
594 static const struct dev_pm_ops dwc3_omap_dev_pm_ops = {
596 SET_SYSTEM_SLEEP_PM_OPS(dwc3_omap_suspend, dwc3_omap_resume)
599 #define DEV_PM_OPS (&dwc3_omap_dev_pm_ops)
601 #define DEV_PM_OPS NULL
602 #endif /* CONFIG_PM_SLEEP */
604 static struct platform_driver dwc3_omap_driver = {
605 .probe = dwc3_omap_probe,
606 .remove = dwc3_omap_remove,
609 .of_match_table = of_dwc3_match,
614 module_platform_driver(dwc3_omap_driver);
616 MODULE_ALIAS("platform:omap-dwc3");
617 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
618 MODULE_LICENSE("GPL v2");
619 MODULE_DESCRIPTION("DesignWare USB3 OMAP Glue Layer");