2 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. The names of the above-listed copyright holders may not be used
19 * to endorse or promote products derived from this software without
20 * specific prior written permission.
22 * ALTERNATIVELY, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2, as published by the Free
24 * Software Foundation.
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 #include <linux/kernel.h>
40 #include <linux/slab.h>
41 #include <linux/spinlock.h>
42 #include <linux/platform_device.h>
43 #include <linux/pm_runtime.h>
44 #include <linux/interrupt.h>
46 #include <linux/list.h>
47 #include <linux/dma-mapping.h>
49 #include <linux/usb/ch9.h>
50 #include <linux/usb/gadget.h>
56 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
57 const struct dwc3_event_depevt *event);
59 static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
68 case EP0_STATUS_PHASE:
69 return "Status Phase";
75 static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
78 struct dwc3_gadget_ep_cmd_params params;
79 struct dwc3_trb_hw *trb_hw;
85 dep = dwc->eps[epnum];
86 if (dep->flags & DWC3_EP_BUSY) {
87 dev_vdbg(dwc->dev, "%s: still busy\n", dep->name);
91 trb_hw = dwc->ep0_trb;
92 memset(&trb, 0, sizeof(trb));
103 dwc3_trb_to_hw(&trb, trb_hw);
105 memset(¶ms, 0, sizeof(params));
106 params.param0 = upper_32_bits(dwc->ep0_trb_addr);
107 params.param1 = lower_32_bits(dwc->ep0_trb_addr);
109 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
110 DWC3_DEPCMD_STARTTRANSFER, ¶ms);
112 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
116 dep->flags |= DWC3_EP_BUSY;
117 dep->res_trans_idx = dwc3_gadget_ep_get_transfer_index(dwc,
120 dwc->ep0_next_event = DWC3_EP0_COMPLETE;
125 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
126 struct dwc3_request *req)
130 req->request.actual = 0;
131 req->request.status = -EINPROGRESS;
132 req->epnum = dep->number;
134 list_add_tail(&req->list, &dep->request_list);
137 * Gadget driver might not be quick enough to queue a request
138 * before we get a Transfer Not Ready event on this endpoint.
140 * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
141 * flag is set, it's telling us that as soon as Gadget queues the
142 * required request, we should kick the transfer here because the
143 * IRQ we were waiting for is long gone.
145 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
146 struct dwc3 *dwc = dep->dwc;
150 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
152 if (dwc->ep0state == EP0_STATUS_PHASE) {
153 type = dwc->three_stage_setup
154 ? DWC3_TRBCTL_CONTROL_STATUS3
155 : DWC3_TRBCTL_CONTROL_STATUS2;
156 } else if (dwc->ep0state == EP0_DATA_PHASE) {
157 type = DWC3_TRBCTL_CONTROL_DATA;
159 /* should never happen */
164 ret = dwc3_ep0_start_trans(dwc, direction,
165 req->request.dma, req->request.length, type);
166 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
173 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
176 struct dwc3_request *req = to_dwc3_request(request);
177 struct dwc3_ep *dep = to_dwc3_ep(ep);
178 struct dwc3 *dwc = dep->dwc;
184 spin_lock_irqsave(&dwc->lock, flags);
186 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
192 /* we share one TRB for ep0/1 */
193 if (!list_empty(&dwc->eps[0]->request_list) ||
194 !list_empty(&dwc->eps[1]->request_list) ||
195 dwc->ep0_status_pending) {
200 dev_vdbg(dwc->dev, "queueing request %p to %s length %d, state '%s'\n",
201 request, dep->name, request->length,
202 dwc3_ep0_state_string(dwc->ep0state));
204 ret = __dwc3_gadget_ep0_queue(dep, req);
207 spin_unlock_irqrestore(&dwc->lock, flags);
212 static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
214 struct dwc3_ep *dep = dwc->eps[0];
216 /* stall is always issued on EP0 */
217 __dwc3_gadget_ep_set_halt(dwc->eps[0], 1);
218 dwc->eps[0]->flags = DWC3_EP_ENABLED;
220 if (!list_empty(&dep->request_list)) {
221 struct dwc3_request *req;
223 req = next_request(&dep->request_list);
224 dwc3_gadget_giveback(dep, req, -ECONNRESET);
227 dwc->ep0state = EP0_SETUP_PHASE;
228 dwc3_ep0_out_start(dwc);
231 void dwc3_ep0_out_start(struct dwc3 *dwc)
235 ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8,
236 DWC3_TRBCTL_CONTROL_SETUP);
240 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
243 u32 windex = le16_to_cpu(wIndex_le);
246 epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
247 if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
250 dep = dwc->eps[epnum];
251 if (dep->flags & DWC3_EP_ENABLED)
257 static void dwc3_ep0_send_status_response(struct dwc3 *dwc)
259 dwc3_ep0_start_trans(dwc, 1, dwc->setup_buf_addr,
260 dwc->ep0_usb_req.length,
261 DWC3_TRBCTL_CONTROL_DATA);
267 static int dwc3_ep0_handle_status(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
272 __le16 *response_pkt;
274 recip = ctrl->bRequestType & USB_RECIP_MASK;
276 case USB_RECIP_DEVICE:
278 * We are self-powered. U1/U2/LTM will be set later
279 * once we handle this states. RemoteWakeup is 0 on SS
281 usb_status |= dwc->is_selfpowered << USB_DEVICE_SELF_POWERED;
284 case USB_RECIP_INTERFACE:
286 * Function Remote Wake Capable D0
287 * Function Remote Wakeup D1
291 case USB_RECIP_ENDPOINT:
292 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
296 if (dep->flags & DWC3_EP_STALL)
297 usb_status = 1 << USB_ENDPOINT_HALT;
303 response_pkt = (__le16 *) dwc->setup_buf;
304 *response_pkt = cpu_to_le16(usb_status);
305 dwc->ep0_usb_req.length = sizeof(*response_pkt);
306 dwc->ep0_status_pending = 1;
311 static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
312 struct usb_ctrlrequest *ctrl, int set)
322 wValue = le16_to_cpu(ctrl->wValue);
323 wIndex = le16_to_cpu(ctrl->wIndex);
324 recip = ctrl->bRequestType & USB_RECIP_MASK;
326 case USB_RECIP_DEVICE:
329 * 9.4.1 says only only for SS, in AddressState only for
330 * default control pipe
333 case USB_DEVICE_U1_ENABLE:
334 case USB_DEVICE_U2_ENABLE:
335 case USB_DEVICE_LTM_ENABLE:
336 if (dwc->dev_state != DWC3_CONFIGURED_STATE)
338 if (dwc->speed != DWC3_DSTS_SUPERSPEED)
342 /* XXX add U[12] & LTM */
344 case USB_DEVICE_REMOTE_WAKEUP:
346 case USB_DEVICE_U1_ENABLE:
348 case USB_DEVICE_U2_ENABLE:
350 case USB_DEVICE_LTM_ENABLE:
353 case USB_DEVICE_TEST_MODE:
354 if ((wIndex & 0xff) != 0)
360 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
361 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
374 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
381 case USB_RECIP_INTERFACE:
383 case USB_INTRF_FUNC_SUSPEND:
384 if (wIndex & USB_INTRF_FUNC_SUSPEND_LP)
385 /* XXX enable Low power suspend */
387 if (wIndex & USB_INTRF_FUNC_SUSPEND_RW)
388 /* XXX enable remote wakeup */
396 case USB_RECIP_ENDPOINT:
398 case USB_ENDPOINT_HALT:
400 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
403 ret = __dwc3_gadget_ep_set_halt(dep, set);
419 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
424 addr = le16_to_cpu(ctrl->wValue);
428 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
429 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
430 reg |= DWC3_DCFG_DEVADDR(addr);
431 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
434 dwc->dev_state = DWC3_ADDRESS_STATE;
436 dwc->dev_state = DWC3_DEFAULT_STATE;
441 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
445 spin_unlock(&dwc->lock);
446 ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
447 spin_lock(&dwc->lock);
451 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
456 dwc->start_config_issued = false;
457 cfg = le16_to_cpu(ctrl->wValue);
459 switch (dwc->dev_state) {
460 case DWC3_DEFAULT_STATE:
464 case DWC3_ADDRESS_STATE:
465 ret = dwc3_ep0_delegate_req(dwc, ctrl);
466 /* if the cfg matches and the cfg is non zero */
468 dwc->dev_state = DWC3_CONFIGURED_STATE;
471 case DWC3_CONFIGURED_STATE:
472 ret = dwc3_ep0_delegate_req(dwc, ctrl);
474 dwc->dev_state = DWC3_ADDRESS_STATE;
480 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
484 switch (ctrl->bRequest) {
485 case USB_REQ_GET_STATUS:
486 dev_vdbg(dwc->dev, "USB_REQ_GET_STATUS\n");
487 ret = dwc3_ep0_handle_status(dwc, ctrl);
489 case USB_REQ_CLEAR_FEATURE:
490 dev_vdbg(dwc->dev, "USB_REQ_CLEAR_FEATURE\n");
491 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
493 case USB_REQ_SET_FEATURE:
494 dev_vdbg(dwc->dev, "USB_REQ_SET_FEATURE\n");
495 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
497 case USB_REQ_SET_ADDRESS:
498 dev_vdbg(dwc->dev, "USB_REQ_SET_ADDRESS\n");
499 ret = dwc3_ep0_set_address(dwc, ctrl);
501 case USB_REQ_SET_CONFIGURATION:
502 dev_vdbg(dwc->dev, "USB_REQ_SET_CONFIGURATION\n");
503 ret = dwc3_ep0_set_config(dwc, ctrl);
506 dev_vdbg(dwc->dev, "Forwarding to gadget driver\n");
507 ret = dwc3_ep0_delegate_req(dwc, ctrl);
514 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
515 const struct dwc3_event_depevt *event)
517 struct usb_ctrlrequest *ctrl = dwc->ctrl_req;
521 if (!dwc->gadget_driver)
524 len = le16_to_cpu(ctrl->wLength);
526 dwc->three_stage_setup = false;
527 dwc->ep0_expect_in = false;
528 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
530 dwc->three_stage_setup = true;
531 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
532 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
535 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
536 ret = dwc3_ep0_std_request(dwc, ctrl);
538 ret = dwc3_ep0_delegate_req(dwc, ctrl);
544 dwc3_ep0_stall_and_restart(dwc);
547 static void dwc3_ep0_complete_data(struct dwc3 *dwc,
548 const struct dwc3_event_depevt *event)
550 struct dwc3_request *r = NULL;
551 struct usb_request *ur;
557 epnum = event->endpoint_number;
558 dep = dwc->eps[epnum];
560 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
562 if (!dwc->ep0_status_pending) {
563 r = next_request(&dwc->eps[0]->request_list);
566 ur = &dwc->ep0_usb_req;
567 dwc->ep0_status_pending = 0;
570 dwc3_trb_to_nat(dwc->ep0_trb, &trb);
572 if (dwc->ep0_bounced) {
573 struct dwc3_ep *ep0 = dwc->eps[0];
575 transferred = min_t(u32, ur->length,
576 ep0->endpoint.maxpacket - trb.length);
577 memcpy(ur->buf, dwc->ep0_bounce, transferred);
578 dwc->ep0_bounced = false;
580 transferred = ur->length - trb.length;
581 ur->actual += transferred;
584 if ((epnum & 1) && ur->actual < ur->length) {
585 /* for some reason we did not get everything out */
587 dwc3_ep0_stall_and_restart(dwc);
590 * handle the case where we have to send a zero packet. This
591 * seems to be case when req.length > maxpacket. Could it be?
594 dwc3_gadget_giveback(dep, r, 0);
598 static void dwc3_ep0_complete_req(struct dwc3 *dwc,
599 const struct dwc3_event_depevt *event)
601 struct dwc3_request *r;
606 if (!list_empty(&dep->request_list)) {
607 r = next_request(&dep->request_list);
609 dwc3_gadget_giveback(dep, r, 0);
612 dwc->ep0state = EP0_SETUP_PHASE;
613 dwc3_ep0_out_start(dwc);
616 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
617 const struct dwc3_event_depevt *event)
619 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
621 dep->flags &= ~DWC3_EP_BUSY;
623 switch (dwc->ep0state) {
624 case EP0_SETUP_PHASE:
625 dev_vdbg(dwc->dev, "Inspecting Setup Bytes\n");
626 dwc3_ep0_inspect_setup(dwc, event);
630 dev_vdbg(dwc->dev, "Data Phase\n");
631 dwc3_ep0_complete_data(dwc, event);
634 case EP0_STATUS_PHASE:
635 dev_vdbg(dwc->dev, "Status Phase\n");
636 dwc3_ep0_complete_req(dwc, event);
639 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
643 static void dwc3_ep0_do_control_setup(struct dwc3 *dwc,
644 const struct dwc3_event_depevt *event)
646 dwc->ep0state = EP0_SETUP_PHASE;
647 dwc3_ep0_out_start(dwc);
650 static void dwc3_ep0_do_control_data(struct dwc3 *dwc,
651 const struct dwc3_event_depevt *event)
654 struct dwc3_request *req;
658 dwc->ep0state = EP0_DATA_PHASE;
660 if (dwc->ep0_status_pending) {
661 dwc3_ep0_send_status_response(dwc);
665 if (list_empty(&dep->request_list)) {
666 dev_vdbg(dwc->dev, "pending request for EP0 Data phase\n");
667 dep->flags |= DWC3_EP_PENDING_REQUEST;
669 if (event->endpoint_number)
670 dep->flags |= DWC3_EP0_DIR_IN;
674 req = next_request(&dep->request_list);
675 req->direction = !!event->endpoint_number;
677 dwc->ep0state = EP0_DATA_PHASE;
678 if (req->request.length == 0) {
679 ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
680 dwc->ctrl_req_addr, 0,
681 DWC3_TRBCTL_CONTROL_DATA);
682 } else if ((req->request.length % dep->endpoint.maxpacket)
683 && (event->endpoint_number == 0)) {
684 dwc3_map_buffer_to_dma(req);
686 WARN_ON(req->request.length > dep->endpoint.maxpacket);
688 dwc->ep0_bounced = true;
691 * REVISIT in case request length is bigger than EP0
692 * wMaxPacketSize, we will need two chained TRBs to handle
695 ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
696 dwc->ep0_bounce_addr, dep->endpoint.maxpacket,
697 DWC3_TRBCTL_CONTROL_DATA);
699 dwc3_map_buffer_to_dma(req);
701 ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
702 req->request.dma, req->request.length,
703 DWC3_TRBCTL_CONTROL_DATA);
709 static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
710 const struct dwc3_event_depevt *event)
715 dwc->ep0state = EP0_STATUS_PHASE;
717 type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
718 : DWC3_TRBCTL_CONTROL_STATUS2;
720 ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
721 dwc->ctrl_req_addr, 0, type);
726 static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
727 const struct dwc3_event_depevt *event)
729 switch (event->status) {
730 case DEPEVT_STATUS_CONTROL_SETUP:
731 dev_vdbg(dwc->dev, "Control Setup\n");
732 dwc3_ep0_do_control_setup(dwc, event);
735 case DEPEVT_STATUS_CONTROL_DATA:
736 dev_vdbg(dwc->dev, "Control Data\n");
738 if (dwc->ep0_next_event != DWC3_EP0_NRDY_DATA) {
739 dev_vdbg(dwc->dev, "Expected %d got %d\n",
743 dwc3_ep0_stall_and_restart(dwc);
748 * One of the possible error cases is when Host _does_
749 * request for Data Phase, but it does so on the wrong
752 * Here, we already know ep0_next_event is DATA (see above),
753 * so we only need to check for direction.
755 if (dwc->ep0_expect_in != event->endpoint_number) {
756 dev_vdbg(dwc->dev, "Wrong direction for Data phase\n");
757 dwc3_ep0_stall_and_restart(dwc);
761 dwc3_ep0_do_control_data(dwc, event);
764 case DEPEVT_STATUS_CONTROL_STATUS:
765 dev_vdbg(dwc->dev, "Control Status\n");
767 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS) {
768 dev_vdbg(dwc->dev, "Expected %d got %d\n",
770 DWC3_EP0_NRDY_STATUS);
772 dwc3_ep0_stall_and_restart(dwc);
775 dwc3_ep0_do_control_status(dwc, event);
779 void dwc3_ep0_interrupt(struct dwc3 *dwc,
780 const const struct dwc3_event_depevt *event)
782 u8 epnum = event->endpoint_number;
784 dev_dbg(dwc->dev, "%s while ep%d%s in state '%s'\n",
785 dwc3_ep_event_string(event->endpoint_event),
786 epnum >> 1, (epnum & 1) ? "in" : "out",
787 dwc3_ep0_state_string(dwc->ep0state));
789 switch (event->endpoint_event) {
790 case DWC3_DEPEVT_XFERCOMPLETE:
791 dwc3_ep0_xfer_complete(dwc, event);
794 case DWC3_DEPEVT_XFERNOTREADY:
795 dwc3_ep0_xfernotready(dwc, event);
798 case DWC3_DEPEVT_XFERINPROGRESS:
799 case DWC3_DEPEVT_RXTXFIFOEVT:
800 case DWC3_DEPEVT_STREAMEVT:
801 case DWC3_DEPEVT_EPCMDCMPLT: