drivers/usb/dwc3/ep0.c

   1 /**
   2  * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
   3  *
   4  * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/ep0.c) and ported
  10  * to uboot.
  11  *
  12  * commit c00552ebaf : Merge 3.18-rc7 into usb-next
  13  *
  14  * SPDX-License-Identifier:     GPL-2.0
  15  */
  16
  17 #include <linux/kernel.h>
  18 #include <linux/slab.h>
  19 #include <linux/spinlock.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/io.h>
  24 #include <linux/list.h>
  25 #include <linux/dma-mapping.h>
  26
  27 #include <linux/usb/ch9.h>
  28 #include <linux/usb/gadget.h>
  29 #include <linux/usb/composite.h>
  30
  31 #include "core.h"
  32 #include "debug.h"
  33 #include "gadget.h"
  34 #include "io.h"
  35
  36 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
  37 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
  38                 struct dwc3_ep *dep, struct dwc3_request *req);
  39
  40 static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
  41 {
  42         switch (state) {
  43         case EP0_UNCONNECTED:
  44                 return "Unconnected";
  45         case EP0_SETUP_PHASE:
  46                 return "Setup Phase";
  47         case EP0_DATA_PHASE:
  48                 return "Data Phase";
  49         case EP0_STATUS_PHASE:
  50                 return "Status Phase";
  51         default:
  52                 return "UNKNOWN";
  53         }
  54 }
  55
  56 static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
  57                 u32 len, u32 type)
  58 {
  59         struct dwc3_gadget_ep_cmd_params params;
  60         struct dwc3_trb                 *trb;
  61         struct dwc3_ep                  *dep;
  62
  63         int                             ret;
  64
  65         dep = dwc->eps[epnum];
  66         if (dep->flags & DWC3_EP_BUSY) {
  67                 dwc3_trace(trace_dwc3_ep0, "%s still busy", dep->name);
  68                 return 0;
  69         }
  70
  71         trb = dwc->ep0_trb;
  72
  73         trb->bpl = lower_32_bits(buf_dma);
  74         trb->bph = upper_32_bits(buf_dma);
  75         trb->size = len;
  76         trb->ctrl = type;
  77
  78         trb->ctrl |= (DWC3_TRB_CTRL_HWO
  79                         | DWC3_TRB_CTRL_LST
  80                         | DWC3_TRB_CTRL_IOC
  81                         | DWC3_TRB_CTRL_ISP_IMI);
  82
  83         memset(&params, 0, sizeof(params));
  84         params.param0 = upper_32_bits(dwc->ep0_trb_addr);
  85         params.param1 = lower_32_bits(dwc->ep0_trb_addr);
  86
  87         trace_dwc3_prepare_trb(dep, trb);
  88
  89         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
  90                         DWC3_DEPCMD_STARTTRANSFER, &params);
  91         if (ret < 0) {
  92                 dwc3_trace(trace_dwc3_ep0, "%s STARTTRANSFER failed",
  93                                 dep->name);
  94                 return ret;
  95         }
  96
  97         dep->flags |= DWC3_EP_BUSY;
  98         dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
  99                         dep->number);
 100
 101         dwc->ep0_next_event = DWC3_EP0_COMPLETE;
 102
 103         return 0;
 104 }
 105
 106 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
 107                 struct dwc3_request *req)
 108 {
 109         struct dwc3             *dwc = dep->dwc;
 110
 111         req->request.actual     = 0;
 112         req->request.status     = -EINPROGRESS;
 113         req->epnum              = dep->number;
 114
 115         list_add_tail(&req->list, &dep->request_list);
 116
 117         /*
 118          * Gadget driver might not be quick enough to queue a request
 119          * before we get a Transfer Not Ready event on this endpoint.
 120          *
 121          * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
 122          * flag is set, it's telling us that as soon as Gadget queues the
 123          * required request, we should kick the transfer here because the
 124          * IRQ we were waiting for is long gone.
 125          */
 126         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
 127                 unsigned        direction;
 128
 129                 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
 130
 131                 if (dwc->ep0state != EP0_DATA_PHASE) {
 132                         dev_WARN(dwc->dev, "Unexpected pending request\n");
 133                         return 0;
 134                 }
 135
 136                 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
 137
 138                 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
 139                                 DWC3_EP0_DIR_IN);
 140
 141                 return 0;
 142         }
 143
 144         /*
 145          * In case gadget driver asked us to delay the STATUS phase,
 146          * handle it here.
 147          */
 148         if (dwc->delayed_status) {
 149                 unsigned        direction;
 150
 151                 direction = !dwc->ep0_expect_in;
 152                 dwc->delayed_status = false;
 153                 usb_gadget_set_state(&dwc->gadget, USB_STATE_CONFIGURED);
 154
 155                 if (dwc->ep0state == EP0_STATUS_PHASE)
 156                         __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
 157                 else
 158                         dwc3_trace(trace_dwc3_ep0,
 159                                         "too early for delayed status");
 160
 161                 return 0;
 162         }
 163
 164         /*
 165          * Unfortunately we have uncovered a limitation wrt the Data Phase.
 166          *
 167          * Section 9.4 says we can wait for the XferNotReady(DATA) event to
 168          * come before issueing Start Transfer command, but if we do, we will
 169          * miss situations where the host starts another SETUP phase instead of
 170          * the DATA phase.  Such cases happen at least on TD.7.6 of the Link
 171          * Layer Compliance Suite.
 172          *
 173          * The problem surfaces due to the fact that in case of back-to-back
 174          * SETUP packets there will be no XferNotReady(DATA) generated and we
 175          * will be stuck waiting for XferNotReady(DATA) forever.
 176          *
 177          * By looking at tables 9-13 and 9-14 of the Databook, we can see that
 178          * it tells us to start Data Phase right away. It also mentions that if
 179          * we receive a SETUP phase instead of the DATA phase, core will issue
 180          * XferComplete for the DATA phase, before actually initiating it in
 181          * the wire, with the TRB's status set to "SETUP_PENDING". Such status
 182          * can only be used to print some debugging logs, as the core expects
 183          * us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
 184          * just so it completes right away, without transferring anything and,
 185          * only then, we can go back to the SETUP phase.
 186          *
 187          * Because of this scenario, SNPS decided to change the programming
 188          * model of control transfers and support on-demand transfers only for
 189          * the STATUS phase. To fix the issue we have now, we will always wait
 190          * for gadget driver to queue the DATA phase's struct usb_request, then
 191          * start it right away.
 192          *
 193          * If we're actually in a 2-stage transfer, we will wait for
 194          * XferNotReady(STATUS).
 195          */
 196         if (dwc->three_stage_setup) {
 197                 unsigned        direction;
 198
 199                 direction = dwc->ep0_expect_in;
 200                 dwc->ep0state = EP0_DATA_PHASE;
 201
 202                 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
 203
 204                 dep->flags &= ~DWC3_EP0_DIR_IN;
 205         }
 206
 207         return 0;
 208 }
 209
 210 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
 211                 gfp_t gfp_flags)
 212 {
 213         struct dwc3_request             *req = to_dwc3_request(request);
 214         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 215         struct dwc3                     *dwc = dep->dwc;
 216
 217         unsigned long                   flags;
 218
 219         int                             ret;
 220
 221         spin_lock_irqsave(&dwc->lock, flags);
 222         if (!dep->endpoint.desc) {
 223                 dwc3_trace(trace_dwc3_ep0,
 224                                 "trying to queue request %p to disabled %s",
 225                                 request, dep->name);
 226                 ret = -ESHUTDOWN;
 227                 goto out;
 228         }
 229
 230         /* we share one TRB for ep0/1 */
 231         if (!list_empty(&dep->request_list)) {
 232                 ret = -EBUSY;
 233                 goto out;
 234         }
 235
 236         dwc3_trace(trace_dwc3_ep0,
 237                         "queueing request %p to %s length %d state '%s'",
 238                         request, dep->name, request->length,
 239                         dwc3_ep0_state_string(dwc->ep0state));
 240
 241         ret = __dwc3_gadget_ep0_queue(dep, req);
 242
 243 out:
 244         spin_unlock_irqrestore(&dwc->lock, flags);
 245
 246         return ret;
 247 }
 248
 249 static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
 250 {
 251         struct dwc3_ep          *dep;
 252
 253         /* reinitialize physical ep1 */
 254         dep = dwc->eps[1];
 255         dep->flags = DWC3_EP_ENABLED;
 256
 257         /* stall is always issued on EP0 */
 258         dep = dwc->eps[0];
 259         __dwc3_gadget_ep_set_halt(dep, 1, false);
 260         dep->flags = DWC3_EP_ENABLED;
 261         dwc->delayed_status = false;
 262
 263         if (!list_empty(&dep->request_list)) {
 264                 struct dwc3_request     *req;
 265
 266                 req = next_request(&dep->request_list);
 267                 dwc3_gadget_giveback(dep, req, -ECONNRESET);
 268         }
 269
 270         dwc->ep0state = EP0_SETUP_PHASE;
 271         dwc3_ep0_out_start(dwc);
 272 }
 273
 274 int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
 275 {
 276         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 277         struct dwc3                     *dwc = dep->dwc;
 278
 279         dwc3_ep0_stall_and_restart(dwc);
 280
 281         return 0;
 282 }
 283
 284 int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
 285 {
 286         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 287         struct dwc3                     *dwc = dep->dwc;
 288         unsigned long                   flags;
 289         int                             ret;
 290
 291         spin_lock_irqsave(&dwc->lock, flags);
 292         ret = __dwc3_gadget_ep0_set_halt(ep, value);
 293         spin_unlock_irqrestore(&dwc->lock, flags);
 294
 295         return ret;
 296 }
 297
 298 void dwc3_ep0_out_start(struct dwc3 *dwc)
 299 {
 300         int                             ret;
 301
 302         ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8,
 303                         DWC3_TRBCTL_CONTROL_SETUP);
 304         WARN_ON(ret < 0);
 305 }
 306
 307 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
 308 {
 309         struct dwc3_ep          *dep;
 310         u32                     windex = le16_to_cpu(wIndex_le);
 311         u32                     epnum;
 312
 313         epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
 314         if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
 315                 epnum |= 1;
 316
 317         dep = dwc->eps[epnum];
 318         if (dep->flags & DWC3_EP_ENABLED)
 319                 return dep;
 320
 321         return NULL;
 322 }
 323
 324 static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
 325 {
 326 }
 327 /*
 328  * ch 9.4.5
 329  */
 330 static int dwc3_ep0_handle_status(struct dwc3 *dwc,
 331                 struct usb_ctrlrequest *ctrl)
 332 {
 333         struct dwc3_ep          *dep;
 334         u32                     recip;
 335         u32                     reg;
 336         u16                     usb_status = 0;
 337         __le16                  *response_pkt;
 338
 339         recip = ctrl->bRequestType & USB_RECIP_MASK;
 340         switch (recip) {
 341         case USB_RECIP_DEVICE:
 342                 /*
 343                  * LTM will be set once we know how to set this in HW.
 344                  */
 345                 usb_status |= dwc->is_selfpowered << USB_DEVICE_SELF_POWERED;
 346
 347                 if (dwc->speed == DWC3_DSTS_SUPERSPEED) {
 348                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 349                         if (reg & DWC3_DCTL_INITU1ENA)
 350                                 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
 351                         if (reg & DWC3_DCTL_INITU2ENA)
 352                                 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
 353                 }
 354
 355                 break;
 356
 357         case USB_RECIP_INTERFACE:
 358                 /*
 359                  * Function Remote Wake Capable D0
 360                  * Function Remote Wakeup       D1
 361                  */
 362                 break;
 363
 364         case USB_RECIP_ENDPOINT:
 365                 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
 366                 if (!dep)
 367                         return -EINVAL;
 368
 369                 if (dep->flags & DWC3_EP_STALL)
 370                         usb_status = 1 << USB_ENDPOINT_HALT;
 371                 break;
 372         default:
 373                 return -EINVAL;
 374         }
 375
 376         response_pkt = (__le16 *) dwc->setup_buf;
 377         *response_pkt = cpu_to_le16(usb_status);
 378
 379         dep = dwc->eps[0];
 380         dwc->ep0_usb_req.dep = dep;
 381         dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
 382         dwc->ep0_usb_req.request.buf = dwc->setup_buf;
 383         dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
 384
 385         return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
 386 }
 387
 388 static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
 389                 struct usb_ctrlrequest *ctrl, int set)
 390 {
 391         struct dwc3_ep          *dep;
 392         u32                     recip;
 393         u32                     wValue;
 394         u32                     wIndex;
 395         u32                     reg;
 396         int                     ret;
 397         enum usb_device_state   state;
 398
 399         wValue = le16_to_cpu(ctrl->wValue);
 400         wIndex = le16_to_cpu(ctrl->wIndex);
 401         recip = ctrl->bRequestType & USB_RECIP_MASK;
 402         state = dwc->gadget.state;
 403
 404         switch (recip) {
 405         case USB_RECIP_DEVICE:
 406
 407                 switch (wValue) {
 408                 case USB_DEVICE_REMOTE_WAKEUP:
 409                         break;
 410                 /*
 411                  * 9.4.1 says only only for SS, in AddressState only for
 412                  * default control pipe
 413                  */
 414                 case USB_DEVICE_U1_ENABLE:
 415                         if (state != USB_STATE_CONFIGURED)
 416                                 return -EINVAL;
 417                         if (dwc->speed != DWC3_DSTS_SUPERSPEED)
 418                                 return -EINVAL;
 419
 420                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 421                         if (set)
 422                                 reg |= DWC3_DCTL_INITU1ENA;
 423                         else
 424                                 reg &= ~DWC3_DCTL_INITU1ENA;
 425                         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 426                         break;
 427
 428                 case USB_DEVICE_U2_ENABLE:
 429                         if (state != USB_STATE_CONFIGURED)
 430                                 return -EINVAL;
 431                         if (dwc->speed != DWC3_DSTS_SUPERSPEED)
 432                                 return -EINVAL;
 433
 434                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 435                         if (set)
 436                                 reg |= DWC3_DCTL_INITU2ENA;
 437                         else
 438                                 reg &= ~DWC3_DCTL_INITU2ENA;
 439                         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 440                         break;
 441
 442                 case USB_DEVICE_LTM_ENABLE:
 443                         return -EINVAL;
 444
 445                 case USB_DEVICE_TEST_MODE:
 446                         if ((wIndex & 0xff) != 0)
 447                                 return -EINVAL;
 448                         if (!set)
 449                                 return -EINVAL;
 450
 451                         dwc->test_mode_nr = wIndex >> 8;
 452                         dwc->test_mode = true;
 453                         break;
 454                 default:
 455                         return -EINVAL;
 456                 }
 457                 break;
 458
 459         case USB_RECIP_INTERFACE:
 460                 switch (wValue) {
 461                 case USB_INTRF_FUNC_SUSPEND:
 462                         if (wIndex & USB_INTRF_FUNC_SUSPEND_LP)
 463                                 /* XXX enable Low power suspend */
 464                                 ;
 465                         if (wIndex & USB_INTRF_FUNC_SUSPEND_RW)
 466                                 /* XXX enable remote wakeup */
 467                                 ;
 468                         break;
 469                 default:
 470                         return -EINVAL;
 471                 }
 472                 break;
 473
 474         case USB_RECIP_ENDPOINT:
 475                 switch (wValue) {
 476                 case USB_ENDPOINT_HALT:
 477                         dep = dwc3_wIndex_to_dep(dwc, wIndex);
 478                         if (!dep)
 479                                 return -EINVAL;
 480                         if (set == 0 && (dep->flags & DWC3_EP_WEDGE))
 481                                 break;
 482                         ret = __dwc3_gadget_ep_set_halt(dep, set, true);
 483                         if (ret)
 484                                 return -EINVAL;
 485                         break;
 486                 default:
 487                         return -EINVAL;
 488                 }
 489                 break;
 490
 491         default:
 492                 return -EINVAL;
 493         }
 494
 495         return 0;
 496 }
 497
 498 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 499 {
 500         enum usb_device_state state = dwc->gadget.state;
 501         u32 addr;
 502         u32 reg;
 503
 504         addr = le16_to_cpu(ctrl->wValue);
 505         if (addr > 127) {
 506                 dwc3_trace(trace_dwc3_ep0, "invalid device address %d", addr);
 507                 return -EINVAL;
 508         }
 509
 510         if (state == USB_STATE_CONFIGURED) {
 511                 dwc3_trace(trace_dwc3_ep0,
 512                                 "trying to set address when configured");
 513                 return -EINVAL;
 514         }
 515
 516         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
 517         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
 518         reg |= DWC3_DCFG_DEVADDR(addr);
 519         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
 520
 521         if (addr)
 522                 usb_gadget_set_state(&dwc->gadget, USB_STATE_ADDRESS);
 523         else
 524                 usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT);
 525
 526         return 0;
 527 }
 528
 529 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 530 {
 531         int ret;
 532
 533         spin_unlock(&dwc->lock);
 534         ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
 535         spin_lock(&dwc->lock);
 536         return ret;
 537 }
 538
 539 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 540 {
 541         enum usb_device_state state = dwc->gadget.state;
 542         u32 cfg;
 543         int ret;
 544         u32 reg;
 545
 546         dwc->start_config_issued = false;
 547         cfg = le16_to_cpu(ctrl->wValue);
 548
 549         switch (state) {
 550         case USB_STATE_DEFAULT:
 551                 return -EINVAL;
 552
 553         case USB_STATE_ADDRESS:
 554                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 555                 /* if the cfg matches and the cfg is non zero */
 556                 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
 557
 558                         /*
 559                          * only change state if set_config has already
 560                          * been processed. If gadget driver returns
 561                          * USB_GADGET_DELAYED_STATUS, we will wait
 562                          * to change the state on the next usb_ep_queue()
 563                          */
 564                         if (ret == 0)
 565                                 usb_gadget_set_state(&dwc->gadget,
 566                                                 USB_STATE_CONFIGURED);
 567
 568                         /*
 569                          * Enable transition to U1/U2 state when
 570                          * nothing is pending from application.
 571                          */
 572                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 573                         reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA);
 574                         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 575
 576                         dwc->resize_fifos = true;
 577                         dwc3_trace(trace_dwc3_ep0, "resize FIFOs flag SET");
 578                 }
 579                 break;
 580
 581         case USB_STATE_CONFIGURED:
 582                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 583                 if (!cfg && !ret)
 584                         usb_gadget_set_state(&dwc->gadget,
 585                                         USB_STATE_ADDRESS);
 586                 break;
 587         default:
 588                 ret = -EINVAL;
 589         }
 590         return ret;
 591 }
 592
 593 static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
 594 {
 595         struct dwc3_ep  *dep = to_dwc3_ep(ep);
 596         struct dwc3     *dwc = dep->dwc;
 597
 598         u32             param = 0;
 599         u32             reg;
 600
 601         struct timing {
 602                 u8      u1sel;
 603                 u8      u1pel;
 604                 u16     u2sel;
 605                 u16     u2pel;
 606         } __packed timing;
 607
 608         int             ret;
 609
 610         memcpy(&timing, req->buf, sizeof(timing));
 611
 612         dwc->u1sel = timing.u1sel;
 613         dwc->u1pel = timing.u1pel;
 614         dwc->u2sel = le16_to_cpu(timing.u2sel);
 615         dwc->u2pel = le16_to_cpu(timing.u2pel);
 616
 617         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 618         if (reg & DWC3_DCTL_INITU2ENA)
 619                 param = dwc->u2pel;
 620         if (reg & DWC3_DCTL_INITU1ENA)
 621                 param = dwc->u1pel;
 622
 623         /*
 624          * According to Synopsys Databook, if parameter is
 625          * greater than 125, a value of zero should be
 626          * programmed in the register.
 627          */
 628         if (param > 125)
 629                 param = 0;
 630
 631         /* now that we have the time, issue DGCMD Set Sel */
 632         ret = dwc3_send_gadget_generic_command(dwc,
 633                         DWC3_DGCMD_SET_PERIODIC_PAR, param);
 634         WARN_ON(ret < 0);
 635 }
 636
 637 static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 638 {
 639         struct dwc3_ep  *dep;
 640         enum usb_device_state state = dwc->gadget.state;
 641         u16             wLength;
 642         u16             wValue;
 643
 644         if (state == USB_STATE_DEFAULT)
 645                 return -EINVAL;
 646
 647         wValue = le16_to_cpu(ctrl->wValue);
 648         wLength = le16_to_cpu(ctrl->wLength);
 649
 650         if (wLength != 6) {
 651                 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
 652                                 wLength);
 653                 return -EINVAL;
 654         }
 655
 656         /*
 657          * To handle Set SEL we need to receive 6 bytes from Host. So let's
 658          * queue a usb_request for 6 bytes.
 659          *
 660          * Remember, though, this controller can't handle non-wMaxPacketSize
 661          * aligned transfers on the OUT direction, so we queue a request for
 662          * wMaxPacketSize instead.
 663          */
 664         dep = dwc->eps[0];
 665         dwc->ep0_usb_req.dep = dep;
 666         dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
 667         dwc->ep0_usb_req.request.buf = dwc->setup_buf;
 668         dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
 669
 670         return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
 671 }
 672
 673 static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 674 {
 675         u16             wLength;
 676         u16             wValue;
 677         u16             wIndex;
 678
 679         wValue = le16_to_cpu(ctrl->wValue);
 680         wLength = le16_to_cpu(ctrl->wLength);
 681         wIndex = le16_to_cpu(ctrl->wIndex);
 682
 683         if (wIndex || wLength)
 684                 return -EINVAL;
 685
 686         /*
 687          * REVISIT It's unclear from Databook what to do with this
 688          * value. For now, just cache it.
 689          */
 690         dwc->isoch_delay = wValue;
 691
 692         return 0;
 693 }
 694
 695 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 696 {
 697         int ret;
 698
 699         switch (ctrl->bRequest) {
 700         case USB_REQ_GET_STATUS:
 701                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_GET_STATUS");
 702                 ret = dwc3_ep0_handle_status(dwc, ctrl);
 703                 break;
 704         case USB_REQ_CLEAR_FEATURE:
 705                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_CLEAR_FEATURE");
 706                 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
 707                 break;
 708         case USB_REQ_SET_FEATURE:
 709                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_FEATURE");
 710                 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
 711                 break;
 712         case USB_REQ_SET_ADDRESS:
 713                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_ADDRESS");
 714                 ret = dwc3_ep0_set_address(dwc, ctrl);
 715                 break;
 716         case USB_REQ_SET_CONFIGURATION:
 717                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_CONFIGURATION");
 718                 ret = dwc3_ep0_set_config(dwc, ctrl);
 719                 break;
 720         case USB_REQ_SET_SEL:
 721                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_SEL");
 722                 ret = dwc3_ep0_set_sel(dwc, ctrl);
 723                 break;
 724         case USB_REQ_SET_ISOCH_DELAY:
 725                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_ISOCH_DELAY");
 726                 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
 727                 break;
 728         default:
 729                 dwc3_trace(trace_dwc3_ep0, "Forwarding to gadget driver");
 730                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 731                 break;
 732         }
 733
 734         return ret;
 735 }
 736
 737 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
 738                 const struct dwc3_event_depevt *event)
 739 {
 740         struct usb_ctrlrequest *ctrl = dwc->ctrl_req;
 741         int ret = -EINVAL;
 742         u32 len;
 743
 744         if (!dwc->gadget_driver)
 745                 goto out;
 746
 747         trace_dwc3_ctrl_req(ctrl);
 748
 749         len = le16_to_cpu(ctrl->wLength);
 750         if (!len) {
 751                 dwc->three_stage_setup = false;
 752                 dwc->ep0_expect_in = false;
 753                 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
 754         } else {
 755                 dwc->three_stage_setup = true;
 756                 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
 757                 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
 758         }
 759
 760         if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
 761                 ret = dwc3_ep0_std_request(dwc, ctrl);
 762         else
 763                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 764
 765         if (ret == USB_GADGET_DELAYED_STATUS)
 766                 dwc->delayed_status = true;
 767
 768 out:
 769         if (ret < 0)
 770                 dwc3_ep0_stall_and_restart(dwc);
 771 }
 772
 773 static void dwc3_ep0_complete_data(struct dwc3 *dwc,
 774                 const struct dwc3_event_depevt *event)
 775 {
 776         struct dwc3_request     *r = NULL;
 777         struct usb_request      *ur;
 778         struct dwc3_trb         *trb;
 779         struct dwc3_ep          *ep0;
 780         u32                     transferred;
 781         u32                     status;
 782         u32                     length;
 783         u8                      epnum;
 784
 785         epnum = event->endpoint_number;
 786         ep0 = dwc->eps[0];
 787
 788         dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
 789
 790         trb = dwc->ep0_trb;
 791
 792         trace_dwc3_complete_trb(ep0, trb);
 793
 794         r = next_request(&ep0->request_list);
 795         if (!r)
 796                 return;
 797
 798         status = DWC3_TRB_SIZE_TRBSTS(trb->size);
 799         if (status == DWC3_TRBSTS_SETUP_PENDING) {
 800                 dwc3_trace(trace_dwc3_ep0, "Setup Pending received");
 801
 802                 if (r)
 803                         dwc3_gadget_giveback(ep0, r, -ECONNRESET);
 804
 805                 return;
 806         }
 807
 808         ur = &r->request;
 809
 810         length = trb->size & DWC3_TRB_SIZE_MASK;
 811
 812         if (dwc->ep0_bounced) {
 813                 unsigned transfer_size = ur->length;
 814                 unsigned maxp = ep0->endpoint.maxpacket;
 815
 816                 transfer_size += (maxp - (transfer_size % maxp));
 817                 transferred = min_t(u32, ur->length,
 818                                 transfer_size - length);
 819                 memcpy(ur->buf, dwc->ep0_bounce, transferred);
 820         } else {
 821                 transferred = ur->length - length;
 822         }
 823
 824         ur->actual += transferred;
 825
 826         if ((epnum & 1) && ur->actual < ur->length) {
 827                 /* for some reason we did not get everything out */
 828
 829                 dwc3_ep0_stall_and_restart(dwc);
 830         } else {
 831                 dwc3_gadget_giveback(ep0, r, 0);
 832
 833                 if (IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) &&
 834                                 ur->length && ur->zero) {
 835                         int ret;
 836
 837                         dwc->ep0_next_event = DWC3_EP0_COMPLETE;
 838
 839                         ret = dwc3_ep0_start_trans(dwc, epnum,
 840                                         dwc->ctrl_req_addr, 0,
 841                                         DWC3_TRBCTL_CONTROL_DATA);
 842                         WARN_ON(ret < 0);
 843                 }
 844         }
 845 }
 846
 847 static void dwc3_ep0_complete_status(struct dwc3 *dwc,
 848                 const struct dwc3_event_depevt *event)
 849 {
 850         struct dwc3_request     *r;
 851         struct dwc3_ep          *dep;
 852         struct dwc3_trb         *trb;
 853         u32                     status;
 854
 855         dep = dwc->eps[0];
 856         trb = dwc->ep0_trb;
 857
 858         trace_dwc3_complete_trb(dep, trb);
 859
 860         if (!list_empty(&dep->request_list)) {
 861                 r = next_request(&dep->request_list);
 862
 863                 dwc3_gadget_giveback(dep, r, 0);
 864         }
 865
 866         if (dwc->test_mode) {
 867                 int ret;
 868
 869                 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
 870                 if (ret < 0) {
 871                         dwc3_trace(trace_dwc3_ep0, "Invalid Test #%d",
 872                                         dwc->test_mode_nr);
 873                         dwc3_ep0_stall_and_restart(dwc);
 874                         return;
 875                 }
 876         }
 877
 878         status = DWC3_TRB_SIZE_TRBSTS(trb->size);
 879         if (status == DWC3_TRBSTS_SETUP_PENDING)
 880                 dwc3_trace(trace_dwc3_ep0, "Setup Pending received");
 881
 882         dwc->ep0state = EP0_SETUP_PHASE;
 883         dwc3_ep0_out_start(dwc);
 884 }
 885
 886 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
 887                         const struct dwc3_event_depevt *event)
 888 {
 889         struct dwc3_ep          *dep = dwc->eps[event->endpoint_number];
 890
 891         dep->flags &= ~DWC3_EP_BUSY;
 892         dep->resource_index = 0;
 893         dwc->setup_packet_pending = false;
 894
 895         switch (dwc->ep0state) {
 896         case EP0_SETUP_PHASE:
 897                 dwc3_trace(trace_dwc3_ep0, "Setup Phase");
 898                 dwc3_ep0_inspect_setup(dwc, event);
 899                 break;
 900
 901         case EP0_DATA_PHASE:
 902                 dwc3_trace(trace_dwc3_ep0, "Data Phase");
 903                 dwc3_ep0_complete_data(dwc, event);
 904                 break;
 905
 906         case EP0_STATUS_PHASE:
 907                 dwc3_trace(trace_dwc3_ep0, "Status Phase");
 908                 dwc3_ep0_complete_status(dwc, event);
 909                 break;
 910         default:
 911                 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
 912         }
 913 }
 914
 915 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
 916                 struct dwc3_ep *dep, struct dwc3_request *req)
 917 {
 918         int                     ret;
 919
 920         req->direction = !!dep->number;
 921
 922         if (req->request.length == 0) {
 923                 ret = dwc3_ep0_start_trans(dwc, dep->number,
 924                                 dwc->ctrl_req_addr, 0,
 925                                 DWC3_TRBCTL_CONTROL_DATA);
 926         } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket)
 927                         && (dep->number == 0)) {
 928                 u32     transfer_size;
 929                 u32     maxpacket;
 930
 931                 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
 932                                 dep->number);
 933                 if (ret) {
 934                         dev_dbg(dwc->dev, "failed to map request\n");
 935                         return;
 936                 }
 937
 938                 WARN_ON(req->request.length > DWC3_EP0_BOUNCE_SIZE);
 939
 940                 maxpacket = dep->endpoint.maxpacket;
 941                 transfer_size = roundup(req->request.length, maxpacket);
 942
 943                 dwc->ep0_bounced = true;
 944
 945                 /*
 946                  * REVISIT in case request length is bigger than
 947                  * DWC3_EP0_BOUNCE_SIZE we will need two chained
 948                  * TRBs to handle the transfer.
 949                  */
 950                 ret = dwc3_ep0_start_trans(dwc, dep->number,
 951                                 dwc->ep0_bounce_addr, transfer_size,
 952                                 DWC3_TRBCTL_CONTROL_DATA);
 953         } else {
 954                 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
 955                                 dep->number);
 956                 if (ret) {
 957                         dev_dbg(dwc->dev, "failed to map request\n");
 958                         return;
 959                 }
 960
 961                 ret = dwc3_ep0_start_trans(dwc, dep->number, req->request.dma,
 962                                 req->request.length, DWC3_TRBCTL_CONTROL_DATA);
 963         }
 964
 965         WARN_ON(ret < 0);
 966 }
 967
 968 static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
 969 {
 970         struct dwc3             *dwc = dep->dwc;
 971         u32                     type;
 972
 973         type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
 974                 : DWC3_TRBCTL_CONTROL_STATUS2;
 975
 976         return dwc3_ep0_start_trans(dwc, dep->number,
 977                         dwc->ctrl_req_addr, 0, type);
 978 }
 979
 980 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
 981 {
 982         if (dwc->resize_fifos) {
 983                 dwc3_trace(trace_dwc3_ep0, "Resizing FIFOs");
 984                 dwc3_gadget_resize_tx_fifos(dwc);
 985                 dwc->resize_fifos = 0;
 986         }
 987
 988         WARN_ON(dwc3_ep0_start_control_status(dep));
 989 }
 990
 991 static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
 992                 const struct dwc3_event_depevt *event)
 993 {
 994         struct dwc3_ep          *dep = dwc->eps[event->endpoint_number];
 995
 996         __dwc3_ep0_do_control_status(dwc, dep);
 997 }
 998
 999 static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
1000 {
1001         struct dwc3_gadget_ep_cmd_params params;
1002         u32                     cmd;
1003         int                     ret;
1004
1005         if (!dep->resource_index)
1006                 return;
1007
1008         cmd = DWC3_DEPCMD_ENDTRANSFER;
1009         cmd |= DWC3_DEPCMD_CMDIOC;
1010         cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1011         memset(&params, 0, sizeof(params));
1012         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
1013         WARN_ON_ONCE(ret);
1014         dep->resource_index = 0;
1015 }
1016
1017 static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
1018                 const struct dwc3_event_depevt *event)
1019 {
1020         dwc->setup_packet_pending = true;
1021
1022         switch (event->status) {
1023         case DEPEVT_STATUS_CONTROL_DATA:
1024                 dwc3_trace(trace_dwc3_ep0, "Control Data");
1025
1026                 /*
1027                  * We already have a DATA transfer in the controller's cache,
1028                  * if we receive a XferNotReady(DATA) we will ignore it, unless
1029                  * it's for the wrong direction.
1030                  *
1031                  * In that case, we must issue END_TRANSFER command to the Data
1032                  * Phase we already have started and issue SetStall on the
1033                  * control endpoint.
1034                  */
1035                 if (dwc->ep0_expect_in != event->endpoint_number) {
1036                         struct dwc3_ep  *dep = dwc->eps[dwc->ep0_expect_in];
1037
1038                         dwc3_trace(trace_dwc3_ep0,
1039                                         "Wrong direction for Data phase");
1040                         dwc3_ep0_end_control_data(dwc, dep);
1041                         dwc3_ep0_stall_and_restart(dwc);
1042                         return;
1043                 }
1044
1045                 break;
1046
1047         case DEPEVT_STATUS_CONTROL_STATUS:
1048                 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
1049                         return;
1050
1051                 dwc3_trace(trace_dwc3_ep0, "Control Status");
1052
1053                 dwc->ep0state = EP0_STATUS_PHASE;
1054
1055                 if (dwc->delayed_status) {
1056                         WARN_ON_ONCE(event->endpoint_number != 1);
1057                         dwc3_trace(trace_dwc3_ep0, "Delayed Status");
1058                         return;
1059                 }
1060
1061                 dwc3_ep0_do_control_status(dwc, event);
1062         }
1063 }
1064
1065 void dwc3_ep0_interrupt(struct dwc3 *dwc,
1066                 const struct dwc3_event_depevt *event)
1067 {
1068         u8                      epnum = event->endpoint_number;
1069
1070         dwc3_trace(trace_dwc3_ep0, "%s while ep%d%s in state '%s'",
1071                         dwc3_ep_event_string(event->endpoint_event),
1072                         epnum >> 1, (epnum & 1) ? "in" : "out",
1073                         dwc3_ep0_state_string(dwc->ep0state));
1074
1075         switch (event->endpoint_event) {
1076         case DWC3_DEPEVT_XFERCOMPLETE:
1077                 dwc3_ep0_xfer_complete(dwc, event);
1078                 break;
1079
1080         case DWC3_DEPEVT_XFERNOTREADY:
1081                 dwc3_ep0_xfernotready(dwc, event);
1082                 break;
1083
1084         case DWC3_DEPEVT_XFERINPROGRESS:
1085         case DWC3_DEPEVT_RXTXFIFOEVT:
1086         case DWC3_DEPEVT_STREAMEVT:
1087         case DWC3_DEPEVT_EPCMDCMPLT:
1088                 break;
1089         }
1090 }