drivers/usb/dwc3/ep0.c

   1 /**
   2  * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * This program is free software: you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2  of
  11  * the License as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/slab.h>
  21 #include <linux/spinlock.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/pm_runtime.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/io.h>
  26 #include <linux/list.h>
  27 #include <linux/dma-mapping.h>
  28
  29 #include <linux/usb/ch9.h>
  30 #include <linux/usb/gadget.h>
  31 #include <linux/usb/composite.h>
  32
  33 #include "core.h"
  34 #include "debug.h"
  35 #include "gadget.h"
  36 #include "io.h"
  37
  38 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
  39 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
  40                 struct dwc3_ep *dep, struct dwc3_request *req);
  41
  42 static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
  43 {
  44         switch (state) {
  45         case EP0_UNCONNECTED:
  46                 return "Unconnected";
  47         case EP0_SETUP_PHASE:
  48                 return "Setup Phase";
  49         case EP0_DATA_PHASE:
  50                 return "Data Phase";
  51         case EP0_STATUS_PHASE:
  52                 return "Status Phase";
  53         default:
  54                 return "UNKNOWN";
  55         }
  56 }
  57
  58 static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
  59                 u32 len, u32 type, bool chain)
  60 {
  61         struct dwc3_gadget_ep_cmd_params params;
  62         struct dwc3_trb                 *trb;
  63         struct dwc3_ep                  *dep;
  64
  65         int                             ret;
  66
  67         dep = dwc->eps[epnum];
  68         if (dep->flags & DWC3_EP_BUSY) {
  69                 dwc3_trace(trace_dwc3_ep0, "%s still busy", dep->name);
  70                 return 0;
  71         }
  72
  73         trb = &dwc->ep0_trb[dep->trb_enqueue];
  74
  75         if (chain)
  76                 dep->trb_enqueue++;
  77
  78         trb->bpl = lower_32_bits(buf_dma);
  79         trb->bph = upper_32_bits(buf_dma);
  80         trb->size = len;
  81         trb->ctrl = type;
  82
  83         trb->ctrl |= (DWC3_TRB_CTRL_HWO
  84                         | DWC3_TRB_CTRL_ISP_IMI);
  85
  86         if (chain)
  87                 trb->ctrl |= DWC3_TRB_CTRL_CHN;
  88         else
  89                 trb->ctrl |= (DWC3_TRB_CTRL_IOC
  90                                 | DWC3_TRB_CTRL_LST);
  91
  92         if (chain)
  93                 return 0;
  94
  95         memset(&params, 0, sizeof(params));
  96         params.param0 = upper_32_bits(dwc->ep0_trb_addr);
  97         params.param1 = lower_32_bits(dwc->ep0_trb_addr);
  98
  99         trace_dwc3_prepare_trb(dep, trb);
 100
 101         ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_STARTTRANSFER, &params);
 102         if (ret < 0) {
 103                 dwc3_trace(trace_dwc3_ep0, "%s STARTTRANSFER failed",
 104                                 dep->name);
 105                 return ret;
 106         }
 107
 108         dep->flags |= DWC3_EP_BUSY;
 109         dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
 110                         dep->number);
 111
 112         dwc->ep0_next_event = DWC3_EP0_COMPLETE;
 113
 114         return 0;
 115 }
 116
 117 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
 118                 struct dwc3_request *req)
 119 {
 120         struct dwc3             *dwc = dep->dwc;
 121
 122         req->request.actual     = 0;
 123         req->request.status     = -EINPROGRESS;
 124         req->epnum              = dep->number;
 125
 126         list_add_tail(&req->list, &dep->pending_list);
 127
 128         /*
 129          * Gadget driver might not be quick enough to queue a request
 130          * before we get a Transfer Not Ready event on this endpoint.
 131          *
 132          * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
 133          * flag is set, it's telling us that as soon as Gadget queues the
 134          * required request, we should kick the transfer here because the
 135          * IRQ we were waiting for is long gone.
 136          */
 137         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
 138                 unsigned        direction;
 139
 140                 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
 141
 142                 if (dwc->ep0state != EP0_DATA_PHASE) {
 143                         dev_WARN(dwc->dev, "Unexpected pending request\n");
 144                         return 0;
 145                 }
 146
 147                 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
 148
 149                 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
 150                                 DWC3_EP0_DIR_IN);
 151
 152                 return 0;
 153         }
 154
 155         /*
 156          * In case gadget driver asked us to delay the STATUS phase,
 157          * handle it here.
 158          */
 159         if (dwc->delayed_status) {
 160                 unsigned        direction;
 161
 162                 direction = !dwc->ep0_expect_in;
 163                 dwc->delayed_status = false;
 164                 usb_gadget_set_state(&dwc->gadget, USB_STATE_CONFIGURED);
 165
 166                 if (dwc->ep0state == EP0_STATUS_PHASE)
 167                         __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
 168                 else
 169                         dwc3_trace(trace_dwc3_ep0,
 170                                         "too early for delayed status");
 171
 172                 return 0;
 173         }
 174
 175         /*
 176          * Unfortunately we have uncovered a limitation wrt the Data Phase.
 177          *
 178          * Section 9.4 says we can wait for the XferNotReady(DATA) event to
 179          * come before issueing Start Transfer command, but if we do, we will
 180          * miss situations where the host starts another SETUP phase instead of
 181          * the DATA phase.  Such cases happen at least on TD.7.6 of the Link
 182          * Layer Compliance Suite.
 183          *
 184          * The problem surfaces due to the fact that in case of back-to-back
 185          * SETUP packets there will be no XferNotReady(DATA) generated and we
 186          * will be stuck waiting for XferNotReady(DATA) forever.
 187          *
 188          * By looking at tables 9-13 and 9-14 of the Databook, we can see that
 189          * it tells us to start Data Phase right away. It also mentions that if
 190          * we receive a SETUP phase instead of the DATA phase, core will issue
 191          * XferComplete for the DATA phase, before actually initiating it in
 192          * the wire, with the TRB's status set to "SETUP_PENDING". Such status
 193          * can only be used to print some debugging logs, as the core expects
 194          * us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
 195          * just so it completes right away, without transferring anything and,
 196          * only then, we can go back to the SETUP phase.
 197          *
 198          * Because of this scenario, SNPS decided to change the programming
 199          * model of control transfers and support on-demand transfers only for
 200          * the STATUS phase. To fix the issue we have now, we will always wait
 201          * for gadget driver to queue the DATA phase's struct usb_request, then
 202          * start it right away.
 203          *
 204          * If we're actually in a 2-stage transfer, we will wait for
 205          * XferNotReady(STATUS).
 206          */
 207         if (dwc->three_stage_setup) {
 208                 unsigned        direction;
 209
 210                 direction = dwc->ep0_expect_in;
 211                 dwc->ep0state = EP0_DATA_PHASE;
 212
 213                 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
 214
 215                 dep->flags &= ~DWC3_EP0_DIR_IN;
 216         }
 217
 218         return 0;
 219 }
 220
 221 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
 222                 gfp_t gfp_flags)
 223 {
 224         struct dwc3_request             *req = to_dwc3_request(request);
 225         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 226         struct dwc3                     *dwc = dep->dwc;
 227
 228         unsigned long                   flags;
 229
 230         int                             ret;
 231
 232         spin_lock_irqsave(&dwc->lock, flags);
 233         if (!dep->endpoint.desc) {
 234                 dwc3_trace(trace_dwc3_ep0,
 235                                 "trying to queue request %p to disabled %s",
 236                                 request, dep->name);
 237                 ret = -ESHUTDOWN;
 238                 goto out;
 239         }
 240
 241         /* we share one TRB for ep0/1 */
 242         if (!list_empty(&dep->pending_list)) {
 243                 ret = -EBUSY;
 244                 goto out;
 245         }
 246
 247         dwc3_trace(trace_dwc3_ep0,
 248                         "queueing request %p to %s length %d state '%s'",
 249                         request, dep->name, request->length,
 250                         dwc3_ep0_state_string(dwc->ep0state));
 251
 252         ret = __dwc3_gadget_ep0_queue(dep, req);
 253
 254 out:
 255         spin_unlock_irqrestore(&dwc->lock, flags);
 256
 257         return ret;
 258 }
 259
 260 static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
 261 {
 262         struct dwc3_ep          *dep;
 263
 264         /* reinitialize physical ep1 */
 265         dep = dwc->eps[1];
 266         dep->flags = DWC3_EP_ENABLED;
 267
 268         /* stall is always issued on EP0 */
 269         dep = dwc->eps[0];
 270         __dwc3_gadget_ep_set_halt(dep, 1, false);
 271         dep->flags = DWC3_EP_ENABLED;
 272         dwc->delayed_status = false;
 273
 274         if (!list_empty(&dep->pending_list)) {
 275                 struct dwc3_request     *req;
 276
 277                 req = next_request(&dep->pending_list);
 278                 dwc3_gadget_giveback(dep, req, -ECONNRESET);
 279         }
 280
 281         dwc->ep0state = EP0_SETUP_PHASE;
 282         dwc3_ep0_out_start(dwc);
 283 }
 284
 285 int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
 286 {
 287         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 288         struct dwc3                     *dwc = dep->dwc;
 289
 290         dwc3_ep0_stall_and_restart(dwc);
 291
 292         return 0;
 293 }
 294
 295 int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
 296 {
 297         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 298         struct dwc3                     *dwc = dep->dwc;
 299         unsigned long                   flags;
 300         int                             ret;
 301
 302         spin_lock_irqsave(&dwc->lock, flags);
 303         ret = __dwc3_gadget_ep0_set_halt(ep, value);
 304         spin_unlock_irqrestore(&dwc->lock, flags);
 305
 306         return ret;
 307 }
 308
 309 void dwc3_ep0_out_start(struct dwc3 *dwc)
 310 {
 311         int                             ret;
 312
 313         ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8,
 314                         DWC3_TRBCTL_CONTROL_SETUP, false);
 315         WARN_ON(ret < 0);
 316 }
 317
 318 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
 319 {
 320         struct dwc3_ep          *dep;
 321         u32                     windex = le16_to_cpu(wIndex_le);
 322         u32                     epnum;
 323
 324         epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
 325         if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
 326                 epnum |= 1;
 327
 328         dep = dwc->eps[epnum];
 329         if (dep->flags & DWC3_EP_ENABLED)
 330                 return dep;
 331
 332         return NULL;
 333 }
 334
 335 static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
 336 {
 337 }
 338 /*
 339  * ch 9.4.5
 340  */
 341 static int dwc3_ep0_handle_status(struct dwc3 *dwc,
 342                 struct usb_ctrlrequest *ctrl)
 343 {
 344         struct dwc3_ep          *dep;
 345         u32                     recip;
 346         u32                     reg;
 347         u16                     usb_status = 0;
 348         __le16                  *response_pkt;
 349
 350         recip = ctrl->bRequestType & USB_RECIP_MASK;
 351         switch (recip) {
 352         case USB_RECIP_DEVICE:
 353                 /*
 354                  * LTM will be set once we know how to set this in HW.
 355                  */
 356                 usb_status |= dwc->gadget.is_selfpowered;
 357
 358                 if ((dwc->speed == DWC3_DSTS_SUPERSPEED) ||
 359                     (dwc->speed == DWC3_DSTS_SUPERSPEED_PLUS)) {
 360                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 361                         if (reg & DWC3_DCTL_INITU1ENA)
 362                                 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
 363                         if (reg & DWC3_DCTL_INITU2ENA)
 364                                 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
 365                 }
 366
 367                 break;
 368
 369         case USB_RECIP_INTERFACE:
 370                 /*
 371                  * Function Remote Wake Capable D0
 372                  * Function Remote Wakeup       D1
 373                  */
 374                 break;
 375
 376         case USB_RECIP_ENDPOINT:
 377                 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
 378                 if (!dep)
 379                         return -EINVAL;
 380
 381                 if (dep->flags & DWC3_EP_STALL)
 382                         usb_status = 1 << USB_ENDPOINT_HALT;
 383                 break;
 384         default:
 385                 return -EINVAL;
 386         }
 387
 388         response_pkt = (__le16 *) dwc->setup_buf;
 389         *response_pkt = cpu_to_le16(usb_status);
 390
 391         dep = dwc->eps[0];
 392         dwc->ep0_usb_req.dep = dep;
 393         dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
 394         dwc->ep0_usb_req.request.buf = dwc->setup_buf;
 395         dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
 396
 397         return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
 398 }
 399
 400 static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
 401                 struct usb_ctrlrequest *ctrl, int set)
 402 {
 403         struct dwc3_ep          *dep;
 404         u32                     recip;
 405         u32                     wValue;
 406         u32                     wIndex;
 407         u32                     reg;
 408         int                     ret;
 409         enum usb_device_state   state;
 410
 411         wValue = le16_to_cpu(ctrl->wValue);
 412         wIndex = le16_to_cpu(ctrl->wIndex);
 413         recip = ctrl->bRequestType & USB_RECIP_MASK;
 414         state = dwc->gadget.state;
 415
 416         switch (recip) {
 417         case USB_RECIP_DEVICE:
 418
 419                 switch (wValue) {
 420                 case USB_DEVICE_REMOTE_WAKEUP:
 421                         break;
 422                 /*
 423                  * 9.4.1 says only only for SS, in AddressState only for
 424                  * default control pipe
 425                  */
 426                 case USB_DEVICE_U1_ENABLE:
 427                         if (state != USB_STATE_CONFIGURED)
 428                                 return -EINVAL;
 429                         if ((dwc->speed != DWC3_DSTS_SUPERSPEED) &&
 430                             (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))
 431                                 return -EINVAL;
 432
 433                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 434                         if (set)
 435                                 reg |= DWC3_DCTL_INITU1ENA;
 436                         else
 437                                 reg &= ~DWC3_DCTL_INITU1ENA;
 438                         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 439                         break;
 440
 441                 case USB_DEVICE_U2_ENABLE:
 442                         if (state != USB_STATE_CONFIGURED)
 443                                 return -EINVAL;
 444                         if ((dwc->speed != DWC3_DSTS_SUPERSPEED) &&
 445                             (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))
 446                                 return -EINVAL;
 447
 448                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 449                         if (set)
 450                                 reg |= DWC3_DCTL_INITU2ENA;
 451                         else
 452                                 reg &= ~DWC3_DCTL_INITU2ENA;
 453                         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 454                         break;
 455
 456                 case USB_DEVICE_LTM_ENABLE:
 457                         return -EINVAL;
 458
 459                 case USB_DEVICE_TEST_MODE:
 460                         if ((wIndex & 0xff) != 0)
 461                                 return -EINVAL;
 462                         if (!set)
 463                                 return -EINVAL;
 464
 465                         switch (wIndex >> 8) {
 466                         case TEST_J:
 467                         case TEST_K:
 468                         case TEST_SE0_NAK:
 469                         case TEST_PACKET:
 470                         case TEST_FORCE_EN:
 471                                 dwc->test_mode_nr = wIndex >> 8;
 472                                 dwc->test_mode = true;
 473                                 break;
 474                         default:
 475                                 return -EINVAL;
 476                         }
 477                         break;
 478                 default:
 479                         return -EINVAL;
 480                 }
 481                 break;
 482
 483         case USB_RECIP_INTERFACE:
 484                 switch (wValue) {
 485                 case USB_INTRF_FUNC_SUSPEND:
 486                         if (wIndex & USB_INTRF_FUNC_SUSPEND_LP)
 487                                 /* XXX enable Low power suspend */
 488                                 ;
 489                         if (wIndex & USB_INTRF_FUNC_SUSPEND_RW)
 490                                 /* XXX enable remote wakeup */
 491                                 ;
 492                         break;
 493                 default:
 494                         return -EINVAL;
 495                 }
 496                 break;
 497
 498         case USB_RECIP_ENDPOINT:
 499                 switch (wValue) {
 500                 case USB_ENDPOINT_HALT:
 501                         dep = dwc3_wIndex_to_dep(dwc, wIndex);
 502                         if (!dep)
 503                                 return -EINVAL;
 504                         if (set == 0 && (dep->flags & DWC3_EP_WEDGE))
 505                                 break;
 506                         ret = __dwc3_gadget_ep_set_halt(dep, set, true);
 507                         if (ret)
 508                                 return -EINVAL;
 509                         break;
 510                 default:
 511                         return -EINVAL;
 512                 }
 513                 break;
 514
 515         default:
 516                 return -EINVAL;
 517         }
 518
 519         return 0;
 520 }
 521
 522 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 523 {
 524         enum usb_device_state state = dwc->gadget.state;
 525         u32 addr;
 526         u32 reg;
 527
 528         addr = le16_to_cpu(ctrl->wValue);
 529         if (addr > 127) {
 530                 dwc3_trace(trace_dwc3_ep0, "invalid device address %d", addr);
 531                 return -EINVAL;
 532         }
 533
 534         if (state == USB_STATE_CONFIGURED) {
 535                 dwc3_trace(trace_dwc3_ep0,
 536                                 "trying to set address when configured");
 537                 return -EINVAL;
 538         }
 539
 540         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
 541         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
 542         reg |= DWC3_DCFG_DEVADDR(addr);
 543         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
 544
 545         if (addr)
 546                 usb_gadget_set_state(&dwc->gadget, USB_STATE_ADDRESS);
 547         else
 548                 usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT);
 549
 550         return 0;
 551 }
 552
 553 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 554 {
 555         int ret;
 556
 557         spin_unlock(&dwc->lock);
 558         ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
 559         spin_lock(&dwc->lock);
 560         return ret;
 561 }
 562
 563 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 564 {
 565         enum usb_device_state state = dwc->gadget.state;
 566         u32 cfg;
 567         int ret;
 568         u32 reg;
 569
 570         cfg = le16_to_cpu(ctrl->wValue);
 571
 572         switch (state) {
 573         case USB_STATE_DEFAULT:
 574                 return -EINVAL;
 575
 576         case USB_STATE_ADDRESS:
 577                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 578                 /* if the cfg matches and the cfg is non zero */
 579                 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
 580
 581                         /*
 582                          * only change state if set_config has already
 583                          * been processed. If gadget driver returns
 584                          * USB_GADGET_DELAYED_STATUS, we will wait
 585                          * to change the state on the next usb_ep_queue()
 586                          */
 587                         if (ret == 0)
 588                                 usb_gadget_set_state(&dwc->gadget,
 589                                                 USB_STATE_CONFIGURED);
 590
 591                         /*
 592                          * Enable transition to U1/U2 state when
 593                          * nothing is pending from application.
 594                          */
 595                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 596                         reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA);
 597                         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 598                 }
 599                 break;
 600
 601         case USB_STATE_CONFIGURED:
 602                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 603                 if (!cfg && !ret)
 604                         usb_gadget_set_state(&dwc->gadget,
 605                                         USB_STATE_ADDRESS);
 606                 break;
 607         default:
 608                 ret = -EINVAL;
 609         }
 610         return ret;
 611 }
 612
 613 static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
 614 {
 615         struct dwc3_ep  *dep = to_dwc3_ep(ep);
 616         struct dwc3     *dwc = dep->dwc;
 617
 618         u32             param = 0;
 619         u32             reg;
 620
 621         struct timing {
 622                 u8      u1sel;
 623                 u8      u1pel;
 624                 u16     u2sel;
 625                 u16     u2pel;
 626         } __packed timing;
 627
 628         int             ret;
 629
 630         memcpy(&timing, req->buf, sizeof(timing));
 631
 632         dwc->u1sel = timing.u1sel;
 633         dwc->u1pel = timing.u1pel;
 634         dwc->u2sel = le16_to_cpu(timing.u2sel);
 635         dwc->u2pel = le16_to_cpu(timing.u2pel);
 636
 637         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 638         if (reg & DWC3_DCTL_INITU2ENA)
 639                 param = dwc->u2pel;
 640         if (reg & DWC3_DCTL_INITU1ENA)
 641                 param = dwc->u1pel;
 642
 643         /*
 644          * According to Synopsys Databook, if parameter is
 645          * greater than 125, a value of zero should be
 646          * programmed in the register.
 647          */
 648         if (param > 125)
 649                 param = 0;
 650
 651         /* now that we have the time, issue DGCMD Set Sel */
 652         ret = dwc3_send_gadget_generic_command(dwc,
 653                         DWC3_DGCMD_SET_PERIODIC_PAR, param);
 654         WARN_ON(ret < 0);
 655 }
 656
 657 static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 658 {
 659         struct dwc3_ep  *dep;
 660         enum usb_device_state state = dwc->gadget.state;
 661         u16             wLength;
 662         u16             wValue;
 663
 664         if (state == USB_STATE_DEFAULT)
 665                 return -EINVAL;
 666
 667         wValue = le16_to_cpu(ctrl->wValue);
 668         wLength = le16_to_cpu(ctrl->wLength);
 669
 670         if (wLength != 6) {
 671                 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
 672                                 wLength);
 673                 return -EINVAL;
 674         }
 675
 676         /*
 677          * To handle Set SEL we need to receive 6 bytes from Host. So let's
 678          * queue a usb_request for 6 bytes.
 679          *
 680          * Remember, though, this controller can't handle non-wMaxPacketSize
 681          * aligned transfers on the OUT direction, so we queue a request for
 682          * wMaxPacketSize instead.
 683          */
 684         dep = dwc->eps[0];
 685         dwc->ep0_usb_req.dep = dep;
 686         dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
 687         dwc->ep0_usb_req.request.buf = dwc->setup_buf;
 688         dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
 689
 690         return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
 691 }
 692
 693 static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 694 {
 695         u16             wLength;
 696         u16             wValue;
 697         u16             wIndex;
 698
 699         wValue = le16_to_cpu(ctrl->wValue);
 700         wLength = le16_to_cpu(ctrl->wLength);
 701         wIndex = le16_to_cpu(ctrl->wIndex);
 702
 703         if (wIndex || wLength)
 704                 return -EINVAL;
 705
 706         /*
 707          * REVISIT It's unclear from Databook what to do with this
 708          * value. For now, just cache it.
 709          */
 710         dwc->isoch_delay = wValue;
 711
 712         return 0;
 713 }
 714
 715 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 716 {
 717         int ret;
 718
 719         switch (ctrl->bRequest) {
 720         case USB_REQ_GET_STATUS:
 721                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_GET_STATUS");
 722                 ret = dwc3_ep0_handle_status(dwc, ctrl);
 723                 break;
 724         case USB_REQ_CLEAR_FEATURE:
 725                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_CLEAR_FEATURE");
 726                 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
 727                 break;
 728         case USB_REQ_SET_FEATURE:
 729                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_FEATURE");
 730                 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
 731                 break;
 732         case USB_REQ_SET_ADDRESS:
 733                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_ADDRESS");
 734                 ret = dwc3_ep0_set_address(dwc, ctrl);
 735                 break;
 736         case USB_REQ_SET_CONFIGURATION:
 737                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_CONFIGURATION");
 738                 ret = dwc3_ep0_set_config(dwc, ctrl);
 739                 break;
 740         case USB_REQ_SET_SEL:
 741                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_SEL");
 742                 ret = dwc3_ep0_set_sel(dwc, ctrl);
 743                 break;
 744         case USB_REQ_SET_ISOCH_DELAY:
 745                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_ISOCH_DELAY");
 746                 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
 747                 break;
 748         default:
 749                 dwc3_trace(trace_dwc3_ep0, "Forwarding to gadget driver");
 750                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 751                 break;
 752         }
 753
 754         return ret;
 755 }
 756
 757 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
 758                 const struct dwc3_event_depevt *event)
 759 {
 760         struct usb_ctrlrequest *ctrl = dwc->ctrl_req;
 761         int ret = -EINVAL;
 762         u32 len;
 763
 764         if (!dwc->gadget_driver)
 765                 goto out;
 766
 767         trace_dwc3_ctrl_req(ctrl);
 768
 769         len = le16_to_cpu(ctrl->wLength);
 770         if (!len) {
 771                 dwc->three_stage_setup = false;
 772                 dwc->ep0_expect_in = false;
 773                 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
 774         } else {
 775                 dwc->three_stage_setup = true;
 776                 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
 777                 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
 778         }
 779
 780         if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
 781                 ret = dwc3_ep0_std_request(dwc, ctrl);
 782         else
 783                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 784
 785         if (ret == USB_GADGET_DELAYED_STATUS)
 786                 dwc->delayed_status = true;
 787
 788 out:
 789         if (ret < 0)
 790                 dwc3_ep0_stall_and_restart(dwc);
 791 }
 792
 793 static void dwc3_ep0_complete_data(struct dwc3 *dwc,
 794                 const struct dwc3_event_depevt *event)
 795 {
 796         struct dwc3_request     *r = NULL;
 797         struct usb_request      *ur;
 798         struct dwc3_trb         *trb;
 799         struct dwc3_ep          *ep0;
 800         unsigned                transfer_size = 0;
 801         unsigned                maxp;
 802         unsigned                remaining_ur_length;
 803         void                    *buf;
 804         u32                     transferred = 0;
 805         u32                     status;
 806         u32                     length;
 807         u8                      epnum;
 808
 809         epnum = event->endpoint_number;
 810         ep0 = dwc->eps[0];
 811
 812         dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
 813
 814         trb = dwc->ep0_trb;
 815
 816         trace_dwc3_complete_trb(ep0, trb);
 817
 818         r = next_request(&ep0->pending_list);
 819         if (!r)
 820                 return;
 821
 822         status = DWC3_TRB_SIZE_TRBSTS(trb->size);
 823         if (status == DWC3_TRBSTS_SETUP_PENDING) {
 824                 dwc->setup_packet_pending = true;
 825
 826                 dwc3_trace(trace_dwc3_ep0, "Setup Pending received");
 827
 828                 if (r)
 829                         dwc3_gadget_giveback(ep0, r, -ECONNRESET);
 830
 831                 return;
 832         }
 833
 834         ur = &r->request;
 835         buf = ur->buf;
 836         remaining_ur_length = ur->length;
 837
 838         length = trb->size & DWC3_TRB_SIZE_MASK;
 839
 840         maxp = ep0->endpoint.maxpacket;
 841
 842         if (dwc->ep0_bounced) {
 843                 /*
 844                  * Handle the first TRB before handling the bounce buffer if
 845                  * the request length is greater than the bounce buffer size
 846                  */
 847                 if (ur->length > DWC3_EP0_BOUNCE_SIZE) {
 848                         transfer_size = ALIGN(ur->length - maxp, maxp);
 849                         transferred = transfer_size - length;
 850                         buf = (u8 *)buf + transferred;
 851                         ur->actual += transferred;
 852                         remaining_ur_length -= transferred;
 853
 854                         trb++;
 855                         length = trb->size & DWC3_TRB_SIZE_MASK;
 856
 857                         ep0->trb_enqueue = 0;
 858                 }
 859
 860                 transfer_size = roundup((ur->length - transfer_size),
 861                                         maxp);
 862
 863                 transferred = min_t(u32, remaining_ur_length,
 864                                     transfer_size - length);
 865                 memcpy(buf, dwc->ep0_bounce, transferred);
 866         } else {
 867                 transferred = ur->length - length;
 868         }
 869
 870         ur->actual += transferred;
 871
 872         if ((epnum & 1) && ur->actual < ur->length) {
 873                 /* for some reason we did not get everything out */
 874
 875                 dwc3_ep0_stall_and_restart(dwc);
 876         } else {
 877                 dwc3_gadget_giveback(ep0, r, 0);
 878
 879                 if (IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) &&
 880                                 ur->length && ur->zero) {
 881                         int ret;
 882
 883                         dwc->ep0_next_event = DWC3_EP0_COMPLETE;
 884
 885                         ret = dwc3_ep0_start_trans(dwc, epnum,
 886                                         dwc->ctrl_req_addr, 0,
 887                                         DWC3_TRBCTL_CONTROL_DATA, false);
 888                         WARN_ON(ret < 0);
 889                 }
 890         }
 891 }
 892
 893 static void dwc3_ep0_complete_status(struct dwc3 *dwc,
 894                 const struct dwc3_event_depevt *event)
 895 {
 896         struct dwc3_request     *r;
 897         struct dwc3_ep          *dep;
 898         struct dwc3_trb         *trb;
 899         u32                     status;
 900
 901         dep = dwc->eps[0];
 902         trb = dwc->ep0_trb;
 903
 904         trace_dwc3_complete_trb(dep, trb);
 905
 906         if (!list_empty(&dep->pending_list)) {
 907                 r = next_request(&dep->pending_list);
 908
 909                 dwc3_gadget_giveback(dep, r, 0);
 910         }
 911
 912         if (dwc->test_mode) {
 913                 int ret;
 914
 915                 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
 916                 if (ret < 0) {
 917                         dwc3_trace(trace_dwc3_ep0, "Invalid Test #%d",
 918                                         dwc->test_mode_nr);
 919                         dwc3_ep0_stall_and_restart(dwc);
 920                         return;
 921                 }
 922         }
 923
 924         status = DWC3_TRB_SIZE_TRBSTS(trb->size);
 925         if (status == DWC3_TRBSTS_SETUP_PENDING) {
 926                 dwc->setup_packet_pending = true;
 927                 dwc3_trace(trace_dwc3_ep0, "Setup Pending received");
 928         }
 929
 930         dwc->ep0state = EP0_SETUP_PHASE;
 931         dwc3_ep0_out_start(dwc);
 932 }
 933
 934 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
 935                         const struct dwc3_event_depevt *event)
 936 {
 937         struct dwc3_ep          *dep = dwc->eps[event->endpoint_number];
 938
 939         dep->flags &= ~DWC3_EP_BUSY;
 940         dep->resource_index = 0;
 941         dwc->setup_packet_pending = false;
 942
 943         switch (dwc->ep0state) {
 944         case EP0_SETUP_PHASE:
 945                 dwc3_trace(trace_dwc3_ep0, "Setup Phase");
 946                 dwc3_ep0_inspect_setup(dwc, event);
 947                 break;
 948
 949         case EP0_DATA_PHASE:
 950                 dwc3_trace(trace_dwc3_ep0, "Data Phase");
 951                 dwc3_ep0_complete_data(dwc, event);
 952                 break;
 953
 954         case EP0_STATUS_PHASE:
 955                 dwc3_trace(trace_dwc3_ep0, "Status Phase");
 956                 dwc3_ep0_complete_status(dwc, event);
 957                 break;
 958         default:
 959                 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
 960         }
 961 }
 962
 963 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
 964                 struct dwc3_ep *dep, struct dwc3_request *req)
 965 {
 966         int                     ret;
 967
 968         req->direction = !!dep->number;
 969
 970         if (req->request.length == 0) {
 971                 ret = dwc3_ep0_start_trans(dwc, dep->number,
 972                                 dwc->ctrl_req_addr, 0,
 973                                 DWC3_TRBCTL_CONTROL_DATA, false);
 974         } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket)
 975                         && (dep->number == 0)) {
 976                 u32     transfer_size = 0;
 977                 u32     maxpacket;
 978
 979                 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
 980                                 dep->number);
 981                 if (ret) {
 982                         dwc3_trace(trace_dwc3_ep0, "failed to map request\n");
 983                         return;
 984                 }
 985
 986                 maxpacket = dep->endpoint.maxpacket;
 987
 988                 if (req->request.length > DWC3_EP0_BOUNCE_SIZE) {
 989                         transfer_size = ALIGN(req->request.length - maxpacket,
 990                                               maxpacket);
 991                         ret = dwc3_ep0_start_trans(dwc, dep->number,
 992                                                    req->request.dma,
 993                                                    transfer_size,
 994                                                    DWC3_TRBCTL_CONTROL_DATA,
 995                                                    true);
 996                 }
 997
 998                 transfer_size = roundup((req->request.length - transfer_size),
 999                                         maxpacket);
1000
1001                 dwc->ep0_bounced = true;
1002
1003                 ret = dwc3_ep0_start_trans(dwc, dep->number,
1004                                 dwc->ep0_bounce_addr, transfer_size,
1005                                 DWC3_TRBCTL_CONTROL_DATA, false);
1006         } else {
1007                 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1008                                 dep->number);
1009                 if (ret) {
1010                         dwc3_trace(trace_dwc3_ep0, "failed to map request\n");
1011                         return;
1012                 }
1013
1014                 ret = dwc3_ep0_start_trans(dwc, dep->number, req->request.dma,
1015                                 req->request.length, DWC3_TRBCTL_CONTROL_DATA,
1016                                 false);
1017         }
1018
1019         WARN_ON(ret < 0);
1020 }
1021
1022 static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
1023 {
1024         struct dwc3             *dwc = dep->dwc;
1025         u32                     type;
1026
1027         type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
1028                 : DWC3_TRBCTL_CONTROL_STATUS2;
1029
1030         return dwc3_ep0_start_trans(dwc, dep->number,
1031                         dwc->ctrl_req_addr, 0, type, false);
1032 }
1033
1034 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
1035 {
1036         WARN_ON(dwc3_ep0_start_control_status(dep));
1037 }
1038
1039 static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
1040                 const struct dwc3_event_depevt *event)
1041 {
1042         struct dwc3_ep          *dep = dwc->eps[event->endpoint_number];
1043
1044         __dwc3_ep0_do_control_status(dwc, dep);
1045 }
1046
1047 static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
1048 {
1049         struct dwc3_gadget_ep_cmd_params params;
1050         u32                     cmd;
1051         int                     ret;
1052
1053         if (!dep->resource_index)
1054                 return;
1055
1056         cmd = DWC3_DEPCMD_ENDTRANSFER;
1057         cmd |= DWC3_DEPCMD_CMDIOC;
1058         cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1059         memset(&params, 0, sizeof(params));
1060         ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
1061         WARN_ON_ONCE(ret);
1062         dep->resource_index = 0;
1063 }
1064
1065 static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
1066                 const struct dwc3_event_depevt *event)
1067 {
1068         switch (event->status) {
1069         case DEPEVT_STATUS_CONTROL_DATA:
1070                 dwc3_trace(trace_dwc3_ep0, "Control Data");
1071
1072                 /*
1073                  * We already have a DATA transfer in the controller's cache,
1074                  * if we receive a XferNotReady(DATA) we will ignore it, unless
1075                  * it's for the wrong direction.
1076                  *
1077                  * In that case, we must issue END_TRANSFER command to the Data
1078                  * Phase we already have started and issue SetStall on the
1079                  * control endpoint.
1080                  */
1081                 if (dwc->ep0_expect_in != event->endpoint_number) {
1082                         struct dwc3_ep  *dep = dwc->eps[dwc->ep0_expect_in];
1083
1084                         dwc3_trace(trace_dwc3_ep0,
1085                                         "Wrong direction for Data phase");
1086                         dwc3_ep0_end_control_data(dwc, dep);
1087                         dwc3_ep0_stall_and_restart(dwc);
1088                         return;
1089                 }
1090
1091                 break;
1092
1093         case DEPEVT_STATUS_CONTROL_STATUS:
1094                 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
1095                         return;
1096
1097                 dwc3_trace(trace_dwc3_ep0, "Control Status");
1098
1099                 dwc->ep0state = EP0_STATUS_PHASE;
1100
1101                 if (dwc->delayed_status) {
1102                         WARN_ON_ONCE(event->endpoint_number != 1);
1103                         dwc3_trace(trace_dwc3_ep0, "Delayed Status");
1104                         return;
1105                 }
1106
1107                 dwc3_ep0_do_control_status(dwc, event);
1108         }
1109 }
1110
1111 void dwc3_ep0_interrupt(struct dwc3 *dwc,
1112                 const struct dwc3_event_depevt *event)
1113 {
1114         u8                      epnum = event->endpoint_number;
1115
1116         dwc3_trace(trace_dwc3_ep0, "%s while ep%d%s in state '%s'",
1117                         dwc3_ep_event_string(event->endpoint_event),
1118                         epnum >> 1, (epnum & 1) ? "in" : "out",
1119                         dwc3_ep0_state_string(dwc->ep0state));
1120
1121         switch (event->endpoint_event) {
1122         case DWC3_DEPEVT_XFERCOMPLETE:
1123                 dwc3_ep0_xfer_complete(dwc, event);
1124                 break;
1125
1126         case DWC3_DEPEVT_XFERNOTREADY:
1127                 dwc3_ep0_xfernotready(dwc, event);
1128                 break;
1129
1130         case DWC3_DEPEVT_XFERINPROGRESS:
1131         case DWC3_DEPEVT_RXTXFIFOEVT:
1132         case DWC3_DEPEVT_STREAMEVT:
1133         case DWC3_DEPEVT_EPCMDCMPLT:
1134                 break;
1135         }
1136 }