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1 /**
2  * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
3  *
4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5  *
6  * Authors: Felipe Balbi <balbi@ti.com>,
7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8  *
9  * This program is free software: you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License version 2  of
11  * the License as published by the Free Software Foundation.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  */
18
19 #include <linux/kernel.h>
20 #include <linux/slab.h>
21 #include <linux/spinlock.h>
22 #include <linux/platform_device.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/interrupt.h>
25 #include <linux/io.h>
26 #include <linux/list.h>
27 #include <linux/dma-mapping.h>
28
29 #include <linux/usb/ch9.h>
30 #include <linux/usb/gadget.h>
31 #include <linux/usb/composite.h>
32
33 #include "core.h"
34 #include "debug.h"
35 #include "gadget.h"
36 #include "io.h"
37
38 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
39 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
40                 struct dwc3_ep *dep, struct dwc3_request *req);
41
42 static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
43 {
44         switch (state) {
45         case EP0_UNCONNECTED:
46                 return "Unconnected";
47         case EP0_SETUP_PHASE:
48                 return "Setup Phase";
49         case EP0_DATA_PHASE:
50                 return "Data Phase";
51         case EP0_STATUS_PHASE:
52                 return "Status Phase";
53         default:
54                 return "UNKNOWN";
55         }
56 }
57
58 static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
59                 u32 len, u32 type, bool chain)
60 {
61         struct dwc3_gadget_ep_cmd_params params;
62         struct dwc3_trb                 *trb;
63         struct dwc3_ep                  *dep;
64
65         int                             ret;
66
67         dep = dwc->eps[epnum];
68         if (dep->flags & DWC3_EP_BUSY) {
69                 dwc3_trace(trace_dwc3_ep0, "%s still busy", dep->name);
70                 return 0;
71         }
72
73         trb = &dwc->ep0_trb[dep->free_slot];
74
75         if (chain)
76                 dep->free_slot++;
77
78         trb->bpl = lower_32_bits(buf_dma);
79         trb->bph = upper_32_bits(buf_dma);
80         trb->size = len;
81         trb->ctrl = type;
82
83         trb->ctrl |= (DWC3_TRB_CTRL_HWO
84                         | DWC3_TRB_CTRL_ISP_IMI);
85
86         if (chain)
87                 trb->ctrl |= DWC3_TRB_CTRL_CHN;
88         else
89                 trb->ctrl |= (DWC3_TRB_CTRL_IOC
90                                 | DWC3_TRB_CTRL_LST);
91
92         if (chain)
93                 return 0;
94
95         memset(&params, 0, sizeof(params));
96         params.param0 = upper_32_bits(dwc->ep0_trb_addr);
97         params.param1 = lower_32_bits(dwc->ep0_trb_addr);
98
99         trace_dwc3_prepare_trb(dep, trb);
100
101         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
102                         DWC3_DEPCMD_STARTTRANSFER, &params);
103         if (ret < 0) {
104                 dwc3_trace(trace_dwc3_ep0, "%s STARTTRANSFER failed",
105                                 dep->name);
106                 return ret;
107         }
108
109         dep->flags |= DWC3_EP_BUSY;
110         dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
111                         dep->number);
112
113         dwc->ep0_next_event = DWC3_EP0_COMPLETE;
114
115         return 0;
116 }
117
118 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
119                 struct dwc3_request *req)
120 {
121         struct dwc3             *dwc = dep->dwc;
122
123         req->request.actual     = 0;
124         req->request.status     = -EINPROGRESS;
125         req->epnum              = dep->number;
126
127         list_add_tail(&req->list, &dep->request_list);
128
129         /*
130          * Gadget driver might not be quick enough to queue a request
131          * before we get a Transfer Not Ready event on this endpoint.
132          *
133          * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
134          * flag is set, it's telling us that as soon as Gadget queues the
135          * required request, we should kick the transfer here because the
136          * IRQ we were waiting for is long gone.
137          */
138         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
139                 unsigned        direction;
140
141                 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
142
143                 if (dwc->ep0state != EP0_DATA_PHASE) {
144                         dev_WARN(dwc->dev, "Unexpected pending request\n");
145                         return 0;
146                 }
147
148                 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
149
150                 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
151                                 DWC3_EP0_DIR_IN);
152
153                 return 0;
154         }
155
156         /*
157          * In case gadget driver asked us to delay the STATUS phase,
158          * handle it here.
159          */
160         if (dwc->delayed_status) {
161                 unsigned        direction;
162
163                 direction = !dwc->ep0_expect_in;
164                 dwc->delayed_status = false;
165                 usb_gadget_set_state(&dwc->gadget, USB_STATE_CONFIGURED);
166
167                 if (dwc->ep0state == EP0_STATUS_PHASE)
168                         __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
169                 else
170                         dwc3_trace(trace_dwc3_ep0,
171                                         "too early for delayed status");
172
173                 return 0;
174         }
175
176         /*
177          * Unfortunately we have uncovered a limitation wrt the Data Phase.
178          *
179          * Section 9.4 says we can wait for the XferNotReady(DATA) event to
180          * come before issueing Start Transfer command, but if we do, we will
181          * miss situations where the host starts another SETUP phase instead of
182          * the DATA phase.  Such cases happen at least on TD.7.6 of the Link
183          * Layer Compliance Suite.
184          *
185          * The problem surfaces due to the fact that in case of back-to-back
186          * SETUP packets there will be no XferNotReady(DATA) generated and we
187          * will be stuck waiting for XferNotReady(DATA) forever.
188          *
189          * By looking at tables 9-13 and 9-14 of the Databook, we can see that
190          * it tells us to start Data Phase right away. It also mentions that if
191          * we receive a SETUP phase instead of the DATA phase, core will issue
192          * XferComplete for the DATA phase, before actually initiating it in
193          * the wire, with the TRB's status set to "SETUP_PENDING". Such status
194          * can only be used to print some debugging logs, as the core expects
195          * us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
196          * just so it completes right away, without transferring anything and,
197          * only then, we can go back to the SETUP phase.
198          *
199          * Because of this scenario, SNPS decided to change the programming
200          * model of control transfers and support on-demand transfers only for
201          * the STATUS phase. To fix the issue we have now, we will always wait
202          * for gadget driver to queue the DATA phase's struct usb_request, then
203          * start it right away.
204          *
205          * If we're actually in a 2-stage transfer, we will wait for
206          * XferNotReady(STATUS).
207          */
208         if (dwc->three_stage_setup) {
209                 unsigned        direction;
210
211                 direction = dwc->ep0_expect_in;
212                 dwc->ep0state = EP0_DATA_PHASE;
213
214                 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
215
216                 dep->flags &= ~DWC3_EP0_DIR_IN;
217         }
218
219         return 0;
220 }
221
222 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
223                 gfp_t gfp_flags)
224 {
225         struct dwc3_request             *req = to_dwc3_request(request);
226         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
227         struct dwc3                     *dwc = dep->dwc;
228
229         unsigned long                   flags;
230
231         int                             ret;
232
233         spin_lock_irqsave(&dwc->lock, flags);
234         if (!dep->endpoint.desc) {
235                 dwc3_trace(trace_dwc3_ep0,
236                                 "trying to queue request %p to disabled %s",
237                                 request, dep->name);
238                 ret = -ESHUTDOWN;
239                 goto out;
240         }
241
242         /* we share one TRB for ep0/1 */
243         if (!list_empty(&dep->request_list)) {
244                 ret = -EBUSY;
245                 goto out;
246         }
247
248         dwc3_trace(trace_dwc3_ep0,
249                         "queueing request %p to %s length %d state '%s'",
250                         request, dep->name, request->length,
251                         dwc3_ep0_state_string(dwc->ep0state));
252
253         ret = __dwc3_gadget_ep0_queue(dep, req);
254
255 out:
256         spin_unlock_irqrestore(&dwc->lock, flags);
257
258         return ret;
259 }
260
261 static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
262 {
263         struct dwc3_ep          *dep;
264
265         /* reinitialize physical ep1 */
266         dep = dwc->eps[1];
267         dep->flags = DWC3_EP_ENABLED;
268
269         /* stall is always issued on EP0 */
270         dep = dwc->eps[0];
271         __dwc3_gadget_ep_set_halt(dep, 1, false);
272         dep->flags = DWC3_EP_ENABLED;
273         dwc->delayed_status = false;
274
275         if (!list_empty(&dep->request_list)) {
276                 struct dwc3_request     *req;
277
278                 req = next_request(&dep->request_list);
279                 dwc3_gadget_giveback(dep, req, -ECONNRESET);
280         }
281
282         dwc->ep0state = EP0_SETUP_PHASE;
283         dwc3_ep0_out_start(dwc);
284 }
285
286 int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
287 {
288         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
289         struct dwc3                     *dwc = dep->dwc;
290
291         dwc3_ep0_stall_and_restart(dwc);
292
293         return 0;
294 }
295
296 int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
297 {
298         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
299         struct dwc3                     *dwc = dep->dwc;
300         unsigned long                   flags;
301         int                             ret;
302
303         spin_lock_irqsave(&dwc->lock, flags);
304         ret = __dwc3_gadget_ep0_set_halt(ep, value);
305         spin_unlock_irqrestore(&dwc->lock, flags);
306
307         return ret;
308 }
309
310 void dwc3_ep0_out_start(struct dwc3 *dwc)
311 {
312         int                             ret;
313
314         ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8,
315                         DWC3_TRBCTL_CONTROL_SETUP, false);
316         WARN_ON(ret < 0);
317 }
318
319 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
320 {
321         struct dwc3_ep          *dep;
322         u32                     windex = le16_to_cpu(wIndex_le);
323         u32                     epnum;
324
325         epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
326         if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
327                 epnum |= 1;
328
329         dep = dwc->eps[epnum];
330         if (dep->flags & DWC3_EP_ENABLED)
331                 return dep;
332
333         return NULL;
334 }
335
336 static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
337 {
338 }
339 /*
340  * ch 9.4.5
341  */
342 static int dwc3_ep0_handle_status(struct dwc3 *dwc,
343                 struct usb_ctrlrequest *ctrl)
344 {
345         struct dwc3_ep          *dep;
346         u32                     recip;
347         u32                     reg;
348         u16                     usb_status = 0;
349         __le16                  *response_pkt;
350
351         recip = ctrl->bRequestType & USB_RECIP_MASK;
352         switch (recip) {
353         case USB_RECIP_DEVICE:
354                 /*
355                  * LTM will be set once we know how to set this in HW.
356                  */
357                 usb_status |= dwc->gadget.is_selfpowered;
358
359                 if (dwc->speed == DWC3_DSTS_SUPERSPEED) {
360                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
361                         if (reg & DWC3_DCTL_INITU1ENA)
362                                 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
363                         if (reg & DWC3_DCTL_INITU2ENA)
364                                 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
365                 }
366
367                 break;
368
369         case USB_RECIP_INTERFACE:
370                 /*
371                  * Function Remote Wake Capable D0
372                  * Function Remote Wakeup       D1
373                  */
374                 break;
375
376         case USB_RECIP_ENDPOINT:
377                 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
378                 if (!dep)
379                         return -EINVAL;
380
381                 if (dep->flags & DWC3_EP_STALL)
382                         usb_status = 1 << USB_ENDPOINT_HALT;
383                 break;
384         default:
385                 return -EINVAL;
386         }
387
388         response_pkt = (__le16 *) dwc->setup_buf;
389         *response_pkt = cpu_to_le16(usb_status);
390
391         dep = dwc->eps[0];
392         dwc->ep0_usb_req.dep = dep;
393         dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
394         dwc->ep0_usb_req.request.buf = dwc->setup_buf;
395         dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
396
397         return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
398 }
399
400 static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
401                 struct usb_ctrlrequest *ctrl, int set)
402 {
403         struct dwc3_ep          *dep;
404         u32                     recip;
405         u32                     wValue;
406         u32                     wIndex;
407         u32                     reg;
408         int                     ret;
409         enum usb_device_state   state;
410
411         wValue = le16_to_cpu(ctrl->wValue);
412         wIndex = le16_to_cpu(ctrl->wIndex);
413         recip = ctrl->bRequestType & USB_RECIP_MASK;
414         state = dwc->gadget.state;
415
416         switch (recip) {
417         case USB_RECIP_DEVICE:
418
419                 switch (wValue) {
420                 case USB_DEVICE_REMOTE_WAKEUP:
421                         break;
422                 /*
423                  * 9.4.1 says only only for SS, in AddressState only for
424                  * default control pipe
425                  */
426                 case USB_DEVICE_U1_ENABLE:
427                         if (state != USB_STATE_CONFIGURED)
428                                 return -EINVAL;
429                         if (dwc->speed != DWC3_DSTS_SUPERSPEED)
430                                 return -EINVAL;
431
432                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
433                         if (set)
434                                 reg |= DWC3_DCTL_INITU1ENA;
435                         else
436                                 reg &= ~DWC3_DCTL_INITU1ENA;
437                         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
438                         break;
439
440                 case USB_DEVICE_U2_ENABLE:
441                         if (state != USB_STATE_CONFIGURED)
442                                 return -EINVAL;
443                         if (dwc->speed != DWC3_DSTS_SUPERSPEED)
444                                 return -EINVAL;
445
446                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
447                         if (set)
448                                 reg |= DWC3_DCTL_INITU2ENA;
449                         else
450                                 reg &= ~DWC3_DCTL_INITU2ENA;
451                         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
452                         break;
453
454                 case USB_DEVICE_LTM_ENABLE:
455                         return -EINVAL;
456
457                 case USB_DEVICE_TEST_MODE:
458                         if ((wIndex & 0xff) != 0)
459                                 return -EINVAL;
460                         if (!set)
461                                 return -EINVAL;
462
463                         dwc->test_mode_nr = wIndex >> 8;
464                         dwc->test_mode = true;
465                         break;
466                 default:
467                         return -EINVAL;
468                 }
469                 break;
470
471         case USB_RECIP_INTERFACE:
472                 switch (wValue) {
473                 case USB_INTRF_FUNC_SUSPEND:
474                         if (wIndex & USB_INTRF_FUNC_SUSPEND_LP)
475                                 /* XXX enable Low power suspend */
476                                 ;
477                         if (wIndex & USB_INTRF_FUNC_SUSPEND_RW)
478                                 /* XXX enable remote wakeup */
479                                 ;
480                         break;
481                 default:
482                         return -EINVAL;
483                 }
484                 break;
485
486         case USB_RECIP_ENDPOINT:
487                 switch (wValue) {
488                 case USB_ENDPOINT_HALT:
489                         dep = dwc3_wIndex_to_dep(dwc, wIndex);
490                         if (!dep)
491                                 return -EINVAL;
492                         if (set == 0 && (dep->flags & DWC3_EP_WEDGE))
493                                 break;
494                         ret = __dwc3_gadget_ep_set_halt(dep, set, true);
495                         if (ret)
496                                 return -EINVAL;
497                         break;
498                 default:
499                         return -EINVAL;
500                 }
501                 break;
502
503         default:
504                 return -EINVAL;
505         }
506
507         return 0;
508 }
509
510 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
511 {
512         enum usb_device_state state = dwc->gadget.state;
513         u32 addr;
514         u32 reg;
515
516         addr = le16_to_cpu(ctrl->wValue);
517         if (addr > 127) {
518                 dwc3_trace(trace_dwc3_ep0, "invalid device address %d", addr);
519                 return -EINVAL;
520         }
521
522         if (state == USB_STATE_CONFIGURED) {
523                 dwc3_trace(trace_dwc3_ep0,
524                                 "trying to set address when configured");
525                 return -EINVAL;
526         }
527
528         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
529         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
530         reg |= DWC3_DCFG_DEVADDR(addr);
531         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
532
533         if (addr)
534                 usb_gadget_set_state(&dwc->gadget, USB_STATE_ADDRESS);
535         else
536                 usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT);
537
538         return 0;
539 }
540
541 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
542 {
543         int ret;
544
545         spin_unlock(&dwc->lock);
546         ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
547         spin_lock(&dwc->lock);
548         return ret;
549 }
550
551 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
552 {
553         enum usb_device_state state = dwc->gadget.state;
554         u32 cfg;
555         int ret;
556         u32 reg;
557
558         dwc->start_config_issued = false;
559         cfg = le16_to_cpu(ctrl->wValue);
560
561         switch (state) {
562         case USB_STATE_DEFAULT:
563                 return -EINVAL;
564
565         case USB_STATE_ADDRESS:
566                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
567                 /* if the cfg matches and the cfg is non zero */
568                 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
569
570                         /*
571                          * only change state if set_config has already
572                          * been processed. If gadget driver returns
573                          * USB_GADGET_DELAYED_STATUS, we will wait
574                          * to change the state on the next usb_ep_queue()
575                          */
576                         if (ret == 0)
577                                 usb_gadget_set_state(&dwc->gadget,
578                                                 USB_STATE_CONFIGURED);
579
580                         /*
581                          * Enable transition to U1/U2 state when
582                          * nothing is pending from application.
583                          */
584                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
585                         reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA);
586                         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
587
588                         dwc->resize_fifos = true;
589                         dwc3_trace(trace_dwc3_ep0, "resize FIFOs flag SET");
590                 }
591                 break;
592
593         case USB_STATE_CONFIGURED:
594                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
595                 if (!cfg && !ret)
596                         usb_gadget_set_state(&dwc->gadget,
597                                         USB_STATE_ADDRESS);
598                 break;
599         default:
600                 ret = -EINVAL;
601         }
602         return ret;
603 }
604
605 static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
606 {
607         struct dwc3_ep  *dep = to_dwc3_ep(ep);
608         struct dwc3     *dwc = dep->dwc;
609
610         u32             param = 0;
611         u32             reg;
612
613         struct timing {
614                 u8      u1sel;
615                 u8      u1pel;
616                 u16     u2sel;
617                 u16     u2pel;
618         } __packed timing;
619
620         int             ret;
621
622         memcpy(&timing, req->buf, sizeof(timing));
623
624         dwc->u1sel = timing.u1sel;
625         dwc->u1pel = timing.u1pel;
626         dwc->u2sel = le16_to_cpu(timing.u2sel);
627         dwc->u2pel = le16_to_cpu(timing.u2pel);
628
629         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
630         if (reg & DWC3_DCTL_INITU2ENA)
631                 param = dwc->u2pel;
632         if (reg & DWC3_DCTL_INITU1ENA)
633                 param = dwc->u1pel;
634
635         /*
636          * According to Synopsys Databook, if parameter is
637          * greater than 125, a value of zero should be
638          * programmed in the register.
639          */
640         if (param > 125)
641                 param = 0;
642
643         /* now that we have the time, issue DGCMD Set Sel */
644         ret = dwc3_send_gadget_generic_command(dwc,
645                         DWC3_DGCMD_SET_PERIODIC_PAR, param);
646         WARN_ON(ret < 0);
647 }
648
649 static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
650 {
651         struct dwc3_ep  *dep;
652         enum usb_device_state state = dwc->gadget.state;
653         u16             wLength;
654         u16             wValue;
655
656         if (state == USB_STATE_DEFAULT)
657                 return -EINVAL;
658
659         wValue = le16_to_cpu(ctrl->wValue);
660         wLength = le16_to_cpu(ctrl->wLength);
661
662         if (wLength != 6) {
663                 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
664                                 wLength);
665                 return -EINVAL;
666         }
667
668         /*
669          * To handle Set SEL we need to receive 6 bytes from Host. So let's
670          * queue a usb_request for 6 bytes.
671          *
672          * Remember, though, this controller can't handle non-wMaxPacketSize
673          * aligned transfers on the OUT direction, so we queue a request for
674          * wMaxPacketSize instead.
675          */
676         dep = dwc->eps[0];
677         dwc->ep0_usb_req.dep = dep;
678         dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
679         dwc->ep0_usb_req.request.buf = dwc->setup_buf;
680         dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
681
682         return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
683 }
684
685 static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
686 {
687         u16             wLength;
688         u16             wValue;
689         u16             wIndex;
690
691         wValue = le16_to_cpu(ctrl->wValue);
692         wLength = le16_to_cpu(ctrl->wLength);
693         wIndex = le16_to_cpu(ctrl->wIndex);
694
695         if (wIndex || wLength)
696                 return -EINVAL;
697
698         /*
699          * REVISIT It's unclear from Databook what to do with this
700          * value. For now, just cache it.
701          */
702         dwc->isoch_delay = wValue;
703
704         return 0;
705 }
706
707 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
708 {
709         int ret;
710
711         switch (ctrl->bRequest) {
712         case USB_REQ_GET_STATUS:
713                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_GET_STATUS");
714                 ret = dwc3_ep0_handle_status(dwc, ctrl);
715                 break;
716         case USB_REQ_CLEAR_FEATURE:
717                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_CLEAR_FEATURE");
718                 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
719                 break;
720         case USB_REQ_SET_FEATURE:
721                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_FEATURE");
722                 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
723                 break;
724         case USB_REQ_SET_ADDRESS:
725                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_ADDRESS");
726                 ret = dwc3_ep0_set_address(dwc, ctrl);
727                 break;
728         case USB_REQ_SET_CONFIGURATION:
729                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_CONFIGURATION");
730                 ret = dwc3_ep0_set_config(dwc, ctrl);
731                 break;
732         case USB_REQ_SET_SEL:
733                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_SEL");
734                 ret = dwc3_ep0_set_sel(dwc, ctrl);
735                 break;
736         case USB_REQ_SET_ISOCH_DELAY:
737                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_ISOCH_DELAY");
738                 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
739                 break;
740         case USB_REQ_SET_INTERFACE:
741                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_INTERFACE");
742                 dwc->start_config_issued = false;
743                 /* Fall through */
744         default:
745                 dwc3_trace(trace_dwc3_ep0, "Forwarding to gadget driver");
746                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
747                 break;
748         }
749
750         return ret;
751 }
752
753 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
754                 const struct dwc3_event_depevt *event)
755 {
756         struct usb_ctrlrequest *ctrl = dwc->ctrl_req;
757         int ret = -EINVAL;
758         u32 len;
759
760         if (!dwc->gadget_driver)
761                 goto out;
762
763         trace_dwc3_ctrl_req(ctrl);
764
765         len = le16_to_cpu(ctrl->wLength);
766         if (!len) {
767                 dwc->three_stage_setup = false;
768                 dwc->ep0_expect_in = false;
769                 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
770         } else {
771                 dwc->three_stage_setup = true;
772                 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
773                 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
774         }
775
776         if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
777                 ret = dwc3_ep0_std_request(dwc, ctrl);
778         else
779                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
780
781         if (ret == USB_GADGET_DELAYED_STATUS)
782                 dwc->delayed_status = true;
783
784 out:
785         if (ret < 0)
786                 dwc3_ep0_stall_and_restart(dwc);
787 }
788
789 static void dwc3_ep0_complete_data(struct dwc3 *dwc,
790                 const struct dwc3_event_depevt *event)
791 {
792         struct dwc3_request     *r = NULL;
793         struct usb_request      *ur;
794         struct dwc3_trb         *trb;
795         struct dwc3_ep          *ep0;
796         unsigned                transfer_size = 0;
797         unsigned                maxp;
798         unsigned                remaining_ur_length;
799         void                    *buf;
800         u32                     transferred = 0;
801         u32                     status;
802         u32                     length;
803         u8                      epnum;
804
805         epnum = event->endpoint_number;
806         ep0 = dwc->eps[0];
807
808         dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
809
810         trb = dwc->ep0_trb;
811
812         trace_dwc3_complete_trb(ep0, trb);
813
814         r = next_request(&ep0->request_list);
815         if (!r)
816                 return;
817
818         status = DWC3_TRB_SIZE_TRBSTS(trb->size);
819         if (status == DWC3_TRBSTS_SETUP_PENDING) {
820                 dwc->setup_packet_pending = true;
821
822                 dwc3_trace(trace_dwc3_ep0, "Setup Pending received");
823
824                 if (r)
825                         dwc3_gadget_giveback(ep0, r, -ECONNRESET);
826
827                 return;
828         }
829
830         ur = &r->request;
831         buf = ur->buf;
832         remaining_ur_length = ur->length;
833
834         length = trb->size & DWC3_TRB_SIZE_MASK;
835
836         maxp = ep0->endpoint.maxpacket;
837
838         if (dwc->ep0_bounced) {
839                 /*
840                  * Handle the first TRB before handling the bounce buffer if
841                  * the request length is greater than the bounce buffer size
842                  */
843                 if (ur->length > DWC3_EP0_BOUNCE_SIZE) {
844                         transfer_size = ALIGN(ur->length - maxp, maxp);
845                         transferred = transfer_size - length;
846                         buf = (u8 *)buf + transferred;
847                         ur->actual += transferred;
848                         remaining_ur_length -= transferred;
849
850                         trb++;
851                         length = trb->size & DWC3_TRB_SIZE_MASK;
852
853                         ep0->free_slot = 0;
854                 }
855
856                 transfer_size = roundup((ur->length - transfer_size),
857                                         maxp);
858
859                 transferred = min_t(u32, remaining_ur_length,
860                                     transfer_size - length);
861                 memcpy(buf, dwc->ep0_bounce, transferred);
862         } else {
863                 transferred = ur->length - length;
864         }
865
866         ur->actual += transferred;
867
868         if ((epnum & 1) && ur->actual < ur->length) {
869                 /* for some reason we did not get everything out */
870
871                 dwc3_ep0_stall_and_restart(dwc);
872         } else {
873                 dwc3_gadget_giveback(ep0, r, 0);
874
875                 if (IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) &&
876                                 ur->length && ur->zero) {
877                         int ret;
878
879                         dwc->ep0_next_event = DWC3_EP0_COMPLETE;
880
881                         ret = dwc3_ep0_start_trans(dwc, epnum,
882                                         dwc->ctrl_req_addr, 0,
883                                         DWC3_TRBCTL_CONTROL_DATA, false);
884                         WARN_ON(ret < 0);
885                 }
886         }
887 }
888
889 static void dwc3_ep0_complete_status(struct dwc3 *dwc,
890                 const struct dwc3_event_depevt *event)
891 {
892         struct dwc3_request     *r;
893         struct dwc3_ep          *dep;
894         struct dwc3_trb         *trb;
895         u32                     status;
896
897         dep = dwc->eps[0];
898         trb = dwc->ep0_trb;
899
900         trace_dwc3_complete_trb(dep, trb);
901
902         if (!list_empty(&dep->request_list)) {
903                 r = next_request(&dep->request_list);
904
905                 dwc3_gadget_giveback(dep, r, 0);
906         }
907
908         if (dwc->test_mode) {
909                 int ret;
910
911                 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
912                 if (ret < 0) {
913                         dwc3_trace(trace_dwc3_ep0, "Invalid Test #%d",
914                                         dwc->test_mode_nr);
915                         dwc3_ep0_stall_and_restart(dwc);
916                         return;
917                 }
918         }
919
920         status = DWC3_TRB_SIZE_TRBSTS(trb->size);
921         if (status == DWC3_TRBSTS_SETUP_PENDING) {
922                 dwc->setup_packet_pending = true;
923                 dwc3_trace(trace_dwc3_ep0, "Setup Pending received");
924         }
925
926         dwc->ep0state = EP0_SETUP_PHASE;
927         dwc3_ep0_out_start(dwc);
928 }
929
930 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
931                         const struct dwc3_event_depevt *event)
932 {
933         struct dwc3_ep          *dep = dwc->eps[event->endpoint_number];
934
935         dep->flags &= ~DWC3_EP_BUSY;
936         dep->resource_index = 0;
937         dwc->setup_packet_pending = false;
938
939         switch (dwc->ep0state) {
940         case EP0_SETUP_PHASE:
941                 dwc3_trace(trace_dwc3_ep0, "Setup Phase");
942                 dwc3_ep0_inspect_setup(dwc, event);
943                 break;
944
945         case EP0_DATA_PHASE:
946                 dwc3_trace(trace_dwc3_ep0, "Data Phase");
947                 dwc3_ep0_complete_data(dwc, event);
948                 break;
949
950         case EP0_STATUS_PHASE:
951                 dwc3_trace(trace_dwc3_ep0, "Status Phase");
952                 dwc3_ep0_complete_status(dwc, event);
953                 break;
954         default:
955                 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
956         }
957 }
958
959 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
960                 struct dwc3_ep *dep, struct dwc3_request *req)
961 {
962         int                     ret;
963
964         req->direction = !!dep->number;
965
966         if (req->request.length == 0) {
967                 ret = dwc3_ep0_start_trans(dwc, dep->number,
968                                 dwc->ctrl_req_addr, 0,
969                                 DWC3_TRBCTL_CONTROL_DATA, false);
970         } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket)
971                         && (dep->number == 0)) {
972                 u32     transfer_size = 0;
973                 u32     maxpacket;
974
975                 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
976                                 dep->number);
977                 if (ret) {
978                         dwc3_trace(trace_dwc3_ep0, "failed to map request\n");
979                         return;
980                 }
981
982                 maxpacket = dep->endpoint.maxpacket;
983
984                 if (req->request.length > DWC3_EP0_BOUNCE_SIZE) {
985                         transfer_size = ALIGN(req->request.length - maxpacket,
986                                               maxpacket);
987                         ret = dwc3_ep0_start_trans(dwc, dep->number,
988                                                    req->request.dma,
989                                                    transfer_size,
990                                                    DWC3_TRBCTL_CONTROL_DATA,
991                                                    true);
992                 }
993
994                 transfer_size = roundup((req->request.length - transfer_size),
995                                         maxpacket);
996
997                 dwc->ep0_bounced = true;
998
999                 ret = dwc3_ep0_start_trans(dwc, dep->number,
1000                                 dwc->ep0_bounce_addr, transfer_size,
1001                                 DWC3_TRBCTL_CONTROL_DATA, false);
1002         } else {
1003                 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1004                                 dep->number);
1005                 if (ret) {
1006                         dwc3_trace(trace_dwc3_ep0, "failed to map request\n");
1007                         return;
1008                 }
1009
1010                 ret = dwc3_ep0_start_trans(dwc, dep->number, req->request.dma,
1011                                 req->request.length, DWC3_TRBCTL_CONTROL_DATA,
1012                                 false);
1013         }
1014
1015         WARN_ON(ret < 0);
1016 }
1017
1018 static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
1019 {
1020         struct dwc3             *dwc = dep->dwc;
1021         u32                     type;
1022
1023         type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
1024                 : DWC3_TRBCTL_CONTROL_STATUS2;
1025
1026         return dwc3_ep0_start_trans(dwc, dep->number,
1027                         dwc->ctrl_req_addr, 0, type, false);
1028 }
1029
1030 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
1031 {
1032         if (dwc->resize_fifos) {
1033                 dwc3_trace(trace_dwc3_ep0, "Resizing FIFOs");
1034                 dwc3_gadget_resize_tx_fifos(dwc);
1035                 dwc->resize_fifos = 0;
1036         }
1037
1038         WARN_ON(dwc3_ep0_start_control_status(dep));
1039 }
1040
1041 static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
1042                 const struct dwc3_event_depevt *event)
1043 {
1044         struct dwc3_ep          *dep = dwc->eps[event->endpoint_number];
1045
1046         __dwc3_ep0_do_control_status(dwc, dep);
1047 }
1048
1049 static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
1050 {
1051         struct dwc3_gadget_ep_cmd_params params;
1052         u32                     cmd;
1053         int                     ret;
1054
1055         if (!dep->resource_index)
1056                 return;
1057
1058         cmd = DWC3_DEPCMD_ENDTRANSFER;
1059         cmd |= DWC3_DEPCMD_CMDIOC;
1060         cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1061         memset(&params, 0, sizeof(params));
1062         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
1063         WARN_ON_ONCE(ret);
1064         dep->resource_index = 0;
1065 }
1066
1067 static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
1068                 const struct dwc3_event_depevt *event)
1069 {
1070         switch (event->status) {
1071         case DEPEVT_STATUS_CONTROL_DATA:
1072                 dwc3_trace(trace_dwc3_ep0, "Control Data");
1073
1074                 /*
1075                  * We already have a DATA transfer in the controller's cache,
1076                  * if we receive a XferNotReady(DATA) we will ignore it, unless
1077                  * it's for the wrong direction.
1078                  *
1079                  * In that case, we must issue END_TRANSFER command to the Data
1080                  * Phase we already have started and issue SetStall on the
1081                  * control endpoint.
1082                  */
1083                 if (dwc->ep0_expect_in != event->endpoint_number) {
1084                         struct dwc3_ep  *dep = dwc->eps[dwc->ep0_expect_in];
1085
1086                         dwc3_trace(trace_dwc3_ep0,
1087                                         "Wrong direction for Data phase");
1088                         dwc3_ep0_end_control_data(dwc, dep);
1089                         dwc3_ep0_stall_and_restart(dwc);
1090                         return;
1091                 }
1092
1093                 break;
1094
1095         case DEPEVT_STATUS_CONTROL_STATUS:
1096                 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
1097                         return;
1098
1099                 dwc3_trace(trace_dwc3_ep0, "Control Status");
1100
1101                 dwc->ep0state = EP0_STATUS_PHASE;
1102
1103                 if (dwc->delayed_status) {
1104                         WARN_ON_ONCE(event->endpoint_number != 1);
1105                         dwc3_trace(trace_dwc3_ep0, "Delayed Status");
1106                         return;
1107                 }
1108
1109                 dwc3_ep0_do_control_status(dwc, event);
1110         }
1111 }
1112
1113 void dwc3_ep0_interrupt(struct dwc3 *dwc,
1114                 const struct dwc3_event_depevt *event)
1115 {
1116         u8                      epnum = event->endpoint_number;
1117
1118         dwc3_trace(trace_dwc3_ep0, "%s while ep%d%s in state '%s'",
1119                         dwc3_ep_event_string(event->endpoint_event),
1120                         epnum >> 1, (epnum & 1) ? "in" : "out",
1121                         dwc3_ep0_state_string(dwc->ep0state));
1122
1123         switch (event->endpoint_event) {
1124         case DWC3_DEPEVT_XFERCOMPLETE:
1125                 dwc3_ep0_xfer_complete(dwc, event);
1126                 break;
1127
1128         case DWC3_DEPEVT_XFERNOTREADY:
1129                 dwc3_ep0_xfernotready(dwc, event);
1130                 break;
1131
1132         case DWC3_DEPEVT_XFERINPROGRESS:
1133         case DWC3_DEPEVT_RXTXFIFOEVT:
1134         case DWC3_DEPEVT_STREAMEVT:
1135         case DWC3_DEPEVT_EPCMDCMPLT:
1136                 break;
1137         }
1138 }