drivers/usb/dwc3/ep0.c

   1 /**
   2  * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * This program is free software: you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2  of
  11  * the License as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/slab.h>
  21 #include <linux/spinlock.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/pm_runtime.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/io.h>
  26 #include <linux/list.h>
  27 #include <linux/dma-mapping.h>
  28
  29 #include <linux/usb/ch9.h>
  30 #include <linux/usb/gadget.h>
  31 #include <linux/usb/composite.h>
  32
  33 #include "core.h"
  34 #include "debug.h"
  35 #include "gadget.h"
  36 #include "io.h"
  37
  38 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
  39 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
  40                 struct dwc3_ep *dep, struct dwc3_request *req);
  41
  42 static void dwc3_ep0_prepare_one_trb(struct dwc3 *dwc, u8 epnum,
  43                 dma_addr_t buf_dma, u32 len, u32 type, bool chain)
  44 {
  45         struct dwc3_trb                 *trb;
  46         struct dwc3_ep                  *dep;
  47
  48         dep = dwc->eps[epnum];
  49
  50         trb = &dwc->ep0_trb[dep->trb_enqueue];
  51
  52         if (chain)
  53                 dep->trb_enqueue++;
  54
  55         trb->bpl = lower_32_bits(buf_dma);
  56         trb->bph = upper_32_bits(buf_dma);
  57         trb->size = len;
  58         trb->ctrl = type;
  59
  60         trb->ctrl |= (DWC3_TRB_CTRL_HWO
  61                         | DWC3_TRB_CTRL_ISP_IMI);
  62
  63         if (chain)
  64                 trb->ctrl |= DWC3_TRB_CTRL_CHN;
  65         else
  66                 trb->ctrl |= (DWC3_TRB_CTRL_IOC
  67                                 | DWC3_TRB_CTRL_LST);
  68
  69         trace_dwc3_prepare_trb(dep, trb);
  70 }
  71
  72 static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
  73                 u32 len, u32 type, bool chain)
  74 {
  75         struct dwc3_gadget_ep_cmd_params params;
  76         struct dwc3_ep                  *dep;
  77         int                             ret;
  78
  79         dep = dwc->eps[epnum];
  80         if (dep->flags & DWC3_EP_BUSY)
  81                 return 0;
  82
  83         dwc3_ep0_prepare_one_trb(dwc, epnum, buf_dma, len, type, chain);
  84
  85         memset(&params, 0, sizeof(params));
  86         params.param0 = upper_32_bits(dwc->ep0_trb_addr);
  87         params.param1 = lower_32_bits(dwc->ep0_trb_addr);
  88
  89         ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_STARTTRANSFER, &params);
  90         if (ret < 0)
  91                 return ret;
  92
  93         dep->flags |= DWC3_EP_BUSY;
  94         dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
  95         dwc->ep0_next_event = DWC3_EP0_COMPLETE;
  96
  97         return 0;
  98 }
  99
 100 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
 101                 struct dwc3_request *req)
 102 {
 103         struct dwc3             *dwc = dep->dwc;
 104
 105         req->request.actual     = 0;
 106         req->request.status     = -EINPROGRESS;
 107         req->epnum              = dep->number;
 108
 109         list_add_tail(&req->list, &dep->pending_list);
 110
 111         /*
 112          * Gadget driver might not be quick enough to queue a request
 113          * before we get a Transfer Not Ready event on this endpoint.
 114          *
 115          * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
 116          * flag is set, it's telling us that as soon as Gadget queues the
 117          * required request, we should kick the transfer here because the
 118          * IRQ we were waiting for is long gone.
 119          */
 120         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
 121                 unsigned        direction;
 122
 123                 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
 124
 125                 if (dwc->ep0state != EP0_DATA_PHASE) {
 126                         dev_WARN(dwc->dev, "Unexpected pending request\n");
 127                         return 0;
 128                 }
 129
 130                 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
 131
 132                 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
 133                                 DWC3_EP0_DIR_IN);
 134
 135                 return 0;
 136         }
 137
 138         /*
 139          * In case gadget driver asked us to delay the STATUS phase,
 140          * handle it here.
 141          */
 142         if (dwc->delayed_status) {
 143                 unsigned        direction;
 144
 145                 direction = !dwc->ep0_expect_in;
 146                 dwc->delayed_status = false;
 147                 usb_gadget_set_state(&dwc->gadget, USB_STATE_CONFIGURED);
 148
 149                 if (dwc->ep0state == EP0_STATUS_PHASE)
 150                         __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
 151
 152                 return 0;
 153         }
 154
 155         /*
 156          * Unfortunately we have uncovered a limitation wrt the Data Phase.
 157          *
 158          * Section 9.4 says we can wait for the XferNotReady(DATA) event to
 159          * come before issueing Start Transfer command, but if we do, we will
 160          * miss situations where the host starts another SETUP phase instead of
 161          * the DATA phase.  Such cases happen at least on TD.7.6 of the Link
 162          * Layer Compliance Suite.
 163          *
 164          * The problem surfaces due to the fact that in case of back-to-back
 165          * SETUP packets there will be no XferNotReady(DATA) generated and we
 166          * will be stuck waiting for XferNotReady(DATA) forever.
 167          *
 168          * By looking at tables 9-13 and 9-14 of the Databook, we can see that
 169          * it tells us to start Data Phase right away. It also mentions that if
 170          * we receive a SETUP phase instead of the DATA phase, core will issue
 171          * XferComplete for the DATA phase, before actually initiating it in
 172          * the wire, with the TRB's status set to "SETUP_PENDING". Such status
 173          * can only be used to print some debugging logs, as the core expects
 174          * us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
 175          * just so it completes right away, without transferring anything and,
 176          * only then, we can go back to the SETUP phase.
 177          *
 178          * Because of this scenario, SNPS decided to change the programming
 179          * model of control transfers and support on-demand transfers only for
 180          * the STATUS phase. To fix the issue we have now, we will always wait
 181          * for gadget driver to queue the DATA phase's struct usb_request, then
 182          * start it right away.
 183          *
 184          * If we're actually in a 2-stage transfer, we will wait for
 185          * XferNotReady(STATUS).
 186          */
 187         if (dwc->three_stage_setup) {
 188                 unsigned        direction;
 189
 190                 direction = dwc->ep0_expect_in;
 191                 dwc->ep0state = EP0_DATA_PHASE;
 192
 193                 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
 194
 195                 dep->flags &= ~DWC3_EP0_DIR_IN;
 196         }
 197
 198         return 0;
 199 }
 200
 201 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
 202                 gfp_t gfp_flags)
 203 {
 204         struct dwc3_request             *req = to_dwc3_request(request);
 205         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 206         struct dwc3                     *dwc = dep->dwc;
 207
 208         unsigned long                   flags;
 209
 210         int                             ret;
 211
 212         spin_lock_irqsave(&dwc->lock, flags);
 213         if (!dep->endpoint.desc) {
 214                 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
 215                                 dep->name);
 216                 ret = -ESHUTDOWN;
 217                 goto out;
 218         }
 219
 220         /* we share one TRB for ep0/1 */
 221         if (!list_empty(&dep->pending_list)) {
 222                 ret = -EBUSY;
 223                 goto out;
 224         }
 225
 226         ret = __dwc3_gadget_ep0_queue(dep, req);
 227
 228 out:
 229         spin_unlock_irqrestore(&dwc->lock, flags);
 230
 231         return ret;
 232 }
 233
 234 static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
 235 {
 236         struct dwc3_ep          *dep;
 237
 238         /* reinitialize physical ep1 */
 239         dep = dwc->eps[1];
 240         dep->flags = DWC3_EP_ENABLED;
 241
 242         /* stall is always issued on EP0 */
 243         dep = dwc->eps[0];
 244         __dwc3_gadget_ep_set_halt(dep, 1, false);
 245         dep->flags = DWC3_EP_ENABLED;
 246         dwc->delayed_status = false;
 247
 248         if (!list_empty(&dep->pending_list)) {
 249                 struct dwc3_request     *req;
 250
 251                 req = next_request(&dep->pending_list);
 252                 dwc3_gadget_giveback(dep, req, -ECONNRESET);
 253         }
 254
 255         dwc->ep0state = EP0_SETUP_PHASE;
 256         dwc3_ep0_out_start(dwc);
 257 }
 258
 259 int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
 260 {
 261         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 262         struct dwc3                     *dwc = dep->dwc;
 263
 264         dwc3_ep0_stall_and_restart(dwc);
 265
 266         return 0;
 267 }
 268
 269 int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
 270 {
 271         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 272         struct dwc3                     *dwc = dep->dwc;
 273         unsigned long                   flags;
 274         int                             ret;
 275
 276         spin_lock_irqsave(&dwc->lock, flags);
 277         ret = __dwc3_gadget_ep0_set_halt(ep, value);
 278         spin_unlock_irqrestore(&dwc->lock, flags);
 279
 280         return ret;
 281 }
 282
 283 void dwc3_ep0_out_start(struct dwc3 *dwc)
 284 {
 285         int                             ret;
 286
 287         complete(&dwc->ep0_in_setup);
 288
 289         ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8,
 290                         DWC3_TRBCTL_CONTROL_SETUP, false);
 291         WARN_ON(ret < 0);
 292 }
 293
 294 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
 295 {
 296         struct dwc3_ep          *dep;
 297         u32                     windex = le16_to_cpu(wIndex_le);
 298         u32                     epnum;
 299
 300         epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
 301         if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
 302                 epnum |= 1;
 303
 304         dep = dwc->eps[epnum];
 305         if (dep->flags & DWC3_EP_ENABLED)
 306                 return dep;
 307
 308         return NULL;
 309 }
 310
 311 static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
 312 {
 313 }
 314 /*
 315  * ch 9.4.5
 316  */
 317 static int dwc3_ep0_handle_status(struct dwc3 *dwc,
 318                 struct usb_ctrlrequest *ctrl)
 319 {
 320         struct dwc3_ep          *dep;
 321         u32                     recip;
 322         u32                     reg;
 323         u16                     usb_status = 0;
 324         __le16                  *response_pkt;
 325
 326         recip = ctrl->bRequestType & USB_RECIP_MASK;
 327         switch (recip) {
 328         case USB_RECIP_DEVICE:
 329                 /*
 330                  * LTM will be set once we know how to set this in HW.
 331                  */
 332                 usb_status |= dwc->gadget.is_selfpowered;
 333
 334                 if ((dwc->speed == DWC3_DSTS_SUPERSPEED) ||
 335                     (dwc->speed == DWC3_DSTS_SUPERSPEED_PLUS)) {
 336                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 337                         if (reg & DWC3_DCTL_INITU1ENA)
 338                                 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
 339                         if (reg & DWC3_DCTL_INITU2ENA)
 340                                 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
 341                 }
 342
 343                 break;
 344
 345         case USB_RECIP_INTERFACE:
 346                 /*
 347                  * Function Remote Wake Capable D0
 348                  * Function Remote Wakeup       D1
 349                  */
 350                 break;
 351
 352         case USB_RECIP_ENDPOINT:
 353                 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
 354                 if (!dep)
 355                         return -EINVAL;
 356
 357                 if (dep->flags & DWC3_EP_STALL)
 358                         usb_status = 1 << USB_ENDPOINT_HALT;
 359                 break;
 360         default:
 361                 return -EINVAL;
 362         }
 363
 364         response_pkt = (__le16 *) dwc->setup_buf;
 365         *response_pkt = cpu_to_le16(usb_status);
 366
 367         dep = dwc->eps[0];
 368         dwc->ep0_usb_req.dep = dep;
 369         dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
 370         dwc->ep0_usb_req.request.buf = dwc->setup_buf;
 371         dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
 372
 373         return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
 374 }
 375
 376 static int dwc3_ep0_handle_u1(struct dwc3 *dwc, enum usb_device_state state,
 377                 int set)
 378 {
 379         u32 reg;
 380
 381         if (state != USB_STATE_CONFIGURED)
 382                 return -EINVAL;
 383         if ((dwc->speed != DWC3_DSTS_SUPERSPEED) &&
 384                         (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))
 385                 return -EINVAL;
 386
 387         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 388         if (set)
 389                 reg |= DWC3_DCTL_INITU1ENA;
 390         else
 391                 reg &= ~DWC3_DCTL_INITU1ENA;
 392         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 393
 394         return 0;
 395 }
 396
 397 static int dwc3_ep0_handle_u2(struct dwc3 *dwc, enum usb_device_state state,
 398                 int set)
 399 {
 400         u32 reg;
 401
 402
 403         if (state != USB_STATE_CONFIGURED)
 404                 return -EINVAL;
 405         if ((dwc->speed != DWC3_DSTS_SUPERSPEED) &&
 406                         (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))
 407                 return -EINVAL;
 408
 409         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 410         if (set)
 411                 reg |= DWC3_DCTL_INITU2ENA;
 412         else
 413                 reg &= ~DWC3_DCTL_INITU2ENA;
 414         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 415
 416         return 0;
 417 }
 418
 419 static int dwc3_ep0_handle_test(struct dwc3 *dwc, enum usb_device_state state,
 420                 u32 wIndex, int set)
 421 {
 422         if ((wIndex & 0xff) != 0)
 423                 return -EINVAL;
 424         if (!set)
 425                 return -EINVAL;
 426
 427         switch (wIndex >> 8) {
 428         case TEST_J:
 429         case TEST_K:
 430         case TEST_SE0_NAK:
 431         case TEST_PACKET:
 432         case TEST_FORCE_EN:
 433                 dwc->test_mode_nr = wIndex >> 8;
 434                 dwc->test_mode = true;
 435                 break;
 436         default:
 437                 return -EINVAL;
 438         }
 439
 440         return 0;
 441 }
 442
 443 static int dwc3_ep0_handle_device(struct dwc3 *dwc,
 444                 struct usb_ctrlrequest *ctrl, int set)
 445 {
 446         enum usb_device_state   state;
 447         u32                     wValue;
 448         u32                     wIndex;
 449         int                     ret = 0;
 450
 451         wValue = le16_to_cpu(ctrl->wValue);
 452         wIndex = le16_to_cpu(ctrl->wIndex);
 453         state = dwc->gadget.state;
 454
 455         switch (wValue) {
 456         case USB_DEVICE_REMOTE_WAKEUP:
 457                 break;
 458         /*
 459          * 9.4.1 says only only for SS, in AddressState only for
 460          * default control pipe
 461          */
 462         case USB_DEVICE_U1_ENABLE:
 463                 ret = dwc3_ep0_handle_u1(dwc, state, set);
 464                 break;
 465         case USB_DEVICE_U2_ENABLE:
 466                 ret = dwc3_ep0_handle_u2(dwc, state, set);
 467                 break;
 468         case USB_DEVICE_LTM_ENABLE:
 469                 ret = -EINVAL;
 470                 break;
 471         case USB_DEVICE_TEST_MODE:
 472                 ret = dwc3_ep0_handle_test(dwc, state, wIndex, set);
 473                 break;
 474         default:
 475                 ret = -EINVAL;
 476         }
 477
 478         return ret;
 479 }
 480
 481 static int dwc3_ep0_handle_intf(struct dwc3 *dwc,
 482                 struct usb_ctrlrequest *ctrl, int set)
 483 {
 484         enum usb_device_state   state;
 485         u32                     wValue;
 486         u32                     wIndex;
 487         int                     ret = 0;
 488
 489         wValue = le16_to_cpu(ctrl->wValue);
 490         wIndex = le16_to_cpu(ctrl->wIndex);
 491         state = dwc->gadget.state;
 492
 493         switch (wValue) {
 494         case USB_INTRF_FUNC_SUSPEND:
 495                 /*
 496                  * REVISIT: Ideally we would enable some low power mode here,
 497                  * however it's unclear what we should be doing here.
 498                  *
 499                  * For now, we're not doing anything, just making sure we return
 500                  * 0 so USB Command Verifier tests pass without any errors.
 501                  */
 502                 break;
 503         default:
 504                 ret = -EINVAL;
 505         }
 506
 507         return ret;
 508 }
 509
 510 static int dwc3_ep0_handle_endpoint(struct dwc3 *dwc,
 511                 struct usb_ctrlrequest *ctrl, int set)
 512 {
 513         struct dwc3_ep          *dep;
 514         enum usb_device_state   state;
 515         u32                     wValue;
 516         u32                     wIndex;
 517         int                     ret;
 518
 519         wValue = le16_to_cpu(ctrl->wValue);
 520         wIndex = le16_to_cpu(ctrl->wIndex);
 521         state = dwc->gadget.state;
 522
 523         switch (wValue) {
 524         case USB_ENDPOINT_HALT:
 525                 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
 526                 if (!dep)
 527                         return -EINVAL;
 528
 529                 if (set == 0 && (dep->flags & DWC3_EP_WEDGE))
 530                         break;
 531
 532                 ret = __dwc3_gadget_ep_set_halt(dep, set, true);
 533                 if (ret)
 534                         return -EINVAL;
 535                 break;
 536         default:
 537                 return -EINVAL;
 538         }
 539
 540         return 0;
 541 }
 542
 543 static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
 544                 struct usb_ctrlrequest *ctrl, int set)
 545 {
 546         u32                     recip;
 547         int                     ret;
 548         enum usb_device_state   state;
 549
 550         recip = ctrl->bRequestType & USB_RECIP_MASK;
 551         state = dwc->gadget.state;
 552
 553         switch (recip) {
 554         case USB_RECIP_DEVICE:
 555                 ret = dwc3_ep0_handle_device(dwc, ctrl, set);
 556                 break;
 557         case USB_RECIP_INTERFACE:
 558                 ret = dwc3_ep0_handle_intf(dwc, ctrl, set);
 559                 break;
 560         case USB_RECIP_ENDPOINT:
 561                 ret = dwc3_ep0_handle_endpoint(dwc, ctrl, set);
 562                 break;
 563         default:
 564                 ret = -EINVAL;
 565         }
 566
 567         return ret;
 568 }
 569
 570 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 571 {
 572         enum usb_device_state state = dwc->gadget.state;
 573         u32 addr;
 574         u32 reg;
 575
 576         addr = le16_to_cpu(ctrl->wValue);
 577         if (addr > 127) {
 578                 dev_err(dwc->dev, "invalid device address %d\n", addr);
 579                 return -EINVAL;
 580         }
 581
 582         if (state == USB_STATE_CONFIGURED) {
 583                 dev_err(dwc->dev, "can't SetAddress() from Configured State\n");
 584                 return -EINVAL;
 585         }
 586
 587         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
 588         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
 589         reg |= DWC3_DCFG_DEVADDR(addr);
 590         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
 591
 592         if (addr)
 593                 usb_gadget_set_state(&dwc->gadget, USB_STATE_ADDRESS);
 594         else
 595                 usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT);
 596
 597         return 0;
 598 }
 599
 600 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 601 {
 602         int ret;
 603
 604         spin_unlock(&dwc->lock);
 605         ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
 606         spin_lock(&dwc->lock);
 607         return ret;
 608 }
 609
 610 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 611 {
 612         enum usb_device_state state = dwc->gadget.state;
 613         u32 cfg;
 614         int ret;
 615         u32 reg;
 616
 617         cfg = le16_to_cpu(ctrl->wValue);
 618
 619         switch (state) {
 620         case USB_STATE_DEFAULT:
 621                 return -EINVAL;
 622
 623         case USB_STATE_ADDRESS:
 624                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 625                 /* if the cfg matches and the cfg is non zero */
 626                 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
 627
 628                         /*
 629                          * only change state if set_config has already
 630                          * been processed. If gadget driver returns
 631                          * USB_GADGET_DELAYED_STATUS, we will wait
 632                          * to change the state on the next usb_ep_queue()
 633                          */
 634                         if (ret == 0)
 635                                 usb_gadget_set_state(&dwc->gadget,
 636                                                 USB_STATE_CONFIGURED);
 637
 638                         /*
 639                          * Enable transition to U1/U2 state when
 640                          * nothing is pending from application.
 641                          */
 642                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 643                         reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA);
 644                         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 645                 }
 646                 break;
 647
 648         case USB_STATE_CONFIGURED:
 649                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 650                 if (!cfg && !ret)
 651                         usb_gadget_set_state(&dwc->gadget,
 652                                         USB_STATE_ADDRESS);
 653                 break;
 654         default:
 655                 ret = -EINVAL;
 656         }
 657         return ret;
 658 }
 659
 660 static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
 661 {
 662         struct dwc3_ep  *dep = to_dwc3_ep(ep);
 663         struct dwc3     *dwc = dep->dwc;
 664
 665         u32             param = 0;
 666         u32             reg;
 667
 668         struct timing {
 669                 u8      u1sel;
 670                 u8      u1pel;
 671                 __le16  u2sel;
 672                 __le16  u2pel;
 673         } __packed timing;
 674
 675         int             ret;
 676
 677         memcpy(&timing, req->buf, sizeof(timing));
 678
 679         dwc->u1sel = timing.u1sel;
 680         dwc->u1pel = timing.u1pel;
 681         dwc->u2sel = le16_to_cpu(timing.u2sel);
 682         dwc->u2pel = le16_to_cpu(timing.u2pel);
 683
 684         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 685         if (reg & DWC3_DCTL_INITU2ENA)
 686                 param = dwc->u2pel;
 687         if (reg & DWC3_DCTL_INITU1ENA)
 688                 param = dwc->u1pel;
 689
 690         /*
 691          * According to Synopsys Databook, if parameter is
 692          * greater than 125, a value of zero should be
 693          * programmed in the register.
 694          */
 695         if (param > 125)
 696                 param = 0;
 697
 698         /* now that we have the time, issue DGCMD Set Sel */
 699         ret = dwc3_send_gadget_generic_command(dwc,
 700                         DWC3_DGCMD_SET_PERIODIC_PAR, param);
 701         WARN_ON(ret < 0);
 702 }
 703
 704 static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 705 {
 706         struct dwc3_ep  *dep;
 707         enum usb_device_state state = dwc->gadget.state;
 708         u16             wLength;
 709         u16             wValue;
 710
 711         if (state == USB_STATE_DEFAULT)
 712                 return -EINVAL;
 713
 714         wValue = le16_to_cpu(ctrl->wValue);
 715         wLength = le16_to_cpu(ctrl->wLength);
 716
 717         if (wLength != 6) {
 718                 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
 719                                 wLength);
 720                 return -EINVAL;
 721         }
 722
 723         /*
 724          * To handle Set SEL we need to receive 6 bytes from Host. So let's
 725          * queue a usb_request for 6 bytes.
 726          *
 727          * Remember, though, this controller can't handle non-wMaxPacketSize
 728          * aligned transfers on the OUT direction, so we queue a request for
 729          * wMaxPacketSize instead.
 730          */
 731         dep = dwc->eps[0];
 732         dwc->ep0_usb_req.dep = dep;
 733         dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
 734         dwc->ep0_usb_req.request.buf = dwc->setup_buf;
 735         dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
 736
 737         return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
 738 }
 739
 740 static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 741 {
 742         u16             wLength;
 743         u16             wValue;
 744         u16             wIndex;
 745
 746         wValue = le16_to_cpu(ctrl->wValue);
 747         wLength = le16_to_cpu(ctrl->wLength);
 748         wIndex = le16_to_cpu(ctrl->wIndex);
 749
 750         if (wIndex || wLength)
 751                 return -EINVAL;
 752
 753         /*
 754          * REVISIT It's unclear from Databook what to do with this
 755          * value. For now, just cache it.
 756          */
 757         dwc->isoch_delay = wValue;
 758
 759         return 0;
 760 }
 761
 762 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 763 {
 764         int ret;
 765
 766         switch (ctrl->bRequest) {
 767         case USB_REQ_GET_STATUS:
 768                 ret = dwc3_ep0_handle_status(dwc, ctrl);
 769                 break;
 770         case USB_REQ_CLEAR_FEATURE:
 771                 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
 772                 break;
 773         case USB_REQ_SET_FEATURE:
 774                 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
 775                 break;
 776         case USB_REQ_SET_ADDRESS:
 777                 ret = dwc3_ep0_set_address(dwc, ctrl);
 778                 break;
 779         case USB_REQ_SET_CONFIGURATION:
 780                 ret = dwc3_ep0_set_config(dwc, ctrl);
 781                 break;
 782         case USB_REQ_SET_SEL:
 783                 ret = dwc3_ep0_set_sel(dwc, ctrl);
 784                 break;
 785         case USB_REQ_SET_ISOCH_DELAY:
 786                 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
 787                 break;
 788         default:
 789                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 790                 break;
 791         }
 792
 793         return ret;
 794 }
 795
 796 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
 797                 const struct dwc3_event_depevt *event)
 798 {
 799         struct usb_ctrlrequest *ctrl = dwc->ctrl_req;
 800         int ret = -EINVAL;
 801         u32 len;
 802
 803         if (!dwc->gadget_driver)
 804                 goto out;
 805
 806         trace_dwc3_ctrl_req(ctrl);
 807
 808         len = le16_to_cpu(ctrl->wLength);
 809         if (!len) {
 810                 dwc->three_stage_setup = false;
 811                 dwc->ep0_expect_in = false;
 812                 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
 813         } else {
 814                 dwc->three_stage_setup = true;
 815                 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
 816                 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
 817         }
 818
 819         if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
 820                 ret = dwc3_ep0_std_request(dwc, ctrl);
 821         else
 822                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 823
 824         if (ret == USB_GADGET_DELAYED_STATUS)
 825                 dwc->delayed_status = true;
 826
 827 out:
 828         if (ret < 0)
 829                 dwc3_ep0_stall_and_restart(dwc);
 830 }
 831
 832 static void dwc3_ep0_complete_data(struct dwc3 *dwc,
 833                 const struct dwc3_event_depevt *event)
 834 {
 835         struct dwc3_request     *r = NULL;
 836         struct usb_request      *ur;
 837         struct dwc3_trb         *trb;
 838         struct dwc3_ep          *ep0;
 839         unsigned                transfer_size = 0;
 840         unsigned                maxp;
 841         unsigned                remaining_ur_length;
 842         void                    *buf;
 843         u32                     transferred = 0;
 844         u32                     status;
 845         u32                     length;
 846         u8                      epnum;
 847
 848         epnum = event->endpoint_number;
 849         ep0 = dwc->eps[0];
 850
 851         dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
 852
 853         trb = dwc->ep0_trb;
 854
 855         trace_dwc3_complete_trb(ep0, trb);
 856
 857         r = next_request(&ep0->pending_list);
 858         if (!r)
 859                 return;
 860
 861         status = DWC3_TRB_SIZE_TRBSTS(trb->size);
 862         if (status == DWC3_TRBSTS_SETUP_PENDING) {
 863                 dwc->setup_packet_pending = true;
 864                 if (r)
 865                         dwc3_gadget_giveback(ep0, r, -ECONNRESET);
 866
 867                 return;
 868         }
 869
 870         ur = &r->request;
 871         buf = ur->buf;
 872         remaining_ur_length = ur->length;
 873
 874         length = trb->size & DWC3_TRB_SIZE_MASK;
 875
 876         maxp = ep0->endpoint.maxpacket;
 877
 878         if (dwc->ep0_bounced) {
 879                 /*
 880                  * Handle the first TRB before handling the bounce buffer if
 881                  * the request length is greater than the bounce buffer size
 882                  */
 883                 if (ur->length > DWC3_EP0_BOUNCE_SIZE) {
 884                         transfer_size = ALIGN(ur->length - maxp, maxp);
 885                         transferred = transfer_size - length;
 886                         buf = (u8 *)buf + transferred;
 887                         ur->actual += transferred;
 888                         remaining_ur_length -= transferred;
 889
 890                         trb++;
 891                         length = trb->size & DWC3_TRB_SIZE_MASK;
 892
 893                         ep0->trb_enqueue = 0;
 894                 }
 895
 896                 transfer_size = roundup((ur->length - transfer_size),
 897                                         maxp);
 898
 899                 transferred = min_t(u32, remaining_ur_length,
 900                                     transfer_size - length);
 901                 memcpy(buf, dwc->ep0_bounce, transferred);
 902         } else {
 903                 transferred = ur->length - length;
 904         }
 905
 906         ur->actual += transferred;
 907
 908         if ((epnum & 1) && ur->actual < ur->length) {
 909                 /* for some reason we did not get everything out */
 910
 911                 dwc3_ep0_stall_and_restart(dwc);
 912         } else {
 913                 dwc3_gadget_giveback(ep0, r, 0);
 914
 915                 if (IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) &&
 916                                 ur->length && ur->zero) {
 917                         int ret;
 918
 919                         dwc->ep0_next_event = DWC3_EP0_COMPLETE;
 920
 921                         ret = dwc3_ep0_start_trans(dwc, epnum,
 922                                         dwc->ctrl_req_addr, 0,
 923                                         DWC3_TRBCTL_CONTROL_DATA, false);
 924                         WARN_ON(ret < 0);
 925                 }
 926         }
 927 }
 928
 929 static void dwc3_ep0_complete_status(struct dwc3 *dwc,
 930                 const struct dwc3_event_depevt *event)
 931 {
 932         struct dwc3_request     *r;
 933         struct dwc3_ep          *dep;
 934         struct dwc3_trb         *trb;
 935         u32                     status;
 936
 937         dep = dwc->eps[0];
 938         trb = dwc->ep0_trb;
 939
 940         trace_dwc3_complete_trb(dep, trb);
 941
 942         if (!list_empty(&dep->pending_list)) {
 943                 r = next_request(&dep->pending_list);
 944
 945                 dwc3_gadget_giveback(dep, r, 0);
 946         }
 947
 948         if (dwc->test_mode) {
 949                 int ret;
 950
 951                 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
 952                 if (ret < 0) {
 953                         dev_err(dwc->dev, "invalid test #%d\n",
 954                                         dwc->test_mode_nr);
 955                         dwc3_ep0_stall_and_restart(dwc);
 956                         return;
 957                 }
 958         }
 959
 960         status = DWC3_TRB_SIZE_TRBSTS(trb->size);
 961         if (status == DWC3_TRBSTS_SETUP_PENDING)
 962                 dwc->setup_packet_pending = true;
 963
 964         dwc->ep0state = EP0_SETUP_PHASE;
 965         dwc3_ep0_out_start(dwc);
 966 }
 967
 968 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
 969                         const struct dwc3_event_depevt *event)
 970 {
 971         struct dwc3_ep          *dep = dwc->eps[event->endpoint_number];
 972
 973         dep->flags &= ~DWC3_EP_BUSY;
 974         dep->resource_index = 0;
 975         dwc->setup_packet_pending = false;
 976
 977         switch (dwc->ep0state) {
 978         case EP0_SETUP_PHASE:
 979                 dwc3_ep0_inspect_setup(dwc, event);
 980                 break;
 981
 982         case EP0_DATA_PHASE:
 983                 dwc3_ep0_complete_data(dwc, event);
 984                 break;
 985
 986         case EP0_STATUS_PHASE:
 987                 dwc3_ep0_complete_status(dwc, event);
 988                 break;
 989         default:
 990                 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
 991         }
 992 }
 993
 994 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
 995                 struct dwc3_ep *dep, struct dwc3_request *req)
 996 {
 997         int                     ret;
 998
 999         req->direction = !!dep->number;
1000
1001         if (req->request.length == 0) {
1002                 ret = dwc3_ep0_start_trans(dwc, dep->number,
1003                                 dwc->ctrl_req_addr, 0,
1004                                 DWC3_TRBCTL_CONTROL_DATA, false);
1005         } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket)
1006                         && (dep->number == 0)) {
1007                 u32     transfer_size = 0;
1008                 u32     maxpacket;
1009
1010                 ret = usb_gadget_map_request_by_dev(dwc->sysdev,
1011                                 &req->request, dep->number);
1012                 if (ret)
1013                         return;
1014
1015                 maxpacket = dep->endpoint.maxpacket;
1016
1017                 if (req->request.length > DWC3_EP0_BOUNCE_SIZE) {
1018                         transfer_size = ALIGN(req->request.length - maxpacket,
1019                                               maxpacket);
1020                         ret = dwc3_ep0_start_trans(dwc, dep->number,
1021                                                    req->request.dma,
1022                                                    transfer_size,
1023                                                    DWC3_TRBCTL_CONTROL_DATA,
1024                                                    true);
1025                 }
1026
1027                 transfer_size = roundup((req->request.length - transfer_size),
1028                                         maxpacket);
1029
1030                 dwc->ep0_bounced = true;
1031
1032                 ret = dwc3_ep0_start_trans(dwc, dep->number,
1033                                 dwc->ep0_bounce_addr, transfer_size,
1034                                 DWC3_TRBCTL_CONTROL_DATA, false);
1035         } else {
1036                 ret = usb_gadget_map_request_by_dev(dwc->sysdev,
1037                                 &req->request, dep->number);
1038                 if (ret)
1039                         return;
1040
1041                 ret = dwc3_ep0_start_trans(dwc, dep->number, req->request.dma,
1042                                 req->request.length, DWC3_TRBCTL_CONTROL_DATA,
1043                                 false);
1044         }
1045
1046         WARN_ON(ret < 0);
1047 }
1048
1049 static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
1050 {
1051         struct dwc3             *dwc = dep->dwc;
1052         u32                     type;
1053
1054         type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
1055                 : DWC3_TRBCTL_CONTROL_STATUS2;
1056
1057         return dwc3_ep0_start_trans(dwc, dep->number,
1058                         dwc->ctrl_req_addr, 0, type, false);
1059 }
1060
1061 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
1062 {
1063         WARN_ON(dwc3_ep0_start_control_status(dep));
1064 }
1065
1066 static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
1067                 const struct dwc3_event_depevt *event)
1068 {
1069         struct dwc3_ep          *dep = dwc->eps[event->endpoint_number];
1070
1071         __dwc3_ep0_do_control_status(dwc, dep);
1072 }
1073
1074 static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
1075 {
1076         struct dwc3_gadget_ep_cmd_params params;
1077         u32                     cmd;
1078         int                     ret;
1079
1080         if (!dep->resource_index)
1081                 return;
1082
1083         cmd = DWC3_DEPCMD_ENDTRANSFER;
1084         cmd |= DWC3_DEPCMD_CMDIOC;
1085         cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1086         memset(&params, 0, sizeof(params));
1087         ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
1088         WARN_ON_ONCE(ret);
1089         dep->resource_index = 0;
1090 }
1091
1092 static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
1093                 const struct dwc3_event_depevt *event)
1094 {
1095         switch (event->status) {
1096         case DEPEVT_STATUS_CONTROL_DATA:
1097                 /*
1098                  * We already have a DATA transfer in the controller's cache,
1099                  * if we receive a XferNotReady(DATA) we will ignore it, unless
1100                  * it's for the wrong direction.
1101                  *
1102                  * In that case, we must issue END_TRANSFER command to the Data
1103                  * Phase we already have started and issue SetStall on the
1104                  * control endpoint.
1105                  */
1106                 if (dwc->ep0_expect_in != event->endpoint_number) {
1107                         struct dwc3_ep  *dep = dwc->eps[dwc->ep0_expect_in];
1108
1109                         dev_err(dwc->dev, "unexpected direction for Data Phase\n");
1110                         dwc3_ep0_end_control_data(dwc, dep);
1111                         dwc3_ep0_stall_and_restart(dwc);
1112                         return;
1113                 }
1114
1115                 break;
1116
1117         case DEPEVT_STATUS_CONTROL_STATUS:
1118                 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
1119                         return;
1120
1121                 dwc->ep0state = EP0_STATUS_PHASE;
1122
1123                 if (dwc->delayed_status) {
1124                         WARN_ON_ONCE(event->endpoint_number != 1);
1125                         return;
1126                 }
1127
1128                 dwc3_ep0_do_control_status(dwc, event);
1129         }
1130 }
1131
1132 void dwc3_ep0_interrupt(struct dwc3 *dwc,
1133                 const struct dwc3_event_depevt *event)
1134 {
1135         switch (event->endpoint_event) {
1136         case DWC3_DEPEVT_XFERCOMPLETE:
1137                 dwc3_ep0_xfer_complete(dwc, event);
1138                 break;
1139
1140         case DWC3_DEPEVT_XFERNOTREADY:
1141                 dwc3_ep0_xfernotready(dwc, event);
1142                 break;
1143
1144         case DWC3_DEPEVT_XFERINPROGRESS:
1145         case DWC3_DEPEVT_RXTXFIFOEVT:
1146         case DWC3_DEPEVT_STREAMEVT:
1147         case DWC3_DEPEVT_EPCMDCMPLT:
1148                 break;
1149         }
1150 }