drivers/usb/dwc3/gadget.c

   1 /**
   2  * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
   3  *
   4  * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/gadget.c) and ported
  10  * to uboot.
  11  *
  12  * commit 8e74475b0e : usb: dwc3: gadget: use udc-core's reset notifier
  13  *
  14  * SPDX-License-Identifier:     GPL-2.0
  15  */
  16
  17 #include <common.h>
  18 #include <malloc.h>
  19 #include <asm/dma-mapping.h>
  20 #include <usb/lin_gadget_compat.h>
  21 #include <linux/list.h>
  22
  23 #include <linux/usb/ch9.h>
  24 #include <linux/usb/gadget.h>
  25 #include <asm/arch/sys_proto.h>
  26
  27 #include "core.h"
  28 #include "gadget.h"
  29 #include "io.h"
  30
  31 #include "linux-compat.h"
  32
  33 /**
  34  * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
  35  * @dwc: pointer to our context structure
  36  * @mode: the mode to set (J, K SE0 NAK, Force Enable)
  37  *
  38  * Caller should take care of locking. This function will
  39  * return 0 on success or -EINVAL if wrong Test Selector
  40  * is passed
  41  */
  42 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
  43 {
  44         u32             reg;
  45
  46         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  47         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
  48
  49         switch (mode) {
  50         case TEST_J:
  51         case TEST_K:
  52         case TEST_SE0_NAK:
  53         case TEST_PACKET:
  54         case TEST_FORCE_EN:
  55                 reg |= mode << 1;
  56                 break;
  57         default:
  58                 return -EINVAL;
  59         }
  60
  61         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  62
  63         return 0;
  64 }
  65
  66 /**
  67  * dwc3_gadget_get_link_state - Gets current state of USB Link
  68  * @dwc: pointer to our context structure
  69  *
  70  * Caller should take care of locking. This function will
  71  * return the link state on success (>= 0) or -ETIMEDOUT.
  72  */
  73 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
  74 {
  75         u32             reg;
  76
  77         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
  78
  79         return DWC3_DSTS_USBLNKST(reg);
  80 }
  81
  82 /**
  83  * dwc3_gadget_set_link_state - Sets USB Link to a particular State
  84  * @dwc: pointer to our context structure
  85  * @state: the state to put link into
  86  *
  87  * Caller should take care of locking. This function will
  88  * return 0 on success or -ETIMEDOUT.
  89  */
  90 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
  91 {
  92         int             retries = 10000;
  93         u32             reg;
  94
  95         /*
  96          * Wait until device controller is ready. Only applies to 1.94a and
  97          * later RTL.
  98          */
  99         if (dwc->revision >= DWC3_REVISION_194A) {
 100                 while (--retries) {
 101                         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 102                         if (reg & DWC3_DSTS_DCNRD)
 103                                 udelay(5);
 104                         else
 105                                 break;
 106                 }
 107
 108                 if (retries <= 0)
 109                         return -ETIMEDOUT;
 110         }
 111
 112         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 113         reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
 114
 115         /* set requested state */
 116         reg |= DWC3_DCTL_ULSTCHNGREQ(state);
 117         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 118
 119         /*
 120          * The following code is racy when called from dwc3_gadget_wakeup,
 121          * and is not needed, at least on newer versions
 122          */
 123         if (dwc->revision >= DWC3_REVISION_194A)
 124                 return 0;
 125
 126         /* wait for a change in DSTS */
 127         retries = 10000;
 128         while (--retries) {
 129                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 130
 131                 if (DWC3_DSTS_USBLNKST(reg) == state)
 132                         return 0;
 133
 134                 udelay(5);
 135         }
 136
 137         dev_vdbg(dwc->dev, "link state change request timed out\n");
 138
 139         return -ETIMEDOUT;
 140 }
 141
 142 /**
 143  * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
 144  * @dwc: pointer to our context structure
 145  *
 146  * This function will a best effort FIFO allocation in order
 147  * to improve FIFO usage and throughput, while still allowing
 148  * us to enable as many endpoints as possible.
 149  *
 150  * Keep in mind that this operation will be highly dependent
 151  * on the configured size for RAM1 - which contains TxFifo -,
 152  * the amount of endpoints enabled on coreConsultant tool, and
 153  * the width of the Master Bus.
 154  *
 155  * In the ideal world, we would always be able to satisfy the
 156  * following equation:
 157  *
 158  * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \
 159  * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes
 160  *
 161  * Unfortunately, due to many variables that's not always the case.
 162  */
 163 int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc)
 164 {
 165         int             last_fifo_depth = 0;
 166         int             fifo_size;
 167         int             mdwidth;
 168         int             num;
 169
 170         if (!dwc->needs_fifo_resize)
 171                 return 0;
 172
 173         mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
 174
 175         /* MDWIDTH is represented in bits, we need it in bytes */
 176         mdwidth >>= 3;
 177
 178         /*
 179          * FIXME For now we will only allocate 1 wMaxPacketSize space
 180          * for each enabled endpoint, later patches will come to
 181          * improve this algorithm so that we better use the internal
 182          * FIFO space
 183          */
 184         for (num = 0; num < dwc->num_in_eps; num++) {
 185                 /* bit0 indicates direction; 1 means IN ep */
 186                 struct dwc3_ep  *dep = dwc->eps[(num << 1) | 1];
 187                 int             mult = 1;
 188                 int             tmp;
 189
 190                 if (!(dep->flags & DWC3_EP_ENABLED))
 191                         continue;
 192
 193                 if (usb_endpoint_xfer_bulk(dep->endpoint.desc)
 194                                 || usb_endpoint_xfer_isoc(dep->endpoint.desc))
 195                         mult = 3;
 196
 197                 /*
 198                  * REVISIT: the following assumes we will always have enough
 199                  * space available on the FIFO RAM for all possible use cases.
 200                  * Make sure that's true somehow and change FIFO allocation
 201                  * accordingly.
 202                  *
 203                  * If we have Bulk or Isochronous endpoints, we want
 204                  * them to be able to be very, very fast. So we're giving
 205                  * those endpoints a fifo_size which is enough for 3 full
 206                  * packets
 207                  */
 208                 tmp = mult * (dep->endpoint.maxpacket + mdwidth);
 209                 tmp += mdwidth;
 210
 211                 fifo_size = DIV_ROUND_UP(tmp, mdwidth);
 212
 213                 fifo_size |= (last_fifo_depth << 16);
 214
 215                 dev_vdbg(dwc->dev, "%s: Fifo Addr %04x Size %d\n",
 216                                 dep->name, last_fifo_depth, fifo_size & 0xffff);
 217
 218                 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(num), fifo_size);
 219
 220                 last_fifo_depth += (fifo_size & 0xffff);
 221         }
 222
 223         return 0;
 224 }
 225
 226 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
 227                 int status)
 228 {
 229         struct dwc3                     *dwc = dep->dwc;
 230
 231         if (req->queued) {
 232                 dep->busy_slot++;
 233                 /*
 234                  * Skip LINK TRB. We can't use req->trb and check for
 235                  * DWC3_TRBCTL_LINK_TRB because it points the TRB we
 236                  * just completed (not the LINK TRB).
 237                  */
 238                 if (((dep->busy_slot & DWC3_TRB_MASK) ==
 239                         DWC3_TRB_NUM- 1) &&
 240                         usb_endpoint_xfer_isoc(dep->endpoint.desc))
 241                         dep->busy_slot++;
 242                 req->queued = false;
 243         }
 244
 245         list_del(&req->list);
 246         req->trb = NULL;
 247
 248         if (req->request.status == -EINPROGRESS)
 249                 req->request.status = status;
 250
 251         if (dwc->ep0_bounced && dep->number == 0)
 252                 dwc->ep0_bounced = false;
 253         else
 254                 usb_gadget_unmap_request(&dwc->gadget, &req->request,
 255                                 req->direction);
 256
 257         dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n",
 258                         req, dep->name, req->request.actual,
 259                         req->request.length, status);
 260
 261         spin_unlock(&dwc->lock);
 262         usb_gadget_giveback_request(&dep->endpoint, &req->request);
 263         spin_lock(&dwc->lock);
 264 }
 265
 266 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
 267 {
 268         u32             timeout = 500;
 269         u32             reg;
 270
 271         dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
 272         dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
 273
 274         do {
 275                 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
 276                 if (!(reg & DWC3_DGCMD_CMDACT)) {
 277                         dev_vdbg(dwc->dev, "Command Complete --> %d\n",
 278                                         DWC3_DGCMD_STATUS(reg));
 279                         return 0;
 280                 }
 281
 282                 /*
 283                  * We can't sleep here, because it's also called from
 284                  * interrupt context.
 285                  */
 286                 timeout--;
 287                 if (!timeout)
 288                         return -ETIMEDOUT;
 289                 udelay(1);
 290         } while (1);
 291 }
 292
 293 int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
 294                 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
 295 {
 296         u32                     timeout = 500;
 297         u32                     reg;
 298
 299         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
 300         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
 301         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
 302
 303         dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
 304         do {
 305                 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
 306                 if (!(reg & DWC3_DEPCMD_CMDACT)) {
 307                         dev_vdbg(dwc->dev, "Command Complete --> %d\n",
 308                                         DWC3_DEPCMD_STATUS(reg));
 309                         return 0;
 310                 }
 311
 312                 /*
 313                  * We can't sleep here, because it is also called from
 314                  * interrupt context.
 315                  */
 316                 timeout--;
 317                 if (!timeout)
 318                         return -ETIMEDOUT;
 319
 320                 udelay(1);
 321         } while (1);
 322 }
 323
 324 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
 325                 struct dwc3_trb *trb)
 326 {
 327         u32             offset = (char *) trb - (char *) dep->trb_pool;
 328
 329         return dep->trb_pool_dma + offset;
 330 }
 331
 332 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
 333 {
 334         if (dep->trb_pool)
 335                 return 0;
 336
 337         if (dep->number == 0 || dep->number == 1)
 338                 return 0;
 339
 340         dep->trb_pool = dma_alloc_coherent(sizeof(struct dwc3_trb) *
 341                                            DWC3_TRB_NUM,
 342                                            (unsigned long *)&dep->trb_pool_dma);
 343         if (!dep->trb_pool) {
 344                 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
 345                                 dep->name);
 346                 return -ENOMEM;
 347         }
 348
 349         return 0;
 350 }
 351
 352 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
 353 {
 354         dma_free_coherent(dep->trb_pool);
 355
 356         dep->trb_pool = NULL;
 357         dep->trb_pool_dma = 0;
 358 }
 359
 360 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
 361 {
 362         struct dwc3_gadget_ep_cmd_params params;
 363         u32                     cmd;
 364
 365         memset(&params, 0x00, sizeof(params));
 366
 367         if (dep->number != 1) {
 368                 cmd = DWC3_DEPCMD_DEPSTARTCFG;
 369                 /* XferRscIdx == 0 for ep0 and 2 for the remaining */
 370                 if (dep->number > 1) {
 371                         if (dwc->start_config_issued)
 372                                 return 0;
 373                         dwc->start_config_issued = true;
 374                         cmd |= DWC3_DEPCMD_PARAM(2);
 375                 }
 376
 377                 return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, &params);
 378         }
 379
 380         return 0;
 381 }
 382
 383 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
 384                 const struct usb_endpoint_descriptor *desc,
 385                 const struct usb_ss_ep_comp_descriptor *comp_desc,
 386                 bool ignore, bool restore)
 387 {
 388         struct dwc3_gadget_ep_cmd_params params;
 389
 390         memset(&params, 0x00, sizeof(params));
 391
 392         params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
 393                 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
 394
 395         /* Burst size is only needed in SuperSpeed mode */
 396         if (dwc->gadget.speed == USB_SPEED_SUPER) {
 397                 u32 burst = dep->endpoint.maxburst - 1;
 398
 399                 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst);
 400         }
 401
 402         if (ignore)
 403                 params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM;
 404
 405         if (restore) {
 406                 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
 407                 params.param2 |= dep->saved_state;
 408         }
 409
 410         params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
 411                 | DWC3_DEPCFG_XFER_NOT_READY_EN;
 412
 413         if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
 414                 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
 415                         | DWC3_DEPCFG_STREAM_EVENT_EN;
 416                 dep->stream_capable = true;
 417         }
 418
 419         if (!usb_endpoint_xfer_control(desc))
 420                 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
 421
 422         /*
 423          * We are doing 1:1 mapping for endpoints, meaning
 424          * Physical Endpoints 2 maps to Logical Endpoint 2 and
 425          * so on. We consider the direction bit as part of the physical
 426          * endpoint number. So USB endpoint 0x81 is 0x03.
 427          */
 428         params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
 429
 430         /*
 431          * We must use the lower 16 TX FIFOs even though
 432          * HW might have more
 433          */
 434         if (dep->direction)
 435                 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
 436
 437         if (desc->bInterval) {
 438                 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
 439                 dep->interval = 1 << (desc->bInterval - 1);
 440         }
 441
 442         return dwc3_send_gadget_ep_cmd(dwc, dep->number,
 443                         DWC3_DEPCMD_SETEPCONFIG, &params);
 444 }
 445
 446 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
 447 {
 448         struct dwc3_gadget_ep_cmd_params params;
 449
 450         memset(&params, 0x00, sizeof(params));
 451
 452         params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
 453
 454         return dwc3_send_gadget_ep_cmd(dwc, dep->number,
 455                         DWC3_DEPCMD_SETTRANSFRESOURCE, &params);
 456 }
 457
 458 /**
 459  * __dwc3_gadget_ep_enable - Initializes a HW endpoint
 460  * @dep: endpoint to be initialized
 461  * @desc: USB Endpoint Descriptor
 462  *
 463  * Caller should take care of locking
 464  */
 465 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
 466                 const struct usb_endpoint_descriptor *desc,
 467                 const struct usb_ss_ep_comp_descriptor *comp_desc,
 468                 bool ignore, bool restore)
 469 {
 470         struct dwc3             *dwc = dep->dwc;
 471         u32                     reg;
 472         int                     ret;
 473
 474         dev_vdbg(dwc->dev, "Enabling %s\n", dep->name);
 475
 476         if (!(dep->flags & DWC3_EP_ENABLED)) {
 477                 ret = dwc3_gadget_start_config(dwc, dep);
 478                 if (ret)
 479                         return ret;
 480         }
 481
 482         ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore,
 483                         restore);
 484         if (ret)
 485                 return ret;
 486
 487         if (!(dep->flags & DWC3_EP_ENABLED)) {
 488                 struct dwc3_trb *trb_st_hw;
 489                 struct dwc3_trb *trb_link;
 490
 491                 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
 492                 if (ret)
 493                         return ret;
 494
 495                 dep->endpoint.desc = desc;
 496                 dep->comp_desc = comp_desc;
 497                 dep->type = usb_endpoint_type(desc);
 498                 dep->flags |= DWC3_EP_ENABLED;
 499
 500                 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 501                 reg |= DWC3_DALEPENA_EP(dep->number);
 502                 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 503
 504                 if (!usb_endpoint_xfer_isoc(desc))
 505                         return 0;
 506
 507                 /* Link TRB for ISOC. The HWO bit is never reset */
 508                 trb_st_hw = &dep->trb_pool[0];
 509
 510                 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
 511                 memset(trb_link, 0, sizeof(*trb_link));
 512
 513                 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 514                 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 515                 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
 516                 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
 517         }
 518
 519         return 0;
 520 }
 521
 522 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
 523 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
 524 {
 525         struct dwc3_request             *req;
 526
 527         if (!list_empty(&dep->req_queued)) {
 528                 dwc3_stop_active_transfer(dwc, dep->number, true);
 529
 530                 /* - giveback all requests to gadget driver */
 531                 while (!list_empty(&dep->req_queued)) {
 532                         req = next_request(&dep->req_queued);
 533
 534                         dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 535                 }
 536         }
 537
 538         while (!list_empty(&dep->request_list)) {
 539                 req = next_request(&dep->request_list);
 540
 541                 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 542         }
 543 }
 544
 545 /**
 546  * __dwc3_gadget_ep_disable - Disables a HW endpoint
 547  * @dep: the endpoint to disable
 548  *
 549  * This function also removes requests which are currently processed ny the
 550  * hardware and those which are not yet scheduled.
 551  * Caller should take care of locking.
 552  */
 553 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
 554 {
 555         struct dwc3             *dwc = dep->dwc;
 556         u32                     reg;
 557
 558         dwc3_remove_requests(dwc, dep);
 559
 560         /* make sure HW endpoint isn't stalled */
 561         if (dep->flags & DWC3_EP_STALL)
 562                 __dwc3_gadget_ep_set_halt(dep, 0, false);
 563
 564         reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 565         reg &= ~DWC3_DALEPENA_EP(dep->number);
 566         dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 567
 568         dep->stream_capable = false;
 569         dep->endpoint.desc = NULL;
 570         dep->comp_desc = NULL;
 571         dep->type = 0;
 572         dep->flags = 0;
 573
 574         return 0;
 575 }
 576
 577 /* -------------------------------------------------------------------------- */
 578
 579 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
 580                 const struct usb_endpoint_descriptor *desc)
 581 {
 582         return -EINVAL;
 583 }
 584
 585 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
 586 {
 587         return -EINVAL;
 588 }
 589
 590 /* -------------------------------------------------------------------------- */
 591
 592 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
 593                 const struct usb_endpoint_descriptor *desc)
 594 {
 595         struct dwc3_ep                  *dep;
 596         unsigned long                   flags;
 597         int                             ret;
 598
 599         if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
 600                 pr_debug("dwc3: invalid parameters\n");
 601                 return -EINVAL;
 602         }
 603
 604         if (!desc->wMaxPacketSize) {
 605                 pr_debug("dwc3: missing wMaxPacketSize\n");
 606                 return -EINVAL;
 607         }
 608
 609         dep = to_dwc3_ep(ep);
 610
 611         if (dep->flags & DWC3_EP_ENABLED) {
 612                 WARN(true, "%s is already enabled\n",
 613                                 dep->name);
 614                 return 0;
 615         }
 616
 617         switch (usb_endpoint_type(desc)) {
 618         case USB_ENDPOINT_XFER_CONTROL:
 619                 strlcat(dep->name, "-control", sizeof(dep->name));
 620                 break;
 621         case USB_ENDPOINT_XFER_ISOC:
 622                 strlcat(dep->name, "-isoc", sizeof(dep->name));
 623                 break;
 624         case USB_ENDPOINT_XFER_BULK:
 625                 strlcat(dep->name, "-bulk", sizeof(dep->name));
 626                 break;
 627         case USB_ENDPOINT_XFER_INT:
 628                 strlcat(dep->name, "-int", sizeof(dep->name));
 629                 break;
 630         default:
 631                 dev_err(dwc->dev, "invalid endpoint transfer type\n");
 632         }
 633
 634         spin_lock_irqsave(&dwc->lock, flags);
 635         ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false);
 636         spin_unlock_irqrestore(&dwc->lock, flags);
 637
 638         return ret;
 639 }
 640
 641 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
 642 {
 643         struct dwc3_ep                  *dep;
 644         unsigned long                   flags;
 645         int                             ret;
 646
 647         if (!ep) {
 648                 pr_debug("dwc3: invalid parameters\n");
 649                 return -EINVAL;
 650         }
 651
 652         dep = to_dwc3_ep(ep);
 653
 654         if (!(dep->flags & DWC3_EP_ENABLED)) {
 655                 WARN(true, "%s is already disabled\n",
 656                                 dep->name);
 657                 return 0;
 658         }
 659
 660         snprintf(dep->name, sizeof(dep->name), "ep%d%s",
 661                         dep->number >> 1,
 662                         (dep->number & 1) ? "in" : "out");
 663
 664         spin_lock_irqsave(&dwc->lock, flags);
 665         ret = __dwc3_gadget_ep_disable(dep);
 666         spin_unlock_irqrestore(&dwc->lock, flags);
 667
 668         return ret;
 669 }
 670
 671 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
 672         gfp_t gfp_flags)
 673 {
 674         struct dwc3_request             *req;
 675         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 676
 677         req = kzalloc(sizeof(*req), gfp_flags);
 678         if (!req)
 679                 return NULL;
 680
 681         req->epnum      = dep->number;
 682         req->dep        = dep;
 683
 684         return &req->request;
 685 }
 686
 687 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
 688                 struct usb_request *request)
 689 {
 690         struct dwc3_request             *req = to_dwc3_request(request);
 691
 692         kfree(req);
 693 }
 694
 695 /**
 696  * dwc3_prepare_one_trb - setup one TRB from one request
 697  * @dep: endpoint for which this request is prepared
 698  * @req: dwc3_request pointer
 699  */
 700 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
 701                 struct dwc3_request *req, dma_addr_t dma,
 702                 unsigned length, unsigned last, unsigned chain, unsigned node)
 703 {
 704         struct dwc3_trb         *trb;
 705
 706         dev_vdbg(dwc->dev, "%s: req %p dma %08llx length %d%s%s\n",
 707                         dep->name, req, (unsigned long long) dma,
 708                         length, last ? " last" : "",
 709                         chain ? " chain" : "");
 710
 711
 712         trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
 713
 714         if (!req->trb) {
 715                 dwc3_gadget_move_request_queued(req);
 716                 req->trb = trb;
 717                 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
 718                 req->start_slot = dep->free_slot & DWC3_TRB_MASK;
 719         }
 720
 721         dep->free_slot++;
 722         /* Skip the LINK-TRB on ISOC */
 723         if (((dep->free_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
 724                         usb_endpoint_xfer_isoc(dep->endpoint.desc))
 725                 dep->free_slot++;
 726
 727         trb->size = DWC3_TRB_SIZE_LENGTH(length);
 728         trb->bpl = lower_32_bits(dma);
 729         trb->bph = upper_32_bits(dma);
 730
 731         switch (usb_endpoint_type(dep->endpoint.desc)) {
 732         case USB_ENDPOINT_XFER_CONTROL:
 733                 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
 734                 break;
 735
 736         case USB_ENDPOINT_XFER_ISOC:
 737                 if (!node)
 738                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
 739                 else
 740                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
 741                 break;
 742
 743         case USB_ENDPOINT_XFER_BULK:
 744         case USB_ENDPOINT_XFER_INT:
 745                 trb->ctrl = DWC3_TRBCTL_NORMAL;
 746                 break;
 747         default:
 748                 /*
 749                  * This is only possible with faulty memory because we
 750                  * checked it already :)
 751                  */
 752                 BUG();
 753         }
 754
 755         if (!req->request.no_interrupt && !chain)
 756                 trb->ctrl |= DWC3_TRB_CTRL_IOC;
 757
 758         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
 759                 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
 760                 trb->ctrl |= DWC3_TRB_CTRL_CSP;
 761         } else if (last) {
 762                 trb->ctrl |= DWC3_TRB_CTRL_LST;
 763         }
 764
 765         if (chain)
 766                 trb->ctrl |= DWC3_TRB_CTRL_CHN;
 767
 768         if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
 769                 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
 770
 771         trb->ctrl |= DWC3_TRB_CTRL_HWO;
 772 }
 773
 774 /*
 775  * dwc3_prepare_trbs - setup TRBs from requests
 776  * @dep: endpoint for which requests are being prepared
 777  * @starting: true if the endpoint is idle and no requests are queued.
 778  *
 779  * The function goes through the requests list and sets up TRBs for the
 780  * transfers. The function returns once there are no more TRBs available or
 781  * it runs out of requests.
 782  */
 783 static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
 784 {
 785         struct dwc3_request     *req, *n;
 786         u32                     trbs_left;
 787         u32                     max;
 788         unsigned int            last_one = 0;
 789
 790         BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
 791
 792         /* the first request must not be queued */
 793         trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
 794
 795         /* Can't wrap around on a non-isoc EP since there's no link TRB */
 796         if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
 797                 max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK);
 798                 if (trbs_left > max)
 799                         trbs_left = max;
 800         }
 801
 802         /*
 803          * If busy & slot are equal than it is either full or empty. If we are
 804          * starting to process requests then we are empty. Otherwise we are
 805          * full and don't do anything
 806          */
 807         if (!trbs_left) {
 808                 if (!starting)
 809                         return;
 810                 trbs_left = DWC3_TRB_NUM;
 811                 /*
 812                  * In case we start from scratch, we queue the ISOC requests
 813                  * starting from slot 1. This is done because we use ring
 814                  * buffer and have no LST bit to stop us. Instead, we place
 815                  * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
 816                  * after the first request so we start at slot 1 and have
 817                  * 7 requests proceed before we hit the first IOC.
 818                  * Other transfer types don't use the ring buffer and are
 819                  * processed from the first TRB until the last one. Since we
 820                  * don't wrap around we have to start at the beginning.
 821                  */
 822                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
 823                         dep->busy_slot = 1;
 824                         dep->free_slot = 1;
 825                 } else {
 826                         dep->busy_slot = 0;
 827                         dep->free_slot = 0;
 828                 }
 829         }
 830
 831         /* The last TRB is a link TRB, not used for xfer */
 832         if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc))
 833                 return;
 834
 835         list_for_each_entry_safe(req, n, &dep->request_list, list) {
 836                 unsigned        length;
 837                 dma_addr_t      dma;
 838                 last_one = false;
 839
 840                 dma = req->request.dma;
 841                 length = req->request.length;
 842                 trbs_left--;
 843
 844                 if (!trbs_left)
 845                         last_one = 1;
 846
 847                 /* Is this the last request? */
 848                 if (list_is_last(&req->list, &dep->request_list))
 849                         last_one = 1;
 850
 851                 dwc3_prepare_one_trb(dep, req, dma, length,
 852                                 last_one, false, 0);
 853
 854                 if (last_one)
 855                         break;
 856         }
 857 }
 858
 859 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
 860                 int start_new)
 861 {
 862         struct dwc3_gadget_ep_cmd_params params;
 863         struct dwc3_request             *req;
 864         struct dwc3                     *dwc = dep->dwc;
 865         int                             ret;
 866         u32                             cmd;
 867
 868         if (start_new && (dep->flags & DWC3_EP_BUSY)) {
 869                 dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name);
 870                 return -EBUSY;
 871         }
 872         dep->flags &= ~DWC3_EP_PENDING_REQUEST;
 873
 874         /*
 875          * If we are getting here after a short-out-packet we don't enqueue any
 876          * new requests as we try to set the IOC bit only on the last request.
 877          */
 878         if (start_new) {
 879                 if (list_empty(&dep->req_queued))
 880                         dwc3_prepare_trbs(dep, start_new);
 881
 882                 /* req points to the first request which will be sent */
 883                 req = next_request(&dep->req_queued);
 884         } else {
 885                 dwc3_prepare_trbs(dep, start_new);
 886
 887                 /*
 888                  * req points to the first request where HWO changed from 0 to 1
 889                  */
 890                 req = next_request(&dep->req_queued);
 891         }
 892         if (!req) {
 893                 dep->flags |= DWC3_EP_PENDING_REQUEST;
 894                 return 0;
 895         }
 896
 897         memset(&params, 0, sizeof(params));
 898
 899         if (start_new) {
 900                 params.param0 = upper_32_bits(req->trb_dma);
 901                 params.param1 = lower_32_bits(req->trb_dma);
 902                 cmd = DWC3_DEPCMD_STARTTRANSFER;
 903         } else {
 904                 cmd = DWC3_DEPCMD_UPDATETRANSFER;
 905         }
 906
 907         cmd |= DWC3_DEPCMD_PARAM(cmd_param);
 908         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
 909         if (ret < 0) {
 910                 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
 911
 912                 /*
 913                  * FIXME we need to iterate over the list of requests
 914                  * here and stop, unmap, free and del each of the linked
 915                  * requests instead of what we do now.
 916                  */
 917                 usb_gadget_unmap_request(&dwc->gadget, &req->request,
 918                                 req->direction);
 919                 list_del(&req->list);
 920                 return ret;
 921         }
 922
 923         dep->flags |= DWC3_EP_BUSY;
 924
 925         if (start_new) {
 926                 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
 927                                 dep->number);
 928                 WARN_ON_ONCE(!dep->resource_index);
 929         }
 930
 931         return 0;
 932 }
 933
 934 static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
 935                 struct dwc3_ep *dep, u32 cur_uf)
 936 {
 937         u32 uf;
 938
 939         if (list_empty(&dep->request_list)) {
 940                 dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n",
 941                         dep->name);
 942                 dep->flags |= DWC3_EP_PENDING_REQUEST;
 943                 return;
 944         }
 945
 946         /* 4 micro frames in the future */
 947         uf = cur_uf + dep->interval * 4;
 948
 949         __dwc3_gadget_kick_transfer(dep, uf, 1);
 950 }
 951
 952 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
 953                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
 954 {
 955         u32 cur_uf, mask;
 956
 957         mask = ~(dep->interval - 1);
 958         cur_uf = event->parameters & mask;
 959
 960         __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
 961 }
 962
 963 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
 964 {
 965         struct dwc3             *dwc = dep->dwc;
 966         int                     ret;
 967
 968         req->request.actual     = 0;
 969         req->request.status     = -EINPROGRESS;
 970         req->direction          = dep->direction;
 971         req->epnum              = dep->number;
 972
 973         /*
 974          * We only add to our list of requests now and
 975          * start consuming the list once we get XferNotReady
 976          * IRQ.
 977          *
 978          * That way, we avoid doing anything that we don't need
 979          * to do now and defer it until the point we receive a
 980          * particular token from the Host side.
 981          *
 982          * This will also avoid Host cancelling URBs due to too
 983          * many NAKs.
 984          */
 985         ret = usb_gadget_map_request(&dwc->gadget, &req->request,
 986                         dep->direction);
 987         if (ret)
 988                 return ret;
 989
 990         list_add_tail(&req->list, &dep->request_list);
 991
 992         /*
 993          * There are a few special cases:
 994          *
 995          * 1. XferNotReady with empty list of requests. We need to kick the
 996          *    transfer here in that situation, otherwise we will be NAKing
 997          *    forever. If we get XferNotReady before gadget driver has a
 998          *    chance to queue a request, we will ACK the IRQ but won't be
 999          *    able to receive the data until the next request is queued.
1000          *    The following code is handling exactly that.
1001          *
1002          */
1003         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
1004                 /*
1005                  * If xfernotready is already elapsed and it is a case
1006                  * of isoc transfer, then issue END TRANSFER, so that
1007                  * you can receive xfernotready again and can have
1008                  * notion of current microframe.
1009                  */
1010                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1011                         if (list_empty(&dep->req_queued)) {
1012                                 dwc3_stop_active_transfer(dwc, dep->number, true);
1013                                 dep->flags = DWC3_EP_ENABLED;
1014                         }
1015                         return 0;
1016                 }
1017
1018                 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1019                 if (ret && ret != -EBUSY)
1020                         dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1021                                         dep->name);
1022                 return ret;
1023         }
1024
1025         /*
1026          * 2. XferInProgress on Isoc EP with an active transfer. We need to
1027          *    kick the transfer here after queuing a request, otherwise the
1028          *    core may not see the modified TRB(s).
1029          */
1030         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1031                         (dep->flags & DWC3_EP_BUSY) &&
1032                         !(dep->flags & DWC3_EP_MISSED_ISOC)) {
1033                 WARN_ON_ONCE(!dep->resource_index);
1034                 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index,
1035                                 false);
1036                 if (ret && ret != -EBUSY)
1037                         dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1038                                         dep->name);
1039                 return ret;
1040         }
1041
1042         /*
1043          * 4. Stream Capable Bulk Endpoints. We need to start the transfer
1044          * right away, otherwise host will not know we have streams to be
1045          * handled.
1046          */
1047         if (dep->stream_capable) {
1048                 int     ret;
1049
1050                 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1051                 if (ret && ret != -EBUSY) {
1052                         dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1053                                         dep->name);
1054                 }
1055         }
1056
1057         return 0;
1058 }
1059
1060 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1061         gfp_t gfp_flags)
1062 {
1063         struct dwc3_request             *req = to_dwc3_request(request);
1064         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1065
1066         unsigned long                   flags;
1067
1068         int                             ret;
1069
1070         spin_lock_irqsave(&dwc->lock, flags);
1071         if (!dep->endpoint.desc) {
1072                 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
1073                                 request, ep->name);
1074                 ret = -ESHUTDOWN;
1075                 goto out;
1076         }
1077
1078         if (req->dep != dep) {
1079                 WARN(true, "request %p belongs to '%s'\n",
1080                                 request, req->dep->name);
1081                 ret = -EINVAL;
1082                 goto out;
1083         }
1084
1085         dev_vdbg(dwc->dev, "queing request %p to %s length %d\n",
1086                         request, ep->name, request->length);
1087
1088         ret = __dwc3_gadget_ep_queue(dep, req);
1089
1090 out:
1091         spin_unlock_irqrestore(&dwc->lock, flags);
1092
1093         return ret;
1094 }
1095
1096 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1097                 struct usb_request *request)
1098 {
1099         struct dwc3_request             *req = to_dwc3_request(request);
1100         struct dwc3_request             *r = NULL;
1101
1102         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1103         struct dwc3                     *dwc = dep->dwc;
1104
1105         unsigned long                   flags;
1106         int                             ret = 0;
1107
1108         spin_lock_irqsave(&dwc->lock, flags);
1109
1110         list_for_each_entry(r, &dep->request_list, list) {
1111                 if (r == req)
1112                         break;
1113         }
1114
1115         if (r != req) {
1116                 list_for_each_entry(r, &dep->req_queued, list) {
1117                         if (r == req)
1118                                 break;
1119                 }
1120                 if (r == req) {
1121                         /* wait until it is processed */
1122                         dwc3_stop_active_transfer(dwc, dep->number, true);
1123                         goto out1;
1124                 }
1125                 dev_err(dwc->dev, "request %p was not queued to %s\n",
1126                                 request, ep->name);
1127                 ret = -EINVAL;
1128                 goto out0;
1129         }
1130
1131 out1:
1132         /* giveback the request */
1133         dwc3_gadget_giveback(dep, req, -ECONNRESET);
1134
1135 out0:
1136         spin_unlock_irqrestore(&dwc->lock, flags);
1137
1138         return ret;
1139 }
1140
1141 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1142 {
1143         struct dwc3_gadget_ep_cmd_params        params;
1144         struct dwc3                             *dwc = dep->dwc;
1145         int                                     ret;
1146
1147         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1148                 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1149                 return -EINVAL;
1150         }
1151
1152         memset(&params, 0x00, sizeof(params));
1153
1154         if (value) {
1155                 if (!protocol && ((dep->direction && dep->flags & DWC3_EP_BUSY) ||
1156                                 (!list_empty(&dep->req_queued) ||
1157                                  !list_empty(&dep->request_list)))) {
1158                         dev_dbg(dwc->dev, "%s: pending request, cannot halt\n",
1159                                         dep->name);
1160                         return -EAGAIN;
1161                 }
1162
1163                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1164                         DWC3_DEPCMD_SETSTALL, &params);
1165                 if (ret)
1166                         dev_err(dwc->dev, "failed to set STALL on %s\n",
1167                                         dep->name);
1168                 else
1169                         dep->flags |= DWC3_EP_STALL;
1170         } else {
1171                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1172                         DWC3_DEPCMD_CLEARSTALL, &params);
1173                 if (ret)
1174                         dev_err(dwc->dev, "failed to clear STALL on %s\n",
1175                                         dep->name);
1176                 else
1177                         dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1178         }
1179
1180         return ret;
1181 }
1182
1183 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1184 {
1185         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1186
1187         unsigned long                   flags;
1188
1189         int                             ret;
1190
1191         spin_lock_irqsave(&dwc->lock, flags);
1192         ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1193         spin_unlock_irqrestore(&dwc->lock, flags);
1194
1195         return ret;
1196 }
1197
1198 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1199 {
1200         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1201         unsigned long                   flags;
1202         int                             ret;
1203
1204         spin_lock_irqsave(&dwc->lock, flags);
1205         dep->flags |= DWC3_EP_WEDGE;
1206
1207         if (dep->number == 0 || dep->number == 1)
1208                 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1209         else
1210                 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1211         spin_unlock_irqrestore(&dwc->lock, flags);
1212
1213         return ret;
1214 }
1215
1216 /* -------------------------------------------------------------------------- */
1217
1218 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1219         .bLength        = USB_DT_ENDPOINT_SIZE,
1220         .bDescriptorType = USB_DT_ENDPOINT,
1221         .bmAttributes   = USB_ENDPOINT_XFER_CONTROL,
1222 };
1223
1224 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1225         .enable         = dwc3_gadget_ep0_enable,
1226         .disable        = dwc3_gadget_ep0_disable,
1227         .alloc_request  = dwc3_gadget_ep_alloc_request,
1228         .free_request   = dwc3_gadget_ep_free_request,
1229         .queue          = dwc3_gadget_ep0_queue,
1230         .dequeue        = dwc3_gadget_ep_dequeue,
1231         .set_halt       = dwc3_gadget_ep0_set_halt,
1232         .set_wedge      = dwc3_gadget_ep_set_wedge,
1233 };
1234
1235 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1236         .enable         = dwc3_gadget_ep_enable,
1237         .disable        = dwc3_gadget_ep_disable,
1238         .alloc_request  = dwc3_gadget_ep_alloc_request,
1239         .free_request   = dwc3_gadget_ep_free_request,
1240         .queue          = dwc3_gadget_ep_queue,
1241         .dequeue        = dwc3_gadget_ep_dequeue,
1242         .set_halt       = dwc3_gadget_ep_set_halt,
1243         .set_wedge      = dwc3_gadget_ep_set_wedge,
1244 };
1245
1246 /* -------------------------------------------------------------------------- */
1247
1248 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1249 {
1250         struct dwc3             *dwc = gadget_to_dwc(g);
1251         u32                     reg;
1252
1253         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1254         return DWC3_DSTS_SOFFN(reg);
1255 }
1256
1257 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1258 {
1259         struct dwc3             *dwc = gadget_to_dwc(g);
1260
1261         unsigned long           timeout;
1262         unsigned long           flags;
1263
1264         u32                     reg;
1265
1266         int                     ret = 0;
1267
1268         u8                      link_state;
1269         u8                      speed;
1270
1271         spin_lock_irqsave(&dwc->lock, flags);
1272
1273         /*
1274          * According to the Databook Remote wakeup request should
1275          * be issued only when the device is in early suspend state.
1276          *
1277          * We can check that via USB Link State bits in DSTS register.
1278          */
1279         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1280
1281         speed = reg & DWC3_DSTS_CONNECTSPD;
1282         if (speed == DWC3_DSTS_SUPERSPEED) {
1283                 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n");
1284                 ret = -EINVAL;
1285                 goto out;
1286         }
1287
1288         link_state = DWC3_DSTS_USBLNKST(reg);
1289
1290         switch (link_state) {
1291         case DWC3_LINK_STATE_RX_DET:    /* in HS, means Early Suspend */
1292         case DWC3_LINK_STATE_U3:        /* in HS, means SUSPEND */
1293                 break;
1294         default:
1295                 dev_dbg(dwc->dev, "can't wakeup from link state %d\n",
1296                                 link_state);
1297                 ret = -EINVAL;
1298                 goto out;
1299         }
1300
1301         ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1302         if (ret < 0) {
1303                 dev_err(dwc->dev, "failed to put link in Recovery\n");
1304                 goto out;
1305         }
1306
1307         /* Recent versions do this automatically */
1308         if (dwc->revision < DWC3_REVISION_194A) {
1309                 /* write zeroes to Link Change Request */
1310                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1311                 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1312                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1313         }
1314
1315         /* poll until Link State changes to ON */
1316         timeout = 1000;
1317
1318         while (timeout--) {
1319                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1320
1321                 /* in HS, means ON */
1322                 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1323                         break;
1324         }
1325
1326         if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1327                 dev_err(dwc->dev, "failed to send remote wakeup\n");
1328                 ret = -EINVAL;
1329         }
1330
1331 out:
1332         spin_unlock_irqrestore(&dwc->lock, flags);
1333
1334         return ret;
1335 }
1336
1337 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1338                 int is_selfpowered)
1339 {
1340         struct dwc3             *dwc = gadget_to_dwc(g);
1341         unsigned long           flags;
1342
1343         spin_lock_irqsave(&dwc->lock, flags);
1344         dwc->is_selfpowered = !!is_selfpowered;
1345         spin_unlock_irqrestore(&dwc->lock, flags);
1346
1347         return 0;
1348 }
1349
1350 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1351 {
1352         u32                     reg;
1353         u32                     timeout = 500;
1354
1355         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1356         if (is_on) {
1357                 if (dwc->revision <= DWC3_REVISION_187A) {
1358                         reg &= ~DWC3_DCTL_TRGTULST_MASK;
1359                         reg |= DWC3_DCTL_TRGTULST_RX_DET;
1360                 }
1361
1362                 if (dwc->revision >= DWC3_REVISION_194A)
1363                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1364                 reg |= DWC3_DCTL_RUN_STOP;
1365
1366                 if (dwc->has_hibernation)
1367                         reg |= DWC3_DCTL_KEEP_CONNECT;
1368
1369                 dwc->pullups_connected = true;
1370         } else {
1371                 reg &= ~DWC3_DCTL_RUN_STOP;
1372
1373                 if (dwc->has_hibernation && !suspend)
1374                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1375
1376                 dwc->pullups_connected = false;
1377         }
1378
1379         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1380
1381         do {
1382                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1383                 if (is_on) {
1384                         if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1385                                 break;
1386                 } else {
1387                         if (reg & DWC3_DSTS_DEVCTRLHLT)
1388                                 break;
1389                 }
1390                 timeout--;
1391                 if (!timeout)
1392                         return -ETIMEDOUT;
1393                 udelay(1);
1394         } while (1);
1395
1396         dev_vdbg(dwc->dev, "gadget %s data soft-%s\n",
1397                         dwc->gadget_driver
1398                         ? dwc->gadget_driver->function : "no-function",
1399                         is_on ? "connect" : "disconnect");
1400
1401         return 0;
1402 }
1403
1404 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1405 {
1406         struct dwc3             *dwc = gadget_to_dwc(g);
1407         unsigned long           flags;
1408         int                     ret;
1409
1410         is_on = !!is_on;
1411
1412         spin_lock_irqsave(&dwc->lock, flags);
1413         ret = dwc3_gadget_run_stop(dwc, is_on, false);
1414         spin_unlock_irqrestore(&dwc->lock, flags);
1415
1416         return ret;
1417 }
1418
1419 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1420 {
1421         u32                     reg;
1422
1423         /* Enable all but Start and End of Frame IRQs */
1424         reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1425                         DWC3_DEVTEN_EVNTOVERFLOWEN |
1426                         DWC3_DEVTEN_CMDCMPLTEN |
1427                         DWC3_DEVTEN_ERRTICERREN |
1428                         DWC3_DEVTEN_WKUPEVTEN |
1429                         DWC3_DEVTEN_ULSTCNGEN |
1430                         DWC3_DEVTEN_CONNECTDONEEN |
1431                         DWC3_DEVTEN_USBRSTEN |
1432                         DWC3_DEVTEN_DISCONNEVTEN);
1433
1434         dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1435 }
1436
1437 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1438 {
1439         /* mask all interrupts */
1440         dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1441 }
1442
1443 static int dwc3_gadget_start(struct usb_gadget *g,
1444                 struct usb_gadget_driver *driver)
1445 {
1446         struct dwc3             *dwc = gadget_to_dwc(g);
1447         struct dwc3_ep          *dep;
1448         unsigned long           flags;
1449         int                     ret = 0;
1450         u32                     reg;
1451
1452         spin_lock_irqsave(&dwc->lock, flags);
1453
1454         if (dwc->gadget_driver) {
1455                 dev_err(dwc->dev, "%s is already bound to %s\n",
1456                                 dwc->gadget.name,
1457                                 dwc->gadget_driver->function);
1458                 ret = -EBUSY;
1459                 goto err1;
1460         }
1461
1462         dwc->gadget_driver      = driver;
1463
1464         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1465         reg &= ~(DWC3_DCFG_SPEED_MASK);
1466
1467         /**
1468          * WORKAROUND: DWC3 revision < 2.20a have an issue
1469          * which would cause metastability state on Run/Stop
1470          * bit if we try to force the IP to USB2-only mode.
1471          *
1472          * Because of that, we cannot configure the IP to any
1473          * speed other than the SuperSpeed
1474          *
1475          * Refers to:
1476          *
1477          * STAR#9000525659: Clock Domain Crossing on DCTL in
1478          * USB 2.0 Mode
1479          */
1480         if (dwc->revision < DWC3_REVISION_220A) {
1481                 reg |= DWC3_DCFG_SUPERSPEED;
1482         } else {
1483                 switch (dwc->maximum_speed) {
1484                 case USB_SPEED_LOW:
1485                         reg |= DWC3_DSTS_LOWSPEED;
1486                         break;
1487                 case USB_SPEED_FULL:
1488                         reg |= DWC3_DSTS_FULLSPEED1;
1489                         break;
1490                 case USB_SPEED_HIGH:
1491                         reg |= DWC3_DSTS_HIGHSPEED;
1492                         break;
1493                 case USB_SPEED_SUPER:   /* FALLTHROUGH */
1494                 case USB_SPEED_UNKNOWN: /* FALTHROUGH */
1495                 default:
1496                         reg |= DWC3_DSTS_SUPERSPEED;
1497                 }
1498         }
1499         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1500
1501         dwc->start_config_issued = false;
1502
1503         /* Start with SuperSpeed Default */
1504         dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1505
1506         dep = dwc->eps[0];
1507         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1508                         false);
1509         if (ret) {
1510                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1511                 goto err2;
1512         }
1513
1514         dep = dwc->eps[1];
1515         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1516                         false);
1517         if (ret) {
1518                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1519                 goto err3;
1520         }
1521
1522         /* begin to receive SETUP packets */
1523         dwc->ep0state = EP0_SETUP_PHASE;
1524         dwc3_ep0_out_start(dwc);
1525
1526         dwc3_gadget_enable_irq(dwc);
1527
1528         spin_unlock_irqrestore(&dwc->lock, flags);
1529
1530         return 0;
1531
1532 err3:
1533         __dwc3_gadget_ep_disable(dwc->eps[0]);
1534
1535 err2:
1536         dwc->gadget_driver = NULL;
1537
1538 err1:
1539         spin_unlock_irqrestore(&dwc->lock, flags);
1540
1541         return ret;
1542 }
1543
1544 static int dwc3_gadget_stop(struct usb_gadget *g)
1545 {
1546         struct dwc3             *dwc = gadget_to_dwc(g);
1547         unsigned long           flags;
1548
1549         spin_lock_irqsave(&dwc->lock, flags);
1550
1551         dwc3_gadget_disable_irq(dwc);
1552         __dwc3_gadget_ep_disable(dwc->eps[0]);
1553         __dwc3_gadget_ep_disable(dwc->eps[1]);
1554
1555         dwc->gadget_driver      = NULL;
1556
1557         spin_unlock_irqrestore(&dwc->lock, flags);
1558
1559         return 0;
1560 }
1561
1562 static const struct usb_gadget_ops dwc3_gadget_ops = {
1563         .get_frame              = dwc3_gadget_get_frame,
1564         .wakeup                 = dwc3_gadget_wakeup,
1565         .set_selfpowered        = dwc3_gadget_set_selfpowered,
1566         .pullup                 = dwc3_gadget_pullup,
1567         .udc_start              = dwc3_gadget_start,
1568         .udc_stop               = dwc3_gadget_stop,
1569 };
1570
1571 /* -------------------------------------------------------------------------- */
1572
1573 static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
1574                 u8 num, u32 direction)
1575 {
1576         struct dwc3_ep                  *dep;
1577         u8                              i;
1578
1579         for (i = 0; i < num; i++) {
1580                 u8 epnum = (i << 1) | (!!direction);
1581
1582                 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1583                 if (!dep)
1584                         return -ENOMEM;
1585
1586                 dep->dwc = dwc;
1587                 dep->number = epnum;
1588                 dep->direction = !!direction;
1589                 dwc->eps[epnum] = dep;
1590
1591                 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1592                                 (epnum & 1) ? "in" : "out");
1593
1594                 dep->endpoint.name = dep->name;
1595
1596                 dev_vdbg(dwc->dev, "initializing %s\n", dep->name);
1597
1598                 if (epnum == 0 || epnum == 1) {
1599                         usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
1600                         dep->endpoint.maxburst = 1;
1601                         dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1602                         if (!epnum)
1603                                 dwc->gadget.ep0 = &dep->endpoint;
1604                 } else {
1605                         int             ret;
1606
1607                         usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
1608                         dep->endpoint.max_streams = 15;
1609                         dep->endpoint.ops = &dwc3_gadget_ep_ops;
1610                         list_add_tail(&dep->endpoint.ep_list,
1611                                         &dwc->gadget.ep_list);
1612
1613                         ret = dwc3_alloc_trb_pool(dep);
1614                         if (ret)
1615                                 return ret;
1616                 }
1617
1618                 INIT_LIST_HEAD(&dep->request_list);
1619                 INIT_LIST_HEAD(&dep->req_queued);
1620         }
1621
1622         return 0;
1623 }
1624
1625 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1626 {
1627         int                             ret;
1628
1629         INIT_LIST_HEAD(&dwc->gadget.ep_list);
1630
1631         ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
1632         if (ret < 0) {
1633                 dev_vdbg(dwc->dev, "failed to allocate OUT endpoints\n");
1634                 return ret;
1635         }
1636
1637         ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
1638         if (ret < 0) {
1639                 dev_vdbg(dwc->dev, "failed to allocate IN endpoints\n");
1640                 return ret;
1641         }
1642
1643         return 0;
1644 }
1645
1646 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1647 {
1648         struct dwc3_ep                  *dep;
1649         u8                              epnum;
1650
1651         for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1652                 dep = dwc->eps[epnum];
1653                 if (!dep)
1654                         continue;
1655                 /*
1656                  * Physical endpoints 0 and 1 are special; they form the
1657                  * bi-directional USB endpoint 0.
1658                  *
1659                  * For those two physical endpoints, we don't allocate a TRB
1660                  * pool nor do we add them the endpoints list. Due to that, we
1661                  * shouldn't do these two operations otherwise we would end up
1662                  * with all sorts of bugs when removing dwc3.ko.
1663                  */
1664                 if (epnum != 0 && epnum != 1) {
1665                         dwc3_free_trb_pool(dep);
1666                         list_del(&dep->endpoint.ep_list);
1667                 }
1668
1669                 kfree(dep);
1670         }
1671 }
1672
1673 /* -------------------------------------------------------------------------- */
1674
1675 static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
1676                 struct dwc3_request *req, struct dwc3_trb *trb,
1677                 const struct dwc3_event_depevt *event, int status)
1678 {
1679         unsigned int            count;
1680         unsigned int            s_pkt = 0;
1681         unsigned int            trb_status;
1682
1683         if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1684                 /*
1685                  * We continue despite the error. There is not much we
1686                  * can do. If we don't clean it up we loop forever. If
1687                  * we skip the TRB then it gets overwritten after a
1688                  * while since we use them in a ring buffer. A BUG()
1689                  * would help. Lets hope that if this occurs, someone
1690                  * fixes the root cause instead of looking away :)
1691                  */
1692                 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1693                                 dep->name, trb);
1694         count = trb->size & DWC3_TRB_SIZE_MASK;
1695
1696         if (dep->direction) {
1697                 if (count) {
1698                         trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1699                         if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
1700                                 dev_dbg(dwc->dev, "incomplete IN transfer %s\n",
1701                                                 dep->name);
1702                                 /*
1703                                  * If missed isoc occurred and there is
1704                                  * no request queued then issue END
1705                                  * TRANSFER, so that core generates
1706                                  * next xfernotready and we will issue
1707                                  * a fresh START TRANSFER.
1708                                  * If there are still queued request
1709                                  * then wait, do not issue either END
1710                                  * or UPDATE TRANSFER, just attach next
1711                                  * request in request_list during
1712                                  * giveback.If any future queued request
1713                                  * is successfully transferred then we
1714                                  * will issue UPDATE TRANSFER for all
1715                                  * request in the request_list.
1716                                  */
1717                                 dep->flags |= DWC3_EP_MISSED_ISOC;
1718                         } else {
1719                                 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1720                                                 dep->name);
1721                                 status = -ECONNRESET;
1722                         }
1723                 } else {
1724                         dep->flags &= ~DWC3_EP_MISSED_ISOC;
1725                 }
1726         } else {
1727                 if (count && (event->status & DEPEVT_STATUS_SHORT))
1728                         s_pkt = 1;
1729         }
1730
1731         /*
1732          * We assume here we will always receive the entire data block
1733          * which we should receive. Meaning, if we program RX to
1734          * receive 4K but we receive only 2K, we assume that's all we
1735          * should receive and we simply bounce the request back to the
1736          * gadget driver for further processing.
1737          */
1738         req->request.actual += req->request.length - count;
1739         if (s_pkt)
1740                 return 1;
1741         if ((event->status & DEPEVT_STATUS_LST) &&
1742                         (trb->ctrl & (DWC3_TRB_CTRL_LST |
1743                                 DWC3_TRB_CTRL_HWO)))
1744                 return 1;
1745         if ((event->status & DEPEVT_STATUS_IOC) &&
1746                         (trb->ctrl & DWC3_TRB_CTRL_IOC))
1747                 return 1;
1748         return 0;
1749 }
1750
1751 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1752                 const struct dwc3_event_depevt *event, int status)
1753 {
1754         struct dwc3_request     *req;
1755         struct dwc3_trb         *trb;
1756         unsigned int            slot;
1757         int                     ret;
1758
1759         do {
1760                 req = next_request(&dep->req_queued);
1761                 if (!req) {
1762                         WARN_ON_ONCE(1);
1763                         return 1;
1764                 }
1765
1766                 slot = req->start_slot;
1767                 if ((slot == DWC3_TRB_NUM - 1) &&
1768                         usb_endpoint_xfer_isoc(dep->endpoint.desc))
1769                         slot++;
1770                 slot %= DWC3_TRB_NUM;
1771                 trb = &dep->trb_pool[slot];
1772
1773                 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
1774                                 event, status);
1775                 if (ret)
1776                         break;
1777
1778                 dwc3_gadget_giveback(dep, req, status);
1779
1780                 if (ret)
1781                         break;
1782         } while (1);
1783
1784         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1785                         list_empty(&dep->req_queued)) {
1786                 if (list_empty(&dep->request_list)) {
1787                         /*
1788                          * If there is no entry in request list then do
1789                          * not issue END TRANSFER now. Just set PENDING
1790                          * flag, so that END TRANSFER is issued when an
1791                          * entry is added into request list.
1792                          */
1793                         dep->flags = DWC3_EP_PENDING_REQUEST;
1794                 } else {
1795                         dwc3_stop_active_transfer(dwc, dep->number, true);
1796                         dep->flags = DWC3_EP_ENABLED;
1797                 }
1798                 return 1;
1799         }
1800
1801         return 1;
1802 }
1803
1804 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
1805                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1806 {
1807         unsigned                status = 0;
1808         int                     clean_busy;
1809
1810         if (event->status & DEPEVT_STATUS_BUSERR)
1811                 status = -ECONNRESET;
1812
1813         clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
1814         if (clean_busy)
1815                 dep->flags &= ~DWC3_EP_BUSY;
1816
1817         /*
1818          * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
1819          * See dwc3_gadget_linksts_change_interrupt() for 1st half.
1820          */
1821         if (dwc->revision < DWC3_REVISION_183A) {
1822                 u32             reg;
1823                 int             i;
1824
1825                 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
1826                         dep = dwc->eps[i];
1827
1828                         if (!(dep->flags & DWC3_EP_ENABLED))
1829                                 continue;
1830
1831                         if (!list_empty(&dep->req_queued))
1832                                 return;
1833                 }
1834
1835                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1836                 reg |= dwc->u1u2;
1837                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1838
1839                 dwc->u1u2 = 0;
1840         }
1841 }
1842
1843 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
1844                 const struct dwc3_event_depevt *event)
1845 {
1846         struct dwc3_ep          *dep;
1847         u8                      epnum = event->endpoint_number;
1848
1849         dep = dwc->eps[epnum];
1850
1851         if (!(dep->flags & DWC3_EP_ENABLED))
1852                 return;
1853
1854         if (epnum == 0 || epnum == 1) {
1855                 dwc3_ep0_interrupt(dwc, event);
1856                 return;
1857         }
1858
1859         switch (event->endpoint_event) {
1860         case DWC3_DEPEVT_XFERCOMPLETE:
1861                 dep->resource_index = 0;
1862
1863                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1864                         dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n",
1865                                         dep->name);
1866                         return;
1867                 }
1868
1869                 dwc3_endpoint_transfer_complete(dwc, dep, event);
1870                 break;
1871         case DWC3_DEPEVT_XFERINPROGRESS:
1872                 dwc3_endpoint_transfer_complete(dwc, dep, event);
1873                 break;
1874         case DWC3_DEPEVT_XFERNOTREADY:
1875                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1876                         dwc3_gadget_start_isoc(dwc, dep, event);
1877                 } else {
1878                         int ret;
1879
1880                         dev_vdbg(dwc->dev, "%s: reason %s\n",
1881                                         dep->name, event->status &
1882                                         DEPEVT_STATUS_TRANSFER_ACTIVE
1883                                         ? "Transfer Active"
1884                                         : "Transfer Not Active");
1885
1886                         ret = __dwc3_gadget_kick_transfer(dep, 0, 1);
1887                         if (!ret || ret == -EBUSY)
1888                                 return;
1889
1890                         dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1891                                         dep->name);
1892                 }
1893
1894                 break;
1895         case DWC3_DEPEVT_STREAMEVT:
1896                 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
1897                         dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
1898                                         dep->name);
1899                         return;
1900                 }
1901
1902                 switch (event->status) {
1903                 case DEPEVT_STREAMEVT_FOUND:
1904                         dev_vdbg(dwc->dev, "Stream %d found and started\n",
1905                                         event->parameters);
1906
1907                         break;
1908                 case DEPEVT_STREAMEVT_NOTFOUND:
1909                         /* FALLTHROUGH */
1910                 default:
1911                         dev_dbg(dwc->dev, "Couldn't find suitable stream\n");
1912                 }
1913                 break;
1914         case DWC3_DEPEVT_RXTXFIFOEVT:
1915                 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name);
1916                 break;
1917         case DWC3_DEPEVT_EPCMDCMPLT:
1918                 dev_vdbg(dwc->dev, "Endpoint Command Complete\n");
1919                 break;
1920         }
1921 }
1922
1923 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
1924 {
1925         if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
1926                 spin_unlock(&dwc->lock);
1927                 dwc->gadget_driver->disconnect(&dwc->gadget);
1928                 spin_lock(&dwc->lock);
1929         }
1930 }
1931
1932 static void dwc3_suspend_gadget(struct dwc3 *dwc)
1933 {
1934         if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
1935                 spin_unlock(&dwc->lock);
1936                 dwc->gadget_driver->suspend(&dwc->gadget);
1937                 spin_lock(&dwc->lock);
1938         }
1939 }
1940
1941 static void dwc3_resume_gadget(struct dwc3 *dwc)
1942 {
1943         if (dwc->gadget_driver && dwc->gadget_driver->resume) {
1944                 spin_unlock(&dwc->lock);
1945                 dwc->gadget_driver->resume(&dwc->gadget);
1946         }
1947 }
1948
1949 static void dwc3_reset_gadget(struct dwc3 *dwc)
1950 {
1951         if (!dwc->gadget_driver)
1952                 return;
1953
1954         if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
1955                 spin_unlock(&dwc->lock);
1956                 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
1957                 spin_lock(&dwc->lock);
1958         }
1959 }
1960
1961 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
1962 {
1963         struct dwc3_ep *dep;
1964         struct dwc3_gadget_ep_cmd_params params;
1965         u32 cmd;
1966         int ret;
1967
1968         dep = dwc->eps[epnum];
1969
1970         if (!dep->resource_index)
1971                 return;
1972
1973         /*
1974          * NOTICE: We are violating what the Databook says about the
1975          * EndTransfer command. Ideally we would _always_ wait for the
1976          * EndTransfer Command Completion IRQ, but that's causing too
1977          * much trouble synchronizing between us and gadget driver.
1978          *
1979          * We have discussed this with the IP Provider and it was
1980          * suggested to giveback all requests here, but give HW some
1981          * extra time to synchronize with the interconnect. We're using
1982          * an arbitraty 100us delay for that.
1983          *
1984          * Note also that a similar handling was tested by Synopsys
1985          * (thanks a lot Paul) and nothing bad has come out of it.
1986          * In short, what we're doing is:
1987          *
1988          * - Issue EndTransfer WITH CMDIOC bit set
1989          * - Wait 100us
1990          */
1991
1992         cmd = DWC3_DEPCMD_ENDTRANSFER;
1993         cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
1994         cmd |= DWC3_DEPCMD_CMDIOC;
1995         cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1996         memset(&params, 0, sizeof(params));
1997         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
1998         WARN_ON_ONCE(ret);
1999         dep->resource_index = 0;
2000         dep->flags &= ~DWC3_EP_BUSY;
2001         udelay(100);
2002 }
2003
2004 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2005 {
2006         u32 epnum;
2007
2008         for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2009                 struct dwc3_ep *dep;
2010
2011                 dep = dwc->eps[epnum];
2012                 if (!dep)
2013                         continue;
2014
2015                 if (!(dep->flags & DWC3_EP_ENABLED))
2016                         continue;
2017
2018                 dwc3_remove_requests(dwc, dep);
2019         }
2020 }
2021
2022 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2023 {
2024         u32 epnum;
2025
2026         for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2027                 struct dwc3_ep *dep;
2028                 struct dwc3_gadget_ep_cmd_params params;
2029                 int ret;
2030
2031                 dep = dwc->eps[epnum];
2032                 if (!dep)
2033                         continue;
2034
2035                 if (!(dep->flags & DWC3_EP_STALL))
2036                         continue;
2037
2038                 dep->flags &= ~DWC3_EP_STALL;
2039
2040                 memset(&params, 0, sizeof(params));
2041                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
2042                                 DWC3_DEPCMD_CLEARSTALL, &params);
2043                 WARN_ON_ONCE(ret);
2044         }
2045 }
2046
2047 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2048 {
2049         int                     reg;
2050
2051         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2052         reg &= ~DWC3_DCTL_INITU1ENA;
2053         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2054
2055         reg &= ~DWC3_DCTL_INITU2ENA;
2056         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2057
2058         dwc3_disconnect_gadget(dwc);
2059         dwc->start_config_issued = false;
2060
2061         dwc->gadget.speed = USB_SPEED_UNKNOWN;
2062         dwc->setup_packet_pending = false;
2063         usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2064 }
2065
2066 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2067 {
2068         u32                     reg;
2069
2070         /*
2071          * WORKAROUND: DWC3 revisions <1.88a have an issue which
2072          * would cause a missing Disconnect Event if there's a
2073          * pending Setup Packet in the FIFO.
2074          *
2075          * There's no suggested workaround on the official Bug
2076          * report, which states that "unless the driver/application
2077          * is doing any special handling of a disconnect event,
2078          * there is no functional issue".
2079          *
2080          * Unfortunately, it turns out that we _do_ some special
2081          * handling of a disconnect event, namely complete all
2082          * pending transfers, notify gadget driver of the
2083          * disconnection, and so on.
2084          *
2085          * Our suggested workaround is to follow the Disconnect
2086          * Event steps here, instead, based on a setup_packet_pending
2087          * flag. Such flag gets set whenever we have a XferNotReady
2088          * event on EP0 and gets cleared on XferComplete for the
2089          * same endpoint.
2090          *
2091          * Refers to:
2092          *
2093          * STAR#9000466709: RTL: Device : Disconnect event not
2094          * generated if setup packet pending in FIFO
2095          */
2096         if (dwc->revision < DWC3_REVISION_188A) {
2097                 if (dwc->setup_packet_pending)
2098                         dwc3_gadget_disconnect_interrupt(dwc);
2099         }
2100
2101         dwc3_reset_gadget(dwc);
2102
2103         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2104         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2105         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2106         dwc->test_mode = false;
2107
2108         dwc3_stop_active_transfers(dwc);
2109         dwc3_clear_stall_all_ep(dwc);
2110         dwc->start_config_issued = false;
2111
2112         /* Reset device address to zero */
2113         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2114         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2115         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2116 }
2117
2118 static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2119 {
2120         u32 reg;
2121         u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2122
2123         /*
2124          * We change the clock only at SS but I dunno why I would want to do
2125          * this. Maybe it becomes part of the power saving plan.
2126          */
2127
2128         if (speed != DWC3_DSTS_SUPERSPEED)
2129                 return;
2130
2131         /*
2132          * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2133          * each time on Connect Done.
2134          */
2135         if (!usb30_clock)
2136                 return;
2137
2138         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2139         reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2140         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2141 }
2142
2143 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2144 {
2145         struct dwc3_ep          *dep;
2146         int                     ret;
2147         u32                     reg;
2148         u8                      speed;
2149
2150         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2151         speed = reg & DWC3_DSTS_CONNECTSPD;
2152         dwc->speed = speed;
2153
2154         dwc3_update_ram_clk_sel(dwc, speed);
2155
2156         switch (speed) {
2157         case DWC3_DCFG_SUPERSPEED:
2158                 /*
2159                  * WORKAROUND: DWC3 revisions <1.90a have an issue which
2160                  * would cause a missing USB3 Reset event.
2161                  *
2162                  * In such situations, we should force a USB3 Reset
2163                  * event by calling our dwc3_gadget_reset_interrupt()
2164                  * routine.
2165                  *
2166                  * Refers to:
2167                  *
2168                  * STAR#9000483510: RTL: SS : USB3 reset event may
2169                  * not be generated always when the link enters poll
2170                  */
2171                 if (dwc->revision < DWC3_REVISION_190A)
2172                         dwc3_gadget_reset_interrupt(dwc);
2173
2174                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2175                 dwc->gadget.ep0->maxpacket = 512;
2176                 dwc->gadget.speed = USB_SPEED_SUPER;
2177                 break;
2178         case DWC3_DCFG_HIGHSPEED:
2179                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2180                 dwc->gadget.ep0->maxpacket = 64;
2181                 dwc->gadget.speed = USB_SPEED_HIGH;
2182                 break;
2183         case DWC3_DCFG_FULLSPEED2:
2184         case DWC3_DCFG_FULLSPEED1:
2185                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2186                 dwc->gadget.ep0->maxpacket = 64;
2187                 dwc->gadget.speed = USB_SPEED_FULL;
2188                 break;
2189         case DWC3_DCFG_LOWSPEED:
2190                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2191                 dwc->gadget.ep0->maxpacket = 8;
2192                 dwc->gadget.speed = USB_SPEED_LOW;
2193                 break;
2194         }
2195
2196         /* Enable USB2 LPM Capability */
2197
2198         if ((dwc->revision > DWC3_REVISION_194A)
2199                         && (speed != DWC3_DCFG_SUPERSPEED)) {
2200                 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2201                 reg |= DWC3_DCFG_LPM_CAP;
2202                 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2203
2204                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2205                 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2206
2207                 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2208
2209                 /*
2210                  * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2211                  * DCFG.LPMCap is set, core responses with an ACK and the
2212                  * BESL value in the LPM token is less than or equal to LPM
2213                  * NYET threshold.
2214                  */
2215                 if (dwc->revision < DWC3_REVISION_240A  && dwc->has_lpm_erratum)
2216                         WARN(true, "LPM Erratum not available on dwc3 revisisions < 2.40a\n");
2217
2218                 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2219                         reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2220
2221                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2222         } else {
2223                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2224                 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2225                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2226         }
2227
2228         dep = dwc->eps[0];
2229         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2230                         false);
2231         if (ret) {
2232                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2233                 return;
2234         }
2235
2236         dep = dwc->eps[1];
2237         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2238                         false);
2239         if (ret) {
2240                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2241                 return;
2242         }
2243
2244         /*
2245          * Configure PHY via GUSB3PIPECTLn if required.
2246          *
2247          * Update GTXFIFOSIZn
2248          *
2249          * In both cases reset values should be sufficient.
2250          */
2251 }
2252
2253 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2254 {
2255         /*
2256          * TODO take core out of low power mode when that's
2257          * implemented.
2258          */
2259
2260         dwc->gadget_driver->resume(&dwc->gadget);
2261 }
2262
2263 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2264                 unsigned int evtinfo)
2265 {
2266         enum dwc3_link_state    next = evtinfo & DWC3_LINK_STATE_MASK;
2267         unsigned int            pwropt;
2268
2269         /*
2270          * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2271          * Hibernation mode enabled which would show up when device detects
2272          * host-initiated U3 exit.
2273          *
2274          * In that case, device will generate a Link State Change Interrupt
2275          * from U3 to RESUME which is only necessary if Hibernation is
2276          * configured in.
2277          *
2278          * There are no functional changes due to such spurious event and we
2279          * just need to ignore it.
2280          *
2281          * Refers to:
2282          *
2283          * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2284          * operational mode
2285          */
2286         pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2287         if ((dwc->revision < DWC3_REVISION_250A) &&
2288                         (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2289                 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2290                                 (next == DWC3_LINK_STATE_RESUME)) {
2291                         dev_vdbg(dwc->dev, "ignoring transition U3 -> Resume\n");
2292                         return;
2293                 }
2294         }
2295
2296         /*
2297          * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2298          * on the link partner, the USB session might do multiple entry/exit
2299          * of low power states before a transfer takes place.
2300          *
2301          * Due to this problem, we might experience lower throughput. The
2302          * suggested workaround is to disable DCTL[12:9] bits if we're
2303          * transitioning from U1/U2 to U0 and enable those bits again
2304          * after a transfer completes and there are no pending transfers
2305          * on any of the enabled endpoints.
2306          *
2307          * This is the first half of that workaround.
2308          *
2309          * Refers to:
2310          *
2311          * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2312          * core send LGO_Ux entering U0
2313          */
2314         if (dwc->revision < DWC3_REVISION_183A) {
2315                 if (next == DWC3_LINK_STATE_U0) {
2316                         u32     u1u2;
2317                         u32     reg;
2318
2319                         switch (dwc->link_state) {
2320                         case DWC3_LINK_STATE_U1:
2321                         case DWC3_LINK_STATE_U2:
2322                                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2323                                 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2324                                                 | DWC3_DCTL_ACCEPTU2ENA
2325                                                 | DWC3_DCTL_INITU1ENA
2326                                                 | DWC3_DCTL_ACCEPTU1ENA);
2327
2328                                 if (!dwc->u1u2)
2329                                         dwc->u1u2 = reg & u1u2;
2330
2331                                 reg &= ~u1u2;
2332
2333                                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2334                                 break;
2335                         default:
2336                                 /* do nothing */
2337                                 break;
2338                         }
2339                 }
2340         }
2341
2342         switch (next) {
2343         case DWC3_LINK_STATE_U1:
2344                 if (dwc->speed == USB_SPEED_SUPER)
2345                         dwc3_suspend_gadget(dwc);
2346                 break;
2347         case DWC3_LINK_STATE_U2:
2348         case DWC3_LINK_STATE_U3:
2349                 dwc3_suspend_gadget(dwc);
2350                 break;
2351         case DWC3_LINK_STATE_RESUME:
2352                 dwc3_resume_gadget(dwc);
2353                 break;
2354         default:
2355                 /* do nothing */
2356                 break;
2357         }
2358
2359         dwc->link_state = next;
2360 }
2361
2362 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2363                 unsigned int evtinfo)
2364 {
2365         unsigned int is_ss = evtinfo & BIT(4);
2366
2367         /**
2368          * WORKAROUND: DWC3 revison 2.20a with hibernation support
2369          * have a known issue which can cause USB CV TD.9.23 to fail
2370          * randomly.
2371          *
2372          * Because of this issue, core could generate bogus hibernation
2373          * events which SW needs to ignore.
2374          *
2375          * Refers to:
2376          *
2377          * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2378          * Device Fallback from SuperSpeed
2379          */
2380         if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2381                 return;
2382
2383         /* enter hibernation here */
2384 }
2385
2386 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2387                 const struct dwc3_event_devt *event)
2388 {
2389         switch (event->type) {
2390         case DWC3_DEVICE_EVENT_DISCONNECT:
2391                 dwc3_gadget_disconnect_interrupt(dwc);
2392                 break;
2393         case DWC3_DEVICE_EVENT_RESET:
2394                 dwc3_gadget_reset_interrupt(dwc);
2395                 break;
2396         case DWC3_DEVICE_EVENT_CONNECT_DONE:
2397                 dwc3_gadget_conndone_interrupt(dwc);
2398                 break;
2399         case DWC3_DEVICE_EVENT_WAKEUP:
2400                 dwc3_gadget_wakeup_interrupt(dwc);
2401                 break;
2402         case DWC3_DEVICE_EVENT_HIBER_REQ:
2403                 if (!dwc->has_hibernation) {
2404                         WARN(1 ,"unexpected hibernation event\n");
2405                         break;
2406                 }
2407                 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2408                 break;
2409         case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2410                 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2411                 break;
2412         case DWC3_DEVICE_EVENT_EOPF:
2413                 dev_vdbg(dwc->dev, "End of Periodic Frame\n");
2414                 break;
2415         case DWC3_DEVICE_EVENT_SOF:
2416                 dev_vdbg(dwc->dev, "Start of Periodic Frame\n");
2417                 break;
2418         case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2419                 dev_vdbg(dwc->dev, "Erratic Error\n");
2420                 break;
2421         case DWC3_DEVICE_EVENT_CMD_CMPL:
2422                 dev_vdbg(dwc->dev, "Command Complete\n");
2423                 break;
2424         case DWC3_DEVICE_EVENT_OVERFLOW:
2425                 dev_vdbg(dwc->dev, "Overflow\n");
2426                 break;
2427         default:
2428                 dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2429         }
2430 }
2431
2432 static void dwc3_process_event_entry(struct dwc3 *dwc,
2433                 const union dwc3_event *event)
2434 {
2435         /* Endpoint IRQ, handle it and return early */
2436         if (event->type.is_devspec == 0) {
2437                 /* depevt */
2438                 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2439         }
2440
2441         switch (event->type.type) {
2442         case DWC3_EVENT_TYPE_DEV:
2443                 dwc3_gadget_interrupt(dwc, &event->devt);
2444                 break;
2445         /* REVISIT what to do with Carkit and I2C events ? */
2446         default:
2447                 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2448         }
2449 }
2450
2451 static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
2452 {
2453         struct dwc3_event_buffer *evt;
2454         irqreturn_t ret = IRQ_NONE;
2455         int left;
2456         u32 reg;
2457
2458         evt = dwc->ev_buffs[buf];
2459         left = evt->count;
2460
2461         if (!(evt->flags & DWC3_EVENT_PENDING))
2462                 return IRQ_NONE;
2463
2464         while (left > 0) {
2465                 union dwc3_event event;
2466
2467                 event.raw = *(u32 *) (evt->buf + evt->lpos);
2468
2469                 dwc3_process_event_entry(dwc, &event);
2470
2471                 /*
2472                  * FIXME we wrap around correctly to the next entry as
2473                  * almost all entries are 4 bytes in size. There is one
2474                  * entry which has 12 bytes which is a regular entry
2475                  * followed by 8 bytes data. ATM I don't know how
2476                  * things are organized if we get next to the a
2477                  * boundary so I worry about that once we try to handle
2478                  * that.
2479                  */
2480                 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2481                 left -= 4;
2482
2483                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4);
2484         }
2485
2486         evt->count = 0;
2487         evt->flags &= ~DWC3_EVENT_PENDING;
2488         ret = IRQ_HANDLED;
2489
2490         /* Unmask interrupt */
2491         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2492         reg &= ~DWC3_GEVNTSIZ_INTMASK;
2493         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
2494
2495         return ret;
2496 }
2497
2498 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc)
2499 {
2500         struct dwc3 *dwc = _dwc;
2501         unsigned long flags;
2502         irqreturn_t ret = IRQ_NONE;
2503         int i;
2504
2505         spin_lock_irqsave(&dwc->lock, flags);
2506
2507         for (i = 0; i < dwc->num_event_buffers; i++)
2508                 ret |= dwc3_process_event_buf(dwc, i);
2509
2510         spin_unlock_irqrestore(&dwc->lock, flags);
2511
2512         return ret;
2513 }
2514
2515 static irqreturn_t dwc3_check_event_buf(struct dwc3 *dwc, u32 buf)
2516 {
2517         struct dwc3_event_buffer *evt;
2518         u32 count;
2519         u32 reg;
2520
2521         evt = dwc->ev_buffs[buf];
2522
2523         count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
2524         count &= DWC3_GEVNTCOUNT_MASK;
2525         if (!count)
2526                 return IRQ_NONE;
2527
2528         evt->count = count;
2529         evt->flags |= DWC3_EVENT_PENDING;
2530
2531         /* Mask interrupt */
2532         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2533         reg |= DWC3_GEVNTSIZ_INTMASK;
2534         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
2535
2536         return IRQ_WAKE_THREAD;
2537 }
2538
2539 static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
2540 {
2541         struct dwc3                     *dwc = _dwc;
2542         int                             i;
2543         irqreturn_t                     ret = IRQ_NONE;
2544
2545         spin_lock(&dwc->lock);
2546
2547         for (i = 0; i < dwc->num_event_buffers; i++) {
2548                 irqreturn_t status;
2549
2550                 status = dwc3_check_event_buf(dwc, i);
2551                 if (status == IRQ_WAKE_THREAD)
2552                         ret = status;
2553         }
2554
2555         spin_unlock(&dwc->lock);
2556
2557         return ret;
2558 }
2559
2560 /**
2561  * dwc3_gadget_init - Initializes gadget related registers
2562  * @dwc: pointer to our controller context structure
2563  *
2564  * Returns 0 on success otherwise negative errno.
2565  */
2566 int dwc3_gadget_init(struct dwc3 *dwc)
2567 {
2568         int                                     ret;
2569
2570         dwc->ctrl_req = dma_alloc_coherent(sizeof(*dwc->ctrl_req),
2571                                         (unsigned long *)&dwc->ctrl_req_addr);
2572         if (!dwc->ctrl_req) {
2573                 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2574                 ret = -ENOMEM;
2575                 goto err0;
2576         }
2577
2578         dwc->ep0_trb = dma_alloc_coherent(sizeof(*dwc->ep0_trb),
2579                                           (unsigned long *)&dwc->ep0_trb_addr);
2580         if (!dwc->ep0_trb) {
2581                 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2582                 ret = -ENOMEM;
2583                 goto err1;
2584         }
2585
2586         dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
2587         if (!dwc->setup_buf) {
2588                 ret = -ENOMEM;
2589                 goto err2;
2590         }
2591
2592         dwc->ep0_bounce = dma_alloc_coherent(DWC3_EP0_BOUNCE_SIZE,
2593                                         (unsigned long *)&dwc->ep0_bounce_addr);
2594         if (!dwc->ep0_bounce) {
2595                 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2596                 ret = -ENOMEM;
2597                 goto err3;
2598         }
2599
2600         dwc->gadget.ops                 = &dwc3_gadget_ops;
2601         dwc->gadget.max_speed           = USB_SPEED_SUPER;
2602         dwc->gadget.speed               = USB_SPEED_UNKNOWN;
2603         dwc->gadget.name                = "dwc3-gadget";
2604
2605         /*
2606          * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
2607          * on ep out.
2608          */
2609         dwc->gadget.quirk_ep_out_aligned_size = true;
2610
2611         /*
2612          * REVISIT: Here we should clear all pending IRQs to be
2613          * sure we're starting from a well known location.
2614          */
2615
2616         ret = dwc3_gadget_init_endpoints(dwc);
2617         if (ret)
2618                 goto err4;
2619
2620         ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2621         if (ret) {
2622                 dev_err(dwc->dev, "failed to register udc\n");
2623                 goto err4;
2624         }
2625
2626         return 0;
2627
2628 err4:
2629         dwc3_gadget_free_endpoints(dwc);
2630         dma_free_coherent(dwc->ep0_bounce);
2631
2632 err3:
2633         kfree(dwc->setup_buf);
2634
2635 err2:
2636         dma_free_coherent(dwc->ep0_trb);
2637
2638 err1:
2639         dma_free_coherent(dwc->ctrl_req);
2640
2641 err0:
2642         return ret;
2643 }
2644
2645 /* -------------------------------------------------------------------------- */
2646
2647 void dwc3_gadget_exit(struct dwc3 *dwc)
2648 {
2649         usb_del_gadget_udc(&dwc->gadget);
2650
2651         dwc3_gadget_free_endpoints(dwc);
2652
2653         dma_free_coherent(dwc->ep0_bounce);
2654
2655         kfree(dwc->setup_buf);
2656
2657         dma_free_coherent(dwc->ep0_trb);
2658
2659         dma_free_coherent(dwc->ctrl_req);
2660 }
2661
2662 /**
2663  * dwc3_gadget_uboot_handle_interrupt - handle dwc3 gadget interrupt
2664  * @dwc: struct dwce *
2665  *
2666  * Handles ep0 and gadget interrupt
2667  *
2668  * Should be called from dwc3 core.
2669  */
2670 void dwc3_gadget_uboot_handle_interrupt(struct dwc3 *dwc)
2671 {
2672         dwc3_interrupt(0, dwc);
2673         dwc3_thread_interrupt(0, dwc);
2674 }