drivers/usb/dwc3/gadget.c

   1 /**
   2  * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * This program is free software: you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2  of
  11  * the License as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/delay.h>
  21 #include <linux/slab.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/pm_runtime.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/io.h>
  27 #include <linux/list.h>
  28 #include <linux/dma-mapping.h>
  29
  30 #include <linux/usb/ch9.h>
  31 #include <linux/usb/gadget.h>
  32
  33 #include "debug.h"
  34 #include "core.h"
  35 #include "gadget.h"
  36 #include "io.h"
  37
  38 /**
  39  * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
  40  * @dwc: pointer to our context structure
  41  * @mode: the mode to set (J, K SE0 NAK, Force Enable)
  42  *
  43  * Caller should take care of locking. This function will
  44  * return 0 on success or -EINVAL if wrong Test Selector
  45  * is passed
  46  */
  47 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
  48 {
  49         u32             reg;
  50
  51         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  52         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
  53
  54         switch (mode) {
  55         case TEST_J:
  56         case TEST_K:
  57         case TEST_SE0_NAK:
  58         case TEST_PACKET:
  59         case TEST_FORCE_EN:
  60                 reg |= mode << 1;
  61                 break;
  62         default:
  63                 return -EINVAL;
  64         }
  65
  66         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  67
  68         return 0;
  69 }
  70
  71 /**
  72  * dwc3_gadget_get_link_state - Gets current state of USB Link
  73  * @dwc: pointer to our context structure
  74  *
  75  * Caller should take care of locking. This function will
  76  * return the link state on success (>= 0) or -ETIMEDOUT.
  77  */
  78 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
  79 {
  80         u32             reg;
  81
  82         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
  83
  84         return DWC3_DSTS_USBLNKST(reg);
  85 }
  86
  87 /**
  88  * dwc3_gadget_set_link_state - Sets USB Link to a particular State
  89  * @dwc: pointer to our context structure
  90  * @state: the state to put link into
  91  *
  92  * Caller should take care of locking. This function will
  93  * return 0 on success or -ETIMEDOUT.
  94  */
  95 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
  96 {
  97         int             retries = 10000;
  98         u32             reg;
  99
 100         /*
 101          * Wait until device controller is ready. Only applies to 1.94a and
 102          * later RTL.
 103          */
 104         if (dwc->revision >= DWC3_REVISION_194A) {
 105                 while (--retries) {
 106                         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 107                         if (reg & DWC3_DSTS_DCNRD)
 108                                 udelay(5);
 109                         else
 110                                 break;
 111                 }
 112
 113                 if (retries <= 0)
 114                         return -ETIMEDOUT;
 115         }
 116
 117         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 118         reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
 119
 120         /* set requested state */
 121         reg |= DWC3_DCTL_ULSTCHNGREQ(state);
 122         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 123
 124         /*
 125          * The following code is racy when called from dwc3_gadget_wakeup,
 126          * and is not needed, at least on newer versions
 127          */
 128         if (dwc->revision >= DWC3_REVISION_194A)
 129                 return 0;
 130
 131         /* wait for a change in DSTS */
 132         retries = 10000;
 133         while (--retries) {
 134                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 135
 136                 if (DWC3_DSTS_USBLNKST(reg) == state)
 137                         return 0;
 138
 139                 udelay(5);
 140         }
 141
 142         return -ETIMEDOUT;
 143 }
 144
 145 /**
 146  * dwc3_ep_inc_trb() - Increment a TRB index.
 147  * @index - Pointer to the TRB index to increment.
 148  *
 149  * The index should never point to the link TRB. After incrementing,
 150  * if it is point to the link TRB, wrap around to the beginning. The
 151  * link TRB is always at the last TRB entry.
 152  */
 153 static void dwc3_ep_inc_trb(u8 *index)
 154 {
 155         (*index)++;
 156         if (*index == (DWC3_TRB_NUM - 1))
 157                 *index = 0;
 158 }
 159
 160 static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
 161 {
 162         dwc3_ep_inc_trb(&dep->trb_enqueue);
 163 }
 164
 165 static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
 166 {
 167         dwc3_ep_inc_trb(&dep->trb_dequeue);
 168 }
 169
 170 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
 171                 int status)
 172 {
 173         struct dwc3                     *dwc = dep->dwc;
 174
 175         req->started = false;
 176         list_del(&req->list);
 177         req->trb = NULL;
 178         req->remaining = 0;
 179
 180         if (req->request.status == -EINPROGRESS)
 181                 req->request.status = status;
 182
 183         usb_gadget_unmap_request_by_dev(dwc->sysdev,
 184                                         &req->request, req->direction);
 185
 186         trace_dwc3_gadget_giveback(req);
 187
 188         spin_unlock(&dwc->lock);
 189         usb_gadget_giveback_request(&dep->endpoint, &req->request);
 190         spin_lock(&dwc->lock);
 191
 192         if (dep->number > 1)
 193                 pm_runtime_put(dwc->dev);
 194 }
 195
 196 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
 197 {
 198         u32             timeout = 500;
 199         int             status = 0;
 200         int             ret = 0;
 201         u32             reg;
 202
 203         dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
 204         dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
 205
 206         do {
 207                 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
 208                 if (!(reg & DWC3_DGCMD_CMDACT)) {
 209                         status = DWC3_DGCMD_STATUS(reg);
 210                         if (status)
 211                                 ret = -EINVAL;
 212                         break;
 213                 }
 214         } while (--timeout);
 215
 216         if (!timeout) {
 217                 ret = -ETIMEDOUT;
 218                 status = -ETIMEDOUT;
 219         }
 220
 221         trace_dwc3_gadget_generic_cmd(cmd, param, status);
 222
 223         return ret;
 224 }
 225
 226 static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
 227
 228 int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
 229                 struct dwc3_gadget_ep_cmd_params *params)
 230 {
 231         const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
 232         struct dwc3             *dwc = dep->dwc;
 233         u32                     timeout = 500;
 234         u32                     reg;
 235
 236         int                     cmd_status = 0;
 237         int                     susphy = false;
 238         int                     ret = -EINVAL;
 239
 240         /*
 241          * Synopsys Databook 2.60a states, on section 6.3.2.5.[1-8], that if
 242          * we're issuing an endpoint command, we must check if
 243          * GUSB2PHYCFG.SUSPHY bit is set. If it is, then we need to clear it.
 244          *
 245          * We will also set SUSPHY bit to what it was before returning as stated
 246          * by the same section on Synopsys databook.
 247          */
 248         if (dwc->gadget.speed <= USB_SPEED_HIGH) {
 249                 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 250                 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
 251                         susphy = true;
 252                         reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 253                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 254                 }
 255         }
 256
 257         if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
 258                 int             needs_wakeup;
 259
 260                 needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 ||
 261                                 dwc->link_state == DWC3_LINK_STATE_U2 ||
 262                                 dwc->link_state == DWC3_LINK_STATE_U3);
 263
 264                 if (unlikely(needs_wakeup)) {
 265                         ret = __dwc3_gadget_wakeup(dwc);
 266                         dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
 267                                         ret);
 268                 }
 269         }
 270
 271         dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
 272         dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
 273         dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
 274
 275         /*
 276          * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're
 277          * not relying on XferNotReady, we can make use of a special "No
 278          * Response Update Transfer" command where we should clear both CmdAct
 279          * and CmdIOC bits.
 280          *
 281          * With this, we don't need to wait for command completion and can
 282          * straight away issue further commands to the endpoint.
 283          *
 284          * NOTICE: We're making an assumption that control endpoints will never
 285          * make use of Update Transfer command. This is a safe assumption
 286          * because we can never have more than one request at a time with
 287          * Control Endpoints. If anybody changes that assumption, this chunk
 288          * needs to be updated accordingly.
 289          */
 290         if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER &&
 291                         !usb_endpoint_xfer_isoc(desc))
 292                 cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT);
 293         else
 294                 cmd |= DWC3_DEPCMD_CMDACT;
 295
 296         dwc3_writel(dep->regs, DWC3_DEPCMD, cmd);
 297         do {
 298                 reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
 299                 if (!(reg & DWC3_DEPCMD_CMDACT)) {
 300                         cmd_status = DWC3_DEPCMD_STATUS(reg);
 301
 302                         switch (cmd_status) {
 303                         case 0:
 304                                 ret = 0;
 305                                 break;
 306                         case DEPEVT_TRANSFER_NO_RESOURCE:
 307                                 ret = -EINVAL;
 308                                 break;
 309                         case DEPEVT_TRANSFER_BUS_EXPIRY:
 310                                 /*
 311                                  * SW issues START TRANSFER command to
 312                                  * isochronous ep with future frame interval. If
 313                                  * future interval time has already passed when
 314                                  * core receives the command, it will respond
 315                                  * with an error status of 'Bus Expiry'.
 316                                  *
 317                                  * Instead of always returning -EINVAL, let's
 318                                  * give a hint to the gadget driver that this is
 319                                  * the case by returning -EAGAIN.
 320                                  */
 321                                 ret = -EAGAIN;
 322                                 break;
 323                         default:
 324                                 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
 325                         }
 326
 327                         break;
 328                 }
 329         } while (--timeout);
 330
 331         if (timeout == 0) {
 332                 ret = -ETIMEDOUT;
 333                 cmd_status = -ETIMEDOUT;
 334         }
 335
 336         trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status);
 337
 338         if (ret == 0) {
 339                 switch (DWC3_DEPCMD_CMD(cmd)) {
 340                 case DWC3_DEPCMD_STARTTRANSFER:
 341                         dep->flags |= DWC3_EP_TRANSFER_STARTED;
 342                         break;
 343                 case DWC3_DEPCMD_ENDTRANSFER:
 344                         dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
 345                         break;
 346                 default:
 347                         /* nothing */
 348                         break;
 349                 }
 350         }
 351
 352         if (unlikely(susphy)) {
 353                 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 354                 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
 355                 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 356         }
 357
 358         return ret;
 359 }
 360
 361 static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
 362 {
 363         struct dwc3 *dwc = dep->dwc;
 364         struct dwc3_gadget_ep_cmd_params params;
 365         u32 cmd = DWC3_DEPCMD_CLEARSTALL;
 366
 367         /*
 368          * As of core revision 2.60a the recommended programming model
 369          * is to set the ClearPendIN bit when issuing a Clear Stall EP
 370          * command for IN endpoints. This is to prevent an issue where
 371          * some (non-compliant) hosts may not send ACK TPs for pending
 372          * IN transfers due to a mishandled error condition. Synopsys
 373          * STAR 9000614252.
 374          */
 375         if (dep->direction && (dwc->revision >= DWC3_REVISION_260A) &&
 376             (dwc->gadget.speed >= USB_SPEED_SUPER))
 377                 cmd |= DWC3_DEPCMD_CLEARPENDIN;
 378
 379         memset(&params, 0, sizeof(params));
 380
 381         return dwc3_send_gadget_ep_cmd(dep, cmd, &params);
 382 }
 383
 384 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
 385                 struct dwc3_trb *trb)
 386 {
 387         u32             offset = (char *) trb - (char *) dep->trb_pool;
 388
 389         return dep->trb_pool_dma + offset;
 390 }
 391
 392 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
 393 {
 394         struct dwc3             *dwc = dep->dwc;
 395
 396         if (dep->trb_pool)
 397                 return 0;
 398
 399         dep->trb_pool = dma_alloc_coherent(dwc->sysdev,
 400                         sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 401                         &dep->trb_pool_dma, GFP_KERNEL);
 402         if (!dep->trb_pool) {
 403                 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
 404                                 dep->name);
 405                 return -ENOMEM;
 406         }
 407
 408         return 0;
 409 }
 410
 411 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
 412 {
 413         struct dwc3             *dwc = dep->dwc;
 414
 415         dma_free_coherent(dwc->sysdev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 416                         dep->trb_pool, dep->trb_pool_dma);
 417
 418         dep->trb_pool = NULL;
 419         dep->trb_pool_dma = 0;
 420 }
 421
 422 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep);
 423
 424 /**
 425  * dwc3_gadget_start_config - Configure EP resources
 426  * @dwc: pointer to our controller context structure
 427  * @dep: endpoint that is being enabled
 428  *
 429  * The assignment of transfer resources cannot perfectly follow the
 430  * data book due to the fact that the controller driver does not have
 431  * all knowledge of the configuration in advance. It is given this
 432  * information piecemeal by the composite gadget framework after every
 433  * SET_CONFIGURATION and SET_INTERFACE. Trying to follow the databook
 434  * programming model in this scenario can cause errors. For two
 435  * reasons:
 436  *
 437  * 1) The databook says to do DEPSTARTCFG for every SET_CONFIGURATION
 438  * and SET_INTERFACE (8.1.5). This is incorrect in the scenario of
 439  * multiple interfaces.
 440  *
 441  * 2) The databook does not mention doing more DEPXFERCFG for new
 442  * endpoint on alt setting (8.1.6).
 443  *
 444  * The following simplified method is used instead:
 445  *
 446  * All hardware endpoints can be assigned a transfer resource and this
 447  * setting will stay persistent until either a core reset or
 448  * hibernation. So whenever we do a DEPSTARTCFG(0) we can go ahead and
 449  * do DEPXFERCFG for every hardware endpoint as well. We are
 450  * guaranteed that there are as many transfer resources as endpoints.
 451  *
 452  * This function is called for each endpoint when it is being enabled
 453  * but is triggered only when called for EP0-out, which always happens
 454  * first, and which should only happen in one of the above conditions.
 455  */
 456 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
 457 {
 458         struct dwc3_gadget_ep_cmd_params params;
 459         u32                     cmd;
 460         int                     i;
 461         int                     ret;
 462
 463         if (dep->number)
 464                 return 0;
 465
 466         memset(&params, 0x00, sizeof(params));
 467         cmd = DWC3_DEPCMD_DEPSTARTCFG;
 468
 469         ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
 470         if (ret)
 471                 return ret;
 472
 473         for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
 474                 struct dwc3_ep *dep = dwc->eps[i];
 475
 476                 if (!dep)
 477                         continue;
 478
 479                 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
 480                 if (ret)
 481                         return ret;
 482         }
 483
 484         return 0;
 485 }
 486
 487 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
 488                 bool modify, bool restore)
 489 {
 490         const struct usb_ss_ep_comp_descriptor *comp_desc;
 491         const struct usb_endpoint_descriptor *desc;
 492         struct dwc3_gadget_ep_cmd_params params;
 493
 494         if (dev_WARN_ONCE(dwc->dev, modify && restore,
 495                                         "Can't modify and restore\n"))
 496                 return -EINVAL;
 497
 498         comp_desc = dep->endpoint.comp_desc;
 499         desc = dep->endpoint.desc;
 500
 501         memset(&params, 0x00, sizeof(params));
 502
 503         params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
 504                 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
 505
 506         /* Burst size is only needed in SuperSpeed mode */
 507         if (dwc->gadget.speed >= USB_SPEED_SUPER) {
 508                 u32 burst = dep->endpoint.maxburst;
 509                 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
 510         }
 511
 512         if (modify) {
 513                 params.param0 |= DWC3_DEPCFG_ACTION_MODIFY;
 514         } else if (restore) {
 515                 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
 516                 params.param2 |= dep->saved_state;
 517         } else {
 518                 params.param0 |= DWC3_DEPCFG_ACTION_INIT;
 519         }
 520
 521         if (usb_endpoint_xfer_control(desc))
 522                 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN;
 523
 524         if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc))
 525                 params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN;
 526
 527         if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
 528                 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
 529                         | DWC3_DEPCFG_STREAM_EVENT_EN;
 530                 dep->stream_capable = true;
 531         }
 532
 533         if (!usb_endpoint_xfer_control(desc))
 534                 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
 535
 536         /*
 537          * We are doing 1:1 mapping for endpoints, meaning
 538          * Physical Endpoints 2 maps to Logical Endpoint 2 and
 539          * so on. We consider the direction bit as part of the physical
 540          * endpoint number. So USB endpoint 0x81 is 0x03.
 541          */
 542         params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
 543
 544         /*
 545          * We must use the lower 16 TX FIFOs even though
 546          * HW might have more
 547          */
 548         if (dep->direction)
 549                 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
 550
 551         if (desc->bInterval) {
 552                 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
 553                 dep->interval = 1 << (desc->bInterval - 1);
 554         }
 555
 556         return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, &params);
 557 }
 558
 559 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
 560 {
 561         struct dwc3_gadget_ep_cmd_params params;
 562
 563         memset(&params, 0x00, sizeof(params));
 564
 565         params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
 566
 567         return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
 568                         &params);
 569 }
 570
 571 /**
 572  * __dwc3_gadget_ep_enable - Initializes a HW endpoint
 573  * @dep: endpoint to be initialized
 574  * @desc: USB Endpoint Descriptor
 575  *
 576  * Caller should take care of locking
 577  */
 578 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
 579                 bool modify, bool restore)
 580 {
 581         const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
 582         struct dwc3             *dwc = dep->dwc;
 583
 584         u32                     reg;
 585         int                     ret;
 586
 587         if (!(dep->flags & DWC3_EP_ENABLED)) {
 588                 ret = dwc3_gadget_start_config(dwc, dep);
 589                 if (ret)
 590                         return ret;
 591         }
 592
 593         ret = dwc3_gadget_set_ep_config(dwc, dep, modify, restore);
 594         if (ret)
 595                 return ret;
 596
 597         if (!(dep->flags & DWC3_EP_ENABLED)) {
 598                 struct dwc3_trb *trb_st_hw;
 599                 struct dwc3_trb *trb_link;
 600
 601                 dep->type = usb_endpoint_type(desc);
 602                 dep->flags |= DWC3_EP_ENABLED;
 603                 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
 604
 605                 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 606                 reg |= DWC3_DALEPENA_EP(dep->number);
 607                 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 608
 609                 init_waitqueue_head(&dep->wait_end_transfer);
 610
 611                 if (usb_endpoint_xfer_control(desc))
 612                         goto out;
 613
 614                 /* Initialize the TRB ring */
 615                 dep->trb_dequeue = 0;
 616                 dep->trb_enqueue = 0;
 617                 memset(dep->trb_pool, 0,
 618                        sizeof(struct dwc3_trb) * DWC3_TRB_NUM);
 619
 620                 /* Link TRB. The HWO bit is never reset */
 621                 trb_st_hw = &dep->trb_pool[0];
 622
 623                 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
 624                 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 625                 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 626                 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
 627                 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
 628         }
 629
 630         /*
 631          * Issue StartTransfer here with no-op TRB so we can always rely on No
 632          * Response Update Transfer command.
 633          */
 634         if (usb_endpoint_xfer_bulk(desc)) {
 635                 struct dwc3_gadget_ep_cmd_params params;
 636                 struct dwc3_trb *trb;
 637                 dma_addr_t trb_dma;
 638                 u32 cmd;
 639
 640                 memset(&params, 0, sizeof(params));
 641                 trb = &dep->trb_pool[0];
 642                 trb_dma = dwc3_trb_dma_offset(dep, trb);
 643
 644                 params.param0 = upper_32_bits(trb_dma);
 645                 params.param1 = lower_32_bits(trb_dma);
 646
 647                 cmd = DWC3_DEPCMD_STARTTRANSFER;
 648
 649                 ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
 650                 if (ret < 0)
 651                         return ret;
 652
 653                 dep->flags |= DWC3_EP_BUSY;
 654
 655                 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
 656                 WARN_ON_ONCE(!dep->resource_index);
 657         }
 658
 659
 660 out:
 661         trace_dwc3_gadget_ep_enable(dep);
 662
 663         return 0;
 664 }
 665
 666 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
 667 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
 668 {
 669         struct dwc3_request             *req;
 670
 671         dwc3_stop_active_transfer(dwc, dep->number, true);
 672
 673         /* - giveback all requests to gadget driver */
 674         while (!list_empty(&dep->started_list)) {
 675                 req = next_request(&dep->started_list);
 676
 677                 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 678         }
 679
 680         while (!list_empty(&dep->pending_list)) {
 681                 req = next_request(&dep->pending_list);
 682
 683                 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 684         }
 685 }
 686
 687 /**
 688  * __dwc3_gadget_ep_disable - Disables a HW endpoint
 689  * @dep: the endpoint to disable
 690  *
 691  * This function also removes requests which are currently processed ny the
 692  * hardware and those which are not yet scheduled.
 693  * Caller should take care of locking.
 694  */
 695 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
 696 {
 697         struct dwc3             *dwc = dep->dwc;
 698         u32                     reg;
 699
 700         trace_dwc3_gadget_ep_disable(dep);
 701
 702         dwc3_remove_requests(dwc, dep);
 703
 704         /* make sure HW endpoint isn't stalled */
 705         if (dep->flags & DWC3_EP_STALL)
 706                 __dwc3_gadget_ep_set_halt(dep, 0, false);
 707
 708         reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 709         reg &= ~DWC3_DALEPENA_EP(dep->number);
 710         dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 711
 712         dep->stream_capable = false;
 713         dep->type = 0;
 714         dep->flags &= DWC3_EP_END_TRANSFER_PENDING;
 715
 716         /* Clear out the ep descriptors for non-ep0 */
 717         if (dep->number > 1) {
 718                 dep->endpoint.comp_desc = NULL;
 719                 dep->endpoint.desc = NULL;
 720         }
 721
 722         return 0;
 723 }
 724
 725 /* -------------------------------------------------------------------------- */
 726
 727 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
 728                 const struct usb_endpoint_descriptor *desc)
 729 {
 730         return -EINVAL;
 731 }
 732
 733 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
 734 {
 735         return -EINVAL;
 736 }
 737
 738 /* -------------------------------------------------------------------------- */
 739
 740 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
 741                 const struct usb_endpoint_descriptor *desc)
 742 {
 743         struct dwc3_ep                  *dep;
 744         struct dwc3                     *dwc;
 745         unsigned long                   flags;
 746         int                             ret;
 747
 748         if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
 749                 pr_debug("dwc3: invalid parameters\n");
 750                 return -EINVAL;
 751         }
 752
 753         if (!desc->wMaxPacketSize) {
 754                 pr_debug("dwc3: missing wMaxPacketSize\n");
 755                 return -EINVAL;
 756         }
 757
 758         dep = to_dwc3_ep(ep);
 759         dwc = dep->dwc;
 760
 761         if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
 762                                         "%s is already enabled\n",
 763                                         dep->name))
 764                 return 0;
 765
 766         spin_lock_irqsave(&dwc->lock, flags);
 767         ret = __dwc3_gadget_ep_enable(dep, false, false);
 768         spin_unlock_irqrestore(&dwc->lock, flags);
 769
 770         return ret;
 771 }
 772
 773 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
 774 {
 775         struct dwc3_ep                  *dep;
 776         struct dwc3                     *dwc;
 777         unsigned long                   flags;
 778         int                             ret;
 779
 780         if (!ep) {
 781                 pr_debug("dwc3: invalid parameters\n");
 782                 return -EINVAL;
 783         }
 784
 785         dep = to_dwc3_ep(ep);
 786         dwc = dep->dwc;
 787
 788         if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
 789                                         "%s is already disabled\n",
 790                                         dep->name))
 791                 return 0;
 792
 793         spin_lock_irqsave(&dwc->lock, flags);
 794         ret = __dwc3_gadget_ep_disable(dep);
 795         spin_unlock_irqrestore(&dwc->lock, flags);
 796
 797         return ret;
 798 }
 799
 800 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
 801         gfp_t gfp_flags)
 802 {
 803         struct dwc3_request             *req;
 804         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 805
 806         req = kzalloc(sizeof(*req), gfp_flags);
 807         if (!req)
 808                 return NULL;
 809
 810         req->epnum      = dep->number;
 811         req->dep        = dep;
 812
 813         dep->allocated_requests++;
 814
 815         trace_dwc3_alloc_request(req);
 816
 817         return &req->request;
 818 }
 819
 820 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
 821                 struct usb_request *request)
 822 {
 823         struct dwc3_request             *req = to_dwc3_request(request);
 824         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 825
 826         dep->allocated_requests--;
 827         trace_dwc3_free_request(req);
 828         kfree(req);
 829 }
 830
 831 static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep);
 832
 833 static void __dwc3_prepare_one_trb(struct dwc3_ep *dep, struct dwc3_trb *trb,
 834                 dma_addr_t dma, unsigned length, unsigned chain, unsigned node,
 835                 unsigned stream_id, unsigned short_not_ok, unsigned no_interrupt)
 836 {
 837         struct dwc3             *dwc = dep->dwc;
 838         struct usb_gadget       *gadget = &dwc->gadget;
 839         enum usb_device_speed   speed = gadget->speed;
 840
 841         dwc3_ep_inc_enq(dep);
 842
 843         trb->size = DWC3_TRB_SIZE_LENGTH(length);
 844         trb->bpl = lower_32_bits(dma);
 845         trb->bph = upper_32_bits(dma);
 846
 847         switch (usb_endpoint_type(dep->endpoint.desc)) {
 848         case USB_ENDPOINT_XFER_CONTROL:
 849                 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
 850                 break;
 851
 852         case USB_ENDPOINT_XFER_ISOC:
 853                 if (!node) {
 854                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
 855
 856                         if (speed == USB_SPEED_HIGH) {
 857                                 struct usb_ep *ep = &dep->endpoint;
 858                                 trb->size |= DWC3_TRB_SIZE_PCM1(ep->mult - 1);
 859                         }
 860                 } else {
 861                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
 862                 }
 863
 864                 /* always enable Interrupt on Missed ISOC */
 865                 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
 866                 break;
 867
 868         case USB_ENDPOINT_XFER_BULK:
 869         case USB_ENDPOINT_XFER_INT:
 870                 trb->ctrl = DWC3_TRBCTL_NORMAL;
 871                 break;
 872         default:
 873                 /*
 874                  * This is only possible with faulty memory because we
 875                  * checked it already :)
 876                  */
 877                 dev_WARN(dwc->dev, "Unknown endpoint type %d\n",
 878                                 usb_endpoint_type(dep->endpoint.desc));
 879         }
 880
 881         /* always enable Continue on Short Packet */
 882         if (usb_endpoint_dir_out(dep->endpoint.desc)) {
 883                 trb->ctrl |= DWC3_TRB_CTRL_CSP;
 884
 885                 if (short_not_ok)
 886                         trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
 887         }
 888
 889         if ((!no_interrupt && !chain) ||
 890                         (dwc3_calc_trbs_left(dep) == 0))
 891                 trb->ctrl |= DWC3_TRB_CTRL_IOC;
 892
 893         if (chain)
 894                 trb->ctrl |= DWC3_TRB_CTRL_CHN;
 895
 896         if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
 897                 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(stream_id);
 898
 899         trb->ctrl |= DWC3_TRB_CTRL_HWO;
 900
 901         trace_dwc3_prepare_trb(dep, trb);
 902 }
 903
 904 /**
 905  * dwc3_prepare_one_trb - setup one TRB from one request
 906  * @dep: endpoint for which this request is prepared
 907  * @req: dwc3_request pointer
 908  * @chain: should this TRB be chained to the next?
 909  * @node: only for isochronous endpoints. First TRB needs different type.
 910  */
 911 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
 912                 struct dwc3_request *req, unsigned chain, unsigned node)
 913 {
 914         struct dwc3_trb         *trb;
 915         unsigned                length = req->request.length;
 916         unsigned                stream_id = req->request.stream_id;
 917         unsigned                short_not_ok = req->request.short_not_ok;
 918         unsigned                no_interrupt = req->request.no_interrupt;
 919         dma_addr_t              dma = req->request.dma;
 920
 921         trb = &dep->trb_pool[dep->trb_enqueue];
 922
 923         if (!req->trb) {
 924                 dwc3_gadget_move_started_request(req);
 925                 req->trb = trb;
 926                 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
 927                 dep->queued_requests++;
 928         }
 929
 930         __dwc3_prepare_one_trb(dep, trb, dma, length, chain, node,
 931                         stream_id, short_not_ok, no_interrupt);
 932 }
 933
 934 /**
 935  * dwc3_ep_prev_trb() - Returns the previous TRB in the ring
 936  * @dep: The endpoint with the TRB ring
 937  * @index: The index of the current TRB in the ring
 938  *
 939  * Returns the TRB prior to the one pointed to by the index. If the
 940  * index is 0, we will wrap backwards, skip the link TRB, and return
 941  * the one just before that.
 942  */
 943 static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
 944 {
 945         u8 tmp = index;
 946
 947         if (!tmp)
 948                 tmp = DWC3_TRB_NUM - 1;
 949
 950         return &dep->trb_pool[tmp - 1];
 951 }
 952
 953 static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
 954 {
 955         struct dwc3_trb         *tmp;
 956         struct dwc3             *dwc = dep->dwc;
 957         u8                      trbs_left;
 958
 959         /*
 960          * If enqueue & dequeue are equal than it is either full or empty.
 961          *
 962          * One way to know for sure is if the TRB right before us has HWO bit
 963          * set or not. If it has, then we're definitely full and can't fit any
 964          * more transfers in our ring.
 965          */
 966         if (dep->trb_enqueue == dep->trb_dequeue) {
 967                 tmp = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
 968                 if (dev_WARN_ONCE(dwc->dev, tmp->ctrl & DWC3_TRB_CTRL_HWO,
 969                                   "%s No TRBS left\n", dep->name))
 970                         return 0;
 971
 972                 return DWC3_TRB_NUM - 1;
 973         }
 974
 975         trbs_left = dep->trb_dequeue - dep->trb_enqueue;
 976         trbs_left &= (DWC3_TRB_NUM - 1);
 977
 978         if (dep->trb_dequeue < dep->trb_enqueue)
 979                 trbs_left--;
 980
 981         return trbs_left;
 982 }
 983
 984 static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep,
 985                 struct dwc3_request *req)
 986 {
 987         struct scatterlist *sg = req->sg;
 988         struct scatterlist *s;
 989         int             i;
 990
 991         for_each_sg(sg, s, req->num_pending_sgs, i) {
 992                 unsigned int length = req->request.length;
 993                 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
 994                 unsigned int rem = length % maxp;
 995                 unsigned chain = true;
 996
 997                 if (sg_is_last(s))
 998                         chain = false;
 999
1000                 if (rem && usb_endpoint_dir_out(dep->endpoint.desc) && !chain) {
1001                         struct dwc3     *dwc = dep->dwc;
1002                         struct dwc3_trb *trb;
1003
1004                         req->unaligned = true;
1005
1006                         /* prepare normal TRB */
1007                         dwc3_prepare_one_trb(dep, req, true, i);
1008
1009                         /* Now prepare one extra TRB to align transfer size */
1010                         trb = &dep->trb_pool[dep->trb_enqueue];
1011                         __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr,
1012                                         maxp - rem, false, 0,
1013                                         req->request.stream_id,
1014                                         req->request.short_not_ok,
1015                                         req->request.no_interrupt);
1016                 } else {
1017                         dwc3_prepare_one_trb(dep, req, chain, i);
1018                 }
1019
1020                 if (!dwc3_calc_trbs_left(dep))
1021                         break;
1022         }
1023 }
1024
1025 static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep,
1026                 struct dwc3_request *req)
1027 {
1028         unsigned int length = req->request.length;
1029         unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1030         unsigned int rem = length % maxp;
1031
1032         if (rem && usb_endpoint_dir_out(dep->endpoint.desc)) {
1033                 struct dwc3     *dwc = dep->dwc;
1034                 struct dwc3_trb *trb;
1035
1036                 req->unaligned = true;
1037
1038                 /* prepare normal TRB */
1039                 dwc3_prepare_one_trb(dep, req, true, 0);
1040
1041                 /* Now prepare one extra TRB to align transfer size */
1042                 trb = &dep->trb_pool[dep->trb_enqueue];
1043                 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, maxp - rem,
1044                                 false, 0, req->request.stream_id,
1045                                 req->request.short_not_ok,
1046                                 req->request.no_interrupt);
1047         } else if (req->request.zero && req->request.length &&
1048                    (IS_ALIGNED(req->request.length,dep->endpoint.maxpacket))) {
1049                 struct dwc3     *dwc = dep->dwc;
1050                 struct dwc3_trb *trb;
1051
1052                 req->zero = true;
1053
1054                 /* prepare normal TRB */
1055                 dwc3_prepare_one_trb(dep, req, true, 0);
1056
1057                 /* Now prepare one extra TRB to handle ZLP */
1058                 trb = &dep->trb_pool[dep->trb_enqueue];
1059                 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, 0,
1060                                 false, 0, req->request.stream_id,
1061                                 req->request.short_not_ok,
1062                                 req->request.no_interrupt);
1063         } else {
1064                 dwc3_prepare_one_trb(dep, req, false, 0);
1065         }
1066 }
1067
1068 /*
1069  * dwc3_prepare_trbs - setup TRBs from requests
1070  * @dep: endpoint for which requests are being prepared
1071  *
1072  * The function goes through the requests list and sets up TRBs for the
1073  * transfers. The function returns once there are no more TRBs available or
1074  * it runs out of requests.
1075  */
1076 static void dwc3_prepare_trbs(struct dwc3_ep *dep)
1077 {
1078         struct dwc3_request     *req, *n;
1079
1080         BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
1081
1082         if (!dwc3_calc_trbs_left(dep))
1083                 return;
1084
1085         /*
1086          * We can get in a situation where there's a request in the started list
1087          * but there weren't enough TRBs to fully kick it in the first time
1088          * around, so it has been waiting for more TRBs to be freed up.
1089          *
1090          * In that case, we should check if we have a request with pending_sgs
1091          * in the started list and prepare TRBs for that request first,
1092          * otherwise we will prepare TRBs completely out of order and that will
1093          * break things.
1094          */
1095         list_for_each_entry(req, &dep->started_list, list) {
1096                 if (req->num_pending_sgs > 0)
1097                         dwc3_prepare_one_trb_sg(dep, req);
1098
1099                 if (!dwc3_calc_trbs_left(dep))
1100                         return;
1101         }
1102
1103         list_for_each_entry_safe(req, n, &dep->pending_list, list) {
1104                 if (req->num_pending_sgs > 0)
1105                         dwc3_prepare_one_trb_sg(dep, req);
1106                 else
1107                         dwc3_prepare_one_trb_linear(dep, req);
1108
1109                 if (!dwc3_calc_trbs_left(dep))
1110                         return;
1111         }
1112 }
1113
1114 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param)
1115 {
1116         struct dwc3_gadget_ep_cmd_params params;
1117         struct dwc3_request             *req;
1118         int                             starting;
1119         int                             ret;
1120         u32                             cmd;
1121
1122         starting = !(dep->flags & DWC3_EP_BUSY);
1123
1124         dwc3_prepare_trbs(dep);
1125         req = next_request(&dep->started_list);
1126         if (!req) {
1127                 dep->flags |= DWC3_EP_PENDING_REQUEST;
1128                 return 0;
1129         }
1130
1131         memset(&params, 0, sizeof(params));
1132
1133         if (starting) {
1134                 params.param0 = upper_32_bits(req->trb_dma);
1135                 params.param1 = lower_32_bits(req->trb_dma);
1136                 cmd = DWC3_DEPCMD_STARTTRANSFER |
1137                         DWC3_DEPCMD_PARAM(cmd_param);
1138         } else {
1139                 cmd = DWC3_DEPCMD_UPDATETRANSFER |
1140                         DWC3_DEPCMD_PARAM(dep->resource_index);
1141         }
1142
1143         ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
1144         if (ret < 0) {
1145                 /*
1146                  * FIXME we need to iterate over the list of requests
1147                  * here and stop, unmap, free and del each of the linked
1148                  * requests instead of what we do now.
1149                  */
1150                 if (req->trb)
1151                         memset(req->trb, 0, sizeof(struct dwc3_trb));
1152                 dep->queued_requests--;
1153                 dwc3_gadget_giveback(dep, req, ret);
1154                 return ret;
1155         }
1156
1157         dep->flags |= DWC3_EP_BUSY;
1158
1159         if (starting) {
1160                 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
1161                 WARN_ON_ONCE(!dep->resource_index);
1162         }
1163
1164         return 0;
1165 }
1166
1167 static int __dwc3_gadget_get_frame(struct dwc3 *dwc)
1168 {
1169         u32                     reg;
1170
1171         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1172         return DWC3_DSTS_SOFFN(reg);
1173 }
1174
1175 static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1176                 struct dwc3_ep *dep, u32 cur_uf)
1177 {
1178         u32 uf;
1179
1180         if (list_empty(&dep->pending_list)) {
1181                 dev_info(dwc->dev, "%s: ran out of requests\n",
1182                                 dep->name);
1183                 dep->flags |= DWC3_EP_PENDING_REQUEST;
1184                 return;
1185         }
1186
1187         /*
1188          * Schedule the first trb for one interval in the future or at
1189          * least 4 microframes.
1190          */
1191         uf = cur_uf + max_t(u32, 4, dep->interval);
1192
1193         __dwc3_gadget_kick_transfer(dep, uf);
1194 }
1195
1196 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1197                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1198 {
1199         u32 cur_uf, mask;
1200
1201         mask = ~(dep->interval - 1);
1202         cur_uf = event->parameters & mask;
1203
1204         __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1205 }
1206
1207 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1208 {
1209         struct dwc3             *dwc = dep->dwc;
1210         int                     ret;
1211
1212         if (!dep->endpoint.desc) {
1213                 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
1214                                 dep->name);
1215                 return -ESHUTDOWN;
1216         }
1217
1218         if (WARN(req->dep != dep, "request %p belongs to '%s'\n",
1219                                 &req->request, req->dep->name)) {
1220                 dev_err(dwc->dev, "%s: request %p belongs to '%s'\n",
1221                                 dep->name, &req->request, req->dep->name);
1222                 return -EINVAL;
1223         }
1224
1225         pm_runtime_get(dwc->dev);
1226
1227         req->request.actual     = 0;
1228         req->request.status     = -EINPROGRESS;
1229         req->direction          = dep->direction;
1230         req->epnum              = dep->number;
1231
1232         trace_dwc3_ep_queue(req);
1233
1234         ret = usb_gadget_map_request_by_dev(dwc->sysdev, &req->request,
1235                                             dep->direction);
1236         if (ret)
1237                 return ret;
1238
1239         req->sg                 = req->request.sg;
1240         req->num_pending_sgs    = req->request.num_mapped_sgs;
1241
1242         list_add_tail(&req->list, &dep->pending_list);
1243
1244         /*
1245          * NOTICE: Isochronous endpoints should NEVER be prestarted. We must
1246          * wait for a XferNotReady event so we will know what's the current
1247          * (micro-)frame number.
1248          *
1249          * Without this trick, we are very, very likely gonna get Bus Expiry
1250          * errors which will force us issue EndTransfer command.
1251          */
1252         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1253                 if ((dep->flags & DWC3_EP_PENDING_REQUEST)) {
1254                         if (dep->flags & DWC3_EP_TRANSFER_STARTED) {
1255                                 dwc3_stop_active_transfer(dwc, dep->number, true);
1256                                 dep->flags = DWC3_EP_ENABLED;
1257                         } else {
1258                                 u32 cur_uf;
1259
1260                                 cur_uf = __dwc3_gadget_get_frame(dwc);
1261                                 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1262                                 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
1263                         }
1264                 }
1265                 return 0;
1266         }
1267
1268         if (!dwc3_calc_trbs_left(dep))
1269                 return 0;
1270
1271         ret = __dwc3_gadget_kick_transfer(dep, 0);
1272         if (ret == -EBUSY)
1273                 ret = 0;
1274
1275         return ret;
1276 }
1277
1278 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1279         gfp_t gfp_flags)
1280 {
1281         struct dwc3_request             *req = to_dwc3_request(request);
1282         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1283         struct dwc3                     *dwc = dep->dwc;
1284
1285         unsigned long                   flags;
1286
1287         int                             ret;
1288
1289         spin_lock_irqsave(&dwc->lock, flags);
1290         ret = __dwc3_gadget_ep_queue(dep, req);
1291         spin_unlock_irqrestore(&dwc->lock, flags);
1292
1293         return ret;
1294 }
1295
1296 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1297                 struct usb_request *request)
1298 {
1299         struct dwc3_request             *req = to_dwc3_request(request);
1300         struct dwc3_request             *r = NULL;
1301
1302         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1303         struct dwc3                     *dwc = dep->dwc;
1304
1305         unsigned long                   flags;
1306         int                             ret = 0;
1307
1308         trace_dwc3_ep_dequeue(req);
1309
1310         spin_lock_irqsave(&dwc->lock, flags);
1311
1312         list_for_each_entry(r, &dep->pending_list, list) {
1313                 if (r == req)
1314                         break;
1315         }
1316
1317         if (r != req) {
1318                 list_for_each_entry(r, &dep->started_list, list) {
1319                         if (r == req)
1320                                 break;
1321                 }
1322                 if (r == req) {
1323                         /* wait until it is processed */
1324                         dwc3_stop_active_transfer(dwc, dep->number, true);
1325
1326                         /*
1327                          * If request was already started, this means we had to
1328                          * stop the transfer. With that we also need to ignore
1329                          * all TRBs used by the request, however TRBs can only
1330                          * be modified after completion of END_TRANSFER
1331                          * command. So what we do here is that we wait for
1332                          * END_TRANSFER completion and only after that, we jump
1333                          * over TRBs by clearing HWO and incrementing dequeue
1334                          * pointer.
1335                          *
1336                          * Note that we have 2 possible types of transfers here:
1337                          *
1338                          * i) Linear buffer request
1339                          * ii) SG-list based request
1340                          *
1341                          * SG-list based requests will have r->num_pending_sgs
1342                          * set to a valid number (> 0). Linear requests,
1343                          * normally use a single TRB.
1344                          *
1345                          * For each of these two cases, if r->unaligned flag is
1346                          * set, one extra TRB has been used to align transfer
1347                          * size to wMaxPacketSize.
1348                          *
1349                          * All of these cases need to be taken into
1350                          * consideration so we don't mess up our TRB ring
1351                          * pointers.
1352                          */
1353                         wait_event_lock_irq(dep->wait_end_transfer,
1354                                         !(dep->flags & DWC3_EP_END_TRANSFER_PENDING),
1355                                         dwc->lock);
1356
1357                         if (!r->trb)
1358                                 goto out1;
1359
1360                         if (r->num_pending_sgs) {
1361                                 struct dwc3_trb *trb;
1362                                 int i = 0;
1363
1364                                 for (i = 0; i < r->num_pending_sgs; i++) {
1365                                         trb = r->trb + i;
1366                                         trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1367                                         dwc3_ep_inc_deq(dep);
1368                                 }
1369
1370                                 if (r->unaligned || r->zero) {
1371                                         trb = r->trb + r->num_pending_sgs + 1;
1372                                         trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1373                                         dwc3_ep_inc_deq(dep);
1374                                 }
1375                         } else {
1376                                 struct dwc3_trb *trb = r->trb;
1377
1378                                 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1379                                 dwc3_ep_inc_deq(dep);
1380
1381                                 if (r->unaligned || r->zero) {
1382                                         trb = r->trb + 1;
1383                                         trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1384                                         dwc3_ep_inc_deq(dep);
1385                                 }
1386                         }
1387                         goto out1;
1388                 }
1389                 dev_err(dwc->dev, "request %p was not queued to %s\n",
1390                                 request, ep->name);
1391                 ret = -EINVAL;
1392                 goto out0;
1393         }
1394
1395 out1:
1396         /* giveback the request */
1397         dep->queued_requests--;
1398         dwc3_gadget_giveback(dep, req, -ECONNRESET);
1399
1400 out0:
1401         spin_unlock_irqrestore(&dwc->lock, flags);
1402
1403         return ret;
1404 }
1405
1406 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1407 {
1408         struct dwc3_gadget_ep_cmd_params        params;
1409         struct dwc3                             *dwc = dep->dwc;
1410         int                                     ret;
1411
1412         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1413                 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1414                 return -EINVAL;
1415         }
1416
1417         memset(&params, 0x00, sizeof(params));
1418
1419         if (value) {
1420                 struct dwc3_trb *trb;
1421
1422                 unsigned transfer_in_flight;
1423                 unsigned started;
1424
1425                 if (dep->flags & DWC3_EP_STALL)
1426                         return 0;
1427
1428                 if (dep->number > 1)
1429                         trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
1430                 else
1431                         trb = &dwc->ep0_trb[dep->trb_enqueue];
1432
1433                 transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO;
1434                 started = !list_empty(&dep->started_list);
1435
1436                 if (!protocol && ((dep->direction && transfer_in_flight) ||
1437                                 (!dep->direction && started))) {
1438                         return -EAGAIN;
1439                 }
1440
1441                 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
1442                                 &params);
1443                 if (ret)
1444                         dev_err(dwc->dev, "failed to set STALL on %s\n",
1445                                         dep->name);
1446                 else
1447                         dep->flags |= DWC3_EP_STALL;
1448         } else {
1449                 if (!(dep->flags & DWC3_EP_STALL))
1450                         return 0;
1451
1452                 ret = dwc3_send_clear_stall_ep_cmd(dep);
1453                 if (ret)
1454                         dev_err(dwc->dev, "failed to clear STALL on %s\n",
1455                                         dep->name);
1456                 else
1457                         dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1458         }
1459
1460         return ret;
1461 }
1462
1463 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1464 {
1465         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1466         struct dwc3                     *dwc = dep->dwc;
1467
1468         unsigned long                   flags;
1469
1470         int                             ret;
1471
1472         spin_lock_irqsave(&dwc->lock, flags);
1473         ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1474         spin_unlock_irqrestore(&dwc->lock, flags);
1475
1476         return ret;
1477 }
1478
1479 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1480 {
1481         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1482         struct dwc3                     *dwc = dep->dwc;
1483         unsigned long                   flags;
1484         int                             ret;
1485
1486         spin_lock_irqsave(&dwc->lock, flags);
1487         dep->flags |= DWC3_EP_WEDGE;
1488
1489         if (dep->number == 0 || dep->number == 1)
1490                 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1491         else
1492                 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1493         spin_unlock_irqrestore(&dwc->lock, flags);
1494
1495         return ret;
1496 }
1497
1498 /* -------------------------------------------------------------------------- */
1499
1500 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1501         .bLength        = USB_DT_ENDPOINT_SIZE,
1502         .bDescriptorType = USB_DT_ENDPOINT,
1503         .bmAttributes   = USB_ENDPOINT_XFER_CONTROL,
1504 };
1505
1506 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1507         .enable         = dwc3_gadget_ep0_enable,
1508         .disable        = dwc3_gadget_ep0_disable,
1509         .alloc_request  = dwc3_gadget_ep_alloc_request,
1510         .free_request   = dwc3_gadget_ep_free_request,
1511         .queue          = dwc3_gadget_ep0_queue,
1512         .dequeue        = dwc3_gadget_ep_dequeue,
1513         .set_halt       = dwc3_gadget_ep0_set_halt,
1514         .set_wedge      = dwc3_gadget_ep_set_wedge,
1515 };
1516
1517 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1518         .enable         = dwc3_gadget_ep_enable,
1519         .disable        = dwc3_gadget_ep_disable,
1520         .alloc_request  = dwc3_gadget_ep_alloc_request,
1521         .free_request   = dwc3_gadget_ep_free_request,
1522         .queue          = dwc3_gadget_ep_queue,
1523         .dequeue        = dwc3_gadget_ep_dequeue,
1524         .set_halt       = dwc3_gadget_ep_set_halt,
1525         .set_wedge      = dwc3_gadget_ep_set_wedge,
1526 };
1527
1528 /* -------------------------------------------------------------------------- */
1529
1530 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1531 {
1532         struct dwc3             *dwc = gadget_to_dwc(g);
1533
1534         return __dwc3_gadget_get_frame(dwc);
1535 }
1536
1537 static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
1538 {
1539         int                     retries;
1540
1541         int                     ret;
1542         u32                     reg;
1543
1544         u8                      link_state;
1545         u8                      speed;
1546
1547         /*
1548          * According to the Databook Remote wakeup request should
1549          * be issued only when the device is in early suspend state.
1550          *
1551          * We can check that via USB Link State bits in DSTS register.
1552          */
1553         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1554
1555         speed = reg & DWC3_DSTS_CONNECTSPD;
1556         if ((speed == DWC3_DSTS_SUPERSPEED) ||
1557             (speed == DWC3_DSTS_SUPERSPEED_PLUS))
1558                 return 0;
1559
1560         link_state = DWC3_DSTS_USBLNKST(reg);
1561
1562         switch (link_state) {
1563         case DWC3_LINK_STATE_RX_DET:    /* in HS, means Early Suspend */
1564         case DWC3_LINK_STATE_U3:        /* in HS, means SUSPEND */
1565                 break;
1566         default:
1567                 return -EINVAL;
1568         }
1569
1570         ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1571         if (ret < 0) {
1572                 dev_err(dwc->dev, "failed to put link in Recovery\n");
1573                 return ret;
1574         }
1575
1576         /* Recent versions do this automatically */
1577         if (dwc->revision < DWC3_REVISION_194A) {
1578                 /* write zeroes to Link Change Request */
1579                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1580                 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1581                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1582         }
1583
1584         /* poll until Link State changes to ON */
1585         retries = 20000;
1586
1587         while (retries--) {
1588                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1589
1590                 /* in HS, means ON */
1591                 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1592                         break;
1593         }
1594
1595         if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1596                 dev_err(dwc->dev, "failed to send remote wakeup\n");
1597                 return -EINVAL;
1598         }
1599
1600         return 0;
1601 }
1602
1603 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1604 {
1605         struct dwc3             *dwc = gadget_to_dwc(g);
1606         unsigned long           flags;
1607         int                     ret;
1608
1609         spin_lock_irqsave(&dwc->lock, flags);
1610         ret = __dwc3_gadget_wakeup(dwc);
1611         spin_unlock_irqrestore(&dwc->lock, flags);
1612
1613         return ret;
1614 }
1615
1616 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1617                 int is_selfpowered)
1618 {
1619         struct dwc3             *dwc = gadget_to_dwc(g);
1620         unsigned long           flags;
1621
1622         spin_lock_irqsave(&dwc->lock, flags);
1623         g->is_selfpowered = !!is_selfpowered;
1624         spin_unlock_irqrestore(&dwc->lock, flags);
1625
1626         return 0;
1627 }
1628
1629 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1630 {
1631         u32                     reg;
1632         u32                     timeout = 500;
1633
1634         if (pm_runtime_suspended(dwc->dev))
1635                 return 0;
1636
1637         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1638         if (is_on) {
1639                 if (dwc->revision <= DWC3_REVISION_187A) {
1640                         reg &= ~DWC3_DCTL_TRGTULST_MASK;
1641                         reg |= DWC3_DCTL_TRGTULST_RX_DET;
1642                 }
1643
1644                 if (dwc->revision >= DWC3_REVISION_194A)
1645                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1646                 reg |= DWC3_DCTL_RUN_STOP;
1647
1648                 if (dwc->has_hibernation)
1649                         reg |= DWC3_DCTL_KEEP_CONNECT;
1650
1651                 dwc->pullups_connected = true;
1652         } else {
1653                 reg &= ~DWC3_DCTL_RUN_STOP;
1654
1655                 if (dwc->has_hibernation && !suspend)
1656                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1657
1658                 dwc->pullups_connected = false;
1659         }
1660
1661         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1662
1663         do {
1664                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1665                 reg &= DWC3_DSTS_DEVCTRLHLT;
1666         } while (--timeout && !(!is_on ^ !reg));
1667
1668         if (!timeout)
1669                 return -ETIMEDOUT;
1670
1671         return 0;
1672 }
1673
1674 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1675 {
1676         struct dwc3             *dwc = gadget_to_dwc(g);
1677         unsigned long           flags;
1678         int                     ret;
1679
1680         is_on = !!is_on;
1681
1682         /*
1683          * Per databook, when we want to stop the gadget, if a control transfer
1684          * is still in process, complete it and get the core into setup phase.
1685          */
1686         if (!is_on && dwc->ep0state != EP0_SETUP_PHASE) {
1687                 reinit_completion(&dwc->ep0_in_setup);
1688
1689                 ret = wait_for_completion_timeout(&dwc->ep0_in_setup,
1690                                 msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT));
1691                 if (ret == 0) {
1692                         dev_err(dwc->dev, "timed out waiting for SETUP phase\n");
1693                         return -ETIMEDOUT;
1694                 }
1695         }
1696
1697         spin_lock_irqsave(&dwc->lock, flags);
1698         ret = dwc3_gadget_run_stop(dwc, is_on, false);
1699         spin_unlock_irqrestore(&dwc->lock, flags);
1700
1701         return ret;
1702 }
1703
1704 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1705 {
1706         u32                     reg;
1707
1708         /* Enable all but Start and End of Frame IRQs */
1709         reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1710                         DWC3_DEVTEN_EVNTOVERFLOWEN |
1711                         DWC3_DEVTEN_CMDCMPLTEN |
1712                         DWC3_DEVTEN_ERRTICERREN |
1713                         DWC3_DEVTEN_WKUPEVTEN |
1714                         DWC3_DEVTEN_CONNECTDONEEN |
1715                         DWC3_DEVTEN_USBRSTEN |
1716                         DWC3_DEVTEN_DISCONNEVTEN);
1717
1718         if (dwc->revision < DWC3_REVISION_250A)
1719                 reg |= DWC3_DEVTEN_ULSTCNGEN;
1720
1721         dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1722 }
1723
1724 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1725 {
1726         /* mask all interrupts */
1727         dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1728 }
1729
1730 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1731 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1732
1733 /**
1734  * dwc3_gadget_setup_nump - Calculate and initialize NUMP field of DCFG
1735  * dwc: pointer to our context structure
1736  *
1737  * The following looks like complex but it's actually very simple. In order to
1738  * calculate the number of packets we can burst at once on OUT transfers, we're
1739  * gonna use RxFIFO size.
1740  *
1741  * To calculate RxFIFO size we need two numbers:
1742  * MDWIDTH = size, in bits, of the internal memory bus
1743  * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
1744  *
1745  * Given these two numbers, the formula is simple:
1746  *
1747  * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
1748  *
1749  * 24 bytes is for 3x SETUP packets
1750  * 16 bytes is a clock domain crossing tolerance
1751  *
1752  * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
1753  */
1754 static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
1755 {
1756         u32 ram2_depth;
1757         u32 mdwidth;
1758         u32 nump;
1759         u32 reg;
1760
1761         ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
1762         mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0);
1763
1764         nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
1765         nump = min_t(u32, nump, 16);
1766
1767         /* update NumP */
1768         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1769         reg &= ~DWC3_DCFG_NUMP_MASK;
1770         reg |= nump << DWC3_DCFG_NUMP_SHIFT;
1771         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1772 }
1773
1774 static int __dwc3_gadget_start(struct dwc3 *dwc)
1775 {
1776         struct dwc3_ep          *dep;
1777         int                     ret = 0;
1778         u32                     reg;
1779
1780         /*
1781          * Use IMOD if enabled via dwc->imod_interval. Otherwise, if
1782          * the core supports IMOD, disable it.
1783          */
1784         if (dwc->imod_interval) {
1785                 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
1786                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
1787         } else if (dwc3_has_imod(dwc)) {
1788                 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), 0);
1789         }
1790
1791         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1792         reg &= ~(DWC3_DCFG_SPEED_MASK);
1793
1794         /**
1795          * WORKAROUND: DWC3 revision < 2.20a have an issue
1796          * which would cause metastability state on Run/Stop
1797          * bit if we try to force the IP to USB2-only mode.
1798          *
1799          * Because of that, we cannot configure the IP to any
1800          * speed other than the SuperSpeed
1801          *
1802          * Refers to:
1803          *
1804          * STAR#9000525659: Clock Domain Crossing on DCTL in
1805          * USB 2.0 Mode
1806          */
1807         if (dwc->revision < DWC3_REVISION_220A) {
1808                 reg |= DWC3_DCFG_SUPERSPEED;
1809         } else {
1810                 switch (dwc->maximum_speed) {
1811                 case USB_SPEED_LOW:
1812                         reg |= DWC3_DCFG_LOWSPEED;
1813                         break;
1814                 case USB_SPEED_FULL:
1815                         reg |= DWC3_DCFG_FULLSPEED;
1816                         break;
1817                 case USB_SPEED_HIGH:
1818                         reg |= DWC3_DCFG_HIGHSPEED;
1819                         break;
1820                 case USB_SPEED_SUPER_PLUS:
1821                         reg |= DWC3_DCFG_SUPERSPEED_PLUS;
1822                         break;
1823                 default:
1824                         dev_err(dwc->dev, "invalid dwc->maximum_speed (%d)\n",
1825                                 dwc->maximum_speed);
1826                         /* fall through */
1827                 case USB_SPEED_SUPER:
1828                         reg |= DWC3_DCFG_SUPERSPEED;
1829                         break;
1830                 }
1831         }
1832         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1833
1834         /*
1835          * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
1836          * field instead of letting dwc3 itself calculate that automatically.
1837          *
1838          * This way, we maximize the chances that we'll be able to get several
1839          * bursts of data without going through any sort of endpoint throttling.
1840          */
1841         reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1842         reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
1843         dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1844
1845         dwc3_gadget_setup_nump(dwc);
1846
1847         /* Start with SuperSpeed Default */
1848         dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1849
1850         dep = dwc->eps[0];
1851         ret = __dwc3_gadget_ep_enable(dep, false, false);
1852         if (ret) {
1853                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1854                 goto err0;
1855         }
1856
1857         dep = dwc->eps[1];
1858         ret = __dwc3_gadget_ep_enable(dep, false, false);
1859         if (ret) {
1860                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1861                 goto err1;
1862         }
1863
1864         /* begin to receive SETUP packets */
1865         dwc->ep0state = EP0_SETUP_PHASE;
1866         dwc3_ep0_out_start(dwc);
1867
1868         dwc3_gadget_enable_irq(dwc);
1869
1870         return 0;
1871
1872 err1:
1873         __dwc3_gadget_ep_disable(dwc->eps[0]);
1874
1875 err0:
1876         return ret;
1877 }
1878
1879 static int dwc3_gadget_start(struct usb_gadget *g,
1880                 struct usb_gadget_driver *driver)
1881 {
1882         struct dwc3             *dwc = gadget_to_dwc(g);
1883         unsigned long           flags;
1884         int                     ret = 0;
1885         int                     irq;
1886
1887         irq = dwc->irq_gadget;
1888         ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1889                         IRQF_SHARED, "dwc3", dwc->ev_buf);
1890         if (ret) {
1891                 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1892                                 irq, ret);
1893                 goto err0;
1894         }
1895
1896         spin_lock_irqsave(&dwc->lock, flags);
1897         if (dwc->gadget_driver) {
1898                 dev_err(dwc->dev, "%s is already bound to %s\n",
1899                                 dwc->gadget.name,
1900                                 dwc->gadget_driver->driver.name);
1901                 ret = -EBUSY;
1902                 goto err1;
1903         }
1904
1905         dwc->gadget_driver      = driver;
1906
1907         if (pm_runtime_active(dwc->dev))
1908                 __dwc3_gadget_start(dwc);
1909
1910         spin_unlock_irqrestore(&dwc->lock, flags);
1911
1912         return 0;
1913
1914 err1:
1915         spin_unlock_irqrestore(&dwc->lock, flags);
1916         free_irq(irq, dwc);
1917
1918 err0:
1919         return ret;
1920 }
1921
1922 static void __dwc3_gadget_stop(struct dwc3 *dwc)
1923 {
1924         dwc3_gadget_disable_irq(dwc);
1925         __dwc3_gadget_ep_disable(dwc->eps[0]);
1926         __dwc3_gadget_ep_disable(dwc->eps[1]);
1927 }
1928
1929 static int dwc3_gadget_stop(struct usb_gadget *g)
1930 {
1931         struct dwc3             *dwc = gadget_to_dwc(g);
1932         unsigned long           flags;
1933         int                     epnum;
1934
1935         spin_lock_irqsave(&dwc->lock, flags);
1936
1937         if (pm_runtime_suspended(dwc->dev))
1938                 goto out;
1939
1940         __dwc3_gadget_stop(dwc);
1941
1942         for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1943                 struct dwc3_ep  *dep = dwc->eps[epnum];
1944
1945                 if (!dep)
1946                         continue;
1947
1948                 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
1949                         continue;
1950
1951                 wait_event_lock_irq(dep->wait_end_transfer,
1952                                     !(dep->flags & DWC3_EP_END_TRANSFER_PENDING),
1953                                     dwc->lock);
1954         }
1955
1956 out:
1957         dwc->gadget_driver      = NULL;
1958         spin_unlock_irqrestore(&dwc->lock, flags);
1959
1960         free_irq(dwc->irq_gadget, dwc->ev_buf);
1961
1962         return 0;
1963 }
1964
1965 static const struct usb_gadget_ops dwc3_gadget_ops = {
1966         .get_frame              = dwc3_gadget_get_frame,
1967         .wakeup                 = dwc3_gadget_wakeup,
1968         .set_selfpowered        = dwc3_gadget_set_selfpowered,
1969         .pullup                 = dwc3_gadget_pullup,
1970         .udc_start              = dwc3_gadget_start,
1971         .udc_stop               = dwc3_gadget_stop,
1972 };
1973
1974 /* -------------------------------------------------------------------------- */
1975
1976 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc, u8 num)
1977 {
1978         struct dwc3_ep                  *dep;
1979         u8                              epnum;
1980
1981         INIT_LIST_HEAD(&dwc->gadget.ep_list);
1982
1983         for (epnum = 0; epnum < num; epnum++) {
1984                 bool                    direction = epnum & 1;
1985
1986                 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1987                 if (!dep)
1988                         return -ENOMEM;
1989
1990                 dep->dwc = dwc;
1991                 dep->number = epnum;
1992                 dep->direction = direction;
1993                 dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
1994                 dwc->eps[epnum] = dep;
1995
1996                 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1997                                 direction ? "in" : "out");
1998
1999                 dep->endpoint.name = dep->name;
2000
2001                 if (!(dep->number > 1)) {
2002                         dep->endpoint.desc = &dwc3_gadget_ep0_desc;
2003                         dep->endpoint.comp_desc = NULL;
2004                 }
2005
2006                 spin_lock_init(&dep->lock);
2007
2008                 if (epnum == 0 || epnum == 1) {
2009                         usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
2010                         dep->endpoint.maxburst = 1;
2011                         dep->endpoint.ops = &dwc3_gadget_ep0_ops;
2012                         if (!epnum)
2013                                 dwc->gadget.ep0 = &dep->endpoint;
2014                 } else if (direction) {
2015                         int mdwidth;
2016                         int size;
2017                         int ret;
2018                         int num;
2019
2020                         mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
2021                         /* MDWIDTH is represented in bits, we need it in bytes */
2022                         mdwidth /= 8;
2023
2024                         size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(epnum >> 1));
2025                         size = DWC3_GTXFIFOSIZ_TXFDEF(size);
2026
2027                         /* FIFO Depth is in MDWDITH bytes. Multiply */
2028                         size *= mdwidth;
2029
2030                         num = size / 1024;
2031                         if (num == 0)
2032                                 num = 1;
2033
2034                         /*
2035                          * FIFO sizes account an extra MDWIDTH * (num + 1) bytes for
2036                          * internal overhead. We don't really know how these are used,
2037                          * but documentation say it exists.
2038                          */
2039                         size -= mdwidth * (num + 1);
2040                         size /= num;
2041
2042                         usb_ep_set_maxpacket_limit(&dep->endpoint, size);
2043
2044                         dep->endpoint.max_streams = 15;
2045                         dep->endpoint.ops = &dwc3_gadget_ep_ops;
2046                         list_add_tail(&dep->endpoint.ep_list,
2047                                         &dwc->gadget.ep_list);
2048
2049                         ret = dwc3_alloc_trb_pool(dep);
2050                         if (ret)
2051                                 return ret;
2052                 } else {
2053                         int             ret;
2054
2055                         usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
2056                         dep->endpoint.max_streams = 15;
2057                         dep->endpoint.ops = &dwc3_gadget_ep_ops;
2058                         list_add_tail(&dep->endpoint.ep_list,
2059                                         &dwc->gadget.ep_list);
2060
2061                         ret = dwc3_alloc_trb_pool(dep);
2062                         if (ret)
2063                                 return ret;
2064                 }
2065
2066                 if (epnum == 0 || epnum == 1) {
2067                         dep->endpoint.caps.type_control = true;
2068                 } else {
2069                         dep->endpoint.caps.type_iso = true;
2070                         dep->endpoint.caps.type_bulk = true;
2071                         dep->endpoint.caps.type_int = true;
2072                 }
2073
2074                 dep->endpoint.caps.dir_in = direction;
2075                 dep->endpoint.caps.dir_out = !direction;
2076
2077                 INIT_LIST_HEAD(&dep->pending_list);
2078                 INIT_LIST_HEAD(&dep->started_list);
2079         }
2080
2081         return 0;
2082 }
2083
2084 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
2085 {
2086         struct dwc3_ep                  *dep;
2087         u8                              epnum;
2088
2089         for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2090                 dep = dwc->eps[epnum];
2091                 if (!dep)
2092                         continue;
2093                 /*
2094                  * Physical endpoints 0 and 1 are special; they form the
2095                  * bi-directional USB endpoint 0.
2096                  *
2097                  * For those two physical endpoints, we don't allocate a TRB
2098                  * pool nor do we add them the endpoints list. Due to that, we
2099                  * shouldn't do these two operations otherwise we would end up
2100                  * with all sorts of bugs when removing dwc3.ko.
2101                  */
2102                 if (epnum != 0 && epnum != 1) {
2103                         dwc3_free_trb_pool(dep);
2104                         list_del(&dep->endpoint.ep_list);
2105                 }
2106
2107                 kfree(dep);
2108         }
2109 }
2110
2111 /* -------------------------------------------------------------------------- */
2112
2113 static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
2114                 struct dwc3_request *req, struct dwc3_trb *trb,
2115                 const struct dwc3_event_depevt *event, int status,
2116                 int chain)
2117 {
2118         unsigned int            count;
2119         unsigned int            s_pkt = 0;
2120         unsigned int            trb_status;
2121
2122         dwc3_ep_inc_deq(dep);
2123
2124         if (req->trb == trb)
2125                 dep->queued_requests--;
2126
2127         trace_dwc3_complete_trb(dep, trb);
2128
2129         /*
2130          * If we're in the middle of series of chained TRBs and we
2131          * receive a short transfer along the way, DWC3 will skip
2132          * through all TRBs including the last TRB in the chain (the
2133          * where CHN bit is zero. DWC3 will also avoid clearing HWO
2134          * bit and SW has to do it manually.
2135          *
2136          * We're going to do that here to avoid problems of HW trying
2137          * to use bogus TRBs for transfers.
2138          */
2139         if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO))
2140                 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2141
2142         /*
2143          * If we're dealing with unaligned size OUT transfer, we will be left
2144          * with one TRB pending in the ring. We need to manually clear HWO bit
2145          * from that TRB.
2146          */
2147         if ((req->zero || req->unaligned) && (trb->ctrl & DWC3_TRB_CTRL_HWO)) {
2148                 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2149                 return 1;
2150         }
2151
2152         count = trb->size & DWC3_TRB_SIZE_MASK;
2153         req->remaining += count;
2154
2155         if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
2156                 return 1;
2157
2158         if (dep->direction) {
2159                 if (count) {
2160                         trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
2161                         if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
2162                                 /*
2163                                  * If missed isoc occurred and there is
2164                                  * no request queued then issue END
2165                                  * TRANSFER, so that core generates
2166                                  * next xfernotready and we will issue
2167                                  * a fresh START TRANSFER.
2168                                  * If there are still queued request
2169                                  * then wait, do not issue either END
2170                                  * or UPDATE TRANSFER, just attach next
2171                                  * request in pending_list during
2172                                  * giveback.If any future queued request
2173                                  * is successfully transferred then we
2174                                  * will issue UPDATE TRANSFER for all
2175                                  * request in the pending_list.
2176                                  */
2177                                 dep->flags |= DWC3_EP_MISSED_ISOC;
2178                         } else {
2179                                 dev_err(dwc->dev, "incomplete IN transfer %s\n",
2180                                                 dep->name);
2181                                 status = -ECONNRESET;
2182                         }
2183                 } else {
2184                         dep->flags &= ~DWC3_EP_MISSED_ISOC;
2185                 }
2186         } else {
2187                 if (count && (event->status & DEPEVT_STATUS_SHORT))
2188                         s_pkt = 1;
2189         }
2190
2191         if (s_pkt && !chain)
2192                 return 1;
2193
2194         if ((event->status & DEPEVT_STATUS_IOC) &&
2195                         (trb->ctrl & DWC3_TRB_CTRL_IOC))
2196                 return 1;
2197
2198         return 0;
2199 }
2200
2201 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
2202                 const struct dwc3_event_depevt *event, int status)
2203 {
2204         struct dwc3_request     *req, *n;
2205         struct dwc3_trb         *trb;
2206         bool                    ioc = false;
2207         int                     ret = 0;
2208
2209         list_for_each_entry_safe(req, n, &dep->started_list, list) {
2210                 unsigned length;
2211                 int chain;
2212
2213                 length = req->request.length;
2214                 chain = req->num_pending_sgs > 0;
2215                 if (chain) {
2216                         struct scatterlist *sg = req->sg;
2217                         struct scatterlist *s;
2218                         unsigned int pending = req->num_pending_sgs;
2219                         unsigned int i;
2220
2221                         for_each_sg(sg, s, pending, i) {
2222                                 trb = &dep->trb_pool[dep->trb_dequeue];
2223
2224                                 if (trb->ctrl & DWC3_TRB_CTRL_HWO)
2225                                         break;
2226
2227                                 req->sg = sg_next(s);
2228                                 req->num_pending_sgs--;
2229
2230                                 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2231                                                 event, status, chain);
2232                                 if (ret)
2233                                         break;
2234                         }
2235                 } else {
2236                         trb = &dep->trb_pool[dep->trb_dequeue];
2237                         ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2238                                         event, status, chain);
2239                 }
2240
2241                 if (req->unaligned || req->zero) {
2242                         trb = &dep->trb_pool[dep->trb_dequeue];
2243                         ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2244                                         event, status, false);
2245                         req->unaligned = false;
2246                         req->zero = false;
2247                 }
2248
2249                 req->request.actual = length - req->remaining;
2250
2251                 if ((req->request.actual < length) && req->num_pending_sgs)
2252                         return __dwc3_gadget_kick_transfer(dep, 0);
2253
2254                 dwc3_gadget_giveback(dep, req, status);
2255
2256                 if (ret) {
2257                         if ((event->status & DEPEVT_STATUS_IOC) &&
2258                             (trb->ctrl & DWC3_TRB_CTRL_IOC))
2259                                 ioc = true;
2260                         break;
2261                 }
2262         }
2263
2264         /*
2265          * Our endpoint might get disabled by another thread during
2266          * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2267          * early on so DWC3_EP_BUSY flag gets cleared
2268          */
2269         if (!dep->endpoint.desc)
2270                 return 1;
2271
2272         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
2273                         list_empty(&dep->started_list)) {
2274                 if (list_empty(&dep->pending_list)) {
2275                         /*
2276                          * If there is no entry in request list then do
2277                          * not issue END TRANSFER now. Just set PENDING
2278                          * flag, so that END TRANSFER is issued when an
2279                          * entry is added into request list.
2280                          */
2281                         dep->flags = DWC3_EP_PENDING_REQUEST;
2282                 } else {
2283                         dwc3_stop_active_transfer(dwc, dep->number, true);
2284                         dep->flags = DWC3_EP_ENABLED;
2285                 }
2286                 return 1;
2287         }
2288
2289         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && ioc)
2290                 return 0;
2291
2292         return 1;
2293 }
2294
2295 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
2296                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
2297 {
2298         unsigned                status = 0;
2299         int                     clean_busy;
2300         u32                     is_xfer_complete;
2301
2302         is_xfer_complete = (event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE);
2303
2304         if (event->status & DEPEVT_STATUS_BUSERR)
2305                 status = -ECONNRESET;
2306
2307         clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
2308         if (clean_busy && (!dep->endpoint.desc || is_xfer_complete ||
2309                                 usb_endpoint_xfer_isoc(dep->endpoint.desc)))
2310                 dep->flags &= ~DWC3_EP_BUSY;
2311
2312         /*
2313          * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2314          * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2315          */
2316         if (dwc->revision < DWC3_REVISION_183A) {
2317                 u32             reg;
2318                 int             i;
2319
2320                 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
2321                         dep = dwc->eps[i];
2322
2323                         if (!(dep->flags & DWC3_EP_ENABLED))
2324                                 continue;
2325
2326                         if (!list_empty(&dep->started_list))
2327                                 return;
2328                 }
2329
2330                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2331                 reg |= dwc->u1u2;
2332                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2333
2334                 dwc->u1u2 = 0;
2335         }
2336
2337         /*
2338          * Our endpoint might get disabled by another thread during
2339          * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2340          * early on so DWC3_EP_BUSY flag gets cleared
2341          */
2342         if (!dep->endpoint.desc)
2343                 return;
2344
2345         if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2346                 int ret;
2347
2348                 ret = __dwc3_gadget_kick_transfer(dep, 0);
2349                 if (!ret || ret == -EBUSY)
2350                         return;
2351         }
2352 }
2353
2354 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2355                 const struct dwc3_event_depevt *event)
2356 {
2357         struct dwc3_ep          *dep;
2358         u8                      epnum = event->endpoint_number;
2359         u8                      cmd;
2360
2361         dep = dwc->eps[epnum];
2362
2363         if (!(dep->flags & DWC3_EP_ENABLED)) {
2364                 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
2365                         return;
2366
2367                 /* Handle only EPCMDCMPLT when EP disabled */
2368                 if (event->endpoint_event != DWC3_DEPEVT_EPCMDCMPLT)
2369                         return;
2370         }
2371
2372         if (epnum == 0 || epnum == 1) {
2373                 dwc3_ep0_interrupt(dwc, event);
2374                 return;
2375         }
2376
2377         switch (event->endpoint_event) {
2378         case DWC3_DEPEVT_XFERCOMPLETE:
2379                 dep->resource_index = 0;
2380
2381                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2382                         dev_err(dwc->dev, "XferComplete for Isochronous endpoint\n");
2383                         return;
2384                 }
2385
2386                 dwc3_endpoint_transfer_complete(dwc, dep, event);
2387                 break;
2388         case DWC3_DEPEVT_XFERINPROGRESS:
2389                 dwc3_endpoint_transfer_complete(dwc, dep, event);
2390                 break;
2391         case DWC3_DEPEVT_XFERNOTREADY:
2392                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2393                         dwc3_gadget_start_isoc(dwc, dep, event);
2394                 } else {
2395                         int ret;
2396
2397                         ret = __dwc3_gadget_kick_transfer(dep, 0);
2398                         if (!ret || ret == -EBUSY)
2399                                 return;
2400                 }
2401
2402                 break;
2403         case DWC3_DEPEVT_STREAMEVT:
2404                 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
2405                         dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
2406                                         dep->name);
2407                         return;
2408                 }
2409                 break;
2410         case DWC3_DEPEVT_EPCMDCMPLT:
2411                 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
2412
2413                 if (cmd == DWC3_DEPCMD_ENDTRANSFER) {
2414                         dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
2415                         wake_up(&dep->wait_end_transfer);
2416                 }
2417                 break;
2418         case DWC3_DEPEVT_RXTXFIFOEVT:
2419                 break;
2420         }
2421 }
2422
2423 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2424 {
2425         if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2426                 spin_unlock(&dwc->lock);
2427                 dwc->gadget_driver->disconnect(&dwc->gadget);
2428                 spin_lock(&dwc->lock);
2429         }
2430 }
2431
2432 static void dwc3_suspend_gadget(struct dwc3 *dwc)
2433 {
2434         if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
2435                 spin_unlock(&dwc->lock);
2436                 dwc->gadget_driver->suspend(&dwc->gadget);
2437                 spin_lock(&dwc->lock);
2438         }
2439 }
2440
2441 static void dwc3_resume_gadget(struct dwc3 *dwc)
2442 {
2443         if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2444                 spin_unlock(&dwc->lock);
2445                 dwc->gadget_driver->resume(&dwc->gadget);
2446                 spin_lock(&dwc->lock);
2447         }
2448 }
2449
2450 static void dwc3_reset_gadget(struct dwc3 *dwc)
2451 {
2452         if (!dwc->gadget_driver)
2453                 return;
2454
2455         if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2456                 spin_unlock(&dwc->lock);
2457                 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
2458                 spin_lock(&dwc->lock);
2459         }
2460 }
2461
2462 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
2463 {
2464         struct dwc3_ep *dep;
2465         struct dwc3_gadget_ep_cmd_params params;
2466         u32 cmd;
2467         int ret;
2468
2469         dep = dwc->eps[epnum];
2470
2471         if ((dep->flags & DWC3_EP_END_TRANSFER_PENDING) ||
2472             !dep->resource_index)
2473                 return;
2474
2475         /*
2476          * NOTICE: We are violating what the Databook says about the
2477          * EndTransfer command. Ideally we would _always_ wait for the
2478          * EndTransfer Command Completion IRQ, but that's causing too
2479          * much trouble synchronizing between us and gadget driver.
2480          *
2481          * We have discussed this with the IP Provider and it was
2482          * suggested to giveback all requests here, but give HW some
2483          * extra time to synchronize with the interconnect. We're using
2484          * an arbitrary 100us delay for that.
2485          *
2486          * Note also that a similar handling was tested by Synopsys
2487          * (thanks a lot Paul) and nothing bad has come out of it.
2488          * In short, what we're doing is:
2489          *
2490          * - Issue EndTransfer WITH CMDIOC bit set
2491          * - Wait 100us
2492          *
2493          * As of IP version 3.10a of the DWC_usb3 IP, the controller
2494          * supports a mode to work around the above limitation. The
2495          * software can poll the CMDACT bit in the DEPCMD register
2496          * after issuing a EndTransfer command. This mode is enabled
2497          * by writing GUCTL2[14]. This polling is already done in the
2498          * dwc3_send_gadget_ep_cmd() function so if the mode is
2499          * enabled, the EndTransfer command will have completed upon
2500          * returning from this function and we don't need to delay for
2501          * 100us.
2502          *
2503          * This mode is NOT available on the DWC_usb31 IP.
2504          */
2505
2506         cmd = DWC3_DEPCMD_ENDTRANSFER;
2507         cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2508         cmd |= DWC3_DEPCMD_CMDIOC;
2509         cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2510         memset(&params, 0, sizeof(params));
2511         ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
2512         WARN_ON_ONCE(ret);
2513         dep->resource_index = 0;
2514         dep->flags &= ~DWC3_EP_BUSY;
2515
2516         if (dwc3_is_usb31(dwc) || dwc->revision < DWC3_REVISION_310A) {
2517                 dep->flags |= DWC3_EP_END_TRANSFER_PENDING;
2518                 udelay(100);
2519         }
2520 }
2521
2522 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2523 {
2524         u32 epnum;
2525
2526         for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2527                 struct dwc3_ep *dep;
2528                 int ret;
2529
2530                 dep = dwc->eps[epnum];
2531                 if (!dep)
2532                         continue;
2533
2534                 if (!(dep->flags & DWC3_EP_STALL))
2535                         continue;
2536
2537                 dep->flags &= ~DWC3_EP_STALL;
2538
2539                 ret = dwc3_send_clear_stall_ep_cmd(dep);
2540                 WARN_ON_ONCE(ret);
2541         }
2542 }
2543
2544 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2545 {
2546         int                     reg;
2547
2548         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2549         reg &= ~DWC3_DCTL_INITU1ENA;
2550         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2551
2552         reg &= ~DWC3_DCTL_INITU2ENA;
2553         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2554
2555         dwc3_disconnect_gadget(dwc);
2556
2557         dwc->gadget.speed = USB_SPEED_UNKNOWN;
2558         dwc->setup_packet_pending = false;
2559         usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2560
2561         dwc->connected = false;
2562 }
2563
2564 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2565 {
2566         u32                     reg;
2567
2568         dwc->connected = true;
2569
2570         /*
2571          * WORKAROUND: DWC3 revisions <1.88a have an issue which
2572          * would cause a missing Disconnect Event if there's a
2573          * pending Setup Packet in the FIFO.
2574          *
2575          * There's no suggested workaround on the official Bug
2576          * report, which states that "unless the driver/application
2577          * is doing any special handling of a disconnect event,
2578          * there is no functional issue".
2579          *
2580          * Unfortunately, it turns out that we _do_ some special
2581          * handling of a disconnect event, namely complete all
2582          * pending transfers, notify gadget driver of the
2583          * disconnection, and so on.
2584          *
2585          * Our suggested workaround is to follow the Disconnect
2586          * Event steps here, instead, based on a setup_packet_pending
2587          * flag. Such flag gets set whenever we have a SETUP_PENDING
2588          * status for EP0 TRBs and gets cleared on XferComplete for the
2589          * same endpoint.
2590          *
2591          * Refers to:
2592          *
2593          * STAR#9000466709: RTL: Device : Disconnect event not
2594          * generated if setup packet pending in FIFO
2595          */
2596         if (dwc->revision < DWC3_REVISION_188A) {
2597                 if (dwc->setup_packet_pending)
2598                         dwc3_gadget_disconnect_interrupt(dwc);
2599         }
2600
2601         dwc3_reset_gadget(dwc);
2602
2603         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2604         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2605         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2606         dwc->test_mode = false;
2607         dwc3_clear_stall_all_ep(dwc);
2608
2609         /* Reset device address to zero */
2610         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2611         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2612         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2613 }
2614
2615 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2616 {
2617         struct dwc3_ep          *dep;
2618         int                     ret;
2619         u32                     reg;
2620         u8                      speed;
2621
2622         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2623         speed = reg & DWC3_DSTS_CONNECTSPD;
2624         dwc->speed = speed;
2625
2626         /*
2627          * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2628          * each time on Connect Done.
2629          *
2630          * Currently we always use the reset value. If any platform
2631          * wants to set this to a different value, we need to add a
2632          * setting and update GCTL.RAMCLKSEL here.
2633          */
2634
2635         switch (speed) {
2636         case DWC3_DSTS_SUPERSPEED_PLUS:
2637                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2638                 dwc->gadget.ep0->maxpacket = 512;
2639                 dwc->gadget.speed = USB_SPEED_SUPER_PLUS;
2640                 break;
2641         case DWC3_DSTS_SUPERSPEED:
2642                 /*
2643                  * WORKAROUND: DWC3 revisions <1.90a have an issue which
2644                  * would cause a missing USB3 Reset event.
2645                  *
2646                  * In such situations, we should force a USB3 Reset
2647                  * event by calling our dwc3_gadget_reset_interrupt()
2648                  * routine.
2649                  *
2650                  * Refers to:
2651                  *
2652                  * STAR#9000483510: RTL: SS : USB3 reset event may
2653                  * not be generated always when the link enters poll
2654                  */
2655                 if (dwc->revision < DWC3_REVISION_190A)
2656                         dwc3_gadget_reset_interrupt(dwc);
2657
2658                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2659                 dwc->gadget.ep0->maxpacket = 512;
2660                 dwc->gadget.speed = USB_SPEED_SUPER;
2661                 break;
2662         case DWC3_DSTS_HIGHSPEED:
2663                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2664                 dwc->gadget.ep0->maxpacket = 64;
2665                 dwc->gadget.speed = USB_SPEED_HIGH;
2666                 break;
2667         case DWC3_DSTS_FULLSPEED:
2668                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2669                 dwc->gadget.ep0->maxpacket = 64;
2670                 dwc->gadget.speed = USB_SPEED_FULL;
2671                 break;
2672         case DWC3_DSTS_LOWSPEED:
2673                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2674                 dwc->gadget.ep0->maxpacket = 8;
2675                 dwc->gadget.speed = USB_SPEED_LOW;
2676                 break;
2677         }
2678
2679         /* Enable USB2 LPM Capability */
2680
2681         if ((dwc->revision > DWC3_REVISION_194A) &&
2682             (speed != DWC3_DSTS_SUPERSPEED) &&
2683             (speed != DWC3_DSTS_SUPERSPEED_PLUS)) {
2684                 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2685                 reg |= DWC3_DCFG_LPM_CAP;
2686                 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2687
2688                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2689                 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2690
2691                 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2692
2693                 /*
2694                  * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2695                  * DCFG.LPMCap is set, core responses with an ACK and the
2696                  * BESL value in the LPM token is less than or equal to LPM
2697                  * NYET threshold.
2698                  */
2699                 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2700                                 && dwc->has_lpm_erratum,
2701                                 "LPM Erratum not available on dwc3 revisions < 2.40a\n");
2702
2703                 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2704                         reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2705
2706                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2707         } else {
2708                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2709                 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2710                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2711         }
2712
2713         dep = dwc->eps[0];
2714         ret = __dwc3_gadget_ep_enable(dep, true, false);
2715         if (ret) {
2716                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2717                 return;
2718         }
2719
2720         dep = dwc->eps[1];
2721         ret = __dwc3_gadget_ep_enable(dep, true, false);
2722         if (ret) {
2723                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2724                 return;
2725         }
2726
2727         /*
2728          * Configure PHY via GUSB3PIPECTLn if required.
2729          *
2730          * Update GTXFIFOSIZn
2731          *
2732          * In both cases reset values should be sufficient.
2733          */
2734 }
2735
2736 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2737 {
2738         /*
2739          * TODO take core out of low power mode when that's
2740          * implemented.
2741          */
2742
2743         if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2744                 spin_unlock(&dwc->lock);
2745                 dwc->gadget_driver->resume(&dwc->gadget);
2746                 spin_lock(&dwc->lock);
2747         }
2748 }
2749
2750 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2751                 unsigned int evtinfo)
2752 {
2753         enum dwc3_link_state    next = evtinfo & DWC3_LINK_STATE_MASK;
2754         unsigned int            pwropt;
2755
2756         /*
2757          * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2758          * Hibernation mode enabled which would show up when device detects
2759          * host-initiated U3 exit.
2760          *
2761          * In that case, device will generate a Link State Change Interrupt
2762          * from U3 to RESUME which is only necessary if Hibernation is
2763          * configured in.
2764          *
2765          * There are no functional changes due to such spurious event and we
2766          * just need to ignore it.
2767          *
2768          * Refers to:
2769          *
2770          * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2771          * operational mode
2772          */
2773         pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2774         if ((dwc->revision < DWC3_REVISION_250A) &&
2775                         (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2776                 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2777                                 (next == DWC3_LINK_STATE_RESUME)) {
2778                         return;
2779                 }
2780         }
2781
2782         /*
2783          * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2784          * on the link partner, the USB session might do multiple entry/exit
2785          * of low power states before a transfer takes place.
2786          *
2787          * Due to this problem, we might experience lower throughput. The
2788          * suggested workaround is to disable DCTL[12:9] bits if we're
2789          * transitioning from U1/U2 to U0 and enable those bits again
2790          * after a transfer completes and there are no pending transfers
2791          * on any of the enabled endpoints.
2792          *
2793          * This is the first half of that workaround.
2794          *
2795          * Refers to:
2796          *
2797          * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2798          * core send LGO_Ux entering U0
2799          */
2800         if (dwc->revision < DWC3_REVISION_183A) {
2801                 if (next == DWC3_LINK_STATE_U0) {
2802                         u32     u1u2;
2803                         u32     reg;
2804
2805                         switch (dwc->link_state) {
2806                         case DWC3_LINK_STATE_U1:
2807                         case DWC3_LINK_STATE_U2:
2808                                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2809                                 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2810                                                 | DWC3_DCTL_ACCEPTU2ENA
2811                                                 | DWC3_DCTL_INITU1ENA
2812                                                 | DWC3_DCTL_ACCEPTU1ENA);
2813
2814                                 if (!dwc->u1u2)
2815                                         dwc->u1u2 = reg & u1u2;
2816
2817                                 reg &= ~u1u2;
2818
2819                                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2820                                 break;
2821                         default:
2822                                 /* do nothing */
2823                                 break;
2824                         }
2825                 }
2826         }
2827
2828         switch (next) {
2829         case DWC3_LINK_STATE_U1:
2830                 if (dwc->speed == USB_SPEED_SUPER)
2831                         dwc3_suspend_gadget(dwc);
2832                 break;
2833         case DWC3_LINK_STATE_U2:
2834         case DWC3_LINK_STATE_U3:
2835                 dwc3_suspend_gadget(dwc);
2836                 break;
2837         case DWC3_LINK_STATE_RESUME:
2838                 dwc3_resume_gadget(dwc);
2839                 break;
2840         default:
2841                 /* do nothing */
2842                 break;
2843         }
2844
2845         dwc->link_state = next;
2846 }
2847
2848 static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc,
2849                                           unsigned int evtinfo)
2850 {
2851         enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2852
2853         if (dwc->link_state != next && next == DWC3_LINK_STATE_U3)
2854                 dwc3_suspend_gadget(dwc);
2855
2856         dwc->link_state = next;
2857 }
2858
2859 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2860                 unsigned int evtinfo)
2861 {
2862         unsigned int is_ss = evtinfo & BIT(4);
2863
2864         /**
2865          * WORKAROUND: DWC3 revison 2.20a with hibernation support
2866          * have a known issue which can cause USB CV TD.9.23 to fail
2867          * randomly.
2868          *
2869          * Because of this issue, core could generate bogus hibernation
2870          * events which SW needs to ignore.
2871          *
2872          * Refers to:
2873          *
2874          * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2875          * Device Fallback from SuperSpeed
2876          */
2877         if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2878                 return;
2879
2880         /* enter hibernation here */
2881 }
2882
2883 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2884                 const struct dwc3_event_devt *event)
2885 {
2886         switch (event->type) {
2887         case DWC3_DEVICE_EVENT_DISCONNECT:
2888                 dwc3_gadget_disconnect_interrupt(dwc);
2889                 break;
2890         case DWC3_DEVICE_EVENT_RESET:
2891                 dwc3_gadget_reset_interrupt(dwc);
2892                 break;
2893         case DWC3_DEVICE_EVENT_CONNECT_DONE:
2894                 dwc3_gadget_conndone_interrupt(dwc);
2895                 break;
2896         case DWC3_DEVICE_EVENT_WAKEUP:
2897                 dwc3_gadget_wakeup_interrupt(dwc);
2898                 break;
2899         case DWC3_DEVICE_EVENT_HIBER_REQ:
2900                 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
2901                                         "unexpected hibernation event\n"))
2902                         break;
2903
2904                 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2905                 break;
2906         case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2907                 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2908                 break;
2909         case DWC3_DEVICE_EVENT_EOPF:
2910                 /* It changed to be suspend event for version 2.30a and above */
2911                 if (dwc->revision >= DWC3_REVISION_230A) {
2912                         /*
2913                          * Ignore suspend event until the gadget enters into
2914                          * USB_STATE_CONFIGURED state.
2915                          */
2916                         if (dwc->gadget.state >= USB_STATE_CONFIGURED)
2917                                 dwc3_gadget_suspend_interrupt(dwc,
2918                                                 event->event_info);
2919                 }
2920                 break;
2921         case DWC3_DEVICE_EVENT_SOF:
2922         case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2923         case DWC3_DEVICE_EVENT_CMD_CMPL:
2924         case DWC3_DEVICE_EVENT_OVERFLOW:
2925                 break;
2926         default:
2927                 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2928         }
2929 }
2930
2931 static void dwc3_process_event_entry(struct dwc3 *dwc,
2932                 const union dwc3_event *event)
2933 {
2934         trace_dwc3_event(event->raw, dwc);
2935
2936         /* Endpoint IRQ, handle it and return early */
2937         if (event->type.is_devspec == 0) {
2938                 /* depevt */
2939                 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2940         }
2941
2942         switch (event->type.type) {
2943         case DWC3_EVENT_TYPE_DEV:
2944                 dwc3_gadget_interrupt(dwc, &event->devt);
2945                 break;
2946         /* REVISIT what to do with Carkit and I2C events ? */
2947         default:
2948                 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2949         }
2950 }
2951
2952 static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
2953 {
2954         struct dwc3 *dwc = evt->dwc;
2955         irqreturn_t ret = IRQ_NONE;
2956         int left;
2957         u32 reg;
2958
2959         left = evt->count;
2960
2961         if (!(evt->flags & DWC3_EVENT_PENDING))
2962                 return IRQ_NONE;
2963
2964         while (left > 0) {
2965                 union dwc3_event event;
2966
2967                 event.raw = *(u32 *) (evt->cache + evt->lpos);
2968
2969                 dwc3_process_event_entry(dwc, &event);
2970
2971                 /*
2972                  * FIXME we wrap around correctly to the next entry as
2973                  * almost all entries are 4 bytes in size. There is one
2974                  * entry which has 12 bytes which is a regular entry
2975                  * followed by 8 bytes data. ATM I don't know how
2976                  * things are organized if we get next to the a
2977                  * boundary so I worry about that once we try to handle
2978                  * that.
2979                  */
2980                 evt->lpos = (evt->lpos + 4) % evt->length;
2981                 left -= 4;
2982         }
2983
2984         evt->count = 0;
2985         evt->flags &= ~DWC3_EVENT_PENDING;
2986         ret = IRQ_HANDLED;
2987
2988         /* Unmask interrupt */
2989         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
2990         reg &= ~DWC3_GEVNTSIZ_INTMASK;
2991         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
2992
2993         if (dwc->imod_interval) {
2994                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
2995                 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
2996         }
2997
2998         return ret;
2999 }
3000
3001 static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
3002 {
3003         struct dwc3_event_buffer *evt = _evt;
3004         struct dwc3 *dwc = evt->dwc;
3005         unsigned long flags;
3006         irqreturn_t ret = IRQ_NONE;
3007
3008         spin_lock_irqsave(&dwc->lock, flags);
3009         ret = dwc3_process_event_buf(evt);
3010         spin_unlock_irqrestore(&dwc->lock, flags);
3011
3012         return ret;
3013 }
3014
3015 static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
3016 {
3017         struct dwc3 *dwc = evt->dwc;
3018         u32 amount;
3019         u32 count;
3020         u32 reg;
3021
3022         if (pm_runtime_suspended(dwc->dev)) {
3023                 pm_runtime_get(dwc->dev);
3024                 disable_irq_nosync(dwc->irq_gadget);
3025                 dwc->pending_events = true;
3026                 return IRQ_HANDLED;
3027         }
3028
3029         count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
3030         count &= DWC3_GEVNTCOUNT_MASK;
3031         if (!count)
3032                 return IRQ_NONE;
3033
3034         evt->count = count;
3035         evt->flags |= DWC3_EVENT_PENDING;
3036
3037         /* Mask interrupt */
3038         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
3039         reg |= DWC3_GEVNTSIZ_INTMASK;
3040         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
3041
3042         amount = min(count, evt->length - evt->lpos);
3043         memcpy(evt->cache + evt->lpos, evt->buf + evt->lpos, amount);
3044
3045         if (amount < count)
3046                 memcpy(evt->cache, evt->buf, count - amount);
3047
3048         dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
3049
3050         return IRQ_WAKE_THREAD;
3051 }
3052
3053 static irqreturn_t dwc3_interrupt(int irq, void *_evt)
3054 {
3055         struct dwc3_event_buffer        *evt = _evt;
3056
3057         return dwc3_check_event_buf(evt);
3058 }
3059
3060 static int dwc3_gadget_get_irq(struct dwc3 *dwc)
3061 {
3062         struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
3063         int irq;
3064
3065         irq = platform_get_irq_byname(dwc3_pdev, "peripheral");
3066         if (irq > 0)
3067                 goto out;
3068
3069         if (irq == -EPROBE_DEFER)
3070                 goto out;
3071
3072         irq = platform_get_irq_byname(dwc3_pdev, "dwc_usb3");
3073         if (irq > 0)
3074                 goto out;
3075
3076         if (irq == -EPROBE_DEFER)
3077                 goto out;
3078
3079         irq = platform_get_irq(dwc3_pdev, 0);
3080         if (irq > 0)
3081                 goto out;
3082
3083         if (irq != -EPROBE_DEFER)
3084                 dev_err(dwc->dev, "missing peripheral IRQ\n");
3085
3086         if (!irq)
3087                 irq = -EINVAL;
3088
3089 out:
3090         return irq;
3091 }
3092
3093 /**
3094  * dwc3_gadget_init - Initializes gadget related registers
3095  * @dwc: pointer to our controller context structure
3096  *
3097  * Returns 0 on success otherwise negative errno.
3098  */
3099 int dwc3_gadget_init(struct dwc3 *dwc)
3100 {
3101         int ret;
3102         int irq;
3103
3104         irq = dwc3_gadget_get_irq(dwc);
3105         if (irq < 0) {
3106                 ret = irq;
3107                 goto err0;
3108         }
3109
3110         dwc->irq_gadget = irq;
3111
3112         dwc->ep0_trb = dma_alloc_coherent(dwc->sysdev,
3113                                           sizeof(*dwc->ep0_trb) * 2,
3114                                           &dwc->ep0_trb_addr, GFP_KERNEL);
3115         if (!dwc->ep0_trb) {
3116                 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
3117                 ret = -ENOMEM;
3118                 goto err0;
3119         }
3120
3121         dwc->setup_buf = kzalloc(DWC3_EP0_SETUP_SIZE, GFP_KERNEL);
3122         if (!dwc->setup_buf) {
3123                 ret = -ENOMEM;
3124                 goto err1;
3125         }
3126
3127         dwc->bounce = dma_alloc_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE,
3128                         &dwc->bounce_addr, GFP_KERNEL);
3129         if (!dwc->bounce) {
3130                 ret = -ENOMEM;
3131                 goto err2;
3132         }
3133
3134         init_completion(&dwc->ep0_in_setup);
3135
3136         dwc->gadget.ops                 = &dwc3_gadget_ops;
3137         dwc->gadget.speed               = USB_SPEED_UNKNOWN;
3138         dwc->gadget.sg_supported        = true;
3139         dwc->gadget.name                = "dwc3-gadget";
3140         dwc->gadget.is_otg              = dwc->dr_mode == USB_DR_MODE_OTG;
3141
3142         /*
3143          * FIXME We might be setting max_speed to <SUPER, however versions
3144          * <2.20a of dwc3 have an issue with metastability (documented
3145          * elsewhere in this driver) which tells us we can't set max speed to
3146          * anything lower than SUPER.
3147          *
3148          * Because gadget.max_speed is only used by composite.c and function
3149          * drivers (i.e. it won't go into dwc3's registers) we are allowing this
3150          * to happen so we avoid sending SuperSpeed Capability descriptor
3151          * together with our BOS descriptor as that could confuse host into
3152          * thinking we can handle super speed.
3153          *
3154          * Note that, in fact, we won't even support GetBOS requests when speed
3155          * is less than super speed because we don't have means, yet, to tell
3156          * composite.c that we are USB 2.0 + LPM ECN.
3157          */
3158         if (dwc->revision < DWC3_REVISION_220A)
3159                 dev_info(dwc->dev, "changing max_speed on rev %08x\n",
3160                                 dwc->revision);
3161
3162         dwc->gadget.max_speed           = dwc->maximum_speed;
3163
3164         /*
3165          * REVISIT: Here we should clear all pending IRQs to be
3166          * sure we're starting from a well known location.
3167          */
3168
3169         ret = dwc3_gadget_init_endpoints(dwc, dwc->num_eps);
3170         if (ret)
3171                 goto err3;
3172
3173         ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
3174         if (ret) {
3175                 dev_err(dwc->dev, "failed to register udc\n");
3176                 goto err4;
3177         }
3178
3179         return 0;
3180
3181 err4:
3182         dwc3_gadget_free_endpoints(dwc);
3183
3184 err3:
3185         dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
3186                         dwc->bounce_addr);
3187
3188 err2:
3189         kfree(dwc->setup_buf);
3190
3191 err1:
3192         dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
3193                         dwc->ep0_trb, dwc->ep0_trb_addr);
3194
3195 err0:
3196         return ret;
3197 }
3198
3199 /* -------------------------------------------------------------------------- */
3200
3201 void dwc3_gadget_exit(struct dwc3 *dwc)
3202 {
3203         usb_del_gadget_udc(&dwc->gadget);
3204         dwc3_gadget_free_endpoints(dwc);
3205         dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
3206                           dwc->bounce_addr);
3207         kfree(dwc->setup_buf);
3208         dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
3209                           dwc->ep0_trb, dwc->ep0_trb_addr);
3210 }
3211
3212 int dwc3_gadget_suspend(struct dwc3 *dwc)
3213 {
3214         if (!dwc->gadget_driver)
3215                 return 0;
3216
3217         dwc3_gadget_run_stop(dwc, false, false);
3218         dwc3_disconnect_gadget(dwc);
3219         __dwc3_gadget_stop(dwc);
3220
3221         return 0;
3222 }
3223
3224 int dwc3_gadget_resume(struct dwc3 *dwc)
3225 {
3226         int                     ret;
3227
3228         if (!dwc->gadget_driver)
3229                 return 0;
3230
3231         ret = __dwc3_gadget_start(dwc);
3232         if (ret < 0)
3233                 goto err0;
3234
3235         ret = dwc3_gadget_run_stop(dwc, true, false);
3236         if (ret < 0)
3237                 goto err1;
3238
3239         return 0;
3240
3241 err1:
3242         __dwc3_gadget_stop(dwc);
3243
3244 err0:
3245         return ret;
3246 }
3247
3248 void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
3249 {
3250         if (dwc->pending_events) {
3251                 dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf);
3252                 dwc->pending_events = false;
3253                 enable_irq(dwc->irq_gadget);
3254         }
3255 }