drivers/usb/dwc3/gadget.c

   1 /**
   2  * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * This program is free software: you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2  of
  11  * the License as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/delay.h>
  21 #include <linux/slab.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/pm_runtime.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/io.h>
  27 #include <linux/list.h>
  28 #include <linux/dma-mapping.h>
  29
  30 #include <linux/usb/ch9.h>
  31 #include <linux/usb/gadget.h>
  32
  33 #include "core.h"
  34 #include "gadget.h"
  35 #include "io.h"
  36
  37 /**
  38  * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
  39  * @dwc: pointer to our context structure
  40  * @mode: the mode to set (J, K SE0 NAK, Force Enable)
  41  *
  42  * Caller should take care of locking. This function will
  43  * return 0 on success or -EINVAL if wrong Test Selector
  44  * is passed
  45  */
  46 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
  47 {
  48         u32             reg;
  49
  50         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  51         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
  52
  53         switch (mode) {
  54         case TEST_J:
  55         case TEST_K:
  56         case TEST_SE0_NAK:
  57         case TEST_PACKET:
  58         case TEST_FORCE_EN:
  59                 reg |= mode << 1;
  60                 break;
  61         default:
  62                 return -EINVAL;
  63         }
  64
  65         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  66
  67         return 0;
  68 }
  69
  70 /**
  71  * dwc3_gadget_get_link_state - Gets current state of USB Link
  72  * @dwc: pointer to our context structure
  73  *
  74  * Caller should take care of locking. This function will
  75  * return the link state on success (>= 0) or -ETIMEDOUT.
  76  */
  77 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
  78 {
  79         u32             reg;
  80
  81         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
  82
  83         return DWC3_DSTS_USBLNKST(reg);
  84 }
  85
  86 /**
  87  * dwc3_gadget_set_link_state - Sets USB Link to a particular State
  88  * @dwc: pointer to our context structure
  89  * @state: the state to put link into
  90  *
  91  * Caller should take care of locking. This function will
  92  * return 0 on success or -ETIMEDOUT.
  93  */
  94 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
  95 {
  96         int             retries = 10000;
  97         u32             reg;
  98
  99         /*
 100          * Wait until device controller is ready. Only applies to 1.94a and
 101          * later RTL.
 102          */
 103         if (dwc->revision >= DWC3_REVISION_194A) {
 104                 while (--retries) {
 105                         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 106                         if (reg & DWC3_DSTS_DCNRD)
 107                                 udelay(5);
 108                         else
 109                                 break;
 110                 }
 111
 112                 if (retries <= 0)
 113                         return -ETIMEDOUT;
 114         }
 115
 116         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 117         reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
 118
 119         /* set requested state */
 120         reg |= DWC3_DCTL_ULSTCHNGREQ(state);
 121         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 122
 123         /*
 124          * The following code is racy when called from dwc3_gadget_wakeup,
 125          * and is not needed, at least on newer versions
 126          */
 127         if (dwc->revision >= DWC3_REVISION_194A)
 128                 return 0;
 129
 130         /* wait for a change in DSTS */
 131         retries = 10000;
 132         while (--retries) {
 133                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 134
 135                 if (DWC3_DSTS_USBLNKST(reg) == state)
 136                         return 0;
 137
 138                 udelay(5);
 139         }
 140
 141         dev_vdbg(dwc->dev, "link state change request timed out\n");
 142
 143         return -ETIMEDOUT;
 144 }
 145
 146 /**
 147  * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
 148  * @dwc: pointer to our context structure
 149  *
 150  * This function will a best effort FIFO allocation in order
 151  * to improve FIFO usage and throughput, while still allowing
 152  * us to enable as many endpoints as possible.
 153  *
 154  * Keep in mind that this operation will be highly dependent
 155  * on the configured size for RAM1 - which contains TxFifo -,
 156  * the amount of endpoints enabled on coreConsultant tool, and
 157  * the width of the Master Bus.
 158  *
 159  * In the ideal world, we would always be able to satisfy the
 160  * following equation:
 161  *
 162  * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \
 163  * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes
 164  *
 165  * Unfortunately, due to many variables that's not always the case.
 166  */
 167 int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc)
 168 {
 169         int             last_fifo_depth = 0;
 170         int             ram1_depth;
 171         int             fifo_size;
 172         int             mdwidth;
 173         int             num;
 174
 175         if (!dwc->needs_fifo_resize)
 176                 return 0;
 177
 178         ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
 179         mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
 180
 181         /* MDWIDTH is represented in bits, we need it in bytes */
 182         mdwidth >>= 3;
 183
 184         /*
 185          * FIXME For now we will only allocate 1 wMaxPacketSize space
 186          * for each enabled endpoint, later patches will come to
 187          * improve this algorithm so that we better use the internal
 188          * FIFO space
 189          */
 190         for (num = 0; num < dwc->num_in_eps; num++) {
 191                 /* bit0 indicates direction; 1 means IN ep */
 192                 struct dwc3_ep  *dep = dwc->eps[(num << 1) | 1];
 193                 int             mult = 1;
 194                 int             tmp;
 195
 196                 if (!(dep->flags & DWC3_EP_ENABLED))
 197                         continue;
 198
 199                 if (usb_endpoint_xfer_bulk(dep->endpoint.desc)
 200                                 || usb_endpoint_xfer_isoc(dep->endpoint.desc))
 201                         mult = 3;
 202
 203                 /*
 204                  * REVISIT: the following assumes we will always have enough
 205                  * space available on the FIFO RAM for all possible use cases.
 206                  * Make sure that's true somehow and change FIFO allocation
 207                  * accordingly.
 208                  *
 209                  * If we have Bulk or Isochronous endpoints, we want
 210                  * them to be able to be very, very fast. So we're giving
 211                  * those endpoints a fifo_size which is enough for 3 full
 212                  * packets
 213                  */
 214                 tmp = mult * (dep->endpoint.maxpacket + mdwidth);
 215                 tmp += mdwidth;
 216
 217                 fifo_size = DIV_ROUND_UP(tmp, mdwidth);
 218
 219                 fifo_size |= (last_fifo_depth << 16);
 220
 221                 dev_vdbg(dwc->dev, "%s: Fifo Addr %04x Size %d\n",
 222                                 dep->name, last_fifo_depth, fifo_size & 0xffff);
 223
 224                 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(num), fifo_size);
 225
 226                 last_fifo_depth += (fifo_size & 0xffff);
 227         }
 228
 229         return 0;
 230 }
 231
 232 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
 233                 int status)
 234 {
 235         struct dwc3                     *dwc = dep->dwc;
 236         int                             i;
 237
 238         if (req->queued) {
 239                 i = 0;
 240                 do {
 241                         dep->busy_slot++;
 242                         /*
 243                          * Skip LINK TRB. We can't use req->trb and check for
 244                          * DWC3_TRBCTL_LINK_TRB because it points the TRB we
 245                          * just completed (not the LINK TRB).
 246                          */
 247                         if (((dep->busy_slot & DWC3_TRB_MASK) ==
 248                                 DWC3_TRB_NUM- 1) &&
 249                                 usb_endpoint_xfer_isoc(dep->endpoint.desc))
 250                                 dep->busy_slot++;
 251                 } while(++i < req->request.num_mapped_sgs);
 252                 req->queued = false;
 253         }
 254         list_del(&req->list);
 255         req->trb = NULL;
 256
 257         if (req->request.status == -EINPROGRESS)
 258                 req->request.status = status;
 259
 260         if (dwc->ep0_bounced && dep->number == 0)
 261                 dwc->ep0_bounced = false;
 262         else
 263                 usb_gadget_unmap_request(&dwc->gadget, &req->request,
 264                                 req->direction);
 265
 266         dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n",
 267                         req, dep->name, req->request.actual,
 268                         req->request.length, status);
 269
 270         spin_unlock(&dwc->lock);
 271         req->request.complete(&dep->endpoint, &req->request);
 272         spin_lock(&dwc->lock);
 273 }
 274
 275 static const char *dwc3_gadget_ep_cmd_string(u8 cmd)
 276 {
 277         switch (cmd) {
 278         case DWC3_DEPCMD_DEPSTARTCFG:
 279                 return "Start New Configuration";
 280         case DWC3_DEPCMD_ENDTRANSFER:
 281                 return "End Transfer";
 282         case DWC3_DEPCMD_UPDATETRANSFER:
 283                 return "Update Transfer";
 284         case DWC3_DEPCMD_STARTTRANSFER:
 285                 return "Start Transfer";
 286         case DWC3_DEPCMD_CLEARSTALL:
 287                 return "Clear Stall";
 288         case DWC3_DEPCMD_SETSTALL:
 289                 return "Set Stall";
 290         case DWC3_DEPCMD_GETEPSTATE:
 291                 return "Get Endpoint State";
 292         case DWC3_DEPCMD_SETTRANSFRESOURCE:
 293                 return "Set Endpoint Transfer Resource";
 294         case DWC3_DEPCMD_SETEPCONFIG:
 295                 return "Set Endpoint Configuration";
 296         default:
 297                 return "UNKNOWN command";
 298         }
 299 }
 300
 301 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, int cmd, u32 param)
 302 {
 303         u32             timeout = 500;
 304         u32             reg;
 305
 306         dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
 307         dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
 308
 309         do {
 310                 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
 311                 if (!(reg & DWC3_DGCMD_CMDACT)) {
 312                         dev_vdbg(dwc->dev, "Command Complete --> %d\n",
 313                                         DWC3_DGCMD_STATUS(reg));
 314                         return 0;
 315                 }
 316
 317                 /*
 318                  * We can't sleep here, because it's also called from
 319                  * interrupt context.
 320                  */
 321                 timeout--;
 322                 if (!timeout)
 323                         return -ETIMEDOUT;
 324                 udelay(1);
 325         } while (1);
 326 }
 327
 328 int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
 329                 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
 330 {
 331         struct dwc3_ep          *dep = dwc->eps[ep];
 332         u32                     timeout = 500;
 333         u32                     reg;
 334
 335         dev_vdbg(dwc->dev, "%s: cmd '%s' params %08x %08x %08x\n",
 336                         dep->name,
 337                         dwc3_gadget_ep_cmd_string(cmd), params->param0,
 338                         params->param1, params->param2);
 339
 340         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
 341         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
 342         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
 343
 344         dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
 345         do {
 346                 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
 347                 if (!(reg & DWC3_DEPCMD_CMDACT)) {
 348                         dev_vdbg(dwc->dev, "Command Complete --> %d\n",
 349                                         DWC3_DEPCMD_STATUS(reg));
 350                         return 0;
 351                 }
 352
 353                 /*
 354                  * We can't sleep here, because it is also called from
 355                  * interrupt context.
 356                  */
 357                 timeout--;
 358                 if (!timeout)
 359                         return -ETIMEDOUT;
 360
 361                 udelay(1);
 362         } while (1);
 363 }
 364
 365 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
 366                 struct dwc3_trb *trb)
 367 {
 368         u32             offset = (char *) trb - (char *) dep->trb_pool;
 369
 370         return dep->trb_pool_dma + offset;
 371 }
 372
 373 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
 374 {
 375         struct dwc3             *dwc = dep->dwc;
 376
 377         if (dep->trb_pool)
 378                 return 0;
 379
 380         if (dep->number == 0 || dep->number == 1)
 381                 return 0;
 382
 383         dep->trb_pool = dma_alloc_coherent(dwc->dev,
 384                         sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 385                         &dep->trb_pool_dma, GFP_KERNEL);
 386         if (!dep->trb_pool) {
 387                 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
 388                                 dep->name);
 389                 return -ENOMEM;
 390         }
 391
 392         return 0;
 393 }
 394
 395 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
 396 {
 397         struct dwc3             *dwc = dep->dwc;
 398
 399         dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 400                         dep->trb_pool, dep->trb_pool_dma);
 401
 402         dep->trb_pool = NULL;
 403         dep->trb_pool_dma = 0;
 404 }
 405
 406 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
 407 {
 408         struct dwc3_gadget_ep_cmd_params params;
 409         u32                     cmd;
 410
 411         memset(&params, 0x00, sizeof(params));
 412
 413         if (dep->number != 1) {
 414                 cmd = DWC3_DEPCMD_DEPSTARTCFG;
 415                 /* XferRscIdx == 0 for ep0 and 2 for the remaining */
 416                 if (dep->number > 1) {
 417                         if (dwc->start_config_issued)
 418                                 return 0;
 419                         dwc->start_config_issued = true;
 420                         cmd |= DWC3_DEPCMD_PARAM(2);
 421                 }
 422
 423                 return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, &params);
 424         }
 425
 426         return 0;
 427 }
 428
 429 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
 430                 const struct usb_endpoint_descriptor *desc,
 431                 const struct usb_ss_ep_comp_descriptor *comp_desc,
 432                 bool ignore, bool restore)
 433 {
 434         struct dwc3_gadget_ep_cmd_params params;
 435
 436         memset(&params, 0x00, sizeof(params));
 437
 438         params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
 439                 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
 440
 441         /* Burst size is only needed in SuperSpeed mode */
 442         if (dwc->gadget.speed == USB_SPEED_SUPER) {
 443                 u32 burst = dep->endpoint.maxburst - 1;
 444
 445                 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst);
 446         }
 447
 448         if (ignore)
 449                 params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM;
 450
 451         if (restore) {
 452                 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
 453                 params.param2 |= dep->saved_state;
 454         }
 455
 456         params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
 457                 | DWC3_DEPCFG_XFER_NOT_READY_EN;
 458
 459         if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
 460                 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
 461                         | DWC3_DEPCFG_STREAM_EVENT_EN;
 462                 dep->stream_capable = true;
 463         }
 464
 465         if (usb_endpoint_xfer_isoc(desc))
 466                 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
 467
 468         /*
 469          * We are doing 1:1 mapping for endpoints, meaning
 470          * Physical Endpoints 2 maps to Logical Endpoint 2 and
 471          * so on. We consider the direction bit as part of the physical
 472          * endpoint number. So USB endpoint 0x81 is 0x03.
 473          */
 474         params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
 475
 476         /*
 477          * We must use the lower 16 TX FIFOs even though
 478          * HW might have more
 479          */
 480         if (dep->direction)
 481                 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
 482
 483         if (desc->bInterval) {
 484                 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
 485                 dep->interval = 1 << (desc->bInterval - 1);
 486         }
 487
 488         return dwc3_send_gadget_ep_cmd(dwc, dep->number,
 489                         DWC3_DEPCMD_SETEPCONFIG, &params);
 490 }
 491
 492 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
 493 {
 494         struct dwc3_gadget_ep_cmd_params params;
 495
 496         memset(&params, 0x00, sizeof(params));
 497
 498         params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
 499
 500         return dwc3_send_gadget_ep_cmd(dwc, dep->number,
 501                         DWC3_DEPCMD_SETTRANSFRESOURCE, &params);
 502 }
 503
 504 /**
 505  * __dwc3_gadget_ep_enable - Initializes a HW endpoint
 506  * @dep: endpoint to be initialized
 507  * @desc: USB Endpoint Descriptor
 508  *
 509  * Caller should take care of locking
 510  */
 511 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
 512                 const struct usb_endpoint_descriptor *desc,
 513                 const struct usb_ss_ep_comp_descriptor *comp_desc,
 514                 bool ignore, bool restore)
 515 {
 516         struct dwc3             *dwc = dep->dwc;
 517         u32                     reg;
 518         int                     ret = -ENOMEM;
 519
 520         dev_vdbg(dwc->dev, "Enabling %s\n", dep->name);
 521
 522         if (!(dep->flags & DWC3_EP_ENABLED)) {
 523                 ret = dwc3_gadget_start_config(dwc, dep);
 524                 if (ret)
 525                         return ret;
 526         }
 527
 528         ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore,
 529                         restore);
 530         if (ret)
 531                 return ret;
 532
 533         if (!(dep->flags & DWC3_EP_ENABLED)) {
 534                 struct dwc3_trb *trb_st_hw;
 535                 struct dwc3_trb *trb_link;
 536
 537                 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
 538                 if (ret)
 539                         return ret;
 540
 541                 dep->endpoint.desc = desc;
 542                 dep->comp_desc = comp_desc;
 543                 dep->type = usb_endpoint_type(desc);
 544                 dep->flags |= DWC3_EP_ENABLED;
 545
 546                 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 547                 reg |= DWC3_DALEPENA_EP(dep->number);
 548                 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 549
 550                 if (!usb_endpoint_xfer_isoc(desc))
 551                         return 0;
 552
 553                 memset(&trb_link, 0, sizeof(trb_link));
 554
 555                 /* Link TRB for ISOC. The HWO bit is never reset */
 556                 trb_st_hw = &dep->trb_pool[0];
 557
 558                 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
 559
 560                 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 561                 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 562                 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
 563                 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
 564         }
 565
 566         return 0;
 567 }
 568
 569 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
 570 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
 571 {
 572         struct dwc3_request             *req;
 573
 574         if (!list_empty(&dep->req_queued)) {
 575                 dwc3_stop_active_transfer(dwc, dep->number, true);
 576
 577                 /* - giveback all requests to gadget driver */
 578                 while (!list_empty(&dep->req_queued)) {
 579                         req = next_request(&dep->req_queued);
 580
 581                         dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 582                 }
 583         }
 584
 585         while (!list_empty(&dep->request_list)) {
 586                 req = next_request(&dep->request_list);
 587
 588                 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 589         }
 590 }
 591
 592 /**
 593  * __dwc3_gadget_ep_disable - Disables a HW endpoint
 594  * @dep: the endpoint to disable
 595  *
 596  * This function also removes requests which are currently processed ny the
 597  * hardware and those which are not yet scheduled.
 598  * Caller should take care of locking.
 599  */
 600 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
 601 {
 602         struct dwc3             *dwc = dep->dwc;
 603         u32                     reg;
 604
 605         dwc3_remove_requests(dwc, dep);
 606
 607         reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 608         reg &= ~DWC3_DALEPENA_EP(dep->number);
 609         dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 610
 611         dep->stream_capable = false;
 612         dep->endpoint.desc = NULL;
 613         dep->comp_desc = NULL;
 614         dep->type = 0;
 615         dep->flags = 0;
 616
 617         return 0;
 618 }
 619
 620 /* -------------------------------------------------------------------------- */
 621
 622 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
 623                 const struct usb_endpoint_descriptor *desc)
 624 {
 625         return -EINVAL;
 626 }
 627
 628 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
 629 {
 630         return -EINVAL;
 631 }
 632
 633 /* -------------------------------------------------------------------------- */
 634
 635 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
 636                 const struct usb_endpoint_descriptor *desc)
 637 {
 638         struct dwc3_ep                  *dep;
 639         struct dwc3                     *dwc;
 640         unsigned long                   flags;
 641         int                             ret;
 642
 643         if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
 644                 pr_debug("dwc3: invalid parameters\n");
 645                 return -EINVAL;
 646         }
 647
 648         if (!desc->wMaxPacketSize) {
 649                 pr_debug("dwc3: missing wMaxPacketSize\n");
 650                 return -EINVAL;
 651         }
 652
 653         dep = to_dwc3_ep(ep);
 654         dwc = dep->dwc;
 655
 656         if (dep->flags & DWC3_EP_ENABLED) {
 657                 dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n",
 658                                 dep->name);
 659                 return 0;
 660         }
 661
 662         switch (usb_endpoint_type(desc)) {
 663         case USB_ENDPOINT_XFER_CONTROL:
 664                 strlcat(dep->name, "-control", sizeof(dep->name));
 665                 break;
 666         case USB_ENDPOINT_XFER_ISOC:
 667                 strlcat(dep->name, "-isoc", sizeof(dep->name));
 668                 break;
 669         case USB_ENDPOINT_XFER_BULK:
 670                 strlcat(dep->name, "-bulk", sizeof(dep->name));
 671                 break;
 672         case USB_ENDPOINT_XFER_INT:
 673                 strlcat(dep->name, "-int", sizeof(dep->name));
 674                 break;
 675         default:
 676                 dev_err(dwc->dev, "invalid endpoint transfer type\n");
 677         }
 678
 679         spin_lock_irqsave(&dwc->lock, flags);
 680         ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false);
 681         spin_unlock_irqrestore(&dwc->lock, flags);
 682
 683         return ret;
 684 }
 685
 686 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
 687 {
 688         struct dwc3_ep                  *dep;
 689         struct dwc3                     *dwc;
 690         unsigned long                   flags;
 691         int                             ret;
 692
 693         if (!ep) {
 694                 pr_debug("dwc3: invalid parameters\n");
 695                 return -EINVAL;
 696         }
 697
 698         dep = to_dwc3_ep(ep);
 699         dwc = dep->dwc;
 700
 701         if (!(dep->flags & DWC3_EP_ENABLED)) {
 702                 dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n",
 703                                 dep->name);
 704                 return 0;
 705         }
 706
 707         snprintf(dep->name, sizeof(dep->name), "ep%d%s",
 708                         dep->number >> 1,
 709                         (dep->number & 1) ? "in" : "out");
 710
 711         spin_lock_irqsave(&dwc->lock, flags);
 712         ret = __dwc3_gadget_ep_disable(dep);
 713         spin_unlock_irqrestore(&dwc->lock, flags);
 714
 715         return ret;
 716 }
 717
 718 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
 719         gfp_t gfp_flags)
 720 {
 721         struct dwc3_request             *req;
 722         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 723         struct dwc3                     *dwc = dep->dwc;
 724
 725         req = kzalloc(sizeof(*req), gfp_flags);
 726         if (!req) {
 727                 dev_err(dwc->dev, "not enough memory\n");
 728                 return NULL;
 729         }
 730
 731         req->epnum      = dep->number;
 732         req->dep        = dep;
 733
 734         return &req->request;
 735 }
 736
 737 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
 738                 struct usb_request *request)
 739 {
 740         struct dwc3_request             *req = to_dwc3_request(request);
 741
 742         kfree(req);
 743 }
 744
 745 /**
 746  * dwc3_prepare_one_trb - setup one TRB from one request
 747  * @dep: endpoint for which this request is prepared
 748  * @req: dwc3_request pointer
 749  */
 750 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
 751                 struct dwc3_request *req, dma_addr_t dma,
 752                 unsigned length, unsigned last, unsigned chain, unsigned node)
 753 {
 754         struct dwc3             *dwc = dep->dwc;
 755         struct dwc3_trb         *trb;
 756
 757         dev_vdbg(dwc->dev, "%s: req %p dma %08llx length %d%s%s\n",
 758                         dep->name, req, (unsigned long long) dma,
 759                         length, last ? " last" : "",
 760                         chain ? " chain" : "");
 761
 762         /* Skip the LINK-TRB on ISOC */
 763         if (((dep->free_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
 764                         usb_endpoint_xfer_isoc(dep->endpoint.desc))
 765                 dep->free_slot++;
 766
 767         trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
 768
 769         if (!req->trb) {
 770                 dwc3_gadget_move_request_queued(req);
 771                 req->trb = trb;
 772                 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
 773                 req->start_slot = dep->free_slot & DWC3_TRB_MASK;
 774         }
 775
 776         dep->free_slot++;
 777
 778         trb->size = DWC3_TRB_SIZE_LENGTH(length);
 779         trb->bpl = lower_32_bits(dma);
 780         trb->bph = upper_32_bits(dma);
 781
 782         switch (usb_endpoint_type(dep->endpoint.desc)) {
 783         case USB_ENDPOINT_XFER_CONTROL:
 784                 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
 785                 break;
 786
 787         case USB_ENDPOINT_XFER_ISOC:
 788                 if (!node)
 789                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
 790                 else
 791                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
 792                 break;
 793
 794         case USB_ENDPOINT_XFER_BULK:
 795         case USB_ENDPOINT_XFER_INT:
 796                 trb->ctrl = DWC3_TRBCTL_NORMAL;
 797                 break;
 798         default:
 799                 /*
 800                  * This is only possible with faulty memory because we
 801                  * checked it already :)
 802                  */
 803                 BUG();
 804         }
 805
 806         if (!req->request.no_interrupt && !chain)
 807                 trb->ctrl |= DWC3_TRB_CTRL_IOC;
 808
 809         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
 810                 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
 811                 trb->ctrl |= DWC3_TRB_CTRL_CSP;
 812         } else if (last) {
 813                 trb->ctrl |= DWC3_TRB_CTRL_LST;
 814         }
 815
 816         if (chain)
 817                 trb->ctrl |= DWC3_TRB_CTRL_CHN;
 818
 819         if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
 820                 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
 821
 822         trb->ctrl |= DWC3_TRB_CTRL_HWO;
 823 }
 824
 825 /*
 826  * dwc3_prepare_trbs - setup TRBs from requests
 827  * @dep: endpoint for which requests are being prepared
 828  * @starting: true if the endpoint is idle and no requests are queued.
 829  *
 830  * The function goes through the requests list and sets up TRBs for the
 831  * transfers. The function returns once there are no more TRBs available or
 832  * it runs out of requests.
 833  */
 834 static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
 835 {
 836         struct dwc3_request     *req, *n;
 837         u32                     trbs_left;
 838         u32                     max;
 839         unsigned int            last_one = 0;
 840
 841         BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
 842
 843         /* the first request must not be queued */
 844         trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
 845
 846         /* Can't wrap around on a non-isoc EP since there's no link TRB */
 847         if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
 848                 max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK);
 849                 if (trbs_left > max)
 850                         trbs_left = max;
 851         }
 852
 853         /*
 854          * If busy & slot are equal than it is either full or empty. If we are
 855          * starting to process requests then we are empty. Otherwise we are
 856          * full and don't do anything
 857          */
 858         if (!trbs_left) {
 859                 if (!starting)
 860                         return;
 861                 trbs_left = DWC3_TRB_NUM;
 862                 /*
 863                  * In case we start from scratch, we queue the ISOC requests
 864                  * starting from slot 1. This is done because we use ring
 865                  * buffer and have no LST bit to stop us. Instead, we place
 866                  * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
 867                  * after the first request so we start at slot 1 and have
 868                  * 7 requests proceed before we hit the first IOC.
 869                  * Other transfer types don't use the ring buffer and are
 870                  * processed from the first TRB until the last one. Since we
 871                  * don't wrap around we have to start at the beginning.
 872                  */
 873                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
 874                         dep->busy_slot = 1;
 875                         dep->free_slot = 1;
 876                 } else {
 877                         dep->busy_slot = 0;
 878                         dep->free_slot = 0;
 879                 }
 880         }
 881
 882         /* The last TRB is a link TRB, not used for xfer */
 883         if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc))
 884                 return;
 885
 886         list_for_each_entry_safe(req, n, &dep->request_list, list) {
 887                 unsigned        length;
 888                 dma_addr_t      dma;
 889                 last_one = false;
 890
 891                 if (req->request.num_mapped_sgs > 0) {
 892                         struct usb_request *request = &req->request;
 893                         struct scatterlist *sg = request->sg;
 894                         struct scatterlist *s;
 895                         int             i;
 896
 897                         for_each_sg(sg, s, request->num_mapped_sgs, i) {
 898                                 unsigned chain = true;
 899
 900                                 length = sg_dma_len(s);
 901                                 dma = sg_dma_address(s);
 902
 903                                 if (i == (request->num_mapped_sgs - 1) ||
 904                                                 sg_is_last(s)) {
 905                                         if (list_is_last(&req->list,
 906                                                         &dep->request_list))
 907                                                 last_one = true;
 908                                         chain = false;
 909                                 }
 910
 911                                 trbs_left--;
 912                                 if (!trbs_left)
 913                                         last_one = true;
 914
 915                                 if (last_one)
 916                                         chain = false;
 917
 918                                 dwc3_prepare_one_trb(dep, req, dma, length,
 919                                                 last_one, chain, i);
 920
 921                                 if (last_one)
 922                                         break;
 923                         }
 924                 } else {
 925                         dma = req->request.dma;
 926                         length = req->request.length;
 927                         trbs_left--;
 928
 929                         if (!trbs_left)
 930                                 last_one = 1;
 931
 932                         /* Is this the last request? */
 933                         if (list_is_last(&req->list, &dep->request_list))
 934                                 last_one = 1;
 935
 936                         dwc3_prepare_one_trb(dep, req, dma, length,
 937                                         last_one, false, 0);
 938
 939                         if (last_one)
 940                                 break;
 941                 }
 942         }
 943 }
 944
 945 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
 946                 int start_new)
 947 {
 948         struct dwc3_gadget_ep_cmd_params params;
 949         struct dwc3_request             *req;
 950         struct dwc3                     *dwc = dep->dwc;
 951         int                             ret;
 952         u32                             cmd;
 953
 954         if (start_new && (dep->flags & DWC3_EP_BUSY)) {
 955                 dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name);
 956                 return -EBUSY;
 957         }
 958         dep->flags &= ~DWC3_EP_PENDING_REQUEST;
 959
 960         /*
 961          * If we are getting here after a short-out-packet we don't enqueue any
 962          * new requests as we try to set the IOC bit only on the last request.
 963          */
 964         if (start_new) {
 965                 if (list_empty(&dep->req_queued))
 966                         dwc3_prepare_trbs(dep, start_new);
 967
 968                 /* req points to the first request which will be sent */
 969                 req = next_request(&dep->req_queued);
 970         } else {
 971                 dwc3_prepare_trbs(dep, start_new);
 972
 973                 /*
 974                  * req points to the first request where HWO changed from 0 to 1
 975                  */
 976                 req = next_request(&dep->req_queued);
 977         }
 978         if (!req) {
 979                 dep->flags |= DWC3_EP_PENDING_REQUEST;
 980                 return 0;
 981         }
 982
 983         memset(&params, 0, sizeof(params));
 984
 985         if (start_new) {
 986                 params.param0 = upper_32_bits(req->trb_dma);
 987                 params.param1 = lower_32_bits(req->trb_dma);
 988                 cmd = DWC3_DEPCMD_STARTTRANSFER;
 989         } else {
 990                 cmd = DWC3_DEPCMD_UPDATETRANSFER;
 991         }
 992
 993         cmd |= DWC3_DEPCMD_PARAM(cmd_param);
 994         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
 995         if (ret < 0) {
 996                 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
 997
 998                 /*
 999                  * FIXME we need to iterate over the list of requests
1000                  * here and stop, unmap, free and del each of the linked
1001                  * requests instead of what we do now.
1002                  */
1003                 usb_gadget_unmap_request(&dwc->gadget, &req->request,
1004                                 req->direction);
1005                 list_del(&req->list);
1006                 return ret;
1007         }
1008
1009         dep->flags |= DWC3_EP_BUSY;
1010
1011         if (start_new) {
1012                 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
1013                                 dep->number);
1014                 WARN_ON_ONCE(!dep->resource_index);
1015         }
1016
1017         return 0;
1018 }
1019
1020 static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1021                 struct dwc3_ep *dep, u32 cur_uf)
1022 {
1023         u32 uf;
1024
1025         if (list_empty(&dep->request_list)) {
1026                 dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n",
1027                         dep->name);
1028                 dep->flags |= DWC3_EP_PENDING_REQUEST;
1029                 return;
1030         }
1031
1032         /* 4 micro frames in the future */
1033         uf = cur_uf + dep->interval * 4;
1034
1035         __dwc3_gadget_kick_transfer(dep, uf, 1);
1036 }
1037
1038 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1039                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1040 {
1041         u32 cur_uf, mask;
1042
1043         mask = ~(dep->interval - 1);
1044         cur_uf = event->parameters & mask;
1045
1046         __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1047 }
1048
1049 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1050 {
1051         struct dwc3             *dwc = dep->dwc;
1052         int                     ret;
1053
1054         req->request.actual     = 0;
1055         req->request.status     = -EINPROGRESS;
1056         req->direction          = dep->direction;
1057         req->epnum              = dep->number;
1058
1059         /*
1060          * We only add to our list of requests now and
1061          * start consuming the list once we get XferNotReady
1062          * IRQ.
1063          *
1064          * That way, we avoid doing anything that we don't need
1065          * to do now and defer it until the point we receive a
1066          * particular token from the Host side.
1067          *
1068          * This will also avoid Host cancelling URBs due to too
1069          * many NAKs.
1070          */
1071         ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1072                         dep->direction);
1073         if (ret)
1074                 return ret;
1075
1076         list_add_tail(&req->list, &dep->request_list);
1077
1078         /*
1079          * There are a few special cases:
1080          *
1081          * 1. XferNotReady with empty list of requests. We need to kick the
1082          *    transfer here in that situation, otherwise we will be NAKing
1083          *    forever. If we get XferNotReady before gadget driver has a
1084          *    chance to queue a request, we will ACK the IRQ but won't be
1085          *    able to receive the data until the next request is queued.
1086          *    The following code is handling exactly that.
1087          *
1088          */
1089         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
1090                 /*
1091                  * If xfernotready is already elapsed and it is a case
1092                  * of isoc transfer, then issue END TRANSFER, so that
1093                  * you can receive xfernotready again and can have
1094                  * notion of current microframe.
1095                  */
1096                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1097                         if (list_empty(&dep->req_queued)) {
1098                                 dwc3_stop_active_transfer(dwc, dep->number, true);
1099                                 dep->flags = DWC3_EP_ENABLED;
1100                         }
1101                         return 0;
1102                 }
1103
1104                 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1105                 if (ret && ret != -EBUSY)
1106                         dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1107                                         dep->name);
1108                 return ret;
1109         }
1110
1111         /*
1112          * 2. XferInProgress on Isoc EP with an active transfer. We need to
1113          *    kick the transfer here after queuing a request, otherwise the
1114          *    core may not see the modified TRB(s).
1115          */
1116         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1117                         (dep->flags & DWC3_EP_BUSY) &&
1118                         !(dep->flags & DWC3_EP_MISSED_ISOC)) {
1119                 WARN_ON_ONCE(!dep->resource_index);
1120                 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index,
1121                                 false);
1122                 if (ret && ret != -EBUSY)
1123                         dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1124                                         dep->name);
1125                 return ret;
1126         }
1127
1128         /*
1129          * 4. Stream Capable Bulk Endpoints. We need to start the transfer
1130          * right away, otherwise host will not know we have streams to be
1131          * handled.
1132          */
1133         if (dep->stream_capable) {
1134                 int     ret;
1135
1136                 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1137                 if (ret && ret != -EBUSY) {
1138                         struct dwc3     *dwc = dep->dwc;
1139
1140                         dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1141                                         dep->name);
1142                 }
1143         }
1144
1145         return 0;
1146 }
1147
1148 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1149         gfp_t gfp_flags)
1150 {
1151         struct dwc3_request             *req = to_dwc3_request(request);
1152         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1153         struct dwc3                     *dwc = dep->dwc;
1154
1155         unsigned long                   flags;
1156
1157         int                             ret;
1158
1159         if (!dep->endpoint.desc) {
1160                 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
1161                                 request, ep->name);
1162                 return -ESHUTDOWN;
1163         }
1164
1165         dev_vdbg(dwc->dev, "queing request %p to %s length %d\n",
1166                         request, ep->name, request->length);
1167
1168         spin_lock_irqsave(&dwc->lock, flags);
1169         ret = __dwc3_gadget_ep_queue(dep, req);
1170         spin_unlock_irqrestore(&dwc->lock, flags);
1171
1172         return ret;
1173 }
1174
1175 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1176                 struct usb_request *request)
1177 {
1178         struct dwc3_request             *req = to_dwc3_request(request);
1179         struct dwc3_request             *r = NULL;
1180
1181         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1182         struct dwc3                     *dwc = dep->dwc;
1183
1184         unsigned long                   flags;
1185         int                             ret = 0;
1186
1187         spin_lock_irqsave(&dwc->lock, flags);
1188
1189         list_for_each_entry(r, &dep->request_list, list) {
1190                 if (r == req)
1191                         break;
1192         }
1193
1194         if (r != req) {
1195                 list_for_each_entry(r, &dep->req_queued, list) {
1196                         if (r == req)
1197                                 break;
1198                 }
1199                 if (r == req) {
1200                         /* wait until it is processed */
1201                         dwc3_stop_active_transfer(dwc, dep->number, true);
1202                         goto out1;
1203                 }
1204                 dev_err(dwc->dev, "request %p was not queued to %s\n",
1205                                 request, ep->name);
1206                 ret = -EINVAL;
1207                 goto out0;
1208         }
1209
1210 out1:
1211         /* giveback the request */
1212         dwc3_gadget_giveback(dep, req, -ECONNRESET);
1213
1214 out0:
1215         spin_unlock_irqrestore(&dwc->lock, flags);
1216
1217         return ret;
1218 }
1219
1220 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value)
1221 {
1222         struct dwc3_gadget_ep_cmd_params        params;
1223         struct dwc3                             *dwc = dep->dwc;
1224         int                                     ret;
1225
1226         memset(&params, 0x00, sizeof(params));
1227
1228         if (value) {
1229                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1230                         DWC3_DEPCMD_SETSTALL, &params);
1231                 if (ret)
1232                         dev_err(dwc->dev, "failed to set STALL on %s\n",
1233                                         dep->name);
1234                 else
1235                         dep->flags |= DWC3_EP_STALL;
1236         } else {
1237                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1238                         DWC3_DEPCMD_CLEARSTALL, &params);
1239                 if (ret)
1240                         dev_err(dwc->dev, "failed to clear STALL on %s\n",
1241                                         dep->name);
1242                 else
1243                         dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1244         }
1245
1246         return ret;
1247 }
1248
1249 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1250 {
1251         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1252         struct dwc3                     *dwc = dep->dwc;
1253
1254         unsigned long                   flags;
1255
1256         int                             ret;
1257
1258         spin_lock_irqsave(&dwc->lock, flags);
1259
1260         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1261                 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1262                 ret = -EINVAL;
1263                 goto out;
1264         }
1265
1266         ret = __dwc3_gadget_ep_set_halt(dep, value);
1267 out:
1268         spin_unlock_irqrestore(&dwc->lock, flags);
1269
1270         return ret;
1271 }
1272
1273 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1274 {
1275         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1276         struct dwc3                     *dwc = dep->dwc;
1277         unsigned long                   flags;
1278
1279         spin_lock_irqsave(&dwc->lock, flags);
1280         dep->flags |= DWC3_EP_WEDGE;
1281         spin_unlock_irqrestore(&dwc->lock, flags);
1282
1283         if (dep->number == 0 || dep->number == 1)
1284                 return dwc3_gadget_ep0_set_halt(ep, 1);
1285         else
1286                 return dwc3_gadget_ep_set_halt(ep, 1);
1287 }
1288
1289 /* -------------------------------------------------------------------------- */
1290
1291 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1292         .bLength        = USB_DT_ENDPOINT_SIZE,
1293         .bDescriptorType = USB_DT_ENDPOINT,
1294         .bmAttributes   = USB_ENDPOINT_XFER_CONTROL,
1295 };
1296
1297 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1298         .enable         = dwc3_gadget_ep0_enable,
1299         .disable        = dwc3_gadget_ep0_disable,
1300         .alloc_request  = dwc3_gadget_ep_alloc_request,
1301         .free_request   = dwc3_gadget_ep_free_request,
1302         .queue          = dwc3_gadget_ep0_queue,
1303         .dequeue        = dwc3_gadget_ep_dequeue,
1304         .set_halt       = dwc3_gadget_ep0_set_halt,
1305         .set_wedge      = dwc3_gadget_ep_set_wedge,
1306 };
1307
1308 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1309         .enable         = dwc3_gadget_ep_enable,
1310         .disable        = dwc3_gadget_ep_disable,
1311         .alloc_request  = dwc3_gadget_ep_alloc_request,
1312         .free_request   = dwc3_gadget_ep_free_request,
1313         .queue          = dwc3_gadget_ep_queue,
1314         .dequeue        = dwc3_gadget_ep_dequeue,
1315         .set_halt       = dwc3_gadget_ep_set_halt,
1316         .set_wedge      = dwc3_gadget_ep_set_wedge,
1317 };
1318
1319 /* -------------------------------------------------------------------------- */
1320
1321 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1322 {
1323         struct dwc3             *dwc = gadget_to_dwc(g);
1324         u32                     reg;
1325
1326         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1327         return DWC3_DSTS_SOFFN(reg);
1328 }
1329
1330 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1331 {
1332         struct dwc3             *dwc = gadget_to_dwc(g);
1333
1334         unsigned long           timeout;
1335         unsigned long           flags;
1336
1337         u32                     reg;
1338
1339         int                     ret = 0;
1340
1341         u8                      link_state;
1342         u8                      speed;
1343
1344         spin_lock_irqsave(&dwc->lock, flags);
1345
1346         /*
1347          * According to the Databook Remote wakeup request should
1348          * be issued only when the device is in early suspend state.
1349          *
1350          * We can check that via USB Link State bits in DSTS register.
1351          */
1352         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1353
1354         speed = reg & DWC3_DSTS_CONNECTSPD;
1355         if (speed == DWC3_DSTS_SUPERSPEED) {
1356                 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n");
1357                 ret = -EINVAL;
1358                 goto out;
1359         }
1360
1361         link_state = DWC3_DSTS_USBLNKST(reg);
1362
1363         switch (link_state) {
1364         case DWC3_LINK_STATE_RX_DET:    /* in HS, means Early Suspend */
1365         case DWC3_LINK_STATE_U3:        /* in HS, means SUSPEND */
1366                 break;
1367         default:
1368                 dev_dbg(dwc->dev, "can't wakeup from link state %d\n",
1369                                 link_state);
1370                 ret = -EINVAL;
1371                 goto out;
1372         }
1373
1374         ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1375         if (ret < 0) {
1376                 dev_err(dwc->dev, "failed to put link in Recovery\n");
1377                 goto out;
1378         }
1379
1380         /* Recent versions do this automatically */
1381         if (dwc->revision < DWC3_REVISION_194A) {
1382                 /* write zeroes to Link Change Request */
1383                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1384                 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1385                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1386         }
1387
1388         /* poll until Link State changes to ON */
1389         timeout = jiffies + msecs_to_jiffies(100);
1390
1391         while (!time_after(jiffies, timeout)) {
1392                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1393
1394                 /* in HS, means ON */
1395                 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1396                         break;
1397         }
1398
1399         if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1400                 dev_err(dwc->dev, "failed to send remote wakeup\n");
1401                 ret = -EINVAL;
1402         }
1403
1404 out:
1405         spin_unlock_irqrestore(&dwc->lock, flags);
1406
1407         return ret;
1408 }
1409
1410 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1411                 int is_selfpowered)
1412 {
1413         struct dwc3             *dwc = gadget_to_dwc(g);
1414         unsigned long           flags;
1415
1416         spin_lock_irqsave(&dwc->lock, flags);
1417         dwc->is_selfpowered = !!is_selfpowered;
1418         spin_unlock_irqrestore(&dwc->lock, flags);
1419
1420         return 0;
1421 }
1422
1423 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1424 {
1425         u32                     reg;
1426         u32                     timeout = 500;
1427
1428         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1429         if (is_on) {
1430                 if (dwc->revision <= DWC3_REVISION_187A) {
1431                         reg &= ~DWC3_DCTL_TRGTULST_MASK;
1432                         reg |= DWC3_DCTL_TRGTULST_RX_DET;
1433                 }
1434
1435                 if (dwc->revision >= DWC3_REVISION_194A)
1436                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1437                 reg |= DWC3_DCTL_RUN_STOP;
1438
1439                 if (dwc->has_hibernation)
1440                         reg |= DWC3_DCTL_KEEP_CONNECT;
1441
1442                 dwc->pullups_connected = true;
1443         } else {
1444                 reg &= ~DWC3_DCTL_RUN_STOP;
1445
1446                 if (dwc->has_hibernation && !suspend)
1447                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1448
1449                 dwc->pullups_connected = false;
1450         }
1451
1452         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1453
1454         do {
1455                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1456                 if (is_on) {
1457                         if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1458                                 break;
1459                 } else {
1460                         if (reg & DWC3_DSTS_DEVCTRLHLT)
1461                                 break;
1462                 }
1463                 timeout--;
1464                 if (!timeout)
1465                         return -ETIMEDOUT;
1466                 udelay(1);
1467         } while (1);
1468
1469         dev_vdbg(dwc->dev, "gadget %s data soft-%s\n",
1470                         dwc->gadget_driver
1471                         ? dwc->gadget_driver->function : "no-function",
1472                         is_on ? "connect" : "disconnect");
1473
1474         return 0;
1475 }
1476
1477 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1478 {
1479         struct dwc3             *dwc = gadget_to_dwc(g);
1480         unsigned long           flags;
1481         int                     ret;
1482
1483         is_on = !!is_on;
1484
1485         spin_lock_irqsave(&dwc->lock, flags);
1486         ret = dwc3_gadget_run_stop(dwc, is_on, false);
1487         spin_unlock_irqrestore(&dwc->lock, flags);
1488
1489         return ret;
1490 }
1491
1492 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1493 {
1494         u32                     reg;
1495
1496         /* Enable all but Start and End of Frame IRQs */
1497         reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1498                         DWC3_DEVTEN_EVNTOVERFLOWEN |
1499                         DWC3_DEVTEN_CMDCMPLTEN |
1500                         DWC3_DEVTEN_ERRTICERREN |
1501                         DWC3_DEVTEN_WKUPEVTEN |
1502                         DWC3_DEVTEN_ULSTCNGEN |
1503                         DWC3_DEVTEN_CONNECTDONEEN |
1504                         DWC3_DEVTEN_USBRSTEN |
1505                         DWC3_DEVTEN_DISCONNEVTEN);
1506
1507         dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1508 }
1509
1510 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1511 {
1512         /* mask all interrupts */
1513         dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1514 }
1515
1516 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1517 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1518
1519 static int dwc3_gadget_start(struct usb_gadget *g,
1520                 struct usb_gadget_driver *driver)
1521 {
1522         struct dwc3             *dwc = gadget_to_dwc(g);
1523         struct dwc3_ep          *dep;
1524         unsigned long           flags;
1525         int                     ret = 0;
1526         int                     irq;
1527         u32                     reg;
1528
1529         irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1530         ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1531                         IRQF_SHARED, "dwc3", dwc);
1532         if (ret) {
1533                 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1534                                 irq, ret);
1535                 goto err0;
1536         }
1537
1538         spin_lock_irqsave(&dwc->lock, flags);
1539
1540         if (dwc->gadget_driver) {
1541                 dev_err(dwc->dev, "%s is already bound to %s\n",
1542                                 dwc->gadget.name,
1543                                 dwc->gadget_driver->driver.name);
1544                 ret = -EBUSY;
1545                 goto err1;
1546         }
1547
1548         dwc->gadget_driver      = driver;
1549
1550         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1551         reg &= ~(DWC3_DCFG_SPEED_MASK);
1552
1553         /**
1554          * WORKAROUND: DWC3 revision < 2.20a have an issue
1555          * which would cause metastability state on Run/Stop
1556          * bit if we try to force the IP to USB2-only mode.
1557          *
1558          * Because of that, we cannot configure the IP to any
1559          * speed other than the SuperSpeed
1560          *
1561          * Refers to:
1562          *
1563          * STAR#9000525659: Clock Domain Crossing on DCTL in
1564          * USB 2.0 Mode
1565          */
1566         if (dwc->revision < DWC3_REVISION_220A) {
1567                 reg |= DWC3_DCFG_SUPERSPEED;
1568         } else {
1569                 switch (dwc->maximum_speed) {
1570                 case USB_SPEED_LOW:
1571                         reg |= DWC3_DSTS_LOWSPEED;
1572                         break;
1573                 case USB_SPEED_FULL:
1574                         reg |= DWC3_DSTS_FULLSPEED1;
1575                         break;
1576                 case USB_SPEED_HIGH:
1577                         reg |= DWC3_DSTS_HIGHSPEED;
1578                         break;
1579                 case USB_SPEED_SUPER:   /* FALLTHROUGH */
1580                 case USB_SPEED_UNKNOWN: /* FALTHROUGH */
1581                 default:
1582                         reg |= DWC3_DSTS_SUPERSPEED;
1583                 }
1584         }
1585         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1586
1587         dwc->start_config_issued = false;
1588
1589         /* Start with SuperSpeed Default */
1590         dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1591
1592         dep = dwc->eps[0];
1593         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1594                         false);
1595         if (ret) {
1596                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1597                 goto err2;
1598         }
1599
1600         dep = dwc->eps[1];
1601         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1602                         false);
1603         if (ret) {
1604                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1605                 goto err3;
1606         }
1607
1608         /* begin to receive SETUP packets */
1609         dwc->ep0state = EP0_SETUP_PHASE;
1610         dwc3_ep0_out_start(dwc);
1611
1612         dwc3_gadget_enable_irq(dwc);
1613
1614         spin_unlock_irqrestore(&dwc->lock, flags);
1615
1616         return 0;
1617
1618 err3:
1619         __dwc3_gadget_ep_disable(dwc->eps[0]);
1620
1621 err2:
1622         dwc->gadget_driver = NULL;
1623
1624 err1:
1625         spin_unlock_irqrestore(&dwc->lock, flags);
1626
1627         free_irq(irq, dwc);
1628
1629 err0:
1630         return ret;
1631 }
1632
1633 static int dwc3_gadget_stop(struct usb_gadget *g,
1634                 struct usb_gadget_driver *driver)
1635 {
1636         struct dwc3             *dwc = gadget_to_dwc(g);
1637         unsigned long           flags;
1638         int                     irq;
1639
1640         spin_lock_irqsave(&dwc->lock, flags);
1641
1642         dwc3_gadget_disable_irq(dwc);
1643         __dwc3_gadget_ep_disable(dwc->eps[0]);
1644         __dwc3_gadget_ep_disable(dwc->eps[1]);
1645
1646         dwc->gadget_driver      = NULL;
1647
1648         spin_unlock_irqrestore(&dwc->lock, flags);
1649
1650         irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1651         free_irq(irq, dwc);
1652
1653         return 0;
1654 }
1655
1656 static const struct usb_gadget_ops dwc3_gadget_ops = {
1657         .get_frame              = dwc3_gadget_get_frame,
1658         .wakeup                 = dwc3_gadget_wakeup,
1659         .set_selfpowered        = dwc3_gadget_set_selfpowered,
1660         .pullup                 = dwc3_gadget_pullup,
1661         .udc_start              = dwc3_gadget_start,
1662         .udc_stop               = dwc3_gadget_stop,
1663 };
1664
1665 /* -------------------------------------------------------------------------- */
1666
1667 static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
1668                 u8 num, u32 direction)
1669 {
1670         struct dwc3_ep                  *dep;
1671         u8                              i;
1672
1673         for (i = 0; i < num; i++) {
1674                 u8 epnum = (i << 1) | (!!direction);
1675
1676                 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1677                 if (!dep) {
1678                         dev_err(dwc->dev, "can't allocate endpoint %d\n",
1679                                         epnum);
1680                         return -ENOMEM;
1681                 }
1682
1683                 dep->dwc = dwc;
1684                 dep->number = epnum;
1685                 dep->direction = !!direction;
1686                 dwc->eps[epnum] = dep;
1687
1688                 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1689                                 (epnum & 1) ? "in" : "out");
1690
1691                 dep->endpoint.name = dep->name;
1692
1693                 dev_vdbg(dwc->dev, "initializing %s\n", dep->name);
1694
1695                 if (epnum == 0 || epnum == 1) {
1696                         usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
1697                         dep->endpoint.maxburst = 1;
1698                         dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1699                         if (!epnum)
1700                                 dwc->gadget.ep0 = &dep->endpoint;
1701                 } else {
1702                         int             ret;
1703
1704                         usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
1705                         dep->endpoint.max_streams = 15;
1706                         dep->endpoint.ops = &dwc3_gadget_ep_ops;
1707                         list_add_tail(&dep->endpoint.ep_list,
1708                                         &dwc->gadget.ep_list);
1709
1710                         ret = dwc3_alloc_trb_pool(dep);
1711                         if (ret)
1712                                 return ret;
1713                 }
1714
1715                 INIT_LIST_HEAD(&dep->request_list);
1716                 INIT_LIST_HEAD(&dep->req_queued);
1717         }
1718
1719         return 0;
1720 }
1721
1722 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1723 {
1724         int                             ret;
1725
1726         INIT_LIST_HEAD(&dwc->gadget.ep_list);
1727
1728         ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
1729         if (ret < 0) {
1730                 dev_vdbg(dwc->dev, "failed to allocate OUT endpoints\n");
1731                 return ret;
1732         }
1733
1734         ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
1735         if (ret < 0) {
1736                 dev_vdbg(dwc->dev, "failed to allocate IN endpoints\n");
1737                 return ret;
1738         }
1739
1740         return 0;
1741 }
1742
1743 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1744 {
1745         struct dwc3_ep                  *dep;
1746         u8                              epnum;
1747
1748         for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1749                 dep = dwc->eps[epnum];
1750                 if (!dep)
1751                         continue;
1752                 /*
1753                  * Physical endpoints 0 and 1 are special; they form the
1754                  * bi-directional USB endpoint 0.
1755                  *
1756                  * For those two physical endpoints, we don't allocate a TRB
1757                  * pool nor do we add them the endpoints list. Due to that, we
1758                  * shouldn't do these two operations otherwise we would end up
1759                  * with all sorts of bugs when removing dwc3.ko.
1760                  */
1761                 if (epnum != 0 && epnum != 1) {
1762                         dwc3_free_trb_pool(dep);
1763                         list_del(&dep->endpoint.ep_list);
1764                 }
1765
1766                 kfree(dep);
1767         }
1768 }
1769
1770 /* -------------------------------------------------------------------------- */
1771
1772 static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
1773                 struct dwc3_request *req, struct dwc3_trb *trb,
1774                 const struct dwc3_event_depevt *event, int status)
1775 {
1776         unsigned int            count;
1777         unsigned int            s_pkt = 0;
1778         unsigned int            trb_status;
1779
1780         if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1781                 /*
1782                  * We continue despite the error. There is not much we
1783                  * can do. If we don't clean it up we loop forever. If
1784                  * we skip the TRB then it gets overwritten after a
1785                  * while since we use them in a ring buffer. A BUG()
1786                  * would help. Lets hope that if this occurs, someone
1787                  * fixes the root cause instead of looking away :)
1788                  */
1789                 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1790                                 dep->name, trb);
1791         count = trb->size & DWC3_TRB_SIZE_MASK;
1792
1793         if (dep->direction) {
1794                 if (count) {
1795                         trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1796                         if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
1797                                 dev_dbg(dwc->dev, "incomplete IN transfer %s\n",
1798                                                 dep->name);
1799                                 /*
1800                                  * If missed isoc occurred and there is
1801                                  * no request queued then issue END
1802                                  * TRANSFER, so that core generates
1803                                  * next xfernotready and we will issue
1804                                  * a fresh START TRANSFER.
1805                                  * If there are still queued request
1806                                  * then wait, do not issue either END
1807                                  * or UPDATE TRANSFER, just attach next
1808                                  * request in request_list during
1809                                  * giveback.If any future queued request
1810                                  * is successfully transferred then we
1811                                  * will issue UPDATE TRANSFER for all
1812                                  * request in the request_list.
1813                                  */
1814                                 dep->flags |= DWC3_EP_MISSED_ISOC;
1815                         } else {
1816                                 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1817                                                 dep->name);
1818                                 status = -ECONNRESET;
1819                         }
1820                 } else {
1821                         dep->flags &= ~DWC3_EP_MISSED_ISOC;
1822                 }
1823         } else {
1824                 if (count && (event->status & DEPEVT_STATUS_SHORT))
1825                         s_pkt = 1;
1826         }
1827
1828         /*
1829          * We assume here we will always receive the entire data block
1830          * which we should receive. Meaning, if we program RX to
1831          * receive 4K but we receive only 2K, we assume that's all we
1832          * should receive and we simply bounce the request back to the
1833          * gadget driver for further processing.
1834          */
1835         req->request.actual += req->request.length - count;
1836         if (s_pkt)
1837                 return 1;
1838         if ((event->status & DEPEVT_STATUS_LST) &&
1839                         (trb->ctrl & (DWC3_TRB_CTRL_LST |
1840                                 DWC3_TRB_CTRL_HWO)))
1841                 return 1;
1842         if ((event->status & DEPEVT_STATUS_IOC) &&
1843                         (trb->ctrl & DWC3_TRB_CTRL_IOC))
1844                 return 1;
1845         return 0;
1846 }
1847
1848 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1849                 const struct dwc3_event_depevt *event, int status)
1850 {
1851         struct dwc3_request     *req;
1852         struct dwc3_trb         *trb;
1853         unsigned int            slot;
1854         unsigned int            i;
1855         int                     ret;
1856
1857         do {
1858                 req = next_request(&dep->req_queued);
1859                 if (!req) {
1860                         WARN_ON_ONCE(1);
1861                         return 1;
1862                 }
1863                 i = 0;
1864                 do {
1865                         slot = req->start_slot + i;
1866                         if ((slot == DWC3_TRB_NUM - 1) &&
1867                                 usb_endpoint_xfer_isoc(dep->endpoint.desc))
1868                                 slot++;
1869                         slot %= DWC3_TRB_NUM;
1870                         trb = &dep->trb_pool[slot];
1871
1872                         ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
1873                                         event, status);
1874                         if (ret)
1875                                 break;
1876                 }while (++i < req->request.num_mapped_sgs);
1877
1878                 dwc3_gadget_giveback(dep, req, status);
1879
1880                 if (ret)
1881                         break;
1882         } while (1);
1883
1884         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1885                         list_empty(&dep->req_queued)) {
1886                 if (list_empty(&dep->request_list)) {
1887                         /*
1888                          * If there is no entry in request list then do
1889                          * not issue END TRANSFER now. Just set PENDING
1890                          * flag, so that END TRANSFER is issued when an
1891                          * entry is added into request list.
1892                          */
1893                         dep->flags = DWC3_EP_PENDING_REQUEST;
1894                 } else {
1895                         dwc3_stop_active_transfer(dwc, dep->number, true);
1896                         dep->flags = DWC3_EP_ENABLED;
1897                 }
1898                 return 1;
1899         }
1900
1901         return 1;
1902 }
1903
1904 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
1905                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event,
1906                 int start_new)
1907 {
1908         unsigned                status = 0;
1909         int                     clean_busy;
1910
1911         if (event->status & DEPEVT_STATUS_BUSERR)
1912                 status = -ECONNRESET;
1913
1914         clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
1915         if (clean_busy)
1916                 dep->flags &= ~DWC3_EP_BUSY;
1917
1918         /*
1919          * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
1920          * See dwc3_gadget_linksts_change_interrupt() for 1st half.
1921          */
1922         if (dwc->revision < DWC3_REVISION_183A) {
1923                 u32             reg;
1924                 int             i;
1925
1926                 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
1927                         dep = dwc->eps[i];
1928
1929                         if (!(dep->flags & DWC3_EP_ENABLED))
1930                                 continue;
1931
1932                         if (!list_empty(&dep->req_queued))
1933                                 return;
1934                 }
1935
1936                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1937                 reg |= dwc->u1u2;
1938                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1939
1940                 dwc->u1u2 = 0;
1941         }
1942 }
1943
1944 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
1945                 const struct dwc3_event_depevt *event)
1946 {
1947         struct dwc3_ep          *dep;
1948         u8                      epnum = event->endpoint_number;
1949
1950         dep = dwc->eps[epnum];
1951
1952         if (!(dep->flags & DWC3_EP_ENABLED))
1953                 return;
1954
1955         dev_vdbg(dwc->dev, "%s: %s\n", dep->name,
1956                         dwc3_ep_event_string(event->endpoint_event));
1957
1958         if (epnum == 0 || epnum == 1) {
1959                 dwc3_ep0_interrupt(dwc, event);
1960                 return;
1961         }
1962
1963         switch (event->endpoint_event) {
1964         case DWC3_DEPEVT_XFERCOMPLETE:
1965                 dep->resource_index = 0;
1966
1967                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1968                         dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n",
1969                                         dep->name);
1970                         return;
1971                 }
1972
1973                 dwc3_endpoint_transfer_complete(dwc, dep, event, 1);
1974                 break;
1975         case DWC3_DEPEVT_XFERINPROGRESS:
1976                 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1977                         dev_dbg(dwc->dev, "%s is not an Isochronous endpoint\n",
1978                                         dep->name);
1979                         return;
1980                 }
1981
1982                 dwc3_endpoint_transfer_complete(dwc, dep, event, 0);
1983                 break;
1984         case DWC3_DEPEVT_XFERNOTREADY:
1985                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1986                         dwc3_gadget_start_isoc(dwc, dep, event);
1987                 } else {
1988                         int ret;
1989
1990                         dev_vdbg(dwc->dev, "%s: reason %s\n",
1991                                         dep->name, event->status &
1992                                         DEPEVT_STATUS_TRANSFER_ACTIVE
1993                                         ? "Transfer Active"
1994                                         : "Transfer Not Active");
1995
1996                         ret = __dwc3_gadget_kick_transfer(dep, 0, 1);
1997                         if (!ret || ret == -EBUSY)
1998                                 return;
1999
2000                         dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
2001                                         dep->name);
2002                 }
2003
2004                 break;
2005         case DWC3_DEPEVT_STREAMEVT:
2006                 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
2007                         dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
2008                                         dep->name);
2009                         return;
2010                 }
2011
2012                 switch (event->status) {
2013                 case DEPEVT_STREAMEVT_FOUND:
2014                         dev_vdbg(dwc->dev, "Stream %d found and started\n",
2015                                         event->parameters);
2016
2017                         break;
2018                 case DEPEVT_STREAMEVT_NOTFOUND:
2019                         /* FALLTHROUGH */
2020                 default:
2021                         dev_dbg(dwc->dev, "Couldn't find suitable stream\n");
2022                 }
2023                 break;
2024         case DWC3_DEPEVT_RXTXFIFOEVT:
2025                 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name);
2026                 break;
2027         case DWC3_DEPEVT_EPCMDCMPLT:
2028                 dev_vdbg(dwc->dev, "Endpoint Command Complete\n");
2029                 break;
2030         }
2031 }
2032
2033 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2034 {
2035         if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2036                 spin_unlock(&dwc->lock);
2037                 dwc->gadget_driver->disconnect(&dwc->gadget);
2038                 spin_lock(&dwc->lock);
2039         }
2040 }
2041
2042 static void dwc3_suspend_gadget(struct dwc3 *dwc)
2043 {
2044         if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
2045                 spin_unlock(&dwc->lock);
2046                 dwc->gadget_driver->suspend(&dwc->gadget);
2047                 spin_lock(&dwc->lock);
2048         }
2049 }
2050
2051 static void dwc3_resume_gadget(struct dwc3 *dwc)
2052 {
2053         if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2054                 spin_unlock(&dwc->lock);
2055                 dwc->gadget_driver->resume(&dwc->gadget);
2056                 spin_lock(&dwc->lock);
2057         }
2058 }
2059
2060 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
2061 {
2062         struct dwc3_ep *dep;
2063         struct dwc3_gadget_ep_cmd_params params;
2064         u32 cmd;
2065         int ret;
2066
2067         dep = dwc->eps[epnum];
2068
2069         if (!dep->resource_index)
2070                 return;
2071
2072         /*
2073          * NOTICE: We are violating what the Databook says about the
2074          * EndTransfer command. Ideally we would _always_ wait for the
2075          * EndTransfer Command Completion IRQ, but that's causing too
2076          * much trouble synchronizing between us and gadget driver.
2077          *
2078          * We have discussed this with the IP Provider and it was
2079          * suggested to giveback all requests here, but give HW some
2080          * extra time to synchronize with the interconnect. We're using
2081          * an arbitraty 100us delay for that.
2082          *
2083          * Note also that a similar handling was tested by Synopsys
2084          * (thanks a lot Paul) and nothing bad has come out of it.
2085          * In short, what we're doing is:
2086          *
2087          * - Issue EndTransfer WITH CMDIOC bit set
2088          * - Wait 100us
2089          */
2090
2091         cmd = DWC3_DEPCMD_ENDTRANSFER;
2092         cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2093         cmd |= DWC3_DEPCMD_CMDIOC;
2094         cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2095         memset(&params, 0, sizeof(params));
2096         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
2097         WARN_ON_ONCE(ret);
2098         dep->resource_index = 0;
2099         dep->flags &= ~DWC3_EP_BUSY;
2100         udelay(100);
2101 }
2102
2103 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2104 {
2105         u32 epnum;
2106
2107         for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2108                 struct dwc3_ep *dep;
2109
2110                 dep = dwc->eps[epnum];
2111                 if (!dep)
2112                         continue;
2113
2114                 if (!(dep->flags & DWC3_EP_ENABLED))
2115                         continue;
2116
2117                 dwc3_remove_requests(dwc, dep);
2118         }
2119 }
2120
2121 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2122 {
2123         u32 epnum;
2124
2125         for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2126                 struct dwc3_ep *dep;
2127                 struct dwc3_gadget_ep_cmd_params params;
2128                 int ret;
2129
2130                 dep = dwc->eps[epnum];
2131                 if (!dep)
2132                         continue;
2133
2134                 if (!(dep->flags & DWC3_EP_STALL))
2135                         continue;
2136
2137                 dep->flags &= ~DWC3_EP_STALL;
2138
2139                 memset(&params, 0, sizeof(params));
2140                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
2141                                 DWC3_DEPCMD_CLEARSTALL, &params);
2142                 WARN_ON_ONCE(ret);
2143         }
2144 }
2145
2146 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2147 {
2148         int                     reg;
2149
2150         dev_vdbg(dwc->dev, "%s\n", __func__);
2151
2152         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2153         reg &= ~DWC3_DCTL_INITU1ENA;
2154         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2155
2156         reg &= ~DWC3_DCTL_INITU2ENA;
2157         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2158
2159         dwc3_disconnect_gadget(dwc);
2160         dwc->start_config_issued = false;
2161
2162         dwc->gadget.speed = USB_SPEED_UNKNOWN;
2163         dwc->setup_packet_pending = false;
2164 }
2165
2166 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2167 {
2168         u32                     reg;
2169
2170         dev_vdbg(dwc->dev, "%s\n", __func__);
2171
2172         /*
2173          * WORKAROUND: DWC3 revisions <1.88a have an issue which
2174          * would cause a missing Disconnect Event if there's a
2175          * pending Setup Packet in the FIFO.
2176          *
2177          * There's no suggested workaround on the official Bug
2178          * report, which states that "unless the driver/application
2179          * is doing any special handling of a disconnect event,
2180          * there is no functional issue".
2181          *
2182          * Unfortunately, it turns out that we _do_ some special
2183          * handling of a disconnect event, namely complete all
2184          * pending transfers, notify gadget driver of the
2185          * disconnection, and so on.
2186          *
2187          * Our suggested workaround is to follow the Disconnect
2188          * Event steps here, instead, based on a setup_packet_pending
2189          * flag. Such flag gets set whenever we have a XferNotReady
2190          * event on EP0 and gets cleared on XferComplete for the
2191          * same endpoint.
2192          *
2193          * Refers to:
2194          *
2195          * STAR#9000466709: RTL: Device : Disconnect event not
2196          * generated if setup packet pending in FIFO
2197          */
2198         if (dwc->revision < DWC3_REVISION_188A) {
2199                 if (dwc->setup_packet_pending)
2200                         dwc3_gadget_disconnect_interrupt(dwc);
2201         }
2202
2203         /* after reset -> Default State */
2204         usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT);
2205
2206         if (dwc->gadget.speed != USB_SPEED_UNKNOWN)
2207                 dwc3_disconnect_gadget(dwc);
2208
2209         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2210         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2211         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2212         dwc->test_mode = false;
2213
2214         dwc3_stop_active_transfers(dwc);
2215         dwc3_clear_stall_all_ep(dwc);
2216         dwc->start_config_issued = false;
2217
2218         /* Reset device address to zero */
2219         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2220         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2221         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2222 }
2223
2224 static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2225 {
2226         u32 reg;
2227         u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2228
2229         /*
2230          * We change the clock only at SS but I dunno why I would want to do
2231          * this. Maybe it becomes part of the power saving plan.
2232          */
2233
2234         if (speed != DWC3_DSTS_SUPERSPEED)
2235                 return;
2236
2237         /*
2238          * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2239          * each time on Connect Done.
2240          */
2241         if (!usb30_clock)
2242                 return;
2243
2244         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2245         reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2246         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2247 }
2248
2249 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2250 {
2251         struct dwc3_ep          *dep;
2252         int                     ret;
2253         u32                     reg;
2254         u8                      speed;
2255
2256         dev_vdbg(dwc->dev, "%s\n", __func__);
2257
2258         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2259         speed = reg & DWC3_DSTS_CONNECTSPD;
2260         dwc->speed = speed;
2261
2262         dwc3_update_ram_clk_sel(dwc, speed);
2263
2264         switch (speed) {
2265         case DWC3_DCFG_SUPERSPEED:
2266                 /*
2267                  * WORKAROUND: DWC3 revisions <1.90a have an issue which
2268                  * would cause a missing USB3 Reset event.
2269                  *
2270                  * In such situations, we should force a USB3 Reset
2271                  * event by calling our dwc3_gadget_reset_interrupt()
2272                  * routine.
2273                  *
2274                  * Refers to:
2275                  *
2276                  * STAR#9000483510: RTL: SS : USB3 reset event may
2277                  * not be generated always when the link enters poll
2278                  */
2279                 if (dwc->revision < DWC3_REVISION_190A)
2280                         dwc3_gadget_reset_interrupt(dwc);
2281
2282                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2283                 dwc->gadget.ep0->maxpacket = 512;
2284                 dwc->gadget.speed = USB_SPEED_SUPER;
2285                 break;
2286         case DWC3_DCFG_HIGHSPEED:
2287                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2288                 dwc->gadget.ep0->maxpacket = 64;
2289                 dwc->gadget.speed = USB_SPEED_HIGH;
2290                 break;
2291         case DWC3_DCFG_FULLSPEED2:
2292         case DWC3_DCFG_FULLSPEED1:
2293                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2294                 dwc->gadget.ep0->maxpacket = 64;
2295                 dwc->gadget.speed = USB_SPEED_FULL;
2296                 break;
2297         case DWC3_DCFG_LOWSPEED:
2298                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2299                 dwc->gadget.ep0->maxpacket = 8;
2300                 dwc->gadget.speed = USB_SPEED_LOW;
2301                 break;
2302         }
2303
2304         /* Enable USB2 LPM Capability */
2305
2306         if ((dwc->revision > DWC3_REVISION_194A)
2307                         && (speed != DWC3_DCFG_SUPERSPEED)) {
2308                 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2309                 reg |= DWC3_DCFG_LPM_CAP;
2310                 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2311
2312                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2313                 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2314
2315                 /*
2316                  * TODO: This should be configurable. For now using
2317                  * maximum allowed HIRD threshold value of 0b1100
2318                  */
2319                 reg |= DWC3_DCTL_HIRD_THRES(12);
2320
2321                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2322         } else {
2323                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2324                 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2325                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2326         }
2327
2328         dep = dwc->eps[0];
2329         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2330                         false);
2331         if (ret) {
2332                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2333                 return;
2334         }
2335
2336         dep = dwc->eps[1];
2337         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2338                         false);
2339         if (ret) {
2340                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2341                 return;
2342         }
2343
2344         /*
2345          * Configure PHY via GUSB3PIPECTLn if required.
2346          *
2347          * Update GTXFIFOSIZn
2348          *
2349          * In both cases reset values should be sufficient.
2350          */
2351 }
2352
2353 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2354 {
2355         dev_vdbg(dwc->dev, "%s\n", __func__);
2356
2357         /*
2358          * TODO take core out of low power mode when that's
2359          * implemented.
2360          */
2361
2362         dwc->gadget_driver->resume(&dwc->gadget);
2363 }
2364
2365 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2366                 unsigned int evtinfo)
2367 {
2368         enum dwc3_link_state    next = evtinfo & DWC3_LINK_STATE_MASK;
2369         unsigned int            pwropt;
2370
2371         /*
2372          * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2373          * Hibernation mode enabled which would show up when device detects
2374          * host-initiated U3 exit.
2375          *
2376          * In that case, device will generate a Link State Change Interrupt
2377          * from U3 to RESUME which is only necessary if Hibernation is
2378          * configured in.
2379          *
2380          * There are no functional changes due to such spurious event and we
2381          * just need to ignore it.
2382          *
2383          * Refers to:
2384          *
2385          * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2386          * operational mode
2387          */
2388         pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2389         if ((dwc->revision < DWC3_REVISION_250A) &&
2390                         (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2391                 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2392                                 (next == DWC3_LINK_STATE_RESUME)) {
2393                         dev_vdbg(dwc->dev, "ignoring transition U3 -> Resume\n");
2394                         return;
2395                 }
2396         }
2397
2398         /*
2399          * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2400          * on the link partner, the USB session might do multiple entry/exit
2401          * of low power states before a transfer takes place.
2402          *
2403          * Due to this problem, we might experience lower throughput. The
2404          * suggested workaround is to disable DCTL[12:9] bits if we're
2405          * transitioning from U1/U2 to U0 and enable those bits again
2406          * after a transfer completes and there are no pending transfers
2407          * on any of the enabled endpoints.
2408          *
2409          * This is the first half of that workaround.
2410          *
2411          * Refers to:
2412          *
2413          * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2414          * core send LGO_Ux entering U0
2415          */
2416         if (dwc->revision < DWC3_REVISION_183A) {
2417                 if (next == DWC3_LINK_STATE_U0) {
2418                         u32     u1u2;
2419                         u32     reg;
2420
2421                         switch (dwc->link_state) {
2422                         case DWC3_LINK_STATE_U1:
2423                         case DWC3_LINK_STATE_U2:
2424                                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2425                                 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2426                                                 | DWC3_DCTL_ACCEPTU2ENA
2427                                                 | DWC3_DCTL_INITU1ENA
2428                                                 | DWC3_DCTL_ACCEPTU1ENA);
2429
2430                                 if (!dwc->u1u2)
2431                                         dwc->u1u2 = reg & u1u2;
2432
2433                                 reg &= ~u1u2;
2434
2435                                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2436                                 break;
2437                         default:
2438                                 /* do nothing */
2439                                 break;
2440                         }
2441                 }
2442         }
2443
2444         dwc->link_state = next;
2445
2446         switch (next) {
2447         case DWC3_LINK_STATE_U1:
2448                 if (dwc->speed == USB_SPEED_SUPER)
2449                         dwc3_suspend_gadget(dwc);
2450                 break;
2451         case DWC3_LINK_STATE_U2:
2452         case DWC3_LINK_STATE_U3:
2453                 dwc3_suspend_gadget(dwc);
2454                 break;
2455         case DWC3_LINK_STATE_RESUME:
2456                 dwc3_resume_gadget(dwc);
2457                 break;
2458         default:
2459                 /* do nothing */
2460                 break;
2461         }
2462
2463         dev_vdbg(dwc->dev, "%s link %d\n", __func__, dwc->link_state);
2464 }
2465
2466 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2467                 unsigned int evtinfo)
2468 {
2469         unsigned int is_ss = evtinfo & BIT(4);
2470
2471         /**
2472          * WORKAROUND: DWC3 revison 2.20a with hibernation support
2473          * have a known issue which can cause USB CV TD.9.23 to fail
2474          * randomly.
2475          *
2476          * Because of this issue, core could generate bogus hibernation
2477          * events which SW needs to ignore.
2478          *
2479          * Refers to:
2480          *
2481          * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2482          * Device Fallback from SuperSpeed
2483          */
2484         if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2485                 return;
2486
2487         /* enter hibernation here */
2488 }
2489
2490 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2491                 const struct dwc3_event_devt *event)
2492 {
2493         switch (event->type) {
2494         case DWC3_DEVICE_EVENT_DISCONNECT:
2495                 dwc3_gadget_disconnect_interrupt(dwc);
2496                 break;
2497         case DWC3_DEVICE_EVENT_RESET:
2498                 dwc3_gadget_reset_interrupt(dwc);
2499                 break;
2500         case DWC3_DEVICE_EVENT_CONNECT_DONE:
2501                 dwc3_gadget_conndone_interrupt(dwc);
2502                 break;
2503         case DWC3_DEVICE_EVENT_WAKEUP:
2504                 dwc3_gadget_wakeup_interrupt(dwc);
2505                 break;
2506         case DWC3_DEVICE_EVENT_HIBER_REQ:
2507                 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
2508                                         "unexpected hibernation event\n"))
2509                         break;
2510
2511                 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2512                 break;
2513         case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2514                 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2515                 break;
2516         case DWC3_DEVICE_EVENT_EOPF:
2517                 dev_vdbg(dwc->dev, "End of Periodic Frame\n");
2518                 break;
2519         case DWC3_DEVICE_EVENT_SOF:
2520                 dev_vdbg(dwc->dev, "Start of Periodic Frame\n");
2521                 break;
2522         case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2523                 dev_vdbg(dwc->dev, "Erratic Error\n");
2524                 break;
2525         case DWC3_DEVICE_EVENT_CMD_CMPL:
2526                 dev_vdbg(dwc->dev, "Command Complete\n");
2527                 break;
2528         case DWC3_DEVICE_EVENT_OVERFLOW:
2529                 dev_vdbg(dwc->dev, "Overflow\n");
2530                 break;
2531         default:
2532                 dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2533         }
2534 }
2535
2536 static void dwc3_process_event_entry(struct dwc3 *dwc,
2537                 const union dwc3_event *event)
2538 {
2539         /* Endpoint IRQ, handle it and return early */
2540         if (event->type.is_devspec == 0) {
2541                 /* depevt */
2542                 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2543         }
2544
2545         switch (event->type.type) {
2546         case DWC3_EVENT_TYPE_DEV:
2547                 dwc3_gadget_interrupt(dwc, &event->devt);
2548                 break;
2549         /* REVISIT what to do with Carkit and I2C events ? */
2550         default:
2551                 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2552         }
2553 }
2554
2555 static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
2556 {
2557         struct dwc3_event_buffer *evt;
2558         irqreturn_t ret = IRQ_NONE;
2559         int left;
2560         u32 reg;
2561
2562         evt = dwc->ev_buffs[buf];
2563         left = evt->count;
2564
2565         if (!(evt->flags & DWC3_EVENT_PENDING))
2566                 return IRQ_NONE;
2567
2568         while (left > 0) {
2569                 union dwc3_event event;
2570
2571                 event.raw = *(u32 *) (evt->buf + evt->lpos);
2572
2573                 dwc3_process_event_entry(dwc, &event);
2574
2575                 /*
2576                  * FIXME we wrap around correctly to the next entry as
2577                  * almost all entries are 4 bytes in size. There is one
2578                  * entry which has 12 bytes which is a regular entry
2579                  * followed by 8 bytes data. ATM I don't know how
2580                  * things are organized if we get next to the a
2581                  * boundary so I worry about that once we try to handle
2582                  * that.
2583                  */
2584                 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2585                 left -= 4;
2586
2587                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4);
2588         }
2589
2590         evt->count = 0;
2591         evt->flags &= ~DWC3_EVENT_PENDING;
2592         ret = IRQ_HANDLED;
2593
2594         /* Unmask interrupt */
2595         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2596         reg &= ~DWC3_GEVNTSIZ_INTMASK;
2597         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
2598
2599         return ret;
2600 }
2601
2602 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc)
2603 {
2604         struct dwc3 *dwc = _dwc;
2605         unsigned long flags;
2606         irqreturn_t ret = IRQ_NONE;
2607         int i;
2608
2609         spin_lock_irqsave(&dwc->lock, flags);
2610
2611         for (i = 0; i < dwc->num_event_buffers; i++)
2612                 ret |= dwc3_process_event_buf(dwc, i);
2613
2614         spin_unlock_irqrestore(&dwc->lock, flags);
2615
2616         return ret;
2617 }
2618
2619 static irqreturn_t dwc3_check_event_buf(struct dwc3 *dwc, u32 buf)
2620 {
2621         struct dwc3_event_buffer *evt;
2622         u32 count;
2623         u32 reg;
2624
2625         evt = dwc->ev_buffs[buf];
2626
2627         count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
2628         count &= DWC3_GEVNTCOUNT_MASK;
2629         if (!count)
2630                 return IRQ_NONE;
2631
2632         evt->count = count;
2633         evt->flags |= DWC3_EVENT_PENDING;
2634
2635         /* Mask interrupt */
2636         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2637         reg |= DWC3_GEVNTSIZ_INTMASK;
2638         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
2639
2640         return IRQ_WAKE_THREAD;
2641 }
2642
2643 static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
2644 {
2645         struct dwc3                     *dwc = _dwc;
2646         int                             i;
2647         irqreturn_t                     ret = IRQ_NONE;
2648
2649         spin_lock(&dwc->lock);
2650
2651         for (i = 0; i < dwc->num_event_buffers; i++) {
2652                 irqreturn_t status;
2653
2654                 status = dwc3_check_event_buf(dwc, i);
2655                 if (status == IRQ_WAKE_THREAD)
2656                         ret = status;
2657         }
2658
2659         spin_unlock(&dwc->lock);
2660
2661         return ret;
2662 }
2663
2664 /**
2665  * dwc3_gadget_init - Initializes gadget related registers
2666  * @dwc: pointer to our controller context structure
2667  *
2668  * Returns 0 on success otherwise negative errno.
2669  */
2670 int dwc3_gadget_init(struct dwc3 *dwc)
2671 {
2672         int                                     ret;
2673
2674         dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2675                         &dwc->ctrl_req_addr, GFP_KERNEL);
2676         if (!dwc->ctrl_req) {
2677                 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2678                 ret = -ENOMEM;
2679                 goto err0;
2680         }
2681
2682         dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2683                         &dwc->ep0_trb_addr, GFP_KERNEL);
2684         if (!dwc->ep0_trb) {
2685                 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2686                 ret = -ENOMEM;
2687                 goto err1;
2688         }
2689
2690         dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
2691         if (!dwc->setup_buf) {
2692                 dev_err(dwc->dev, "failed to allocate setup buffer\n");
2693                 ret = -ENOMEM;
2694                 goto err2;
2695         }
2696
2697         dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
2698                         DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
2699                         GFP_KERNEL);
2700         if (!dwc->ep0_bounce) {
2701                 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2702                 ret = -ENOMEM;
2703                 goto err3;
2704         }
2705
2706         dwc->gadget.ops                 = &dwc3_gadget_ops;
2707         dwc->gadget.max_speed           = USB_SPEED_SUPER;
2708         dwc->gadget.speed               = USB_SPEED_UNKNOWN;
2709         dwc->gadget.sg_supported        = true;
2710         dwc->gadget.name                = "dwc3-gadget";
2711
2712         /*
2713          * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
2714          * on ep out.
2715          */
2716         dwc->gadget.quirk_ep_out_aligned_size = true;
2717
2718         /*
2719          * REVISIT: Here we should clear all pending IRQs to be
2720          * sure we're starting from a well known location.
2721          */
2722
2723         ret = dwc3_gadget_init_endpoints(dwc);
2724         if (ret)
2725                 goto err4;
2726
2727         ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2728         if (ret) {
2729                 dev_err(dwc->dev, "failed to register udc\n");
2730                 goto err4;
2731         }
2732
2733         return 0;
2734
2735 err4:
2736         dwc3_gadget_free_endpoints(dwc);
2737         dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2738                         dwc->ep0_bounce, dwc->ep0_bounce_addr);
2739
2740 err3:
2741         kfree(dwc->setup_buf);
2742
2743 err2:
2744         dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2745                         dwc->ep0_trb, dwc->ep0_trb_addr);
2746
2747 err1:
2748         dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2749                         dwc->ctrl_req, dwc->ctrl_req_addr);
2750
2751 err0:
2752         return ret;
2753 }
2754
2755 /* -------------------------------------------------------------------------- */
2756
2757 void dwc3_gadget_exit(struct dwc3 *dwc)
2758 {
2759         usb_del_gadget_udc(&dwc->gadget);
2760
2761         dwc3_gadget_free_endpoints(dwc);
2762
2763         dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2764                         dwc->ep0_bounce, dwc->ep0_bounce_addr);
2765
2766         kfree(dwc->setup_buf);
2767
2768         dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2769                         dwc->ep0_trb, dwc->ep0_trb_addr);
2770
2771         dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2772                         dwc->ctrl_req, dwc->ctrl_req_addr);
2773 }
2774
2775 int dwc3_gadget_prepare(struct dwc3 *dwc)
2776 {
2777         if (dwc->pullups_connected) {
2778                 dwc3_gadget_disable_irq(dwc);
2779                 dwc3_gadget_run_stop(dwc, true, true);
2780         }
2781
2782         return 0;
2783 }
2784
2785 void dwc3_gadget_complete(struct dwc3 *dwc)
2786 {
2787         if (dwc->pullups_connected) {
2788                 dwc3_gadget_enable_irq(dwc);
2789                 dwc3_gadget_run_stop(dwc, true, false);
2790         }
2791 }
2792
2793 int dwc3_gadget_suspend(struct dwc3 *dwc)
2794 {
2795         __dwc3_gadget_ep_disable(dwc->eps[0]);
2796         __dwc3_gadget_ep_disable(dwc->eps[1]);
2797
2798         dwc->dcfg = dwc3_readl(dwc->regs, DWC3_DCFG);
2799
2800         return 0;
2801 }
2802
2803 int dwc3_gadget_resume(struct dwc3 *dwc)
2804 {
2805         struct dwc3_ep          *dep;
2806         int                     ret;
2807
2808         /* Start with SuperSpeed Default */
2809         dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2810
2811         dep = dwc->eps[0];
2812         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
2813                         false);
2814         if (ret)
2815                 goto err0;
2816
2817         dep = dwc->eps[1];
2818         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
2819                         false);
2820         if (ret)
2821                 goto err1;
2822
2823         /* begin to receive SETUP packets */
2824         dwc->ep0state = EP0_SETUP_PHASE;
2825         dwc3_ep0_out_start(dwc);
2826
2827         dwc3_writel(dwc->regs, DWC3_DCFG, dwc->dcfg);
2828
2829         return 0;
2830
2831 err1:
2832         __dwc3_gadget_ep_disable(dwc->eps[0]);
2833
2834 err0:
2835         return ret;
2836 }