2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/kernel.h>
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/spinlock.h>
23 #include <linux/platform_device.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/interrupt.h>
27 #include <linux/list.h>
28 #include <linux/dma-mapping.h>
30 #include <linux/usb/ch9.h>
31 #include <linux/usb/gadget.h>
39 * dwc3_gadget_set_test_mode - enables usb2 test modes
40 * @dwc: pointer to our context structure
41 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
43 * Caller should take care of locking. This function will return 0 on
44 * success or -EINVAL if wrong Test Selector is passed.
46 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
50 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
51 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
65 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
71 * dwc3_gadget_get_link_state - gets current state of usb link
72 * @dwc: pointer to our context structure
74 * Caller should take care of locking. This function will
75 * return the link state on success (>= 0) or -ETIMEDOUT.
77 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
81 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
83 return DWC3_DSTS_USBLNKST(reg);
87 * dwc3_gadget_set_link_state - sets usb link to a particular state
88 * @dwc: pointer to our context structure
89 * @state: the state to put link into
91 * Caller should take care of locking. This function will
92 * return 0 on success or -ETIMEDOUT.
94 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
100 * Wait until device controller is ready. Only applies to 1.94a and
103 if (dwc->revision >= DWC3_REVISION_194A) {
105 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
106 if (reg & DWC3_DSTS_DCNRD)
116 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
117 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
119 /* set requested state */
120 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
121 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
124 * The following code is racy when called from dwc3_gadget_wakeup,
125 * and is not needed, at least on newer versions
127 if (dwc->revision >= DWC3_REVISION_194A)
130 /* wait for a change in DSTS */
133 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
135 if (DWC3_DSTS_USBLNKST(reg) == state)
145 * dwc3_ep_inc_trb - increment a trb index.
146 * @index: Pointer to the TRB index to increment.
148 * The index should never point to the link TRB. After incrementing,
149 * if it is point to the link TRB, wrap around to the beginning. The
150 * link TRB is always at the last TRB entry.
152 static void dwc3_ep_inc_trb(u8 *index)
155 if (*index == (DWC3_TRB_NUM - 1))
160 * dwc3_ep_inc_enq - increment endpoint's enqueue pointer
161 * @dep: The endpoint whose enqueue pointer we're incrementing
163 static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
165 dwc3_ep_inc_trb(&dep->trb_enqueue);
169 * dwc3_ep_inc_deq - increment endpoint's dequeue pointer
170 * @dep: The endpoint whose enqueue pointer we're incrementing
172 static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
174 dwc3_ep_inc_trb(&dep->trb_dequeue);
178 * dwc3_gadget_giveback - call struct usb_request's ->complete callback
179 * @dep: The endpoint to whom the request belongs to
180 * @req: The request we're giving back
181 * @status: completion code for the request
183 * Must be called with controller's lock held and interrupts disabled. This
184 * function will unmap @req and call its ->complete() callback to notify upper
185 * layers that it has completed.
187 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
190 struct dwc3 *dwc = dep->dwc;
192 req->started = false;
193 list_del(&req->list);
197 if (req->request.status == -EINPROGRESS)
198 req->request.status = status;
200 usb_gadget_unmap_request_by_dev(dwc->sysdev,
201 &req->request, req->direction);
203 trace_dwc3_gadget_giveback(req);
205 spin_unlock(&dwc->lock);
206 usb_gadget_giveback_request(&dep->endpoint, &req->request);
207 spin_lock(&dwc->lock);
210 pm_runtime_put(dwc->dev);
214 * dwc3_send_gadget_generic_command - issue a generic command for the controller
215 * @dwc: pointer to the controller context
216 * @cmd: the command to be issued
217 * @param: command parameter
219 * Caller should take care of locking. Issue @cmd with a given @param to @dwc
220 * and wait for its completion.
222 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
229 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
230 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
233 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
234 if (!(reg & DWC3_DGCMD_CMDACT)) {
235 status = DWC3_DGCMD_STATUS(reg);
247 trace_dwc3_gadget_generic_cmd(cmd, param, status);
252 static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
255 * dwc3_send_gadget_ep_cmd - issue an endpoint command
256 * @dep: the endpoint to which the command is going to be issued
257 * @cmd: the command to be issued
258 * @params: parameters to the command
260 * Caller should handle locking. This function will issue @cmd with given
261 * @params to @dep and wait for its completion.
263 int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
264 struct dwc3_gadget_ep_cmd_params *params)
266 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
267 struct dwc3 *dwc = dep->dwc;
276 * Synopsys Databook 2.60a states, on section 6.3.2.5.[1-8], that if
277 * we're issuing an endpoint command, we must check if
278 * GUSB2PHYCFG.SUSPHY bit is set. If it is, then we need to clear it.
280 * We will also set SUSPHY bit to what it was before returning as stated
281 * by the same section on Synopsys databook.
283 if (dwc->gadget.speed <= USB_SPEED_HIGH) {
284 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
285 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
287 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
288 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
292 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
295 needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 ||
296 dwc->link_state == DWC3_LINK_STATE_U2 ||
297 dwc->link_state == DWC3_LINK_STATE_U3);
299 if (unlikely(needs_wakeup)) {
300 ret = __dwc3_gadget_wakeup(dwc);
301 dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
306 dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
307 dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
308 dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
311 * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're
312 * not relying on XferNotReady, we can make use of a special "No
313 * Response Update Transfer" command where we should clear both CmdAct
316 * With this, we don't need to wait for command completion and can
317 * straight away issue further commands to the endpoint.
319 * NOTICE: We're making an assumption that control endpoints will never
320 * make use of Update Transfer command. This is a safe assumption
321 * because we can never have more than one request at a time with
322 * Control Endpoints. If anybody changes that assumption, this chunk
323 * needs to be updated accordingly.
325 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER &&
326 !usb_endpoint_xfer_isoc(desc))
327 cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT);
329 cmd |= DWC3_DEPCMD_CMDACT;
331 dwc3_writel(dep->regs, DWC3_DEPCMD, cmd);
333 reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
334 if (!(reg & DWC3_DEPCMD_CMDACT)) {
335 cmd_status = DWC3_DEPCMD_STATUS(reg);
337 switch (cmd_status) {
341 case DEPEVT_TRANSFER_NO_RESOURCE:
344 case DEPEVT_TRANSFER_BUS_EXPIRY:
346 * SW issues START TRANSFER command to
347 * isochronous ep with future frame interval. If
348 * future interval time has already passed when
349 * core receives the command, it will respond
350 * with an error status of 'Bus Expiry'.
352 * Instead of always returning -EINVAL, let's
353 * give a hint to the gadget driver that this is
354 * the case by returning -EAGAIN.
359 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
368 cmd_status = -ETIMEDOUT;
371 trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status);
374 switch (DWC3_DEPCMD_CMD(cmd)) {
375 case DWC3_DEPCMD_STARTTRANSFER:
376 dep->flags |= DWC3_EP_TRANSFER_STARTED;
378 case DWC3_DEPCMD_ENDTRANSFER:
379 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
387 if (unlikely(susphy)) {
388 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
389 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
390 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
396 static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
398 struct dwc3 *dwc = dep->dwc;
399 struct dwc3_gadget_ep_cmd_params params;
400 u32 cmd = DWC3_DEPCMD_CLEARSTALL;
403 * As of core revision 2.60a the recommended programming model
404 * is to set the ClearPendIN bit when issuing a Clear Stall EP
405 * command for IN endpoints. This is to prevent an issue where
406 * some (non-compliant) hosts may not send ACK TPs for pending
407 * IN transfers due to a mishandled error condition. Synopsys
410 if (dep->direction && (dwc->revision >= DWC3_REVISION_260A) &&
411 (dwc->gadget.speed >= USB_SPEED_SUPER))
412 cmd |= DWC3_DEPCMD_CLEARPENDIN;
414 memset(¶ms, 0, sizeof(params));
416 return dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
419 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
420 struct dwc3_trb *trb)
422 u32 offset = (char *) trb - (char *) dep->trb_pool;
424 return dep->trb_pool_dma + offset;
427 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
429 struct dwc3 *dwc = dep->dwc;
434 dep->trb_pool = dma_alloc_coherent(dwc->sysdev,
435 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
436 &dep->trb_pool_dma, GFP_KERNEL);
437 if (!dep->trb_pool) {
438 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
446 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
448 struct dwc3 *dwc = dep->dwc;
450 dma_free_coherent(dwc->sysdev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
451 dep->trb_pool, dep->trb_pool_dma);
453 dep->trb_pool = NULL;
454 dep->trb_pool_dma = 0;
457 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep);
460 * dwc3_gadget_start_config - configure ep resources
461 * @dwc: pointer to our controller context structure
462 * @dep: endpoint that is being enabled
464 * Issue a %DWC3_DEPCMD_DEPSTARTCFG command to @dep. After the command's
465 * completion, it will set Transfer Resource for all available endpoints.
467 * The assignment of transfer resources cannot perfectly follow the data book
468 * due to the fact that the controller driver does not have all knowledge of the
469 * configuration in advance. It is given this information piecemeal by the
470 * composite gadget framework after every SET_CONFIGURATION and
471 * SET_INTERFACE. Trying to follow the databook programming model in this
472 * scenario can cause errors. For two reasons:
474 * 1) The databook says to do %DWC3_DEPCMD_DEPSTARTCFG for every
475 * %USB_REQ_SET_CONFIGURATION and %USB_REQ_SET_INTERFACE (8.1.5). This is
476 * incorrect in the scenario of multiple interfaces.
478 * 2) The databook does not mention doing more %DWC3_DEPCMD_DEPXFERCFG for new
479 * endpoint on alt setting (8.1.6).
481 * The following simplified method is used instead:
483 * All hardware endpoints can be assigned a transfer resource and this setting
484 * will stay persistent until either a core reset or hibernation. So whenever we
485 * do a %DWC3_DEPCMD_DEPSTARTCFG(0) we can go ahead and do
486 * %DWC3_DEPCMD_DEPXFERCFG for every hardware endpoint as well. We are
487 * guaranteed that there are as many transfer resources as endpoints.
489 * This function is called for each endpoint when it is being enabled but is
490 * triggered only when called for EP0-out, which always happens first, and which
491 * should only happen in one of the above conditions.
493 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
495 struct dwc3_gadget_ep_cmd_params params;
503 memset(¶ms, 0x00, sizeof(params));
504 cmd = DWC3_DEPCMD_DEPSTARTCFG;
506 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
510 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
511 struct dwc3_ep *dep = dwc->eps[i];
516 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
524 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
525 bool modify, bool restore)
527 const struct usb_ss_ep_comp_descriptor *comp_desc;
528 const struct usb_endpoint_descriptor *desc;
529 struct dwc3_gadget_ep_cmd_params params;
531 if (dev_WARN_ONCE(dwc->dev, modify && restore,
532 "Can't modify and restore\n"))
535 comp_desc = dep->endpoint.comp_desc;
536 desc = dep->endpoint.desc;
538 memset(¶ms, 0x00, sizeof(params));
540 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
541 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
543 /* Burst size is only needed in SuperSpeed mode */
544 if (dwc->gadget.speed >= USB_SPEED_SUPER) {
545 u32 burst = dep->endpoint.maxburst;
546 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
550 params.param0 |= DWC3_DEPCFG_ACTION_MODIFY;
551 } else if (restore) {
552 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
553 params.param2 |= dep->saved_state;
555 params.param0 |= DWC3_DEPCFG_ACTION_INIT;
558 if (usb_endpoint_xfer_control(desc))
559 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN;
561 if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc))
562 params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN;
564 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
565 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
566 | DWC3_DEPCFG_STREAM_EVENT_EN;
567 dep->stream_capable = true;
570 if (!usb_endpoint_xfer_control(desc))
571 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
574 * We are doing 1:1 mapping for endpoints, meaning
575 * Physical Endpoints 2 maps to Logical Endpoint 2 and
576 * so on. We consider the direction bit as part of the physical
577 * endpoint number. So USB endpoint 0x81 is 0x03.
579 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
582 * We must use the lower 16 TX FIFOs even though
586 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
588 if (desc->bInterval) {
589 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
590 dep->interval = 1 << (desc->bInterval - 1);
593 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, ¶ms);
596 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
598 struct dwc3_gadget_ep_cmd_params params;
600 memset(¶ms, 0x00, sizeof(params));
602 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
604 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
609 * __dwc3_gadget_ep_enable - initializes a hw endpoint
610 * @dep: endpoint to be initialized
611 * @modify: if true, modify existing endpoint configuration
612 * @restore: if true, restore endpoint configuration from scratch buffer
614 * Caller should take care of locking. Execute all necessary commands to
615 * initialize a HW endpoint so it can be used by a gadget driver.
617 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
618 bool modify, bool restore)
620 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
621 struct dwc3 *dwc = dep->dwc;
626 if (!(dep->flags & DWC3_EP_ENABLED)) {
627 ret = dwc3_gadget_start_config(dwc, dep);
632 ret = dwc3_gadget_set_ep_config(dwc, dep, modify, restore);
636 if (!(dep->flags & DWC3_EP_ENABLED)) {
637 struct dwc3_trb *trb_st_hw;
638 struct dwc3_trb *trb_link;
640 dep->type = usb_endpoint_type(desc);
641 dep->flags |= DWC3_EP_ENABLED;
642 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
644 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
645 reg |= DWC3_DALEPENA_EP(dep->number);
646 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
648 init_waitqueue_head(&dep->wait_end_transfer);
650 if (usb_endpoint_xfer_control(desc))
653 /* Initialize the TRB ring */
654 dep->trb_dequeue = 0;
655 dep->trb_enqueue = 0;
656 memset(dep->trb_pool, 0,
657 sizeof(struct dwc3_trb) * DWC3_TRB_NUM);
659 /* Link TRB. The HWO bit is never reset */
660 trb_st_hw = &dep->trb_pool[0];
662 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
663 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
664 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
665 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
666 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
670 * Issue StartTransfer here with no-op TRB so we can always rely on No
671 * Response Update Transfer command.
673 if (usb_endpoint_xfer_bulk(desc)) {
674 struct dwc3_gadget_ep_cmd_params params;
675 struct dwc3_trb *trb;
679 memset(¶ms, 0, sizeof(params));
680 trb = &dep->trb_pool[0];
681 trb_dma = dwc3_trb_dma_offset(dep, trb);
683 params.param0 = upper_32_bits(trb_dma);
684 params.param1 = lower_32_bits(trb_dma);
686 cmd = DWC3_DEPCMD_STARTTRANSFER;
688 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
692 dep->flags |= DWC3_EP_BUSY;
694 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
695 WARN_ON_ONCE(!dep->resource_index);
700 trace_dwc3_gadget_ep_enable(dep);
705 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
706 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
708 struct dwc3_request *req;
710 dwc3_stop_active_transfer(dwc, dep->number, true);
712 /* - giveback all requests to gadget driver */
713 while (!list_empty(&dep->started_list)) {
714 req = next_request(&dep->started_list);
716 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
719 while (!list_empty(&dep->pending_list)) {
720 req = next_request(&dep->pending_list);
722 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
727 * __dwc3_gadget_ep_disable - disables a hw endpoint
728 * @dep: the endpoint to disable
730 * This function undoes what __dwc3_gadget_ep_enable did and also removes
731 * requests which are currently being processed by the hardware and those which
732 * are not yet scheduled.
734 * Caller should take care of locking.
736 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
738 struct dwc3 *dwc = dep->dwc;
741 trace_dwc3_gadget_ep_disable(dep);
743 dwc3_remove_requests(dwc, dep);
745 /* make sure HW endpoint isn't stalled */
746 if (dep->flags & DWC3_EP_STALL)
747 __dwc3_gadget_ep_set_halt(dep, 0, false);
749 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
750 reg &= ~DWC3_DALEPENA_EP(dep->number);
751 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
753 dep->stream_capable = false;
755 dep->flags &= DWC3_EP_END_TRANSFER_PENDING;
757 /* Clear out the ep descriptors for non-ep0 */
758 if (dep->number > 1) {
759 dep->endpoint.comp_desc = NULL;
760 dep->endpoint.desc = NULL;
766 /* -------------------------------------------------------------------------- */
768 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
769 const struct usb_endpoint_descriptor *desc)
774 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
779 /* -------------------------------------------------------------------------- */
781 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
782 const struct usb_endpoint_descriptor *desc)
789 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
790 pr_debug("dwc3: invalid parameters\n");
794 if (!desc->wMaxPacketSize) {
795 pr_debug("dwc3: missing wMaxPacketSize\n");
799 dep = to_dwc3_ep(ep);
802 if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
803 "%s is already enabled\n",
807 spin_lock_irqsave(&dwc->lock, flags);
808 ret = __dwc3_gadget_ep_enable(dep, false, false);
809 spin_unlock_irqrestore(&dwc->lock, flags);
814 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
822 pr_debug("dwc3: invalid parameters\n");
826 dep = to_dwc3_ep(ep);
829 if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
830 "%s is already disabled\n",
834 spin_lock_irqsave(&dwc->lock, flags);
835 ret = __dwc3_gadget_ep_disable(dep);
836 spin_unlock_irqrestore(&dwc->lock, flags);
841 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
844 struct dwc3_request *req;
845 struct dwc3_ep *dep = to_dwc3_ep(ep);
847 req = kzalloc(sizeof(*req), gfp_flags);
851 req->epnum = dep->number;
854 dep->allocated_requests++;
856 trace_dwc3_alloc_request(req);
858 return &req->request;
861 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
862 struct usb_request *request)
864 struct dwc3_request *req = to_dwc3_request(request);
865 struct dwc3_ep *dep = to_dwc3_ep(ep);
867 dep->allocated_requests--;
868 trace_dwc3_free_request(req);
872 static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep);
874 static void __dwc3_prepare_one_trb(struct dwc3_ep *dep, struct dwc3_trb *trb,
875 dma_addr_t dma, unsigned length, unsigned chain, unsigned node,
876 unsigned stream_id, unsigned short_not_ok, unsigned no_interrupt)
878 struct dwc3 *dwc = dep->dwc;
879 struct usb_gadget *gadget = &dwc->gadget;
880 enum usb_device_speed speed = gadget->speed;
882 dwc3_ep_inc_enq(dep);
884 trb->size = DWC3_TRB_SIZE_LENGTH(length);
885 trb->bpl = lower_32_bits(dma);
886 trb->bph = upper_32_bits(dma);
888 switch (usb_endpoint_type(dep->endpoint.desc)) {
889 case USB_ENDPOINT_XFER_CONTROL:
890 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
893 case USB_ENDPOINT_XFER_ISOC:
895 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
897 if (speed == USB_SPEED_HIGH) {
898 struct usb_ep *ep = &dep->endpoint;
899 trb->size |= DWC3_TRB_SIZE_PCM1(ep->mult - 1);
902 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
905 /* always enable Interrupt on Missed ISOC */
906 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
909 case USB_ENDPOINT_XFER_BULK:
910 case USB_ENDPOINT_XFER_INT:
911 trb->ctrl = DWC3_TRBCTL_NORMAL;
915 * This is only possible with faulty memory because we
916 * checked it already :)
918 dev_WARN(dwc->dev, "Unknown endpoint type %d\n",
919 usb_endpoint_type(dep->endpoint.desc));
922 /* always enable Continue on Short Packet */
923 if (usb_endpoint_dir_out(dep->endpoint.desc)) {
924 trb->ctrl |= DWC3_TRB_CTRL_CSP;
927 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
930 if ((!no_interrupt && !chain) ||
931 (dwc3_calc_trbs_left(dep) == 0))
932 trb->ctrl |= DWC3_TRB_CTRL_IOC;
935 trb->ctrl |= DWC3_TRB_CTRL_CHN;
937 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
938 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(stream_id);
940 trb->ctrl |= DWC3_TRB_CTRL_HWO;
942 trace_dwc3_prepare_trb(dep, trb);
946 * dwc3_prepare_one_trb - setup one TRB from one request
947 * @dep: endpoint for which this request is prepared
948 * @req: dwc3_request pointer
949 * @chain: should this TRB be chained to the next?
950 * @node: only for isochronous endpoints. First TRB needs different type.
952 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
953 struct dwc3_request *req, unsigned chain, unsigned node)
955 struct dwc3_trb *trb;
956 unsigned length = req->request.length;
957 unsigned stream_id = req->request.stream_id;
958 unsigned short_not_ok = req->request.short_not_ok;
959 unsigned no_interrupt = req->request.no_interrupt;
960 dma_addr_t dma = req->request.dma;
962 trb = &dep->trb_pool[dep->trb_enqueue];
965 dwc3_gadget_move_started_request(req);
967 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
968 dep->queued_requests++;
971 __dwc3_prepare_one_trb(dep, trb, dma, length, chain, node,
972 stream_id, short_not_ok, no_interrupt);
976 * dwc3_ep_prev_trb - returns the previous TRB in the ring
977 * @dep: The endpoint with the TRB ring
978 * @index: The index of the current TRB in the ring
980 * Returns the TRB prior to the one pointed to by the index. If the
981 * index is 0, we will wrap backwards, skip the link TRB, and return
982 * the one just before that.
984 static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
989 tmp = DWC3_TRB_NUM - 1;
991 return &dep->trb_pool[tmp - 1];
994 static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
996 struct dwc3_trb *tmp;
1000 * If enqueue & dequeue are equal than it is either full or empty.
1002 * One way to know for sure is if the TRB right before us has HWO bit
1003 * set or not. If it has, then we're definitely full and can't fit any
1004 * more transfers in our ring.
1006 if (dep->trb_enqueue == dep->trb_dequeue) {
1007 tmp = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
1008 if (tmp->ctrl & DWC3_TRB_CTRL_HWO)
1011 return DWC3_TRB_NUM - 1;
1014 trbs_left = dep->trb_dequeue - dep->trb_enqueue;
1015 trbs_left &= (DWC3_TRB_NUM - 1);
1017 if (dep->trb_dequeue < dep->trb_enqueue)
1023 static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep,
1024 struct dwc3_request *req)
1026 struct scatterlist *sg = req->sg;
1027 struct scatterlist *s;
1030 for_each_sg(sg, s, req->num_pending_sgs, i) {
1031 unsigned int length = req->request.length;
1032 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1033 unsigned int rem = length % maxp;
1034 unsigned chain = true;
1039 if (rem && usb_endpoint_dir_out(dep->endpoint.desc) && !chain) {
1040 struct dwc3 *dwc = dep->dwc;
1041 struct dwc3_trb *trb;
1043 req->unaligned = true;
1045 /* prepare normal TRB */
1046 dwc3_prepare_one_trb(dep, req, true, i);
1048 /* Now prepare one extra TRB to align transfer size */
1049 trb = &dep->trb_pool[dep->trb_enqueue];
1050 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr,
1051 maxp - rem, false, 0,
1052 req->request.stream_id,
1053 req->request.short_not_ok,
1054 req->request.no_interrupt);
1056 dwc3_prepare_one_trb(dep, req, chain, i);
1059 if (!dwc3_calc_trbs_left(dep))
1064 static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep,
1065 struct dwc3_request *req)
1067 unsigned int length = req->request.length;
1068 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1069 unsigned int rem = length % maxp;
1071 if (rem && usb_endpoint_dir_out(dep->endpoint.desc)) {
1072 struct dwc3 *dwc = dep->dwc;
1073 struct dwc3_trb *trb;
1075 req->unaligned = true;
1077 /* prepare normal TRB */
1078 dwc3_prepare_one_trb(dep, req, true, 0);
1080 /* Now prepare one extra TRB to align transfer size */
1081 trb = &dep->trb_pool[dep->trb_enqueue];
1082 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, maxp - rem,
1083 false, 0, req->request.stream_id,
1084 req->request.short_not_ok,
1085 req->request.no_interrupt);
1086 } else if (req->request.zero && req->request.length &&
1087 (IS_ALIGNED(req->request.length,dep->endpoint.maxpacket))) {
1088 struct dwc3 *dwc = dep->dwc;
1089 struct dwc3_trb *trb;
1093 /* prepare normal TRB */
1094 dwc3_prepare_one_trb(dep, req, true, 0);
1096 /* Now prepare one extra TRB to handle ZLP */
1097 trb = &dep->trb_pool[dep->trb_enqueue];
1098 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, 0,
1099 false, 0, req->request.stream_id,
1100 req->request.short_not_ok,
1101 req->request.no_interrupt);
1103 dwc3_prepare_one_trb(dep, req, false, 0);
1108 * dwc3_prepare_trbs - setup TRBs from requests
1109 * @dep: endpoint for which requests are being prepared
1111 * The function goes through the requests list and sets up TRBs for the
1112 * transfers. The function returns once there are no more TRBs available or
1113 * it runs out of requests.
1115 static void dwc3_prepare_trbs(struct dwc3_ep *dep)
1117 struct dwc3_request *req, *n;
1119 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
1121 if (!dwc3_calc_trbs_left(dep))
1125 * We can get in a situation where there's a request in the started list
1126 * but there weren't enough TRBs to fully kick it in the first time
1127 * around, so it has been waiting for more TRBs to be freed up.
1129 * In that case, we should check if we have a request with pending_sgs
1130 * in the started list and prepare TRBs for that request first,
1131 * otherwise we will prepare TRBs completely out of order and that will
1134 list_for_each_entry(req, &dep->started_list, list) {
1135 if (req->num_pending_sgs > 0)
1136 dwc3_prepare_one_trb_sg(dep, req);
1138 if (!dwc3_calc_trbs_left(dep))
1142 list_for_each_entry_safe(req, n, &dep->pending_list, list) {
1143 struct dwc3 *dwc = dep->dwc;
1146 ret = usb_gadget_map_request_by_dev(dwc->sysdev, &req->request,
1151 req->sg = req->request.sg;
1152 req->num_pending_sgs = req->request.num_mapped_sgs;
1154 if (req->num_pending_sgs > 0)
1155 dwc3_prepare_one_trb_sg(dep, req);
1157 dwc3_prepare_one_trb_linear(dep, req);
1159 if (!dwc3_calc_trbs_left(dep))
1164 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param)
1166 struct dwc3_gadget_ep_cmd_params params;
1167 struct dwc3_request *req;
1172 starting = !(dep->flags & DWC3_EP_BUSY);
1174 dwc3_prepare_trbs(dep);
1175 req = next_request(&dep->started_list);
1177 dep->flags |= DWC3_EP_PENDING_REQUEST;
1181 memset(¶ms, 0, sizeof(params));
1184 params.param0 = upper_32_bits(req->trb_dma);
1185 params.param1 = lower_32_bits(req->trb_dma);
1186 cmd = DWC3_DEPCMD_STARTTRANSFER |
1187 DWC3_DEPCMD_PARAM(cmd_param);
1189 cmd = DWC3_DEPCMD_UPDATETRANSFER |
1190 DWC3_DEPCMD_PARAM(dep->resource_index);
1193 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1196 * FIXME we need to iterate over the list of requests
1197 * here and stop, unmap, free and del each of the linked
1198 * requests instead of what we do now.
1201 memset(req->trb, 0, sizeof(struct dwc3_trb));
1202 dep->queued_requests--;
1203 dwc3_gadget_giveback(dep, req, ret);
1207 dep->flags |= DWC3_EP_BUSY;
1210 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
1211 WARN_ON_ONCE(!dep->resource_index);
1217 static int __dwc3_gadget_get_frame(struct dwc3 *dwc)
1221 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1222 return DWC3_DSTS_SOFFN(reg);
1225 static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1226 struct dwc3_ep *dep, u32 cur_uf)
1230 if (list_empty(&dep->pending_list)) {
1231 dev_info(dwc->dev, "%s: ran out of requests\n",
1233 dep->flags |= DWC3_EP_PENDING_REQUEST;
1238 * Schedule the first trb for one interval in the future or at
1239 * least 4 microframes.
1241 uf = cur_uf + max_t(u32, 4, dep->interval);
1243 __dwc3_gadget_kick_transfer(dep, uf);
1246 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1247 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1251 mask = ~(dep->interval - 1);
1252 cur_uf = event->parameters & mask;
1254 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1257 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1259 struct dwc3 *dwc = dep->dwc;
1262 if (!dep->endpoint.desc) {
1263 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
1268 if (WARN(req->dep != dep, "request %pK belongs to '%s'\n",
1269 &req->request, req->dep->name))
1272 pm_runtime_get(dwc->dev);
1274 req->request.actual = 0;
1275 req->request.status = -EINPROGRESS;
1276 req->direction = dep->direction;
1277 req->epnum = dep->number;
1279 trace_dwc3_ep_queue(req);
1281 list_add_tail(&req->list, &dep->pending_list);
1284 * NOTICE: Isochronous endpoints should NEVER be prestarted. We must
1285 * wait for a XferNotReady event so we will know what's the current
1286 * (micro-)frame number.
1288 * Without this trick, we are very, very likely gonna get Bus Expiry
1289 * errors which will force us issue EndTransfer command.
1291 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1292 if ((dep->flags & DWC3_EP_PENDING_REQUEST)) {
1293 if (dep->flags & DWC3_EP_TRANSFER_STARTED) {
1294 dwc3_stop_active_transfer(dwc, dep->number, true);
1295 dep->flags = DWC3_EP_ENABLED;
1299 cur_uf = __dwc3_gadget_get_frame(dwc);
1300 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1301 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
1306 if ((dep->flags & DWC3_EP_BUSY) &&
1307 !(dep->flags & DWC3_EP_MISSED_ISOC)) {
1308 WARN_ON_ONCE(!dep->resource_index);
1309 ret = __dwc3_gadget_kick_transfer(dep,
1310 dep->resource_index);
1316 if (!dwc3_calc_trbs_left(dep))
1319 ret = __dwc3_gadget_kick_transfer(dep, 0);
1327 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1330 struct dwc3_request *req = to_dwc3_request(request);
1331 struct dwc3_ep *dep = to_dwc3_ep(ep);
1332 struct dwc3 *dwc = dep->dwc;
1334 unsigned long flags;
1338 spin_lock_irqsave(&dwc->lock, flags);
1339 ret = __dwc3_gadget_ep_queue(dep, req);
1340 spin_unlock_irqrestore(&dwc->lock, flags);
1345 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1346 struct usb_request *request)
1348 struct dwc3_request *req = to_dwc3_request(request);
1349 struct dwc3_request *r = NULL;
1351 struct dwc3_ep *dep = to_dwc3_ep(ep);
1352 struct dwc3 *dwc = dep->dwc;
1354 unsigned long flags;
1357 trace_dwc3_ep_dequeue(req);
1359 spin_lock_irqsave(&dwc->lock, flags);
1361 list_for_each_entry(r, &dep->pending_list, list) {
1367 list_for_each_entry(r, &dep->started_list, list) {
1372 /* wait until it is processed */
1373 dwc3_stop_active_transfer(dwc, dep->number, true);
1376 * If request was already started, this means we had to
1377 * stop the transfer. With that we also need to ignore
1378 * all TRBs used by the request, however TRBs can only
1379 * be modified after completion of END_TRANSFER
1380 * command. So what we do here is that we wait for
1381 * END_TRANSFER completion and only after that, we jump
1382 * over TRBs by clearing HWO and incrementing dequeue
1385 * Note that we have 2 possible types of transfers here:
1387 * i) Linear buffer request
1388 * ii) SG-list based request
1390 * SG-list based requests will have r->num_pending_sgs
1391 * set to a valid number (> 0). Linear requests,
1392 * normally use a single TRB.
1394 * For each of these two cases, if r->unaligned flag is
1395 * set, one extra TRB has been used to align transfer
1396 * size to wMaxPacketSize.
1398 * All of these cases need to be taken into
1399 * consideration so we don't mess up our TRB ring
1402 wait_event_lock_irq(dep->wait_end_transfer,
1403 !(dep->flags & DWC3_EP_END_TRANSFER_PENDING),
1409 if (r->num_pending_sgs) {
1410 struct dwc3_trb *trb;
1413 for (i = 0; i < r->num_pending_sgs; i++) {
1415 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1416 dwc3_ep_inc_deq(dep);
1419 if (r->unaligned || r->zero) {
1420 trb = r->trb + r->num_pending_sgs + 1;
1421 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1422 dwc3_ep_inc_deq(dep);
1425 struct dwc3_trb *trb = r->trb;
1427 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1428 dwc3_ep_inc_deq(dep);
1430 if (r->unaligned || r->zero) {
1432 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1433 dwc3_ep_inc_deq(dep);
1438 dev_err(dwc->dev, "request %pK was not queued to %s\n",
1445 /* giveback the request */
1446 dep->queued_requests--;
1447 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1450 spin_unlock_irqrestore(&dwc->lock, flags);
1455 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1457 struct dwc3_gadget_ep_cmd_params params;
1458 struct dwc3 *dwc = dep->dwc;
1461 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1462 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1466 memset(¶ms, 0x00, sizeof(params));
1469 struct dwc3_trb *trb;
1471 unsigned transfer_in_flight;
1474 if (dep->flags & DWC3_EP_STALL)
1477 if (dep->number > 1)
1478 trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
1480 trb = &dwc->ep0_trb[dep->trb_enqueue];
1482 transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO;
1483 started = !list_empty(&dep->started_list);
1485 if (!protocol && ((dep->direction && transfer_in_flight) ||
1486 (!dep->direction && started))) {
1490 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
1493 dev_err(dwc->dev, "failed to set STALL on %s\n",
1496 dep->flags |= DWC3_EP_STALL;
1498 if (!(dep->flags & DWC3_EP_STALL))
1501 ret = dwc3_send_clear_stall_ep_cmd(dep);
1503 dev_err(dwc->dev, "failed to clear STALL on %s\n",
1506 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1512 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1514 struct dwc3_ep *dep = to_dwc3_ep(ep);
1515 struct dwc3 *dwc = dep->dwc;
1517 unsigned long flags;
1521 spin_lock_irqsave(&dwc->lock, flags);
1522 ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1523 spin_unlock_irqrestore(&dwc->lock, flags);
1528 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1530 struct dwc3_ep *dep = to_dwc3_ep(ep);
1531 struct dwc3 *dwc = dep->dwc;
1532 unsigned long flags;
1535 spin_lock_irqsave(&dwc->lock, flags);
1536 dep->flags |= DWC3_EP_WEDGE;
1538 if (dep->number == 0 || dep->number == 1)
1539 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1541 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1542 spin_unlock_irqrestore(&dwc->lock, flags);
1547 /* -------------------------------------------------------------------------- */
1549 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1550 .bLength = USB_DT_ENDPOINT_SIZE,
1551 .bDescriptorType = USB_DT_ENDPOINT,
1552 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1555 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1556 .enable = dwc3_gadget_ep0_enable,
1557 .disable = dwc3_gadget_ep0_disable,
1558 .alloc_request = dwc3_gadget_ep_alloc_request,
1559 .free_request = dwc3_gadget_ep_free_request,
1560 .queue = dwc3_gadget_ep0_queue,
1561 .dequeue = dwc3_gadget_ep_dequeue,
1562 .set_halt = dwc3_gadget_ep0_set_halt,
1563 .set_wedge = dwc3_gadget_ep_set_wedge,
1566 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1567 .enable = dwc3_gadget_ep_enable,
1568 .disable = dwc3_gadget_ep_disable,
1569 .alloc_request = dwc3_gadget_ep_alloc_request,
1570 .free_request = dwc3_gadget_ep_free_request,
1571 .queue = dwc3_gadget_ep_queue,
1572 .dequeue = dwc3_gadget_ep_dequeue,
1573 .set_halt = dwc3_gadget_ep_set_halt,
1574 .set_wedge = dwc3_gadget_ep_set_wedge,
1577 /* -------------------------------------------------------------------------- */
1579 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1581 struct dwc3 *dwc = gadget_to_dwc(g);
1583 return __dwc3_gadget_get_frame(dwc);
1586 static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
1597 * According to the Databook Remote wakeup request should
1598 * be issued only when the device is in early suspend state.
1600 * We can check that via USB Link State bits in DSTS register.
1602 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1604 speed = reg & DWC3_DSTS_CONNECTSPD;
1605 if ((speed == DWC3_DSTS_SUPERSPEED) ||
1606 (speed == DWC3_DSTS_SUPERSPEED_PLUS))
1609 link_state = DWC3_DSTS_USBLNKST(reg);
1611 switch (link_state) {
1612 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1613 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1619 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1621 dev_err(dwc->dev, "failed to put link in Recovery\n");
1625 /* Recent versions do this automatically */
1626 if (dwc->revision < DWC3_REVISION_194A) {
1627 /* write zeroes to Link Change Request */
1628 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1629 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1630 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1633 /* poll until Link State changes to ON */
1637 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1639 /* in HS, means ON */
1640 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1644 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1645 dev_err(dwc->dev, "failed to send remote wakeup\n");
1652 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1654 struct dwc3 *dwc = gadget_to_dwc(g);
1655 unsigned long flags;
1658 spin_lock_irqsave(&dwc->lock, flags);
1659 ret = __dwc3_gadget_wakeup(dwc);
1660 spin_unlock_irqrestore(&dwc->lock, flags);
1665 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1668 struct dwc3 *dwc = gadget_to_dwc(g);
1669 unsigned long flags;
1671 spin_lock_irqsave(&dwc->lock, flags);
1672 g->is_selfpowered = !!is_selfpowered;
1673 spin_unlock_irqrestore(&dwc->lock, flags);
1678 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1683 if (pm_runtime_suspended(dwc->dev))
1686 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1688 if (dwc->revision <= DWC3_REVISION_187A) {
1689 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1690 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1693 if (dwc->revision >= DWC3_REVISION_194A)
1694 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1695 reg |= DWC3_DCTL_RUN_STOP;
1697 if (dwc->has_hibernation)
1698 reg |= DWC3_DCTL_KEEP_CONNECT;
1700 dwc->pullups_connected = true;
1702 reg &= ~DWC3_DCTL_RUN_STOP;
1704 if (dwc->has_hibernation && !suspend)
1705 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1707 dwc->pullups_connected = false;
1710 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1713 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1714 reg &= DWC3_DSTS_DEVCTRLHLT;
1715 } while (--timeout && !(!is_on ^ !reg));
1723 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1725 struct dwc3 *dwc = gadget_to_dwc(g);
1726 unsigned long flags;
1732 * Per databook, when we want to stop the gadget, if a control transfer
1733 * is still in process, complete it and get the core into setup phase.
1735 if (!is_on && dwc->ep0state != EP0_SETUP_PHASE) {
1736 reinit_completion(&dwc->ep0_in_setup);
1738 ret = wait_for_completion_timeout(&dwc->ep0_in_setup,
1739 msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT));
1741 dev_err(dwc->dev, "timed out waiting for SETUP phase\n");
1746 spin_lock_irqsave(&dwc->lock, flags);
1747 ret = dwc3_gadget_run_stop(dwc, is_on, false);
1748 spin_unlock_irqrestore(&dwc->lock, flags);
1753 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1757 /* Enable all but Start and End of Frame IRQs */
1758 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1759 DWC3_DEVTEN_EVNTOVERFLOWEN |
1760 DWC3_DEVTEN_CMDCMPLTEN |
1761 DWC3_DEVTEN_ERRTICERREN |
1762 DWC3_DEVTEN_WKUPEVTEN |
1763 DWC3_DEVTEN_CONNECTDONEEN |
1764 DWC3_DEVTEN_USBRSTEN |
1765 DWC3_DEVTEN_DISCONNEVTEN);
1767 if (dwc->revision < DWC3_REVISION_250A)
1768 reg |= DWC3_DEVTEN_ULSTCNGEN;
1770 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1773 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1775 /* mask all interrupts */
1776 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1779 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1780 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1783 * dwc3_gadget_setup_nump - calculate and initialize NUMP field of %DWC3_DCFG
1784 * @dwc: pointer to our context structure
1786 * The following looks like complex but it's actually very simple. In order to
1787 * calculate the number of packets we can burst at once on OUT transfers, we're
1788 * gonna use RxFIFO size.
1790 * To calculate RxFIFO size we need two numbers:
1791 * MDWIDTH = size, in bits, of the internal memory bus
1792 * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
1794 * Given these two numbers, the formula is simple:
1796 * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
1798 * 24 bytes is for 3x SETUP packets
1799 * 16 bytes is a clock domain crossing tolerance
1801 * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
1803 static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
1810 ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
1811 mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0);
1813 nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
1814 nump = min_t(u32, nump, 16);
1817 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1818 reg &= ~DWC3_DCFG_NUMP_MASK;
1819 reg |= nump << DWC3_DCFG_NUMP_SHIFT;
1820 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1823 static int __dwc3_gadget_start(struct dwc3 *dwc)
1825 struct dwc3_ep *dep;
1830 * Use IMOD if enabled via dwc->imod_interval. Otherwise, if
1831 * the core supports IMOD, disable it.
1833 if (dwc->imod_interval) {
1834 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
1835 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
1836 } else if (dwc3_has_imod(dwc)) {
1837 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), 0);
1841 * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
1842 * field instead of letting dwc3 itself calculate that automatically.
1844 * This way, we maximize the chances that we'll be able to get several
1845 * bursts of data without going through any sort of endpoint throttling.
1847 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1848 reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
1849 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1851 dwc3_gadget_setup_nump(dwc);
1853 /* Start with SuperSpeed Default */
1854 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1857 ret = __dwc3_gadget_ep_enable(dep, false, false);
1859 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1864 ret = __dwc3_gadget_ep_enable(dep, false, false);
1866 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1870 /* begin to receive SETUP packets */
1871 dwc->ep0state = EP0_SETUP_PHASE;
1872 dwc3_ep0_out_start(dwc);
1874 dwc3_gadget_enable_irq(dwc);
1879 __dwc3_gadget_ep_disable(dwc->eps[0]);
1885 static int dwc3_gadget_start(struct usb_gadget *g,
1886 struct usb_gadget_driver *driver)
1888 struct dwc3 *dwc = gadget_to_dwc(g);
1889 unsigned long flags;
1893 irq = dwc->irq_gadget;
1894 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1895 IRQF_SHARED, "dwc3", dwc->ev_buf);
1897 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1902 spin_lock_irqsave(&dwc->lock, flags);
1903 if (dwc->gadget_driver) {
1904 dev_err(dwc->dev, "%s is already bound to %s\n",
1906 dwc->gadget_driver->driver.name);
1911 dwc->gadget_driver = driver;
1913 if (pm_runtime_active(dwc->dev))
1914 __dwc3_gadget_start(dwc);
1916 spin_unlock_irqrestore(&dwc->lock, flags);
1921 spin_unlock_irqrestore(&dwc->lock, flags);
1928 static void __dwc3_gadget_stop(struct dwc3 *dwc)
1930 dwc3_gadget_disable_irq(dwc);
1931 __dwc3_gadget_ep_disable(dwc->eps[0]);
1932 __dwc3_gadget_ep_disable(dwc->eps[1]);
1935 static int dwc3_gadget_stop(struct usb_gadget *g)
1937 struct dwc3 *dwc = gadget_to_dwc(g);
1938 unsigned long flags;
1941 spin_lock_irqsave(&dwc->lock, flags);
1943 if (pm_runtime_suspended(dwc->dev))
1946 __dwc3_gadget_stop(dwc);
1948 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1949 struct dwc3_ep *dep = dwc->eps[epnum];
1954 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
1957 wait_event_lock_irq(dep->wait_end_transfer,
1958 !(dep->flags & DWC3_EP_END_TRANSFER_PENDING),
1963 dwc->gadget_driver = NULL;
1964 spin_unlock_irqrestore(&dwc->lock, flags);
1966 free_irq(dwc->irq_gadget, dwc->ev_buf);
1971 static void dwc3_gadget_set_speed(struct usb_gadget *g,
1972 enum usb_device_speed speed)
1974 struct dwc3 *dwc = gadget_to_dwc(g);
1975 unsigned long flags;
1978 spin_lock_irqsave(&dwc->lock, flags);
1979 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1980 reg &= ~(DWC3_DCFG_SPEED_MASK);
1983 * WORKAROUND: DWC3 revision < 2.20a have an issue
1984 * which would cause metastability state on Run/Stop
1985 * bit if we try to force the IP to USB2-only mode.
1987 * Because of that, we cannot configure the IP to any
1988 * speed other than the SuperSpeed
1992 * STAR#9000525659: Clock Domain Crossing on DCTL in
1995 if (dwc->revision < DWC3_REVISION_220A) {
1996 reg |= DWC3_DCFG_SUPERSPEED;
2000 reg |= DWC3_DCFG_LOWSPEED;
2002 case USB_SPEED_FULL:
2003 reg |= DWC3_DCFG_FULLSPEED;
2005 case USB_SPEED_HIGH:
2006 reg |= DWC3_DCFG_HIGHSPEED;
2008 case USB_SPEED_SUPER:
2009 reg |= DWC3_DCFG_SUPERSPEED;
2011 case USB_SPEED_SUPER_PLUS:
2012 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2015 dev_err(dwc->dev, "invalid speed (%d)\n", speed);
2017 if (dwc->revision & DWC3_REVISION_IS_DWC31)
2018 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2020 reg |= DWC3_DCFG_SUPERSPEED;
2023 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2025 spin_unlock_irqrestore(&dwc->lock, flags);
2028 static const struct usb_gadget_ops dwc3_gadget_ops = {
2029 .get_frame = dwc3_gadget_get_frame,
2030 .wakeup = dwc3_gadget_wakeup,
2031 .set_selfpowered = dwc3_gadget_set_selfpowered,
2032 .pullup = dwc3_gadget_pullup,
2033 .udc_start = dwc3_gadget_start,
2034 .udc_stop = dwc3_gadget_stop,
2035 .udc_set_speed = dwc3_gadget_set_speed,
2038 /* -------------------------------------------------------------------------- */
2040 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc, u8 total)
2042 struct dwc3_ep *dep;
2045 INIT_LIST_HEAD(&dwc->gadget.ep_list);
2047 for (epnum = 0; epnum < total; epnum++) {
2048 bool direction = epnum & 1;
2049 u8 num = epnum >> 1;
2051 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
2056 dep->number = epnum;
2057 dep->direction = direction;
2058 dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
2059 dwc->eps[epnum] = dep;
2061 snprintf(dep->name, sizeof(dep->name), "ep%u%s", num,
2062 direction ? "in" : "out");
2064 dep->endpoint.name = dep->name;
2066 if (!(dep->number > 1)) {
2067 dep->endpoint.desc = &dwc3_gadget_ep0_desc;
2068 dep->endpoint.comp_desc = NULL;
2071 spin_lock_init(&dep->lock);
2074 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
2075 dep->endpoint.maxburst = 1;
2076 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
2078 dwc->gadget.ep0 = &dep->endpoint;
2079 } else if (direction) {
2085 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
2086 /* MDWIDTH is represented in bits, we need it in bytes */
2089 size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(num));
2090 size = DWC3_GTXFIFOSIZ_TXFDEF(size);
2092 /* FIFO Depth is in MDWDITH bytes. Multiply */
2095 kbytes = size / 1024;
2100 * FIFO sizes account an extra MDWIDTH * (kbytes + 1) bytes for
2101 * internal overhead. We don't really know how these are used,
2102 * but documentation say it exists.
2104 size -= mdwidth * (kbytes + 1);
2107 usb_ep_set_maxpacket_limit(&dep->endpoint, size);
2109 dep->endpoint.max_streams = 15;
2110 dep->endpoint.ops = &dwc3_gadget_ep_ops;
2111 list_add_tail(&dep->endpoint.ep_list,
2112 &dwc->gadget.ep_list);
2114 ret = dwc3_alloc_trb_pool(dep);
2120 usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
2121 dep->endpoint.max_streams = 15;
2122 dep->endpoint.ops = &dwc3_gadget_ep_ops;
2123 list_add_tail(&dep->endpoint.ep_list,
2124 &dwc->gadget.ep_list);
2126 ret = dwc3_alloc_trb_pool(dep);
2132 dep->endpoint.caps.type_control = true;
2134 dep->endpoint.caps.type_iso = true;
2135 dep->endpoint.caps.type_bulk = true;
2136 dep->endpoint.caps.type_int = true;
2139 dep->endpoint.caps.dir_in = direction;
2140 dep->endpoint.caps.dir_out = !direction;
2142 INIT_LIST_HEAD(&dep->pending_list);
2143 INIT_LIST_HEAD(&dep->started_list);
2149 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
2151 struct dwc3_ep *dep;
2154 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2155 dep = dwc->eps[epnum];
2159 * Physical endpoints 0 and 1 are special; they form the
2160 * bi-directional USB endpoint 0.
2162 * For those two physical endpoints, we don't allocate a TRB
2163 * pool nor do we add them the endpoints list. Due to that, we
2164 * shouldn't do these two operations otherwise we would end up
2165 * with all sorts of bugs when removing dwc3.ko.
2167 if (epnum != 0 && epnum != 1) {
2168 dwc3_free_trb_pool(dep);
2169 list_del(&dep->endpoint.ep_list);
2176 /* -------------------------------------------------------------------------- */
2178 static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
2179 struct dwc3_request *req, struct dwc3_trb *trb,
2180 const struct dwc3_event_depevt *event, int status,
2184 unsigned int s_pkt = 0;
2185 unsigned int trb_status;
2187 dwc3_ep_inc_deq(dep);
2189 if (req->trb == trb)
2190 dep->queued_requests--;
2192 trace_dwc3_complete_trb(dep, trb);
2195 * If we're in the middle of series of chained TRBs and we
2196 * receive a short transfer along the way, DWC3 will skip
2197 * through all TRBs including the last TRB in the chain (the
2198 * where CHN bit is zero. DWC3 will also avoid clearing HWO
2199 * bit and SW has to do it manually.
2201 * We're going to do that here to avoid problems of HW trying
2202 * to use bogus TRBs for transfers.
2204 if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO))
2205 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2208 * If we're dealing with unaligned size OUT transfer, we will be left
2209 * with one TRB pending in the ring. We need to manually clear HWO bit
2212 if ((req->zero || req->unaligned) && (trb->ctrl & DWC3_TRB_CTRL_HWO)) {
2213 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2217 count = trb->size & DWC3_TRB_SIZE_MASK;
2218 req->remaining += count;
2220 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
2223 if (dep->direction) {
2225 trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
2226 if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
2228 * If missed isoc occurred and there is
2229 * no request queued then issue END
2230 * TRANSFER, so that core generates
2231 * next xfernotready and we will issue
2232 * a fresh START TRANSFER.
2233 * If there are still queued request
2234 * then wait, do not issue either END
2235 * or UPDATE TRANSFER, just attach next
2236 * request in pending_list during
2237 * giveback.If any future queued request
2238 * is successfully transferred then we
2239 * will issue UPDATE TRANSFER for all
2240 * request in the pending_list.
2242 dep->flags |= DWC3_EP_MISSED_ISOC;
2244 dev_err(dwc->dev, "incomplete IN transfer %s\n",
2246 status = -ECONNRESET;
2249 dep->flags &= ~DWC3_EP_MISSED_ISOC;
2252 if (count && (event->status & DEPEVT_STATUS_SHORT))
2256 if (s_pkt && !chain)
2259 if ((event->status & DEPEVT_STATUS_IOC) &&
2260 (trb->ctrl & DWC3_TRB_CTRL_IOC))
2266 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
2267 const struct dwc3_event_depevt *event, int status)
2269 struct dwc3_request *req, *n;
2270 struct dwc3_trb *trb;
2274 list_for_each_entry_safe(req, n, &dep->started_list, list) {
2278 length = req->request.length;
2279 chain = req->num_pending_sgs > 0;
2281 struct scatterlist *sg = req->sg;
2282 struct scatterlist *s;
2283 unsigned int pending = req->num_pending_sgs;
2286 for_each_sg(sg, s, pending, i) {
2287 trb = &dep->trb_pool[dep->trb_dequeue];
2289 if (trb->ctrl & DWC3_TRB_CTRL_HWO)
2292 req->sg = sg_next(s);
2293 req->num_pending_sgs--;
2295 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2296 event, status, chain);
2301 trb = &dep->trb_pool[dep->trb_dequeue];
2302 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2303 event, status, chain);
2306 if (req->unaligned || req->zero) {
2307 trb = &dep->trb_pool[dep->trb_dequeue];
2308 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2309 event, status, false);
2310 req->unaligned = false;
2314 req->request.actual = length - req->remaining;
2316 if ((req->request.actual < length) && req->num_pending_sgs)
2317 return __dwc3_gadget_kick_transfer(dep, 0);
2319 dwc3_gadget_giveback(dep, req, status);
2322 if ((event->status & DEPEVT_STATUS_IOC) &&
2323 (trb->ctrl & DWC3_TRB_CTRL_IOC))
2330 * Our endpoint might get disabled by another thread during
2331 * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2332 * early on so DWC3_EP_BUSY flag gets cleared
2334 if (!dep->endpoint.desc)
2337 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
2338 list_empty(&dep->started_list)) {
2339 if (list_empty(&dep->pending_list)) {
2341 * If there is no entry in request list then do
2342 * not issue END TRANSFER now. Just set PENDING
2343 * flag, so that END TRANSFER is issued when an
2344 * entry is added into request list.
2346 dep->flags = DWC3_EP_PENDING_REQUEST;
2348 dwc3_stop_active_transfer(dwc, dep->number, true);
2349 dep->flags = DWC3_EP_ENABLED;
2354 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && ioc)
2360 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
2361 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
2363 unsigned status = 0;
2365 u32 is_xfer_complete;
2367 is_xfer_complete = (event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE);
2369 if (event->status & DEPEVT_STATUS_BUSERR)
2370 status = -ECONNRESET;
2372 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
2373 if (clean_busy && (!dep->endpoint.desc || is_xfer_complete ||
2374 usb_endpoint_xfer_isoc(dep->endpoint.desc)))
2375 dep->flags &= ~DWC3_EP_BUSY;
2378 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2379 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2381 if (dwc->revision < DWC3_REVISION_183A) {
2385 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
2388 if (!(dep->flags & DWC3_EP_ENABLED))
2391 if (!list_empty(&dep->started_list))
2395 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2397 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2403 * Our endpoint might get disabled by another thread during
2404 * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2405 * early on so DWC3_EP_BUSY flag gets cleared
2407 if (!dep->endpoint.desc)
2410 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2413 ret = __dwc3_gadget_kick_transfer(dep, 0);
2414 if (!ret || ret == -EBUSY)
2419 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2420 const struct dwc3_event_depevt *event)
2422 struct dwc3_ep *dep;
2423 u8 epnum = event->endpoint_number;
2426 dep = dwc->eps[epnum];
2428 if (!(dep->flags & DWC3_EP_ENABLED)) {
2429 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
2432 /* Handle only EPCMDCMPLT when EP disabled */
2433 if (event->endpoint_event != DWC3_DEPEVT_EPCMDCMPLT)
2437 if (epnum == 0 || epnum == 1) {
2438 dwc3_ep0_interrupt(dwc, event);
2442 switch (event->endpoint_event) {
2443 case DWC3_DEPEVT_XFERCOMPLETE:
2444 dep->resource_index = 0;
2446 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2447 dev_err(dwc->dev, "XferComplete for Isochronous endpoint\n");
2451 dwc3_endpoint_transfer_complete(dwc, dep, event);
2453 case DWC3_DEPEVT_XFERINPROGRESS:
2454 dwc3_endpoint_transfer_complete(dwc, dep, event);
2456 case DWC3_DEPEVT_XFERNOTREADY:
2457 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2458 dwc3_gadget_start_isoc(dwc, dep, event);
2462 ret = __dwc3_gadget_kick_transfer(dep, 0);
2463 if (!ret || ret == -EBUSY)
2468 case DWC3_DEPEVT_STREAMEVT:
2469 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
2470 dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
2475 case DWC3_DEPEVT_EPCMDCMPLT:
2476 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
2478 if (cmd == DWC3_DEPCMD_ENDTRANSFER) {
2479 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
2480 wake_up(&dep->wait_end_transfer);
2483 case DWC3_DEPEVT_RXTXFIFOEVT:
2488 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2490 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2491 spin_unlock(&dwc->lock);
2492 dwc->gadget_driver->disconnect(&dwc->gadget);
2493 spin_lock(&dwc->lock);
2497 static void dwc3_suspend_gadget(struct dwc3 *dwc)
2499 if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
2500 spin_unlock(&dwc->lock);
2501 dwc->gadget_driver->suspend(&dwc->gadget);
2502 spin_lock(&dwc->lock);
2506 static void dwc3_resume_gadget(struct dwc3 *dwc)
2508 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2509 spin_unlock(&dwc->lock);
2510 dwc->gadget_driver->resume(&dwc->gadget);
2511 spin_lock(&dwc->lock);
2515 static void dwc3_reset_gadget(struct dwc3 *dwc)
2517 if (!dwc->gadget_driver)
2520 if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2521 spin_unlock(&dwc->lock);
2522 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
2523 spin_lock(&dwc->lock);
2527 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
2529 struct dwc3_ep *dep;
2530 struct dwc3_gadget_ep_cmd_params params;
2534 dep = dwc->eps[epnum];
2536 if ((dep->flags & DWC3_EP_END_TRANSFER_PENDING) ||
2537 !dep->resource_index)
2541 * NOTICE: We are violating what the Databook says about the
2542 * EndTransfer command. Ideally we would _always_ wait for the
2543 * EndTransfer Command Completion IRQ, but that's causing too
2544 * much trouble synchronizing between us and gadget driver.
2546 * We have discussed this with the IP Provider and it was
2547 * suggested to giveback all requests here, but give HW some
2548 * extra time to synchronize with the interconnect. We're using
2549 * an arbitrary 100us delay for that.
2551 * Note also that a similar handling was tested by Synopsys
2552 * (thanks a lot Paul) and nothing bad has come out of it.
2553 * In short, what we're doing is:
2555 * - Issue EndTransfer WITH CMDIOC bit set
2558 * As of IP version 3.10a of the DWC_usb3 IP, the controller
2559 * supports a mode to work around the above limitation. The
2560 * software can poll the CMDACT bit in the DEPCMD register
2561 * after issuing a EndTransfer command. This mode is enabled
2562 * by writing GUCTL2[14]. This polling is already done in the
2563 * dwc3_send_gadget_ep_cmd() function so if the mode is
2564 * enabled, the EndTransfer command will have completed upon
2565 * returning from this function and we don't need to delay for
2568 * This mode is NOT available on the DWC_usb31 IP.
2571 cmd = DWC3_DEPCMD_ENDTRANSFER;
2572 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2573 cmd |= DWC3_DEPCMD_CMDIOC;
2574 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2575 memset(¶ms, 0, sizeof(params));
2576 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
2578 dep->resource_index = 0;
2579 dep->flags &= ~DWC3_EP_BUSY;
2581 if (dwc3_is_usb31(dwc) || dwc->revision < DWC3_REVISION_310A) {
2582 dep->flags |= DWC3_EP_END_TRANSFER_PENDING;
2587 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2591 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2592 struct dwc3_ep *dep;
2595 dep = dwc->eps[epnum];
2599 if (!(dep->flags & DWC3_EP_STALL))
2602 dep->flags &= ~DWC3_EP_STALL;
2604 ret = dwc3_send_clear_stall_ep_cmd(dep);
2609 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2613 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2614 reg &= ~DWC3_DCTL_INITU1ENA;
2615 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2617 reg &= ~DWC3_DCTL_INITU2ENA;
2618 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2620 dwc3_disconnect_gadget(dwc);
2622 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2623 dwc->setup_packet_pending = false;
2624 usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2626 dwc->connected = false;
2629 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2633 dwc->connected = true;
2636 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2637 * would cause a missing Disconnect Event if there's a
2638 * pending Setup Packet in the FIFO.
2640 * There's no suggested workaround on the official Bug
2641 * report, which states that "unless the driver/application
2642 * is doing any special handling of a disconnect event,
2643 * there is no functional issue".
2645 * Unfortunately, it turns out that we _do_ some special
2646 * handling of a disconnect event, namely complete all
2647 * pending transfers, notify gadget driver of the
2648 * disconnection, and so on.
2650 * Our suggested workaround is to follow the Disconnect
2651 * Event steps here, instead, based on a setup_packet_pending
2652 * flag. Such flag gets set whenever we have a SETUP_PENDING
2653 * status for EP0 TRBs and gets cleared on XferComplete for the
2658 * STAR#9000466709: RTL: Device : Disconnect event not
2659 * generated if setup packet pending in FIFO
2661 if (dwc->revision < DWC3_REVISION_188A) {
2662 if (dwc->setup_packet_pending)
2663 dwc3_gadget_disconnect_interrupt(dwc);
2666 dwc3_reset_gadget(dwc);
2668 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2669 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2670 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2671 dwc->test_mode = false;
2672 dwc3_clear_stall_all_ep(dwc);
2674 /* Reset device address to zero */
2675 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2676 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2677 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2680 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2682 struct dwc3_ep *dep;
2687 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2688 speed = reg & DWC3_DSTS_CONNECTSPD;
2692 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2693 * each time on Connect Done.
2695 * Currently we always use the reset value. If any platform
2696 * wants to set this to a different value, we need to add a
2697 * setting and update GCTL.RAMCLKSEL here.
2701 case DWC3_DSTS_SUPERSPEED_PLUS:
2702 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2703 dwc->gadget.ep0->maxpacket = 512;
2704 dwc->gadget.speed = USB_SPEED_SUPER_PLUS;
2706 case DWC3_DSTS_SUPERSPEED:
2708 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2709 * would cause a missing USB3 Reset event.
2711 * In such situations, we should force a USB3 Reset
2712 * event by calling our dwc3_gadget_reset_interrupt()
2717 * STAR#9000483510: RTL: SS : USB3 reset event may
2718 * not be generated always when the link enters poll
2720 if (dwc->revision < DWC3_REVISION_190A)
2721 dwc3_gadget_reset_interrupt(dwc);
2723 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2724 dwc->gadget.ep0->maxpacket = 512;
2725 dwc->gadget.speed = USB_SPEED_SUPER;
2727 case DWC3_DSTS_HIGHSPEED:
2728 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2729 dwc->gadget.ep0->maxpacket = 64;
2730 dwc->gadget.speed = USB_SPEED_HIGH;
2732 case DWC3_DSTS_FULLSPEED:
2733 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2734 dwc->gadget.ep0->maxpacket = 64;
2735 dwc->gadget.speed = USB_SPEED_FULL;
2737 case DWC3_DSTS_LOWSPEED:
2738 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2739 dwc->gadget.ep0->maxpacket = 8;
2740 dwc->gadget.speed = USB_SPEED_LOW;
2744 /* Enable USB2 LPM Capability */
2746 if ((dwc->revision > DWC3_REVISION_194A) &&
2747 (speed != DWC3_DSTS_SUPERSPEED) &&
2748 (speed != DWC3_DSTS_SUPERSPEED_PLUS)) {
2749 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2750 reg |= DWC3_DCFG_LPM_CAP;
2751 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2753 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2754 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2756 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2759 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2760 * DCFG.LPMCap is set, core responses with an ACK and the
2761 * BESL value in the LPM token is less than or equal to LPM
2764 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2765 && dwc->has_lpm_erratum,
2766 "LPM Erratum not available on dwc3 revisions < 2.40a\n");
2768 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2769 reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2771 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2773 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2774 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2775 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2779 ret = __dwc3_gadget_ep_enable(dep, true, false);
2781 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2786 ret = __dwc3_gadget_ep_enable(dep, true, false);
2788 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2793 * Configure PHY via GUSB3PIPECTLn if required.
2795 * Update GTXFIFOSIZn
2797 * In both cases reset values should be sufficient.
2801 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2804 * TODO take core out of low power mode when that's
2808 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2809 spin_unlock(&dwc->lock);
2810 dwc->gadget_driver->resume(&dwc->gadget);
2811 spin_lock(&dwc->lock);
2815 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2816 unsigned int evtinfo)
2818 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2819 unsigned int pwropt;
2822 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2823 * Hibernation mode enabled which would show up when device detects
2824 * host-initiated U3 exit.
2826 * In that case, device will generate a Link State Change Interrupt
2827 * from U3 to RESUME which is only necessary if Hibernation is
2830 * There are no functional changes due to such spurious event and we
2831 * just need to ignore it.
2835 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2838 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2839 if ((dwc->revision < DWC3_REVISION_250A) &&
2840 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2841 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2842 (next == DWC3_LINK_STATE_RESUME)) {
2848 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2849 * on the link partner, the USB session might do multiple entry/exit
2850 * of low power states before a transfer takes place.
2852 * Due to this problem, we might experience lower throughput. The
2853 * suggested workaround is to disable DCTL[12:9] bits if we're
2854 * transitioning from U1/U2 to U0 and enable those bits again
2855 * after a transfer completes and there are no pending transfers
2856 * on any of the enabled endpoints.
2858 * This is the first half of that workaround.
2862 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2863 * core send LGO_Ux entering U0
2865 if (dwc->revision < DWC3_REVISION_183A) {
2866 if (next == DWC3_LINK_STATE_U0) {
2870 switch (dwc->link_state) {
2871 case DWC3_LINK_STATE_U1:
2872 case DWC3_LINK_STATE_U2:
2873 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2874 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2875 | DWC3_DCTL_ACCEPTU2ENA
2876 | DWC3_DCTL_INITU1ENA
2877 | DWC3_DCTL_ACCEPTU1ENA);
2880 dwc->u1u2 = reg & u1u2;
2884 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2894 case DWC3_LINK_STATE_U1:
2895 if (dwc->speed == USB_SPEED_SUPER)
2896 dwc3_suspend_gadget(dwc);
2898 case DWC3_LINK_STATE_U2:
2899 case DWC3_LINK_STATE_U3:
2900 dwc3_suspend_gadget(dwc);
2902 case DWC3_LINK_STATE_RESUME:
2903 dwc3_resume_gadget(dwc);
2910 dwc->link_state = next;
2913 static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc,
2914 unsigned int evtinfo)
2916 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2918 if (dwc->link_state != next && next == DWC3_LINK_STATE_U3)
2919 dwc3_suspend_gadget(dwc);
2921 dwc->link_state = next;
2924 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2925 unsigned int evtinfo)
2927 unsigned int is_ss = evtinfo & BIT(4);
2930 * WORKAROUND: DWC3 revison 2.20a with hibernation support
2931 * have a known issue which can cause USB CV TD.9.23 to fail
2934 * Because of this issue, core could generate bogus hibernation
2935 * events which SW needs to ignore.
2939 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2940 * Device Fallback from SuperSpeed
2942 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2945 /* enter hibernation here */
2948 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2949 const struct dwc3_event_devt *event)
2951 switch (event->type) {
2952 case DWC3_DEVICE_EVENT_DISCONNECT:
2953 dwc3_gadget_disconnect_interrupt(dwc);
2955 case DWC3_DEVICE_EVENT_RESET:
2956 dwc3_gadget_reset_interrupt(dwc);
2958 case DWC3_DEVICE_EVENT_CONNECT_DONE:
2959 dwc3_gadget_conndone_interrupt(dwc);
2961 case DWC3_DEVICE_EVENT_WAKEUP:
2962 dwc3_gadget_wakeup_interrupt(dwc);
2964 case DWC3_DEVICE_EVENT_HIBER_REQ:
2965 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
2966 "unexpected hibernation event\n"))
2969 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2971 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2972 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2974 case DWC3_DEVICE_EVENT_EOPF:
2975 /* It changed to be suspend event for version 2.30a and above */
2976 if (dwc->revision >= DWC3_REVISION_230A) {
2978 * Ignore suspend event until the gadget enters into
2979 * USB_STATE_CONFIGURED state.
2981 if (dwc->gadget.state >= USB_STATE_CONFIGURED)
2982 dwc3_gadget_suspend_interrupt(dwc,
2986 case DWC3_DEVICE_EVENT_SOF:
2987 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2988 case DWC3_DEVICE_EVENT_CMD_CMPL:
2989 case DWC3_DEVICE_EVENT_OVERFLOW:
2992 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2996 static void dwc3_process_event_entry(struct dwc3 *dwc,
2997 const union dwc3_event *event)
2999 trace_dwc3_event(event->raw, dwc);
3001 if (!event->type.is_devspec)
3002 dwc3_endpoint_interrupt(dwc, &event->depevt);
3003 else if (event->type.type == DWC3_EVENT_TYPE_DEV)
3004 dwc3_gadget_interrupt(dwc, &event->devt);
3006 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
3009 static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
3011 struct dwc3 *dwc = evt->dwc;
3012 irqreturn_t ret = IRQ_NONE;
3018 if (!(evt->flags & DWC3_EVENT_PENDING))
3022 union dwc3_event event;
3024 event.raw = *(u32 *) (evt->cache + evt->lpos);
3026 dwc3_process_event_entry(dwc, &event);
3029 * FIXME we wrap around correctly to the next entry as
3030 * almost all entries are 4 bytes in size. There is one
3031 * entry which has 12 bytes which is a regular entry
3032 * followed by 8 bytes data. ATM I don't know how
3033 * things are organized if we get next to the a
3034 * boundary so I worry about that once we try to handle
3037 evt->lpos = (evt->lpos + 4) % evt->length;
3042 evt->flags &= ~DWC3_EVENT_PENDING;
3045 /* Unmask interrupt */
3046 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
3047 reg &= ~DWC3_GEVNTSIZ_INTMASK;
3048 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
3050 if (dwc->imod_interval) {
3051 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
3052 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
3058 static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
3060 struct dwc3_event_buffer *evt = _evt;
3061 struct dwc3 *dwc = evt->dwc;
3062 unsigned long flags;
3063 irqreturn_t ret = IRQ_NONE;
3065 spin_lock_irqsave(&dwc->lock, flags);
3066 ret = dwc3_process_event_buf(evt);
3067 spin_unlock_irqrestore(&dwc->lock, flags);
3072 static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
3074 struct dwc3 *dwc = evt->dwc;
3079 if (pm_runtime_suspended(dwc->dev)) {
3080 pm_runtime_get(dwc->dev);
3081 disable_irq_nosync(dwc->irq_gadget);
3082 dwc->pending_events = true;
3087 * With PCIe legacy interrupt, test shows that top-half irq handler can
3088 * be called again after HW interrupt deassertion. Check if bottom-half
3089 * irq event handler completes before caching new event to prevent
3092 if (evt->flags & DWC3_EVENT_PENDING)
3095 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
3096 count &= DWC3_GEVNTCOUNT_MASK;
3101 evt->flags |= DWC3_EVENT_PENDING;
3103 /* Mask interrupt */
3104 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
3105 reg |= DWC3_GEVNTSIZ_INTMASK;
3106 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
3108 amount = min(count, evt->length - evt->lpos);
3109 memcpy(evt->cache + evt->lpos, evt->buf + evt->lpos, amount);
3112 memcpy(evt->cache, evt->buf, count - amount);
3114 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
3116 return IRQ_WAKE_THREAD;
3119 static irqreturn_t dwc3_interrupt(int irq, void *_evt)
3121 struct dwc3_event_buffer *evt = _evt;
3123 return dwc3_check_event_buf(evt);
3126 static int dwc3_gadget_get_irq(struct dwc3 *dwc)
3128 struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
3131 irq = platform_get_irq_byname(dwc3_pdev, "peripheral");
3135 if (irq == -EPROBE_DEFER)
3138 irq = platform_get_irq_byname(dwc3_pdev, "dwc_usb3");
3142 if (irq == -EPROBE_DEFER)
3145 irq = platform_get_irq(dwc3_pdev, 0);
3149 if (irq != -EPROBE_DEFER)
3150 dev_err(dwc->dev, "missing peripheral IRQ\n");
3160 * dwc3_gadget_init - initializes gadget related registers
3161 * @dwc: pointer to our controller context structure
3163 * Returns 0 on success otherwise negative errno.
3165 int dwc3_gadget_init(struct dwc3 *dwc)
3170 irq = dwc3_gadget_get_irq(dwc);
3176 dwc->irq_gadget = irq;
3178 dwc->ep0_trb = dma_alloc_coherent(dwc->sysdev,
3179 sizeof(*dwc->ep0_trb) * 2,
3180 &dwc->ep0_trb_addr, GFP_KERNEL);
3181 if (!dwc->ep0_trb) {
3182 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
3187 dwc->setup_buf = kzalloc(DWC3_EP0_SETUP_SIZE, GFP_KERNEL);
3188 if (!dwc->setup_buf) {
3193 dwc->bounce = dma_alloc_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE,
3194 &dwc->bounce_addr, GFP_KERNEL);
3200 init_completion(&dwc->ep0_in_setup);
3202 dwc->gadget.ops = &dwc3_gadget_ops;
3203 dwc->gadget.speed = USB_SPEED_UNKNOWN;
3204 dwc->gadget.sg_supported = true;
3205 dwc->gadget.name = "dwc3-gadget";
3206 dwc->gadget.is_otg = dwc->dr_mode == USB_DR_MODE_OTG;
3209 * FIXME We might be setting max_speed to <SUPER, however versions
3210 * <2.20a of dwc3 have an issue with metastability (documented
3211 * elsewhere in this driver) which tells us we can't set max speed to
3212 * anything lower than SUPER.
3214 * Because gadget.max_speed is only used by composite.c and function
3215 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
3216 * to happen so we avoid sending SuperSpeed Capability descriptor
3217 * together with our BOS descriptor as that could confuse host into
3218 * thinking we can handle super speed.
3220 * Note that, in fact, we won't even support GetBOS requests when speed
3221 * is less than super speed because we don't have means, yet, to tell
3222 * composite.c that we are USB 2.0 + LPM ECN.
3224 if (dwc->revision < DWC3_REVISION_220A)
3225 dev_info(dwc->dev, "changing max_speed on rev %08x\n",
3228 dwc->gadget.max_speed = dwc->maximum_speed;
3231 * REVISIT: Here we should clear all pending IRQs to be
3232 * sure we're starting from a well known location.
3235 ret = dwc3_gadget_init_endpoints(dwc, dwc->num_eps);
3239 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
3241 dev_err(dwc->dev, "failed to register udc\n");
3248 dwc3_gadget_free_endpoints(dwc);
3251 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
3255 kfree(dwc->setup_buf);
3258 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
3259 dwc->ep0_trb, dwc->ep0_trb_addr);
3265 /* -------------------------------------------------------------------------- */
3267 void dwc3_gadget_exit(struct dwc3 *dwc)
3269 usb_del_gadget_udc(&dwc->gadget);
3270 dwc3_gadget_free_endpoints(dwc);
3271 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
3273 kfree(dwc->setup_buf);
3274 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
3275 dwc->ep0_trb, dwc->ep0_trb_addr);
3278 int dwc3_gadget_suspend(struct dwc3 *dwc)
3280 if (!dwc->gadget_driver)
3283 dwc3_gadget_run_stop(dwc, false, false);
3284 dwc3_disconnect_gadget(dwc);
3285 __dwc3_gadget_stop(dwc);
3290 int dwc3_gadget_resume(struct dwc3 *dwc)
3294 if (!dwc->gadget_driver)
3297 ret = __dwc3_gadget_start(dwc);
3301 ret = dwc3_gadget_run_stop(dwc, true, false);
3308 __dwc3_gadget_stop(dwc);
3314 void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
3316 if (dwc->pending_events) {
3317 dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf);
3318 dwc->pending_events = false;
3319 enable_irq(dwc->irq_gadget);