drivers/usb/dwc3/gadget.c

   1 /**
   2  * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * This program is free software: you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2  of
  11  * the License as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/delay.h>
  21 #include <linux/slab.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/pm_runtime.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/io.h>
  27 #include <linux/list.h>
  28 #include <linux/dma-mapping.h>
  29
  30 #include <linux/usb/ch9.h>
  31 #include <linux/usb/gadget.h>
  32
  33 #include "core.h"
  34 #include "gadget.h"
  35 #include "io.h"
  36
  37 /**
  38  * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
  39  * @dwc: pointer to our context structure
  40  * @mode: the mode to set (J, K SE0 NAK, Force Enable)
  41  *
  42  * Caller should take care of locking. This function will
  43  * return 0 on success or -EINVAL if wrong Test Selector
  44  * is passed
  45  */
  46 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
  47 {
  48         u32             reg;
  49
  50         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  51         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
  52
  53         switch (mode) {
  54         case TEST_J:
  55         case TEST_K:
  56         case TEST_SE0_NAK:
  57         case TEST_PACKET:
  58         case TEST_FORCE_EN:
  59                 reg |= mode << 1;
  60                 break;
  61         default:
  62                 return -EINVAL;
  63         }
  64
  65         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  66
  67         return 0;
  68 }
  69
  70 /**
  71  * dwc3_gadget_get_link_state - Gets current state of USB Link
  72  * @dwc: pointer to our context structure
  73  *
  74  * Caller should take care of locking. This function will
  75  * return the link state on success (>= 0) or -ETIMEDOUT.
  76  */
  77 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
  78 {
  79         u32             reg;
  80
  81         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
  82
  83         return DWC3_DSTS_USBLNKST(reg);
  84 }
  85
  86 /**
  87  * dwc3_gadget_set_link_state - Sets USB Link to a particular State
  88  * @dwc: pointer to our context structure
  89  * @state: the state to put link into
  90  *
  91  * Caller should take care of locking. This function will
  92  * return 0 on success or -ETIMEDOUT.
  93  */
  94 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
  95 {
  96         int             retries = 10000;
  97         u32             reg;
  98
  99         /*
 100          * Wait until device controller is ready. Only applies to 1.94a and
 101          * later RTL.
 102          */
 103         if (dwc->revision >= DWC3_REVISION_194A) {
 104                 while (--retries) {
 105                         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 106                         if (reg & DWC3_DSTS_DCNRD)
 107                                 udelay(5);
 108                         else
 109                                 break;
 110                 }
 111
 112                 if (retries <= 0)
 113                         return -ETIMEDOUT;
 114         }
 115
 116         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 117         reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
 118
 119         /* set requested state */
 120         reg |= DWC3_DCTL_ULSTCHNGREQ(state);
 121         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 122
 123         /*
 124          * The following code is racy when called from dwc3_gadget_wakeup,
 125          * and is not needed, at least on newer versions
 126          */
 127         if (dwc->revision >= DWC3_REVISION_194A)
 128                 return 0;
 129
 130         /* wait for a change in DSTS */
 131         retries = 10000;
 132         while (--retries) {
 133                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 134
 135                 if (DWC3_DSTS_USBLNKST(reg) == state)
 136                         return 0;
 137
 138                 udelay(5);
 139         }
 140
 141         dev_vdbg(dwc->dev, "link state change request timed out\n");
 142
 143         return -ETIMEDOUT;
 144 }
 145
 146 /**
 147  * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
 148  * @dwc: pointer to our context structure
 149  *
 150  * This function will a best effort FIFO allocation in order
 151  * to improve FIFO usage and throughput, while still allowing
 152  * us to enable as many endpoints as possible.
 153  *
 154  * Keep in mind that this operation will be highly dependent
 155  * on the configured size for RAM1 - which contains TxFifo -,
 156  * the amount of endpoints enabled on coreConsultant tool, and
 157  * the width of the Master Bus.
 158  *
 159  * In the ideal world, we would always be able to satisfy the
 160  * following equation:
 161  *
 162  * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \
 163  * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes
 164  *
 165  * Unfortunately, due to many variables that's not always the case.
 166  */
 167 int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc)
 168 {
 169         int             last_fifo_depth = 0;
 170         int             ram1_depth;
 171         int             fifo_size;
 172         int             mdwidth;
 173         int             num;
 174
 175         if (!dwc->needs_fifo_resize)
 176                 return 0;
 177
 178         ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
 179         mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
 180
 181         /* MDWIDTH is represented in bits, we need it in bytes */
 182         mdwidth >>= 3;
 183
 184         /*
 185          * FIXME For now we will only allocate 1 wMaxPacketSize space
 186          * for each enabled endpoint, later patches will come to
 187          * improve this algorithm so that we better use the internal
 188          * FIFO space
 189          */
 190         for (num = 0; num < DWC3_ENDPOINTS_NUM; num++) {
 191                 struct dwc3_ep  *dep = dwc->eps[num];
 192                 int             fifo_number = dep->number >> 1;
 193                 int             mult = 1;
 194                 int             tmp;
 195
 196                 if (!(dep->number & 1))
 197                         continue;
 198
 199                 if (!(dep->flags & DWC3_EP_ENABLED))
 200                         continue;
 201
 202                 if (usb_endpoint_xfer_bulk(dep->endpoint.desc)
 203                                 || usb_endpoint_xfer_isoc(dep->endpoint.desc))
 204                         mult = 3;
 205
 206                 /*
 207                  * REVISIT: the following assumes we will always have enough
 208                  * space available on the FIFO RAM for all possible use cases.
 209                  * Make sure that's true somehow and change FIFO allocation
 210                  * accordingly.
 211                  *
 212                  * If we have Bulk or Isochronous endpoints, we want
 213                  * them to be able to be very, very fast. So we're giving
 214                  * those endpoints a fifo_size which is enough for 3 full
 215                  * packets
 216                  */
 217                 tmp = mult * (dep->endpoint.maxpacket + mdwidth);
 218                 tmp += mdwidth;
 219
 220                 fifo_size = DIV_ROUND_UP(tmp, mdwidth);
 221
 222                 fifo_size |= (last_fifo_depth << 16);
 223
 224                 dev_vdbg(dwc->dev, "%s: Fifo Addr %04x Size %d\n",
 225                                 dep->name, last_fifo_depth, fifo_size & 0xffff);
 226
 227                 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(fifo_number),
 228                                 fifo_size);
 229
 230                 last_fifo_depth += (fifo_size & 0xffff);
 231         }
 232
 233         return 0;
 234 }
 235
 236 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
 237                 int status)
 238 {
 239         struct dwc3                     *dwc = dep->dwc;
 240         int                             i;
 241
 242         if (req->queued) {
 243                 i = 0;
 244                 do {
 245                         dep->busy_slot++;
 246                         /*
 247                          * Skip LINK TRB. We can't use req->trb and check for
 248                          * DWC3_TRBCTL_LINK_TRB because it points the TRB we
 249                          * just completed (not the LINK TRB).
 250                          */
 251                         if (((dep->busy_slot & DWC3_TRB_MASK) ==
 252                                 DWC3_TRB_NUM- 1) &&
 253                                 usb_endpoint_xfer_isoc(dep->endpoint.desc))
 254                                 dep->busy_slot++;
 255                 } while(++i < req->request.num_mapped_sgs);
 256                 req->queued = false;
 257         }
 258         list_del(&req->list);
 259         req->trb = NULL;
 260
 261         if (req->request.status == -EINPROGRESS)
 262                 req->request.status = status;
 263
 264         if (dwc->ep0_bounced && dep->number == 0)
 265                 dwc->ep0_bounced = false;
 266         else
 267                 usb_gadget_unmap_request(&dwc->gadget, &req->request,
 268                                 req->direction);
 269
 270         dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n",
 271                         req, dep->name, req->request.actual,
 272                         req->request.length, status);
 273
 274         spin_unlock(&dwc->lock);
 275         req->request.complete(&dep->endpoint, &req->request);
 276         spin_lock(&dwc->lock);
 277 }
 278
 279 static const char *dwc3_gadget_ep_cmd_string(u8 cmd)
 280 {
 281         switch (cmd) {
 282         case DWC3_DEPCMD_DEPSTARTCFG:
 283                 return "Start New Configuration";
 284         case DWC3_DEPCMD_ENDTRANSFER:
 285                 return "End Transfer";
 286         case DWC3_DEPCMD_UPDATETRANSFER:
 287                 return "Update Transfer";
 288         case DWC3_DEPCMD_STARTTRANSFER:
 289                 return "Start Transfer";
 290         case DWC3_DEPCMD_CLEARSTALL:
 291                 return "Clear Stall";
 292         case DWC3_DEPCMD_SETSTALL:
 293                 return "Set Stall";
 294         case DWC3_DEPCMD_GETEPSTATE:
 295                 return "Get Endpoint State";
 296         case DWC3_DEPCMD_SETTRANSFRESOURCE:
 297                 return "Set Endpoint Transfer Resource";
 298         case DWC3_DEPCMD_SETEPCONFIG:
 299                 return "Set Endpoint Configuration";
 300         default:
 301                 return "UNKNOWN command";
 302         }
 303 }
 304
 305 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, int cmd, u32 param)
 306 {
 307         u32             timeout = 500;
 308         u32             reg;
 309
 310         dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
 311         dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
 312
 313         do {
 314                 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
 315                 if (!(reg & DWC3_DGCMD_CMDACT)) {
 316                         dev_vdbg(dwc->dev, "Command Complete --> %d\n",
 317                                         DWC3_DGCMD_STATUS(reg));
 318                         return 0;
 319                 }
 320
 321                 /*
 322                  * We can't sleep here, because it's also called from
 323                  * interrupt context.
 324                  */
 325                 timeout--;
 326                 if (!timeout)
 327                         return -ETIMEDOUT;
 328                 udelay(1);
 329         } while (1);
 330 }
 331
 332 int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
 333                 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
 334 {
 335         struct dwc3_ep          *dep = dwc->eps[ep];
 336         u32                     timeout = 500;
 337         u32                     reg;
 338
 339         dev_vdbg(dwc->dev, "%s: cmd '%s' params %08x %08x %08x\n",
 340                         dep->name,
 341                         dwc3_gadget_ep_cmd_string(cmd), params->param0,
 342                         params->param1, params->param2);
 343
 344         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
 345         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
 346         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
 347
 348         dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
 349         do {
 350                 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
 351                 if (!(reg & DWC3_DEPCMD_CMDACT)) {
 352                         dev_vdbg(dwc->dev, "Command Complete --> %d\n",
 353                                         DWC3_DEPCMD_STATUS(reg));
 354                         return 0;
 355                 }
 356
 357                 /*
 358                  * We can't sleep here, because it is also called from
 359                  * interrupt context.
 360                  */
 361                 timeout--;
 362                 if (!timeout)
 363                         return -ETIMEDOUT;
 364
 365                 udelay(1);
 366         } while (1);
 367 }
 368
 369 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
 370                 struct dwc3_trb *trb)
 371 {
 372         u32             offset = (char *) trb - (char *) dep->trb_pool;
 373
 374         return dep->trb_pool_dma + offset;
 375 }
 376
 377 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
 378 {
 379         struct dwc3             *dwc = dep->dwc;
 380
 381         if (dep->trb_pool)
 382                 return 0;
 383
 384         if (dep->number == 0 || dep->number == 1)
 385                 return 0;
 386
 387         dep->trb_pool = dma_alloc_coherent(dwc->dev,
 388                         sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 389                         &dep->trb_pool_dma, GFP_KERNEL);
 390         if (!dep->trb_pool) {
 391                 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
 392                                 dep->name);
 393                 return -ENOMEM;
 394         }
 395
 396         return 0;
 397 }
 398
 399 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
 400 {
 401         struct dwc3             *dwc = dep->dwc;
 402
 403         dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 404                         dep->trb_pool, dep->trb_pool_dma);
 405
 406         dep->trb_pool = NULL;
 407         dep->trb_pool_dma = 0;
 408 }
 409
 410 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
 411 {
 412         struct dwc3_gadget_ep_cmd_params params;
 413         u32                     cmd;
 414
 415         memset(&params, 0x00, sizeof(params));
 416
 417         if (dep->number != 1) {
 418                 cmd = DWC3_DEPCMD_DEPSTARTCFG;
 419                 /* XferRscIdx == 0 for ep0 and 2 for the remaining */
 420                 if (dep->number > 1) {
 421                         if (dwc->start_config_issued)
 422                                 return 0;
 423                         dwc->start_config_issued = true;
 424                         cmd |= DWC3_DEPCMD_PARAM(2);
 425                 }
 426
 427                 return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, &params);
 428         }
 429
 430         return 0;
 431 }
 432
 433 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
 434                 const struct usb_endpoint_descriptor *desc,
 435                 const struct usb_ss_ep_comp_descriptor *comp_desc,
 436                 bool ignore, bool restore)
 437 {
 438         struct dwc3_gadget_ep_cmd_params params;
 439
 440         memset(&params, 0x00, sizeof(params));
 441
 442         params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
 443                 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
 444
 445         /* Burst size is only needed in SuperSpeed mode */
 446         if (dwc->gadget.speed == USB_SPEED_SUPER) {
 447                 u32 burst = dep->endpoint.maxburst - 1;
 448
 449                 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst);
 450         }
 451
 452         if (ignore)
 453                 params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM;
 454
 455         if (restore) {
 456                 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
 457                 params.param2 |= dep->saved_state;
 458         }
 459
 460         params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
 461                 | DWC3_DEPCFG_XFER_NOT_READY_EN;
 462
 463         if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
 464                 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
 465                         | DWC3_DEPCFG_STREAM_EVENT_EN;
 466                 dep->stream_capable = true;
 467         }
 468
 469         if (usb_endpoint_xfer_isoc(desc))
 470                 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
 471
 472         /*
 473          * We are doing 1:1 mapping for endpoints, meaning
 474          * Physical Endpoints 2 maps to Logical Endpoint 2 and
 475          * so on. We consider the direction bit as part of the physical
 476          * endpoint number. So USB endpoint 0x81 is 0x03.
 477          */
 478         params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
 479
 480         /*
 481          * We must use the lower 16 TX FIFOs even though
 482          * HW might have more
 483          */
 484         if (dep->direction)
 485                 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
 486
 487         if (desc->bInterval) {
 488                 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
 489                 dep->interval = 1 << (desc->bInterval - 1);
 490         }
 491
 492         return dwc3_send_gadget_ep_cmd(dwc, dep->number,
 493                         DWC3_DEPCMD_SETEPCONFIG, &params);
 494 }
 495
 496 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
 497 {
 498         struct dwc3_gadget_ep_cmd_params params;
 499
 500         memset(&params, 0x00, sizeof(params));
 501
 502         params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
 503
 504         return dwc3_send_gadget_ep_cmd(dwc, dep->number,
 505                         DWC3_DEPCMD_SETTRANSFRESOURCE, &params);
 506 }
 507
 508 /**
 509  * __dwc3_gadget_ep_enable - Initializes a HW endpoint
 510  * @dep: endpoint to be initialized
 511  * @desc: USB Endpoint Descriptor
 512  *
 513  * Caller should take care of locking
 514  */
 515 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
 516                 const struct usb_endpoint_descriptor *desc,
 517                 const struct usb_ss_ep_comp_descriptor *comp_desc,
 518                 bool ignore, bool restore)
 519 {
 520         struct dwc3             *dwc = dep->dwc;
 521         u32                     reg;
 522         int                     ret = -ENOMEM;
 523
 524         dev_vdbg(dwc->dev, "Enabling %s\n", dep->name);
 525
 526         if (!(dep->flags & DWC3_EP_ENABLED)) {
 527                 ret = dwc3_gadget_start_config(dwc, dep);
 528                 if (ret)
 529                         return ret;
 530         }
 531
 532         ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore,
 533                         restore);
 534         if (ret)
 535                 return ret;
 536
 537         if (!(dep->flags & DWC3_EP_ENABLED)) {
 538                 struct dwc3_trb *trb_st_hw;
 539                 struct dwc3_trb *trb_link;
 540
 541                 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
 542                 if (ret)
 543                         return ret;
 544
 545                 dep->endpoint.desc = desc;
 546                 dep->comp_desc = comp_desc;
 547                 dep->type = usb_endpoint_type(desc);
 548                 dep->flags |= DWC3_EP_ENABLED;
 549
 550                 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 551                 reg |= DWC3_DALEPENA_EP(dep->number);
 552                 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 553
 554                 if (!usb_endpoint_xfer_isoc(desc))
 555                         return 0;
 556
 557                 memset(&trb_link, 0, sizeof(trb_link));
 558
 559                 /* Link TRB for ISOC. The HWO bit is never reset */
 560                 trb_st_hw = &dep->trb_pool[0];
 561
 562                 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
 563
 564                 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 565                 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 566                 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
 567                 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
 568         }
 569
 570         return 0;
 571 }
 572
 573 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
 574 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
 575 {
 576         struct dwc3_request             *req;
 577
 578         if (!list_empty(&dep->req_queued)) {
 579                 dwc3_stop_active_transfer(dwc, dep->number, true);
 580
 581                 /* - giveback all requests to gadget driver */
 582                 while (!list_empty(&dep->req_queued)) {
 583                         req = next_request(&dep->req_queued);
 584
 585                         dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 586                 }
 587         }
 588
 589         while (!list_empty(&dep->request_list)) {
 590                 req = next_request(&dep->request_list);
 591
 592                 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 593         }
 594 }
 595
 596 /**
 597  * __dwc3_gadget_ep_disable - Disables a HW endpoint
 598  * @dep: the endpoint to disable
 599  *
 600  * This function also removes requests which are currently processed ny the
 601  * hardware and those which are not yet scheduled.
 602  * Caller should take care of locking.
 603  */
 604 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
 605 {
 606         struct dwc3             *dwc = dep->dwc;
 607         u32                     reg;
 608
 609         dwc3_remove_requests(dwc, dep);
 610
 611         reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 612         reg &= ~DWC3_DALEPENA_EP(dep->number);
 613         dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 614
 615         dep->stream_capable = false;
 616         dep->endpoint.desc = NULL;
 617         dep->comp_desc = NULL;
 618         dep->type = 0;
 619         dep->flags = 0;
 620
 621         return 0;
 622 }
 623
 624 /* -------------------------------------------------------------------------- */
 625
 626 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
 627                 const struct usb_endpoint_descriptor *desc)
 628 {
 629         return -EINVAL;
 630 }
 631
 632 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
 633 {
 634         return -EINVAL;
 635 }
 636
 637 /* -------------------------------------------------------------------------- */
 638
 639 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
 640                 const struct usb_endpoint_descriptor *desc)
 641 {
 642         struct dwc3_ep                  *dep;
 643         struct dwc3                     *dwc;
 644         unsigned long                   flags;
 645         int                             ret;
 646
 647         if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
 648                 pr_debug("dwc3: invalid parameters\n");
 649                 return -EINVAL;
 650         }
 651
 652         if (!desc->wMaxPacketSize) {
 653                 pr_debug("dwc3: missing wMaxPacketSize\n");
 654                 return -EINVAL;
 655         }
 656
 657         dep = to_dwc3_ep(ep);
 658         dwc = dep->dwc;
 659
 660         if (dep->flags & DWC3_EP_ENABLED) {
 661                 dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n",
 662                                 dep->name);
 663                 return 0;
 664         }
 665
 666         switch (usb_endpoint_type(desc)) {
 667         case USB_ENDPOINT_XFER_CONTROL:
 668                 strlcat(dep->name, "-control", sizeof(dep->name));
 669                 break;
 670         case USB_ENDPOINT_XFER_ISOC:
 671                 strlcat(dep->name, "-isoc", sizeof(dep->name));
 672                 break;
 673         case USB_ENDPOINT_XFER_BULK:
 674                 strlcat(dep->name, "-bulk", sizeof(dep->name));
 675                 break;
 676         case USB_ENDPOINT_XFER_INT:
 677                 strlcat(dep->name, "-int", sizeof(dep->name));
 678                 break;
 679         default:
 680                 dev_err(dwc->dev, "invalid endpoint transfer type\n");
 681         }
 682
 683         spin_lock_irqsave(&dwc->lock, flags);
 684         ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false);
 685         spin_unlock_irqrestore(&dwc->lock, flags);
 686
 687         return ret;
 688 }
 689
 690 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
 691 {
 692         struct dwc3_ep                  *dep;
 693         struct dwc3                     *dwc;
 694         unsigned long                   flags;
 695         int                             ret;
 696
 697         if (!ep) {
 698                 pr_debug("dwc3: invalid parameters\n");
 699                 return -EINVAL;
 700         }
 701
 702         dep = to_dwc3_ep(ep);
 703         dwc = dep->dwc;
 704
 705         if (!(dep->flags & DWC3_EP_ENABLED)) {
 706                 dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n",
 707                                 dep->name);
 708                 return 0;
 709         }
 710
 711         snprintf(dep->name, sizeof(dep->name), "ep%d%s",
 712                         dep->number >> 1,
 713                         (dep->number & 1) ? "in" : "out");
 714
 715         spin_lock_irqsave(&dwc->lock, flags);
 716         ret = __dwc3_gadget_ep_disable(dep);
 717         spin_unlock_irqrestore(&dwc->lock, flags);
 718
 719         return ret;
 720 }
 721
 722 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
 723         gfp_t gfp_flags)
 724 {
 725         struct dwc3_request             *req;
 726         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 727         struct dwc3                     *dwc = dep->dwc;
 728
 729         req = kzalloc(sizeof(*req), gfp_flags);
 730         if (!req) {
 731                 dev_err(dwc->dev, "not enough memory\n");
 732                 return NULL;
 733         }
 734
 735         req->epnum      = dep->number;
 736         req->dep        = dep;
 737
 738         return &req->request;
 739 }
 740
 741 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
 742                 struct usb_request *request)
 743 {
 744         struct dwc3_request             *req = to_dwc3_request(request);
 745
 746         kfree(req);
 747 }
 748
 749 /**
 750  * dwc3_prepare_one_trb - setup one TRB from one request
 751  * @dep: endpoint for which this request is prepared
 752  * @req: dwc3_request pointer
 753  */
 754 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
 755                 struct dwc3_request *req, dma_addr_t dma,
 756                 unsigned length, unsigned last, unsigned chain, unsigned node)
 757 {
 758         struct dwc3             *dwc = dep->dwc;
 759         struct dwc3_trb         *trb;
 760
 761         dev_vdbg(dwc->dev, "%s: req %p dma %08llx length %d%s%s\n",
 762                         dep->name, req, (unsigned long long) dma,
 763                         length, last ? " last" : "",
 764                         chain ? " chain" : "");
 765
 766         /* Skip the LINK-TRB on ISOC */
 767         if (((dep->free_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
 768                         usb_endpoint_xfer_isoc(dep->endpoint.desc))
 769                 dep->free_slot++;
 770
 771         trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
 772
 773         if (!req->trb) {
 774                 dwc3_gadget_move_request_queued(req);
 775                 req->trb = trb;
 776                 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
 777                 req->start_slot = dep->free_slot & DWC3_TRB_MASK;
 778         }
 779
 780         dep->free_slot++;
 781
 782         trb->size = DWC3_TRB_SIZE_LENGTH(length);
 783         trb->bpl = lower_32_bits(dma);
 784         trb->bph = upper_32_bits(dma);
 785
 786         switch (usb_endpoint_type(dep->endpoint.desc)) {
 787         case USB_ENDPOINT_XFER_CONTROL:
 788                 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
 789                 break;
 790
 791         case USB_ENDPOINT_XFER_ISOC:
 792                 if (!node)
 793                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
 794                 else
 795                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
 796                 break;
 797
 798         case USB_ENDPOINT_XFER_BULK:
 799         case USB_ENDPOINT_XFER_INT:
 800                 trb->ctrl = DWC3_TRBCTL_NORMAL;
 801                 break;
 802         default:
 803                 /*
 804                  * This is only possible with faulty memory because we
 805                  * checked it already :)
 806                  */
 807                 BUG();
 808         }
 809
 810         if (!req->request.no_interrupt && !chain)
 811                 trb->ctrl |= DWC3_TRB_CTRL_IOC;
 812
 813         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
 814                 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
 815                 trb->ctrl |= DWC3_TRB_CTRL_CSP;
 816         } else if (last) {
 817                 trb->ctrl |= DWC3_TRB_CTRL_LST;
 818         }
 819
 820         if (chain)
 821                 trb->ctrl |= DWC3_TRB_CTRL_CHN;
 822
 823         if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
 824                 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
 825
 826         trb->ctrl |= DWC3_TRB_CTRL_HWO;
 827 }
 828
 829 /*
 830  * dwc3_prepare_trbs - setup TRBs from requests
 831  * @dep: endpoint for which requests are being prepared
 832  * @starting: true if the endpoint is idle and no requests are queued.
 833  *
 834  * The function goes through the requests list and sets up TRBs for the
 835  * transfers. The function returns once there are no more TRBs available or
 836  * it runs out of requests.
 837  */
 838 static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
 839 {
 840         struct dwc3_request     *req, *n;
 841         u32                     trbs_left;
 842         u32                     max;
 843         unsigned int            last_one = 0;
 844
 845         BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
 846
 847         /* the first request must not be queued */
 848         trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
 849
 850         /* Can't wrap around on a non-isoc EP since there's no link TRB */
 851         if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
 852                 max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK);
 853                 if (trbs_left > max)
 854                         trbs_left = max;
 855         }
 856
 857         /*
 858          * If busy & slot are equal than it is either full or empty. If we are
 859          * starting to process requests then we are empty. Otherwise we are
 860          * full and don't do anything
 861          */
 862         if (!trbs_left) {
 863                 if (!starting)
 864                         return;
 865                 trbs_left = DWC3_TRB_NUM;
 866                 /*
 867                  * In case we start from scratch, we queue the ISOC requests
 868                  * starting from slot 1. This is done because we use ring
 869                  * buffer and have no LST bit to stop us. Instead, we place
 870                  * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
 871                  * after the first request so we start at slot 1 and have
 872                  * 7 requests proceed before we hit the first IOC.
 873                  * Other transfer types don't use the ring buffer and are
 874                  * processed from the first TRB until the last one. Since we
 875                  * don't wrap around we have to start at the beginning.
 876                  */
 877                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
 878                         dep->busy_slot = 1;
 879                         dep->free_slot = 1;
 880                 } else {
 881                         dep->busy_slot = 0;
 882                         dep->free_slot = 0;
 883                 }
 884         }
 885
 886         /* The last TRB is a link TRB, not used for xfer */
 887         if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc))
 888                 return;
 889
 890         list_for_each_entry_safe(req, n, &dep->request_list, list) {
 891                 unsigned        length;
 892                 dma_addr_t      dma;
 893                 last_one = false;
 894
 895                 if (req->request.num_mapped_sgs > 0) {
 896                         struct usb_request *request = &req->request;
 897                         struct scatterlist *sg = request->sg;
 898                         struct scatterlist *s;
 899                         int             i;
 900
 901                         for_each_sg(sg, s, request->num_mapped_sgs, i) {
 902                                 unsigned chain = true;
 903
 904                                 length = sg_dma_len(s);
 905                                 dma = sg_dma_address(s);
 906
 907                                 if (i == (request->num_mapped_sgs - 1) ||
 908                                                 sg_is_last(s)) {
 909                                         if (list_is_last(&req->list,
 910                                                         &dep->request_list))
 911                                                 last_one = true;
 912                                         chain = false;
 913                                 }
 914
 915                                 trbs_left--;
 916                                 if (!trbs_left)
 917                                         last_one = true;
 918
 919                                 if (last_one)
 920                                         chain = false;
 921
 922                                 dwc3_prepare_one_trb(dep, req, dma, length,
 923                                                 last_one, chain, i);
 924
 925                                 if (last_one)
 926                                         break;
 927                         }
 928                 } else {
 929                         dma = req->request.dma;
 930                         length = req->request.length;
 931                         trbs_left--;
 932
 933                         if (!trbs_left)
 934                                 last_one = 1;
 935
 936                         /* Is this the last request? */
 937                         if (list_is_last(&req->list, &dep->request_list))
 938                                 last_one = 1;
 939
 940                         dwc3_prepare_one_trb(dep, req, dma, length,
 941                                         last_one, false, 0);
 942
 943                         if (last_one)
 944                                 break;
 945                 }
 946         }
 947 }
 948
 949 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
 950                 int start_new)
 951 {
 952         struct dwc3_gadget_ep_cmd_params params;
 953         struct dwc3_request             *req;
 954         struct dwc3                     *dwc = dep->dwc;
 955         int                             ret;
 956         u32                             cmd;
 957
 958         if (start_new && (dep->flags & DWC3_EP_BUSY)) {
 959                 dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name);
 960                 return -EBUSY;
 961         }
 962         dep->flags &= ~DWC3_EP_PENDING_REQUEST;
 963
 964         /*
 965          * If we are getting here after a short-out-packet we don't enqueue any
 966          * new requests as we try to set the IOC bit only on the last request.
 967          */
 968         if (start_new) {
 969                 if (list_empty(&dep->req_queued))
 970                         dwc3_prepare_trbs(dep, start_new);
 971
 972                 /* req points to the first request which will be sent */
 973                 req = next_request(&dep->req_queued);
 974         } else {
 975                 dwc3_prepare_trbs(dep, start_new);
 976
 977                 /*
 978                  * req points to the first request where HWO changed from 0 to 1
 979                  */
 980                 req = next_request(&dep->req_queued);
 981         }
 982         if (!req) {
 983                 dep->flags |= DWC3_EP_PENDING_REQUEST;
 984                 return 0;
 985         }
 986
 987         memset(&params, 0, sizeof(params));
 988
 989         if (start_new) {
 990                 params.param0 = upper_32_bits(req->trb_dma);
 991                 params.param1 = lower_32_bits(req->trb_dma);
 992                 cmd = DWC3_DEPCMD_STARTTRANSFER;
 993         } else {
 994                 cmd = DWC3_DEPCMD_UPDATETRANSFER;
 995         }
 996
 997         cmd |= DWC3_DEPCMD_PARAM(cmd_param);
 998         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
 999         if (ret < 0) {
1000                 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
1001
1002                 /*
1003                  * FIXME we need to iterate over the list of requests
1004                  * here and stop, unmap, free and del each of the linked
1005                  * requests instead of what we do now.
1006                  */
1007                 usb_gadget_unmap_request(&dwc->gadget, &req->request,
1008                                 req->direction);
1009                 list_del(&req->list);
1010                 return ret;
1011         }
1012
1013         dep->flags |= DWC3_EP_BUSY;
1014
1015         if (start_new) {
1016                 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
1017                                 dep->number);
1018                 WARN_ON_ONCE(!dep->resource_index);
1019         }
1020
1021         return 0;
1022 }
1023
1024 static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1025                 struct dwc3_ep *dep, u32 cur_uf)
1026 {
1027         u32 uf;
1028
1029         if (list_empty(&dep->request_list)) {
1030                 dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n",
1031                         dep->name);
1032                 dep->flags |= DWC3_EP_PENDING_REQUEST;
1033                 return;
1034         }
1035
1036         /* 4 micro frames in the future */
1037         uf = cur_uf + dep->interval * 4;
1038
1039         __dwc3_gadget_kick_transfer(dep, uf, 1);
1040 }
1041
1042 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1043                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1044 {
1045         u32 cur_uf, mask;
1046
1047         mask = ~(dep->interval - 1);
1048         cur_uf = event->parameters & mask;
1049
1050         __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1051 }
1052
1053 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1054 {
1055         struct dwc3             *dwc = dep->dwc;
1056         int                     ret;
1057
1058         req->request.actual     = 0;
1059         req->request.status     = -EINPROGRESS;
1060         req->direction          = dep->direction;
1061         req->epnum              = dep->number;
1062
1063         /*
1064          * We only add to our list of requests now and
1065          * start consuming the list once we get XferNotReady
1066          * IRQ.
1067          *
1068          * That way, we avoid doing anything that we don't need
1069          * to do now and defer it until the point we receive a
1070          * particular token from the Host side.
1071          *
1072          * This will also avoid Host cancelling URBs due to too
1073          * many NAKs.
1074          */
1075         ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1076                         dep->direction);
1077         if (ret)
1078                 return ret;
1079
1080         list_add_tail(&req->list, &dep->request_list);
1081
1082         /*
1083          * There are a few special cases:
1084          *
1085          * 1. XferNotReady with empty list of requests. We need to kick the
1086          *    transfer here in that situation, otherwise we will be NAKing
1087          *    forever. If we get XferNotReady before gadget driver has a
1088          *    chance to queue a request, we will ACK the IRQ but won't be
1089          *    able to receive the data until the next request is queued.
1090          *    The following code is handling exactly that.
1091          *
1092          */
1093         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
1094                 /*
1095                  * If xfernotready is already elapsed and it is a case
1096                  * of isoc transfer, then issue END TRANSFER, so that
1097                  * you can receive xfernotready again and can have
1098                  * notion of current microframe.
1099                  */
1100                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1101                         if (list_empty(&dep->req_queued)) {
1102                                 dwc3_stop_active_transfer(dwc, dep->number, true);
1103                                 dep->flags = DWC3_EP_ENABLED;
1104                         }
1105                         return 0;
1106                 }
1107
1108                 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1109                 if (ret && ret != -EBUSY)
1110                         dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1111                                         dep->name);
1112                 return ret;
1113         }
1114
1115         /*
1116          * 2. XferInProgress on Isoc EP with an active transfer. We need to
1117          *    kick the transfer here after queuing a request, otherwise the
1118          *    core may not see the modified TRB(s).
1119          */
1120         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1121                         (dep->flags & DWC3_EP_BUSY) &&
1122                         !(dep->flags & DWC3_EP_MISSED_ISOC)) {
1123                 WARN_ON_ONCE(!dep->resource_index);
1124                 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index,
1125                                 false);
1126                 if (ret && ret != -EBUSY)
1127                         dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1128                                         dep->name);
1129                 return ret;
1130         }
1131
1132         /*
1133          * 4. Stream Capable Bulk Endpoints. We need to start the transfer
1134          * right away, otherwise host will not know we have streams to be
1135          * handled.
1136          */
1137         if (dep->stream_capable) {
1138                 int     ret;
1139
1140                 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1141                 if (ret && ret != -EBUSY) {
1142                         struct dwc3     *dwc = dep->dwc;
1143
1144                         dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1145                                         dep->name);
1146                 }
1147         }
1148
1149         return 0;
1150 }
1151
1152 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1153         gfp_t gfp_flags)
1154 {
1155         struct dwc3_request             *req = to_dwc3_request(request);
1156         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1157         struct dwc3                     *dwc = dep->dwc;
1158
1159         unsigned long                   flags;
1160
1161         int                             ret;
1162
1163         if (!dep->endpoint.desc) {
1164                 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
1165                                 request, ep->name);
1166                 return -ESHUTDOWN;
1167         }
1168
1169         dev_vdbg(dwc->dev, "queing request %p to %s length %d\n",
1170                         request, ep->name, request->length);
1171
1172         spin_lock_irqsave(&dwc->lock, flags);
1173         ret = __dwc3_gadget_ep_queue(dep, req);
1174         spin_unlock_irqrestore(&dwc->lock, flags);
1175
1176         return ret;
1177 }
1178
1179 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1180                 struct usb_request *request)
1181 {
1182         struct dwc3_request             *req = to_dwc3_request(request);
1183         struct dwc3_request             *r = NULL;
1184
1185         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1186         struct dwc3                     *dwc = dep->dwc;
1187
1188         unsigned long                   flags;
1189         int                             ret = 0;
1190
1191         spin_lock_irqsave(&dwc->lock, flags);
1192
1193         list_for_each_entry(r, &dep->request_list, list) {
1194                 if (r == req)
1195                         break;
1196         }
1197
1198         if (r != req) {
1199                 list_for_each_entry(r, &dep->req_queued, list) {
1200                         if (r == req)
1201                                 break;
1202                 }
1203                 if (r == req) {
1204                         /* wait until it is processed */
1205                         dwc3_stop_active_transfer(dwc, dep->number, true);
1206                         goto out1;
1207                 }
1208                 dev_err(dwc->dev, "request %p was not queued to %s\n",
1209                                 request, ep->name);
1210                 ret = -EINVAL;
1211                 goto out0;
1212         }
1213
1214 out1:
1215         /* giveback the request */
1216         dwc3_gadget_giveback(dep, req, -ECONNRESET);
1217
1218 out0:
1219         spin_unlock_irqrestore(&dwc->lock, flags);
1220
1221         return ret;
1222 }
1223
1224 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value)
1225 {
1226         struct dwc3_gadget_ep_cmd_params        params;
1227         struct dwc3                             *dwc = dep->dwc;
1228         int                                     ret;
1229
1230         memset(&params, 0x00, sizeof(params));
1231
1232         if (value) {
1233                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1234                         DWC3_DEPCMD_SETSTALL, &params);
1235                 if (ret)
1236                         dev_err(dwc->dev, "failed to set STALL on %s\n",
1237                                         dep->name);
1238                 else
1239                         dep->flags |= DWC3_EP_STALL;
1240         } else {
1241                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1242                         DWC3_DEPCMD_CLEARSTALL, &params);
1243                 if (ret)
1244                         dev_err(dwc->dev, "failed to clear STALL on %s\n",
1245                                         dep->name);
1246                 else
1247                         dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1248         }
1249
1250         return ret;
1251 }
1252
1253 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1254 {
1255         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1256         struct dwc3                     *dwc = dep->dwc;
1257
1258         unsigned long                   flags;
1259
1260         int                             ret;
1261
1262         spin_lock_irqsave(&dwc->lock, flags);
1263
1264         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1265                 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1266                 ret = -EINVAL;
1267                 goto out;
1268         }
1269
1270         ret = __dwc3_gadget_ep_set_halt(dep, value);
1271 out:
1272         spin_unlock_irqrestore(&dwc->lock, flags);
1273
1274         return ret;
1275 }
1276
1277 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1278 {
1279         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1280         struct dwc3                     *dwc = dep->dwc;
1281         unsigned long                   flags;
1282
1283         spin_lock_irqsave(&dwc->lock, flags);
1284         dep->flags |= DWC3_EP_WEDGE;
1285         spin_unlock_irqrestore(&dwc->lock, flags);
1286
1287         if (dep->number == 0 || dep->number == 1)
1288                 return dwc3_gadget_ep0_set_halt(ep, 1);
1289         else
1290                 return dwc3_gadget_ep_set_halt(ep, 1);
1291 }
1292
1293 /* -------------------------------------------------------------------------- */
1294
1295 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1296         .bLength        = USB_DT_ENDPOINT_SIZE,
1297         .bDescriptorType = USB_DT_ENDPOINT,
1298         .bmAttributes   = USB_ENDPOINT_XFER_CONTROL,
1299 };
1300
1301 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1302         .enable         = dwc3_gadget_ep0_enable,
1303         .disable        = dwc3_gadget_ep0_disable,
1304         .alloc_request  = dwc3_gadget_ep_alloc_request,
1305         .free_request   = dwc3_gadget_ep_free_request,
1306         .queue          = dwc3_gadget_ep0_queue,
1307         .dequeue        = dwc3_gadget_ep_dequeue,
1308         .set_halt       = dwc3_gadget_ep0_set_halt,
1309         .set_wedge      = dwc3_gadget_ep_set_wedge,
1310 };
1311
1312 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1313         .enable         = dwc3_gadget_ep_enable,
1314         .disable        = dwc3_gadget_ep_disable,
1315         .alloc_request  = dwc3_gadget_ep_alloc_request,
1316         .free_request   = dwc3_gadget_ep_free_request,
1317         .queue          = dwc3_gadget_ep_queue,
1318         .dequeue        = dwc3_gadget_ep_dequeue,
1319         .set_halt       = dwc3_gadget_ep_set_halt,
1320         .set_wedge      = dwc3_gadget_ep_set_wedge,
1321 };
1322
1323 /* -------------------------------------------------------------------------- */
1324
1325 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1326 {
1327         struct dwc3             *dwc = gadget_to_dwc(g);
1328         u32                     reg;
1329
1330         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1331         return DWC3_DSTS_SOFFN(reg);
1332 }
1333
1334 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1335 {
1336         struct dwc3             *dwc = gadget_to_dwc(g);
1337
1338         unsigned long           timeout;
1339         unsigned long           flags;
1340
1341         u32                     reg;
1342
1343         int                     ret = 0;
1344
1345         u8                      link_state;
1346         u8                      speed;
1347
1348         spin_lock_irqsave(&dwc->lock, flags);
1349
1350         /*
1351          * According to the Databook Remote wakeup request should
1352          * be issued only when the device is in early suspend state.
1353          *
1354          * We can check that via USB Link State bits in DSTS register.
1355          */
1356         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1357
1358         speed = reg & DWC3_DSTS_CONNECTSPD;
1359         if (speed == DWC3_DSTS_SUPERSPEED) {
1360                 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n");
1361                 ret = -EINVAL;
1362                 goto out;
1363         }
1364
1365         link_state = DWC3_DSTS_USBLNKST(reg);
1366
1367         switch (link_state) {
1368         case DWC3_LINK_STATE_RX_DET:    /* in HS, means Early Suspend */
1369         case DWC3_LINK_STATE_U3:        /* in HS, means SUSPEND */
1370                 break;
1371         default:
1372                 dev_dbg(dwc->dev, "can't wakeup from link state %d\n",
1373                                 link_state);
1374                 ret = -EINVAL;
1375                 goto out;
1376         }
1377
1378         ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1379         if (ret < 0) {
1380                 dev_err(dwc->dev, "failed to put link in Recovery\n");
1381                 goto out;
1382         }
1383
1384         /* Recent versions do this automatically */
1385         if (dwc->revision < DWC3_REVISION_194A) {
1386                 /* write zeroes to Link Change Request */
1387                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1388                 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1389                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1390         }
1391
1392         /* poll until Link State changes to ON */
1393         timeout = jiffies + msecs_to_jiffies(100);
1394
1395         while (!time_after(jiffies, timeout)) {
1396                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1397
1398                 /* in HS, means ON */
1399                 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1400                         break;
1401         }
1402
1403         if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1404                 dev_err(dwc->dev, "failed to send remote wakeup\n");
1405                 ret = -EINVAL;
1406         }
1407
1408 out:
1409         spin_unlock_irqrestore(&dwc->lock, flags);
1410
1411         return ret;
1412 }
1413
1414 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1415                 int is_selfpowered)
1416 {
1417         struct dwc3             *dwc = gadget_to_dwc(g);
1418         unsigned long           flags;
1419
1420         spin_lock_irqsave(&dwc->lock, flags);
1421         dwc->is_selfpowered = !!is_selfpowered;
1422         spin_unlock_irqrestore(&dwc->lock, flags);
1423
1424         return 0;
1425 }
1426
1427 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1428 {
1429         u32                     reg;
1430         u32                     timeout = 500;
1431
1432         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1433         if (is_on) {
1434                 if (dwc->revision <= DWC3_REVISION_187A) {
1435                         reg &= ~DWC3_DCTL_TRGTULST_MASK;
1436                         reg |= DWC3_DCTL_TRGTULST_RX_DET;
1437                 }
1438
1439                 if (dwc->revision >= DWC3_REVISION_194A)
1440                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1441                 reg |= DWC3_DCTL_RUN_STOP;
1442
1443                 if (dwc->has_hibernation)
1444                         reg |= DWC3_DCTL_KEEP_CONNECT;
1445
1446                 dwc->pullups_connected = true;
1447         } else {
1448                 reg &= ~DWC3_DCTL_RUN_STOP;
1449
1450                 if (dwc->has_hibernation && !suspend)
1451                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1452
1453                 dwc->pullups_connected = false;
1454         }
1455
1456         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1457
1458         do {
1459                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1460                 if (is_on) {
1461                         if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1462                                 break;
1463                 } else {
1464                         if (reg & DWC3_DSTS_DEVCTRLHLT)
1465                                 break;
1466                 }
1467                 timeout--;
1468                 if (!timeout)
1469                         return -ETIMEDOUT;
1470                 udelay(1);
1471         } while (1);
1472
1473         dev_vdbg(dwc->dev, "gadget %s data soft-%s\n",
1474                         dwc->gadget_driver
1475                         ? dwc->gadget_driver->function : "no-function",
1476                         is_on ? "connect" : "disconnect");
1477
1478         return 0;
1479 }
1480
1481 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1482 {
1483         struct dwc3             *dwc = gadget_to_dwc(g);
1484         unsigned long           flags;
1485         int                     ret;
1486
1487         is_on = !!is_on;
1488
1489         spin_lock_irqsave(&dwc->lock, flags);
1490         ret = dwc3_gadget_run_stop(dwc, is_on, false);
1491         spin_unlock_irqrestore(&dwc->lock, flags);
1492
1493         return ret;
1494 }
1495
1496 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1497 {
1498         u32                     reg;
1499
1500         /* Enable all but Start and End of Frame IRQs */
1501         reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1502                         DWC3_DEVTEN_EVNTOVERFLOWEN |
1503                         DWC3_DEVTEN_CMDCMPLTEN |
1504                         DWC3_DEVTEN_ERRTICERREN |
1505                         DWC3_DEVTEN_WKUPEVTEN |
1506                         DWC3_DEVTEN_ULSTCNGEN |
1507                         DWC3_DEVTEN_CONNECTDONEEN |
1508                         DWC3_DEVTEN_USBRSTEN |
1509                         DWC3_DEVTEN_DISCONNEVTEN);
1510
1511         dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1512 }
1513
1514 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1515 {
1516         /* mask all interrupts */
1517         dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1518 }
1519
1520 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1521 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1522
1523 static int dwc3_gadget_start(struct usb_gadget *g,
1524                 struct usb_gadget_driver *driver)
1525 {
1526         struct dwc3             *dwc = gadget_to_dwc(g);
1527         struct dwc3_ep          *dep;
1528         unsigned long           flags;
1529         int                     ret = 0;
1530         int                     irq;
1531         u32                     reg;
1532
1533         irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1534         ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1535                         IRQF_SHARED, "dwc3", dwc);
1536         if (ret) {
1537                 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1538                                 irq, ret);
1539                 goto err0;
1540         }
1541
1542         spin_lock_irqsave(&dwc->lock, flags);
1543
1544         if (dwc->gadget_driver) {
1545                 dev_err(dwc->dev, "%s is already bound to %s\n",
1546                                 dwc->gadget.name,
1547                                 dwc->gadget_driver->driver.name);
1548                 ret = -EBUSY;
1549                 goto err1;
1550         }
1551
1552         dwc->gadget_driver      = driver;
1553
1554         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1555         reg &= ~(DWC3_DCFG_SPEED_MASK);
1556
1557         /**
1558          * WORKAROUND: DWC3 revision < 2.20a have an issue
1559          * which would cause metastability state on Run/Stop
1560          * bit if we try to force the IP to USB2-only mode.
1561          *
1562          * Because of that, we cannot configure the IP to any
1563          * speed other than the SuperSpeed
1564          *
1565          * Refers to:
1566          *
1567          * STAR#9000525659: Clock Domain Crossing on DCTL in
1568          * USB 2.0 Mode
1569          */
1570         if (dwc->revision < DWC3_REVISION_220A) {
1571                 reg |= DWC3_DCFG_SUPERSPEED;
1572         } else {
1573                 switch (dwc->maximum_speed) {
1574                 case USB_SPEED_LOW:
1575                         reg |= DWC3_DSTS_LOWSPEED;
1576                         break;
1577                 case USB_SPEED_FULL:
1578                         reg |= DWC3_DSTS_FULLSPEED1;
1579                         break;
1580                 case USB_SPEED_HIGH:
1581                         reg |= DWC3_DSTS_HIGHSPEED;
1582                         break;
1583                 case USB_SPEED_SUPER:   /* FALLTHROUGH */
1584                 case USB_SPEED_UNKNOWN: /* FALTHROUGH */
1585                 default:
1586                         reg |= DWC3_DSTS_SUPERSPEED;
1587                 }
1588         }
1589         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1590
1591         dwc->start_config_issued = false;
1592
1593         /* Start with SuperSpeed Default */
1594         dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1595
1596         dep = dwc->eps[0];
1597         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1598                         false);
1599         if (ret) {
1600                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1601                 goto err2;
1602         }
1603
1604         dep = dwc->eps[1];
1605         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1606                         false);
1607         if (ret) {
1608                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1609                 goto err3;
1610         }
1611
1612         /* begin to receive SETUP packets */
1613         dwc->ep0state = EP0_SETUP_PHASE;
1614         dwc3_ep0_out_start(dwc);
1615
1616         dwc3_gadget_enable_irq(dwc);
1617
1618         spin_unlock_irqrestore(&dwc->lock, flags);
1619
1620         return 0;
1621
1622 err3:
1623         __dwc3_gadget_ep_disable(dwc->eps[0]);
1624
1625 err2:
1626         dwc->gadget_driver = NULL;
1627
1628 err1:
1629         spin_unlock_irqrestore(&dwc->lock, flags);
1630
1631         free_irq(irq, dwc);
1632
1633 err0:
1634         return ret;
1635 }
1636
1637 static int dwc3_gadget_stop(struct usb_gadget *g,
1638                 struct usb_gadget_driver *driver)
1639 {
1640         struct dwc3             *dwc = gadget_to_dwc(g);
1641         unsigned long           flags;
1642         int                     irq;
1643
1644         spin_lock_irqsave(&dwc->lock, flags);
1645
1646         dwc3_gadget_disable_irq(dwc);
1647         __dwc3_gadget_ep_disable(dwc->eps[0]);
1648         __dwc3_gadget_ep_disable(dwc->eps[1]);
1649
1650         dwc->gadget_driver      = NULL;
1651
1652         spin_unlock_irqrestore(&dwc->lock, flags);
1653
1654         irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1655         free_irq(irq, dwc);
1656
1657         return 0;
1658 }
1659
1660 static const struct usb_gadget_ops dwc3_gadget_ops = {
1661         .get_frame              = dwc3_gadget_get_frame,
1662         .wakeup                 = dwc3_gadget_wakeup,
1663         .set_selfpowered        = dwc3_gadget_set_selfpowered,
1664         .pullup                 = dwc3_gadget_pullup,
1665         .udc_start              = dwc3_gadget_start,
1666         .udc_stop               = dwc3_gadget_stop,
1667 };
1668
1669 /* -------------------------------------------------------------------------- */
1670
1671 static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
1672                 u8 num, u32 direction)
1673 {
1674         struct dwc3_ep                  *dep;
1675         u8                              i;
1676
1677         for (i = 0; i < num; i++) {
1678                 u8 epnum = (i << 1) | (!!direction);
1679
1680                 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1681                 if (!dep) {
1682                         dev_err(dwc->dev, "can't allocate endpoint %d\n",
1683                                         epnum);
1684                         return -ENOMEM;
1685                 }
1686
1687                 dep->dwc = dwc;
1688                 dep->number = epnum;
1689                 dep->direction = !!direction;
1690                 dwc->eps[epnum] = dep;
1691
1692                 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1693                                 (epnum & 1) ? "in" : "out");
1694
1695                 dep->endpoint.name = dep->name;
1696
1697                 dev_vdbg(dwc->dev, "initializing %s\n", dep->name);
1698
1699                 if (epnum == 0 || epnum == 1) {
1700                         usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
1701                         dep->endpoint.maxburst = 1;
1702                         dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1703                         if (!epnum)
1704                                 dwc->gadget.ep0 = &dep->endpoint;
1705                 } else {
1706                         int             ret;
1707
1708                         usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
1709                         dep->endpoint.max_streams = 15;
1710                         dep->endpoint.ops = &dwc3_gadget_ep_ops;
1711                         list_add_tail(&dep->endpoint.ep_list,
1712                                         &dwc->gadget.ep_list);
1713
1714                         ret = dwc3_alloc_trb_pool(dep);
1715                         if (ret)
1716                                 return ret;
1717                 }
1718
1719                 INIT_LIST_HEAD(&dep->request_list);
1720                 INIT_LIST_HEAD(&dep->req_queued);
1721         }
1722
1723         return 0;
1724 }
1725
1726 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1727 {
1728         int                             ret;
1729
1730         INIT_LIST_HEAD(&dwc->gadget.ep_list);
1731
1732         ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
1733         if (ret < 0) {
1734                 dev_vdbg(dwc->dev, "failed to allocate OUT endpoints\n");
1735                 return ret;
1736         }
1737
1738         ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
1739         if (ret < 0) {
1740                 dev_vdbg(dwc->dev, "failed to allocate IN endpoints\n");
1741                 return ret;
1742         }
1743
1744         return 0;
1745 }
1746
1747 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1748 {
1749         struct dwc3_ep                  *dep;
1750         u8                              epnum;
1751
1752         for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1753                 dep = dwc->eps[epnum];
1754                 if (!dep)
1755                         continue;
1756                 /*
1757                  * Physical endpoints 0 and 1 are special; they form the
1758                  * bi-directional USB endpoint 0.
1759                  *
1760                  * For those two physical endpoints, we don't allocate a TRB
1761                  * pool nor do we add them the endpoints list. Due to that, we
1762                  * shouldn't do these two operations otherwise we would end up
1763                  * with all sorts of bugs when removing dwc3.ko.
1764                  */
1765                 if (epnum != 0 && epnum != 1) {
1766                         dwc3_free_trb_pool(dep);
1767                         list_del(&dep->endpoint.ep_list);
1768                 }
1769
1770                 kfree(dep);
1771         }
1772 }
1773
1774 /* -------------------------------------------------------------------------- */
1775
1776 static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
1777                 struct dwc3_request *req, struct dwc3_trb *trb,
1778                 const struct dwc3_event_depevt *event, int status)
1779 {
1780         unsigned int            count;
1781         unsigned int            s_pkt = 0;
1782         unsigned int            trb_status;
1783
1784         if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1785                 /*
1786                  * We continue despite the error. There is not much we
1787                  * can do. If we don't clean it up we loop forever. If
1788                  * we skip the TRB then it gets overwritten after a
1789                  * while since we use them in a ring buffer. A BUG()
1790                  * would help. Lets hope that if this occurs, someone
1791                  * fixes the root cause instead of looking away :)
1792                  */
1793                 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1794                                 dep->name, trb);
1795         count = trb->size & DWC3_TRB_SIZE_MASK;
1796
1797         if (dep->direction) {
1798                 if (count) {
1799                         trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1800                         if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
1801                                 dev_dbg(dwc->dev, "incomplete IN transfer %s\n",
1802                                                 dep->name);
1803                                 /*
1804                                  * If missed isoc occurred and there is
1805                                  * no request queued then issue END
1806                                  * TRANSFER, so that core generates
1807                                  * next xfernotready and we will issue
1808                                  * a fresh START TRANSFER.
1809                                  * If there are still queued request
1810                                  * then wait, do not issue either END
1811                                  * or UPDATE TRANSFER, just attach next
1812                                  * request in request_list during
1813                                  * giveback.If any future queued request
1814                                  * is successfully transferred then we
1815                                  * will issue UPDATE TRANSFER for all
1816                                  * request in the request_list.
1817                                  */
1818                                 dep->flags |= DWC3_EP_MISSED_ISOC;
1819                         } else {
1820                                 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1821                                                 dep->name);
1822                                 status = -ECONNRESET;
1823                         }
1824                 } else {
1825                         dep->flags &= ~DWC3_EP_MISSED_ISOC;
1826                 }
1827         } else {
1828                 if (count && (event->status & DEPEVT_STATUS_SHORT))
1829                         s_pkt = 1;
1830         }
1831
1832         /*
1833          * We assume here we will always receive the entire data block
1834          * which we should receive. Meaning, if we program RX to
1835          * receive 4K but we receive only 2K, we assume that's all we
1836          * should receive and we simply bounce the request back to the
1837          * gadget driver for further processing.
1838          */
1839         req->request.actual += req->request.length - count;
1840         if (s_pkt)
1841                 return 1;
1842         if ((event->status & DEPEVT_STATUS_LST) &&
1843                         (trb->ctrl & (DWC3_TRB_CTRL_LST |
1844                                 DWC3_TRB_CTRL_HWO)))
1845                 return 1;
1846         if ((event->status & DEPEVT_STATUS_IOC) &&
1847                         (trb->ctrl & DWC3_TRB_CTRL_IOC))
1848                 return 1;
1849         return 0;
1850 }
1851
1852 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1853                 const struct dwc3_event_depevt *event, int status)
1854 {
1855         struct dwc3_request     *req;
1856         struct dwc3_trb         *trb;
1857         unsigned int            slot;
1858         unsigned int            i;
1859         int                     ret;
1860
1861         do {
1862                 req = next_request(&dep->req_queued);
1863                 if (!req) {
1864                         WARN_ON_ONCE(1);
1865                         return 1;
1866                 }
1867                 i = 0;
1868                 do {
1869                         slot = req->start_slot + i;
1870                         if ((slot == DWC3_TRB_NUM - 1) &&
1871                                 usb_endpoint_xfer_isoc(dep->endpoint.desc))
1872                                 slot++;
1873                         slot %= DWC3_TRB_NUM;
1874                         trb = &dep->trb_pool[slot];
1875
1876                         ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
1877                                         event, status);
1878                         if (ret)
1879                                 break;
1880                 }while (++i < req->request.num_mapped_sgs);
1881
1882                 dwc3_gadget_giveback(dep, req, status);
1883
1884                 if (ret)
1885                         break;
1886         } while (1);
1887
1888         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1889                         list_empty(&dep->req_queued)) {
1890                 if (list_empty(&dep->request_list)) {
1891                         /*
1892                          * If there is no entry in request list then do
1893                          * not issue END TRANSFER now. Just set PENDING
1894                          * flag, so that END TRANSFER is issued when an
1895                          * entry is added into request list.
1896                          */
1897                         dep->flags = DWC3_EP_PENDING_REQUEST;
1898                 } else {
1899                         dwc3_stop_active_transfer(dwc, dep->number, true);
1900                         dep->flags = DWC3_EP_ENABLED;
1901                 }
1902                 return 1;
1903         }
1904
1905         return 1;
1906 }
1907
1908 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
1909                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event,
1910                 int start_new)
1911 {
1912         unsigned                status = 0;
1913         int                     clean_busy;
1914
1915         if (event->status & DEPEVT_STATUS_BUSERR)
1916                 status = -ECONNRESET;
1917
1918         clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
1919         if (clean_busy)
1920                 dep->flags &= ~DWC3_EP_BUSY;
1921
1922         /*
1923          * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
1924          * See dwc3_gadget_linksts_change_interrupt() for 1st half.
1925          */
1926         if (dwc->revision < DWC3_REVISION_183A) {
1927                 u32             reg;
1928                 int             i;
1929
1930                 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
1931                         dep = dwc->eps[i];
1932
1933                         if (!(dep->flags & DWC3_EP_ENABLED))
1934                                 continue;
1935
1936                         if (!list_empty(&dep->req_queued))
1937                                 return;
1938                 }
1939
1940                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1941                 reg |= dwc->u1u2;
1942                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1943
1944                 dwc->u1u2 = 0;
1945         }
1946 }
1947
1948 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
1949                 const struct dwc3_event_depevt *event)
1950 {
1951         struct dwc3_ep          *dep;
1952         u8                      epnum = event->endpoint_number;
1953
1954         dep = dwc->eps[epnum];
1955
1956         if (!(dep->flags & DWC3_EP_ENABLED))
1957                 return;
1958
1959         dev_vdbg(dwc->dev, "%s: %s\n", dep->name,
1960                         dwc3_ep_event_string(event->endpoint_event));
1961
1962         if (epnum == 0 || epnum == 1) {
1963                 dwc3_ep0_interrupt(dwc, event);
1964                 return;
1965         }
1966
1967         switch (event->endpoint_event) {
1968         case DWC3_DEPEVT_XFERCOMPLETE:
1969                 dep->resource_index = 0;
1970
1971                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1972                         dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n",
1973                                         dep->name);
1974                         return;
1975                 }
1976
1977                 dwc3_endpoint_transfer_complete(dwc, dep, event, 1);
1978                 break;
1979         case DWC3_DEPEVT_XFERINPROGRESS:
1980                 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1981                         dev_dbg(dwc->dev, "%s is not an Isochronous endpoint\n",
1982                                         dep->name);
1983                         return;
1984                 }
1985
1986                 dwc3_endpoint_transfer_complete(dwc, dep, event, 0);
1987                 break;
1988         case DWC3_DEPEVT_XFERNOTREADY:
1989                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1990                         dwc3_gadget_start_isoc(dwc, dep, event);
1991                 } else {
1992                         int ret;
1993
1994                         dev_vdbg(dwc->dev, "%s: reason %s\n",
1995                                         dep->name, event->status &
1996                                         DEPEVT_STATUS_TRANSFER_ACTIVE
1997                                         ? "Transfer Active"
1998                                         : "Transfer Not Active");
1999
2000                         ret = __dwc3_gadget_kick_transfer(dep, 0, 1);
2001                         if (!ret || ret == -EBUSY)
2002                                 return;
2003
2004                         dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
2005                                         dep->name);
2006                 }
2007
2008                 break;
2009         case DWC3_DEPEVT_STREAMEVT:
2010                 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
2011                         dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
2012                                         dep->name);
2013                         return;
2014                 }
2015
2016                 switch (event->status) {
2017                 case DEPEVT_STREAMEVT_FOUND:
2018                         dev_vdbg(dwc->dev, "Stream %d found and started\n",
2019                                         event->parameters);
2020
2021                         break;
2022                 case DEPEVT_STREAMEVT_NOTFOUND:
2023                         /* FALLTHROUGH */
2024                 default:
2025                         dev_dbg(dwc->dev, "Couldn't find suitable stream\n");
2026                 }
2027                 break;
2028         case DWC3_DEPEVT_RXTXFIFOEVT:
2029                 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name);
2030                 break;
2031         case DWC3_DEPEVT_EPCMDCMPLT:
2032                 dev_vdbg(dwc->dev, "Endpoint Command Complete\n");
2033                 break;
2034         }
2035 }
2036
2037 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2038 {
2039         if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2040                 spin_unlock(&dwc->lock);
2041                 dwc->gadget_driver->disconnect(&dwc->gadget);
2042                 spin_lock(&dwc->lock);
2043         }
2044 }
2045
2046 static void dwc3_suspend_gadget(struct dwc3 *dwc)
2047 {
2048         if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
2049                 spin_unlock(&dwc->lock);
2050                 dwc->gadget_driver->suspend(&dwc->gadget);
2051                 spin_lock(&dwc->lock);
2052         }
2053 }
2054
2055 static void dwc3_resume_gadget(struct dwc3 *dwc)
2056 {
2057         if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2058                 spin_unlock(&dwc->lock);
2059                 dwc->gadget_driver->resume(&dwc->gadget);
2060                 spin_lock(&dwc->lock);
2061         }
2062 }
2063
2064 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
2065 {
2066         struct dwc3_ep *dep;
2067         struct dwc3_gadget_ep_cmd_params params;
2068         u32 cmd;
2069         int ret;
2070
2071         dep = dwc->eps[epnum];
2072
2073         if (!dep->resource_index)
2074                 return;
2075
2076         /*
2077          * NOTICE: We are violating what the Databook says about the
2078          * EndTransfer command. Ideally we would _always_ wait for the
2079          * EndTransfer Command Completion IRQ, but that's causing too
2080          * much trouble synchronizing between us and gadget driver.
2081          *
2082          * We have discussed this with the IP Provider and it was
2083          * suggested to giveback all requests here, but give HW some
2084          * extra time to synchronize with the interconnect. We're using
2085          * an arbitraty 100us delay for that.
2086          *
2087          * Note also that a similar handling was tested by Synopsys
2088          * (thanks a lot Paul) and nothing bad has come out of it.
2089          * In short, what we're doing is:
2090          *
2091          * - Issue EndTransfer WITH CMDIOC bit set
2092          * - Wait 100us
2093          */
2094
2095         cmd = DWC3_DEPCMD_ENDTRANSFER;
2096         cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2097         cmd |= DWC3_DEPCMD_CMDIOC;
2098         cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2099         memset(&params, 0, sizeof(params));
2100         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
2101         WARN_ON_ONCE(ret);
2102         dep->resource_index = 0;
2103         dep->flags &= ~DWC3_EP_BUSY;
2104         udelay(100);
2105 }
2106
2107 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2108 {
2109         u32 epnum;
2110
2111         for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2112                 struct dwc3_ep *dep;
2113
2114                 dep = dwc->eps[epnum];
2115                 if (!dep)
2116                         continue;
2117
2118                 if (!(dep->flags & DWC3_EP_ENABLED))
2119                         continue;
2120
2121                 dwc3_remove_requests(dwc, dep);
2122         }
2123 }
2124
2125 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2126 {
2127         u32 epnum;
2128
2129         for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2130                 struct dwc3_ep *dep;
2131                 struct dwc3_gadget_ep_cmd_params params;
2132                 int ret;
2133
2134                 dep = dwc->eps[epnum];
2135                 if (!dep)
2136                         continue;
2137
2138                 if (!(dep->flags & DWC3_EP_STALL))
2139                         continue;
2140
2141                 dep->flags &= ~DWC3_EP_STALL;
2142
2143                 memset(&params, 0, sizeof(params));
2144                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
2145                                 DWC3_DEPCMD_CLEARSTALL, &params);
2146                 WARN_ON_ONCE(ret);
2147         }
2148 }
2149
2150 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2151 {
2152         int                     reg;
2153
2154         dev_vdbg(dwc->dev, "%s\n", __func__);
2155
2156         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2157         reg &= ~DWC3_DCTL_INITU1ENA;
2158         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2159
2160         reg &= ~DWC3_DCTL_INITU2ENA;
2161         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2162
2163         dwc3_disconnect_gadget(dwc);
2164         dwc->start_config_issued = false;
2165
2166         dwc->gadget.speed = USB_SPEED_UNKNOWN;
2167         dwc->setup_packet_pending = false;
2168 }
2169
2170 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2171 {
2172         u32                     reg;
2173
2174         dev_vdbg(dwc->dev, "%s\n", __func__);
2175
2176         /*
2177          * WORKAROUND: DWC3 revisions <1.88a have an issue which
2178          * would cause a missing Disconnect Event if there's a
2179          * pending Setup Packet in the FIFO.
2180          *
2181          * There's no suggested workaround on the official Bug
2182          * report, which states that "unless the driver/application
2183          * is doing any special handling of a disconnect event,
2184          * there is no functional issue".
2185          *
2186          * Unfortunately, it turns out that we _do_ some special
2187          * handling of a disconnect event, namely complete all
2188          * pending transfers, notify gadget driver of the
2189          * disconnection, and so on.
2190          *
2191          * Our suggested workaround is to follow the Disconnect
2192          * Event steps here, instead, based on a setup_packet_pending
2193          * flag. Such flag gets set whenever we have a XferNotReady
2194          * event on EP0 and gets cleared on XferComplete for the
2195          * same endpoint.
2196          *
2197          * Refers to:
2198          *
2199          * STAR#9000466709: RTL: Device : Disconnect event not
2200          * generated if setup packet pending in FIFO
2201          */
2202         if (dwc->revision < DWC3_REVISION_188A) {
2203                 if (dwc->setup_packet_pending)
2204                         dwc3_gadget_disconnect_interrupt(dwc);
2205         }
2206
2207         /* after reset -> Default State */
2208         usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT);
2209
2210         if (dwc->gadget.speed != USB_SPEED_UNKNOWN)
2211                 dwc3_disconnect_gadget(dwc);
2212
2213         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2214         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2215         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2216         dwc->test_mode = false;
2217
2218         dwc3_stop_active_transfers(dwc);
2219         dwc3_clear_stall_all_ep(dwc);
2220         dwc->start_config_issued = false;
2221
2222         /* Reset device address to zero */
2223         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2224         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2225         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2226 }
2227
2228 static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2229 {
2230         u32 reg;
2231         u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2232
2233         /*
2234          * We change the clock only at SS but I dunno why I would want to do
2235          * this. Maybe it becomes part of the power saving plan.
2236          */
2237
2238         if (speed != DWC3_DSTS_SUPERSPEED)
2239                 return;
2240
2241         /*
2242          * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2243          * each time on Connect Done.
2244          */
2245         if (!usb30_clock)
2246                 return;
2247
2248         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2249         reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2250         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2251 }
2252
2253 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2254 {
2255         struct dwc3_ep          *dep;
2256         int                     ret;
2257         u32                     reg;
2258         u8                      speed;
2259
2260         dev_vdbg(dwc->dev, "%s\n", __func__);
2261
2262         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2263         speed = reg & DWC3_DSTS_CONNECTSPD;
2264         dwc->speed = speed;
2265
2266         dwc3_update_ram_clk_sel(dwc, speed);
2267
2268         switch (speed) {
2269         case DWC3_DCFG_SUPERSPEED:
2270                 /*
2271                  * WORKAROUND: DWC3 revisions <1.90a have an issue which
2272                  * would cause a missing USB3 Reset event.
2273                  *
2274                  * In such situations, we should force a USB3 Reset
2275                  * event by calling our dwc3_gadget_reset_interrupt()
2276                  * routine.
2277                  *
2278                  * Refers to:
2279                  *
2280                  * STAR#9000483510: RTL: SS : USB3 reset event may
2281                  * not be generated always when the link enters poll
2282                  */
2283                 if (dwc->revision < DWC3_REVISION_190A)
2284                         dwc3_gadget_reset_interrupt(dwc);
2285
2286                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2287                 dwc->gadget.ep0->maxpacket = 512;
2288                 dwc->gadget.speed = USB_SPEED_SUPER;
2289                 break;
2290         case DWC3_DCFG_HIGHSPEED:
2291                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2292                 dwc->gadget.ep0->maxpacket = 64;
2293                 dwc->gadget.speed = USB_SPEED_HIGH;
2294                 break;
2295         case DWC3_DCFG_FULLSPEED2:
2296         case DWC3_DCFG_FULLSPEED1:
2297                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2298                 dwc->gadget.ep0->maxpacket = 64;
2299                 dwc->gadget.speed = USB_SPEED_FULL;
2300                 break;
2301         case DWC3_DCFG_LOWSPEED:
2302                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2303                 dwc->gadget.ep0->maxpacket = 8;
2304                 dwc->gadget.speed = USB_SPEED_LOW;
2305                 break;
2306         }
2307
2308         /* Enable USB2 LPM Capability */
2309
2310         if ((dwc->revision > DWC3_REVISION_194A)
2311                         && (speed != DWC3_DCFG_SUPERSPEED)) {
2312                 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2313                 reg |= DWC3_DCFG_LPM_CAP;
2314                 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2315
2316                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2317                 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2318
2319                 /*
2320                  * TODO: This should be configurable. For now using
2321                  * maximum allowed HIRD threshold value of 0b1100
2322                  */
2323                 reg |= DWC3_DCTL_HIRD_THRES(12);
2324
2325                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2326         } else {
2327                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2328                 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2329                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2330         }
2331
2332         dep = dwc->eps[0];
2333         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2334                         false);
2335         if (ret) {
2336                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2337                 return;
2338         }
2339
2340         dep = dwc->eps[1];
2341         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2342                         false);
2343         if (ret) {
2344                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2345                 return;
2346         }
2347
2348         /*
2349          * Configure PHY via GUSB3PIPECTLn if required.
2350          *
2351          * Update GTXFIFOSIZn
2352          *
2353          * In both cases reset values should be sufficient.
2354          */
2355 }
2356
2357 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2358 {
2359         dev_vdbg(dwc->dev, "%s\n", __func__);
2360
2361         /*
2362          * TODO take core out of low power mode when that's
2363          * implemented.
2364          */
2365
2366         dwc->gadget_driver->resume(&dwc->gadget);
2367 }
2368
2369 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2370                 unsigned int evtinfo)
2371 {
2372         enum dwc3_link_state    next = evtinfo & DWC3_LINK_STATE_MASK;
2373         unsigned int            pwropt;
2374
2375         /*
2376          * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2377          * Hibernation mode enabled which would show up when device detects
2378          * host-initiated U3 exit.
2379          *
2380          * In that case, device will generate a Link State Change Interrupt
2381          * from U3 to RESUME which is only necessary if Hibernation is
2382          * configured in.
2383          *
2384          * There are no functional changes due to such spurious event and we
2385          * just need to ignore it.
2386          *
2387          * Refers to:
2388          *
2389          * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2390          * operational mode
2391          */
2392         pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2393         if ((dwc->revision < DWC3_REVISION_250A) &&
2394                         (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2395                 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2396                                 (next == DWC3_LINK_STATE_RESUME)) {
2397                         dev_vdbg(dwc->dev, "ignoring transition U3 -> Resume\n");
2398                         return;
2399                 }
2400         }
2401
2402         /*
2403          * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2404          * on the link partner, the USB session might do multiple entry/exit
2405          * of low power states before a transfer takes place.
2406          *
2407          * Due to this problem, we might experience lower throughput. The
2408          * suggested workaround is to disable DCTL[12:9] bits if we're
2409          * transitioning from U1/U2 to U0 and enable those bits again
2410          * after a transfer completes and there are no pending transfers
2411          * on any of the enabled endpoints.
2412          *
2413          * This is the first half of that workaround.
2414          *
2415          * Refers to:
2416          *
2417          * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2418          * core send LGO_Ux entering U0
2419          */
2420         if (dwc->revision < DWC3_REVISION_183A) {
2421                 if (next == DWC3_LINK_STATE_U0) {
2422                         u32     u1u2;
2423                         u32     reg;
2424
2425                         switch (dwc->link_state) {
2426                         case DWC3_LINK_STATE_U1:
2427                         case DWC3_LINK_STATE_U2:
2428                                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2429                                 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2430                                                 | DWC3_DCTL_ACCEPTU2ENA
2431                                                 | DWC3_DCTL_INITU1ENA
2432                                                 | DWC3_DCTL_ACCEPTU1ENA);
2433
2434                                 if (!dwc->u1u2)
2435                                         dwc->u1u2 = reg & u1u2;
2436
2437                                 reg &= ~u1u2;
2438
2439                                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2440                                 break;
2441                         default:
2442                                 /* do nothing */
2443                                 break;
2444                         }
2445                 }
2446         }
2447
2448         dwc->link_state = next;
2449
2450         switch (next) {
2451         case DWC3_LINK_STATE_U1:
2452                 if (dwc->speed == USB_SPEED_SUPER)
2453                         dwc3_suspend_gadget(dwc);
2454                 break;
2455         case DWC3_LINK_STATE_U2:
2456         case DWC3_LINK_STATE_U3:
2457                 dwc3_suspend_gadget(dwc);
2458                 break;
2459         case DWC3_LINK_STATE_RESUME:
2460                 dwc3_resume_gadget(dwc);
2461                 break;
2462         default:
2463                 /* do nothing */
2464                 break;
2465         }
2466
2467         dev_vdbg(dwc->dev, "%s link %d\n", __func__, dwc->link_state);
2468 }
2469
2470 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2471                 unsigned int evtinfo)
2472 {
2473         unsigned int is_ss = evtinfo & BIT(4);
2474
2475         /**
2476          * WORKAROUND: DWC3 revison 2.20a with hibernation support
2477          * have a known issue which can cause USB CV TD.9.23 to fail
2478          * randomly.
2479          *
2480          * Because of this issue, core could generate bogus hibernation
2481          * events which SW needs to ignore.
2482          *
2483          * Refers to:
2484          *
2485          * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2486          * Device Fallback from SuperSpeed
2487          */
2488         if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2489                 return;
2490
2491         /* enter hibernation here */
2492 }
2493
2494 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2495                 const struct dwc3_event_devt *event)
2496 {
2497         switch (event->type) {
2498         case DWC3_DEVICE_EVENT_DISCONNECT:
2499                 dwc3_gadget_disconnect_interrupt(dwc);
2500                 break;
2501         case DWC3_DEVICE_EVENT_RESET:
2502                 dwc3_gadget_reset_interrupt(dwc);
2503                 break;
2504         case DWC3_DEVICE_EVENT_CONNECT_DONE:
2505                 dwc3_gadget_conndone_interrupt(dwc);
2506                 break;
2507         case DWC3_DEVICE_EVENT_WAKEUP:
2508                 dwc3_gadget_wakeup_interrupt(dwc);
2509                 break;
2510         case DWC3_DEVICE_EVENT_HIBER_REQ:
2511                 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
2512                                         "unexpected hibernation event\n"))
2513                         break;
2514
2515                 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2516                 break;
2517         case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2518                 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2519                 break;
2520         case DWC3_DEVICE_EVENT_EOPF:
2521                 dev_vdbg(dwc->dev, "End of Periodic Frame\n");
2522                 break;
2523         case DWC3_DEVICE_EVENT_SOF:
2524                 dev_vdbg(dwc->dev, "Start of Periodic Frame\n");
2525                 break;
2526         case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2527                 dev_vdbg(dwc->dev, "Erratic Error\n");
2528                 break;
2529         case DWC3_DEVICE_EVENT_CMD_CMPL:
2530                 dev_vdbg(dwc->dev, "Command Complete\n");
2531                 break;
2532         case DWC3_DEVICE_EVENT_OVERFLOW:
2533                 dev_vdbg(dwc->dev, "Overflow\n");
2534                 break;
2535         default:
2536                 dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2537         }
2538 }
2539
2540 static void dwc3_process_event_entry(struct dwc3 *dwc,
2541                 const union dwc3_event *event)
2542 {
2543         /* Endpoint IRQ, handle it and return early */
2544         if (event->type.is_devspec == 0) {
2545                 /* depevt */
2546                 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2547         }
2548
2549         switch (event->type.type) {
2550         case DWC3_EVENT_TYPE_DEV:
2551                 dwc3_gadget_interrupt(dwc, &event->devt);
2552                 break;
2553         /* REVISIT what to do with Carkit and I2C events ? */
2554         default:
2555                 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2556         }
2557 }
2558
2559 static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
2560 {
2561         struct dwc3_event_buffer *evt;
2562         irqreturn_t ret = IRQ_NONE;
2563         int left;
2564         u32 reg;
2565
2566         evt = dwc->ev_buffs[buf];
2567         left = evt->count;
2568
2569         if (!(evt->flags & DWC3_EVENT_PENDING))
2570                 return IRQ_NONE;
2571
2572         while (left > 0) {
2573                 union dwc3_event event;
2574
2575                 event.raw = *(u32 *) (evt->buf + evt->lpos);
2576
2577                 dwc3_process_event_entry(dwc, &event);
2578
2579                 /*
2580                  * FIXME we wrap around correctly to the next entry as
2581                  * almost all entries are 4 bytes in size. There is one
2582                  * entry which has 12 bytes which is a regular entry
2583                  * followed by 8 bytes data. ATM I don't know how
2584                  * things are organized if we get next to the a
2585                  * boundary so I worry about that once we try to handle
2586                  * that.
2587                  */
2588                 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2589                 left -= 4;
2590
2591                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4);
2592         }
2593
2594         evt->count = 0;
2595         evt->flags &= ~DWC3_EVENT_PENDING;
2596         ret = IRQ_HANDLED;
2597
2598         /* Unmask interrupt */
2599         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2600         reg &= ~DWC3_GEVNTSIZ_INTMASK;
2601         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
2602
2603         return ret;
2604 }
2605
2606 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc)
2607 {
2608         struct dwc3 *dwc = _dwc;
2609         unsigned long flags;
2610         irqreturn_t ret = IRQ_NONE;
2611         int i;
2612
2613         spin_lock_irqsave(&dwc->lock, flags);
2614
2615         for (i = 0; i < dwc->num_event_buffers; i++)
2616                 ret |= dwc3_process_event_buf(dwc, i);
2617
2618         spin_unlock_irqrestore(&dwc->lock, flags);
2619
2620         return ret;
2621 }
2622
2623 static irqreturn_t dwc3_check_event_buf(struct dwc3 *dwc, u32 buf)
2624 {
2625         struct dwc3_event_buffer *evt;
2626         u32 count;
2627         u32 reg;
2628
2629         evt = dwc->ev_buffs[buf];
2630
2631         count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
2632         count &= DWC3_GEVNTCOUNT_MASK;
2633         if (!count)
2634                 return IRQ_NONE;
2635
2636         evt->count = count;
2637         evt->flags |= DWC3_EVENT_PENDING;
2638
2639         /* Mask interrupt */
2640         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2641         reg |= DWC3_GEVNTSIZ_INTMASK;
2642         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
2643
2644         return IRQ_WAKE_THREAD;
2645 }
2646
2647 static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
2648 {
2649         struct dwc3                     *dwc = _dwc;
2650         int                             i;
2651         irqreturn_t                     ret = IRQ_NONE;
2652
2653         spin_lock(&dwc->lock);
2654
2655         for (i = 0; i < dwc->num_event_buffers; i++) {
2656                 irqreturn_t status;
2657
2658                 status = dwc3_check_event_buf(dwc, i);
2659                 if (status == IRQ_WAKE_THREAD)
2660                         ret = status;
2661         }
2662
2663         spin_unlock(&dwc->lock);
2664
2665         return ret;
2666 }
2667
2668 /**
2669  * dwc3_gadget_init - Initializes gadget related registers
2670  * @dwc: pointer to our controller context structure
2671  *
2672  * Returns 0 on success otherwise negative errno.
2673  */
2674 int dwc3_gadget_init(struct dwc3 *dwc)
2675 {
2676         int                                     ret;
2677
2678         dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2679                         &dwc->ctrl_req_addr, GFP_KERNEL);
2680         if (!dwc->ctrl_req) {
2681                 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2682                 ret = -ENOMEM;
2683                 goto err0;
2684         }
2685
2686         dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2687                         &dwc->ep0_trb_addr, GFP_KERNEL);
2688         if (!dwc->ep0_trb) {
2689                 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2690                 ret = -ENOMEM;
2691                 goto err1;
2692         }
2693
2694         dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
2695         if (!dwc->setup_buf) {
2696                 dev_err(dwc->dev, "failed to allocate setup buffer\n");
2697                 ret = -ENOMEM;
2698                 goto err2;
2699         }
2700
2701         dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
2702                         DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
2703                         GFP_KERNEL);
2704         if (!dwc->ep0_bounce) {
2705                 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2706                 ret = -ENOMEM;
2707                 goto err3;
2708         }
2709
2710         dwc->gadget.ops                 = &dwc3_gadget_ops;
2711         dwc->gadget.max_speed           = USB_SPEED_SUPER;
2712         dwc->gadget.speed               = USB_SPEED_UNKNOWN;
2713         dwc->gadget.sg_supported        = true;
2714         dwc->gadget.name                = "dwc3-gadget";
2715
2716         /*
2717          * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
2718          * on ep out.
2719          */
2720         dwc->gadget.quirk_ep_out_aligned_size = true;
2721
2722         /*
2723          * REVISIT: Here we should clear all pending IRQs to be
2724          * sure we're starting from a well known location.
2725          */
2726
2727         ret = dwc3_gadget_init_endpoints(dwc);
2728         if (ret)
2729                 goto err4;
2730
2731         ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2732         if (ret) {
2733                 dev_err(dwc->dev, "failed to register udc\n");
2734                 goto err4;
2735         }
2736
2737         return 0;
2738
2739 err4:
2740         dwc3_gadget_free_endpoints(dwc);
2741         dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2742                         dwc->ep0_bounce, dwc->ep0_bounce_addr);
2743
2744 err3:
2745         kfree(dwc->setup_buf);
2746
2747 err2:
2748         dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2749                         dwc->ep0_trb, dwc->ep0_trb_addr);
2750
2751 err1:
2752         dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2753                         dwc->ctrl_req, dwc->ctrl_req_addr);
2754
2755 err0:
2756         return ret;
2757 }
2758
2759 /* -------------------------------------------------------------------------- */
2760
2761 void dwc3_gadget_exit(struct dwc3 *dwc)
2762 {
2763         usb_del_gadget_udc(&dwc->gadget);
2764
2765         dwc3_gadget_free_endpoints(dwc);
2766
2767         dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2768                         dwc->ep0_bounce, dwc->ep0_bounce_addr);
2769
2770         kfree(dwc->setup_buf);
2771
2772         dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2773                         dwc->ep0_trb, dwc->ep0_trb_addr);
2774
2775         dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2776                         dwc->ctrl_req, dwc->ctrl_req_addr);
2777 }
2778
2779 int dwc3_gadget_prepare(struct dwc3 *dwc)
2780 {
2781         if (dwc->pullups_connected) {
2782                 dwc3_gadget_disable_irq(dwc);
2783                 dwc3_gadget_run_stop(dwc, true, true);
2784         }
2785
2786         return 0;
2787 }
2788
2789 void dwc3_gadget_complete(struct dwc3 *dwc)
2790 {
2791         if (dwc->pullups_connected) {
2792                 dwc3_gadget_enable_irq(dwc);
2793                 dwc3_gadget_run_stop(dwc, true, false);
2794         }
2795 }
2796
2797 int dwc3_gadget_suspend(struct dwc3 *dwc)
2798 {
2799         __dwc3_gadget_ep_disable(dwc->eps[0]);
2800         __dwc3_gadget_ep_disable(dwc->eps[1]);
2801
2802         dwc->dcfg = dwc3_readl(dwc->regs, DWC3_DCFG);
2803
2804         return 0;
2805 }
2806
2807 int dwc3_gadget_resume(struct dwc3 *dwc)
2808 {
2809         struct dwc3_ep          *dep;
2810         int                     ret;
2811
2812         /* Start with SuperSpeed Default */
2813         dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2814
2815         dep = dwc->eps[0];
2816         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
2817                         false);
2818         if (ret)
2819                 goto err0;
2820
2821         dep = dwc->eps[1];
2822         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
2823                         false);
2824         if (ret)
2825                 goto err1;
2826
2827         /* begin to receive SETUP packets */
2828         dwc->ep0state = EP0_SETUP_PHASE;
2829         dwc3_ep0_out_start(dwc);
2830
2831         dwc3_writel(dwc->regs, DWC3_DCFG, dwc->dcfg);
2832
2833         return 0;
2834
2835 err1:
2836         __dwc3_gadget_ep_disable(dwc->eps[0]);
2837
2838 err0:
2839         return ret;
2840 }