drivers/usb/dwc3/gadget.c

   1 /**
   2  * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
   3  *
   4  * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/gadget.c) and ported
  10  * to uboot.
  11  *
  12  * commit 8e74475b0e : usb: dwc3: gadget: use udc-core's reset notifier
  13  *
  14  * SPDX-License-Identifier:     GPL-2.0
  15  */
  16
  17 #include <common.h>
  18 #include <malloc.h>
  19 #include <asm/dma-mapping.h>
  20 #include <usb/lin_gadget_compat.h>
  21 #include <linux/list.h>
  22
  23 #include <linux/usb/ch9.h>
  24 #include <linux/usb/gadget.h>
  25 #include <asm/arch/sys_proto.h>
  26
  27 #include "core.h"
  28 #include "gadget.h"
  29 #include "io.h"
  30
  31 #include "linux-compat.h"
  32
  33 /**
  34  * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
  35  * @dwc: pointer to our context structure
  36  * @mode: the mode to set (J, K SE0 NAK, Force Enable)
  37  *
  38  * Caller should take care of locking. This function will
  39  * return 0 on success or -EINVAL if wrong Test Selector
  40  * is passed
  41  */
  42 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
  43 {
  44         u32             reg;
  45
  46         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  47         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
  48
  49         switch (mode) {
  50         case TEST_J:
  51         case TEST_K:
  52         case TEST_SE0_NAK:
  53         case TEST_PACKET:
  54         case TEST_FORCE_EN:
  55                 reg |= mode << 1;
  56                 break;
  57         default:
  58                 return -EINVAL;
  59         }
  60
  61         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  62
  63         return 0;
  64 }
  65
  66 /**
  67  * dwc3_gadget_get_link_state - Gets current state of USB Link
  68  * @dwc: pointer to our context structure
  69  *
  70  * Caller should take care of locking. This function will
  71  * return the link state on success (>= 0) or -ETIMEDOUT.
  72  */
  73 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
  74 {
  75         u32             reg;
  76
  77         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
  78
  79         return DWC3_DSTS_USBLNKST(reg);
  80 }
  81
  82 /**
  83  * dwc3_gadget_set_link_state - Sets USB Link to a particular State
  84  * @dwc: pointer to our context structure
  85  * @state: the state to put link into
  86  *
  87  * Caller should take care of locking. This function will
  88  * return 0 on success or -ETIMEDOUT.
  89  */
  90 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
  91 {
  92         int             retries = 10000;
  93         u32             reg;
  94
  95         /*
  96          * Wait until device controller is ready. Only applies to 1.94a and
  97          * later RTL.
  98          */
  99         if (dwc->revision >= DWC3_REVISION_194A) {
 100                 while (--retries) {
 101                         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 102                         if (reg & DWC3_DSTS_DCNRD)
 103                                 udelay(5);
 104                         else
 105                                 break;
 106                 }
 107
 108                 if (retries <= 0)
 109                         return -ETIMEDOUT;
 110         }
 111
 112         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 113         reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
 114
 115         /* set requested state */
 116         reg |= DWC3_DCTL_ULSTCHNGREQ(state);
 117         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 118
 119         /*
 120          * The following code is racy when called from dwc3_gadget_wakeup,
 121          * and is not needed, at least on newer versions
 122          */
 123         if (dwc->revision >= DWC3_REVISION_194A)
 124                 return 0;
 125
 126         /* wait for a change in DSTS */
 127         retries = 10000;
 128         while (--retries) {
 129                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 130
 131                 if (DWC3_DSTS_USBLNKST(reg) == state)
 132                         return 0;
 133
 134                 udelay(5);
 135         }
 136
 137         dev_vdbg(dwc->dev, "link state change request timed out\n");
 138
 139         return -ETIMEDOUT;
 140 }
 141
 142 /**
 143  * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
 144  * @dwc: pointer to our context structure
 145  *
 146  * This function will a best effort FIFO allocation in order
 147  * to improve FIFO usage and throughput, while still allowing
 148  * us to enable as many endpoints as possible.
 149  *
 150  * Keep in mind that this operation will be highly dependent
 151  * on the configured size for RAM1 - which contains TxFifo -,
 152  * the amount of endpoints enabled on coreConsultant tool, and
 153  * the width of the Master Bus.
 154  *
 155  * In the ideal world, we would always be able to satisfy the
 156  * following equation:
 157  *
 158  * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \
 159  * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes
 160  *
 161  * Unfortunately, due to many variables that's not always the case.
 162  */
 163 int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc)
 164 {
 165         int             last_fifo_depth = 0;
 166         int             fifo_size;
 167         int             mdwidth;
 168         int             num;
 169
 170         if (!dwc->needs_fifo_resize)
 171                 return 0;
 172
 173         mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
 174
 175         /* MDWIDTH is represented in bits, we need it in bytes */
 176         mdwidth >>= 3;
 177
 178         /*
 179          * FIXME For now we will only allocate 1 wMaxPacketSize space
 180          * for each enabled endpoint, later patches will come to
 181          * improve this algorithm so that we better use the internal
 182          * FIFO space
 183          */
 184         for (num = 0; num < dwc->num_in_eps; num++) {
 185                 /* bit0 indicates direction; 1 means IN ep */
 186                 struct dwc3_ep  *dep = dwc->eps[(num << 1) | 1];
 187                 int             mult = 1;
 188                 int             tmp;
 189
 190                 if (!(dep->flags & DWC3_EP_ENABLED))
 191                         continue;
 192
 193                 if (usb_endpoint_xfer_bulk(dep->endpoint.desc)
 194                                 || usb_endpoint_xfer_isoc(dep->endpoint.desc))
 195                         mult = 3;
 196
 197                 /*
 198                  * REVISIT: the following assumes we will always have enough
 199                  * space available on the FIFO RAM for all possible use cases.
 200                  * Make sure that's true somehow and change FIFO allocation
 201                  * accordingly.
 202                  *
 203                  * If we have Bulk or Isochronous endpoints, we want
 204                  * them to be able to be very, very fast. So we're giving
 205                  * those endpoints a fifo_size which is enough for 3 full
 206                  * packets
 207                  */
 208                 tmp = mult * (dep->endpoint.maxpacket + mdwidth);
 209                 tmp += mdwidth;
 210
 211                 fifo_size = DIV_ROUND_UP(tmp, mdwidth);
 212
 213                 fifo_size |= (last_fifo_depth << 16);
 214
 215                 dev_vdbg(dwc->dev, "%s: Fifo Addr %04x Size %d\n",
 216                                 dep->name, last_fifo_depth, fifo_size & 0xffff);
 217
 218                 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(num), fifo_size);
 219
 220                 last_fifo_depth += (fifo_size & 0xffff);
 221         }
 222
 223         return 0;
 224 }
 225
 226 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
 227                 int status)
 228 {
 229         struct dwc3                     *dwc = dep->dwc;
 230
 231         if (req->queued) {
 232                 dep->busy_slot++;
 233                 /*
 234                  * Skip LINK TRB. We can't use req->trb and check for
 235                  * DWC3_TRBCTL_LINK_TRB because it points the TRB we
 236                  * just completed (not the LINK TRB).
 237                  */
 238                 if (((dep->busy_slot & DWC3_TRB_MASK) ==
 239                         DWC3_TRB_NUM- 1) &&
 240                         usb_endpoint_xfer_isoc(dep->endpoint.desc))
 241                         dep->busy_slot++;
 242                 req->queued = false;
 243         }
 244
 245         list_del(&req->list);
 246         req->trb = NULL;
 247         dwc3_flush_cache((int)req->request.dma, req->request.length);
 248
 249         if (req->request.status == -EINPROGRESS)
 250                 req->request.status = status;
 251
 252         if (dwc->ep0_bounced && dep->number == 0)
 253                 dwc->ep0_bounced = false;
 254         else
 255                 usb_gadget_unmap_request(&dwc->gadget, &req->request,
 256                                 req->direction);
 257
 258         dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n",
 259                         req, dep->name, req->request.actual,
 260                         req->request.length, status);
 261
 262         spin_unlock(&dwc->lock);
 263         usb_gadget_giveback_request(&dep->endpoint, &req->request);
 264         spin_lock(&dwc->lock);
 265 }
 266
 267 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
 268 {
 269         u32             timeout = 500;
 270         u32             reg;
 271
 272         dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
 273         dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
 274
 275         do {
 276                 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
 277                 if (!(reg & DWC3_DGCMD_CMDACT)) {
 278                         dev_vdbg(dwc->dev, "Command Complete --> %d\n",
 279                                         DWC3_DGCMD_STATUS(reg));
 280                         return 0;
 281                 }
 282
 283                 /*
 284                  * We can't sleep here, because it's also called from
 285                  * interrupt context.
 286                  */
 287                 timeout--;
 288                 if (!timeout)
 289                         return -ETIMEDOUT;
 290                 udelay(1);
 291         } while (1);
 292 }
 293
 294 int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
 295                 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
 296 {
 297         u32                     timeout = 500;
 298         u32                     reg;
 299
 300         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
 301         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
 302         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
 303
 304         dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
 305         do {
 306                 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
 307                 if (!(reg & DWC3_DEPCMD_CMDACT)) {
 308                         dev_vdbg(dwc->dev, "Command Complete --> %d\n",
 309                                         DWC3_DEPCMD_STATUS(reg));
 310                         return 0;
 311                 }
 312
 313                 /*
 314                  * We can't sleep here, because it is also called from
 315                  * interrupt context.
 316                  */
 317                 timeout--;
 318                 if (!timeout)
 319                         return -ETIMEDOUT;
 320
 321                 udelay(1);
 322         } while (1);
 323 }
 324
 325 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
 326                 struct dwc3_trb *trb)
 327 {
 328         u32             offset = (char *) trb - (char *) dep->trb_pool;
 329
 330         return dep->trb_pool_dma + offset;
 331 }
 332
 333 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
 334 {
 335         if (dep->trb_pool)
 336                 return 0;
 337
 338         if (dep->number == 0 || dep->number == 1)
 339                 return 0;
 340
 341         dep->trb_pool = dma_alloc_coherent(sizeof(struct dwc3_trb) *
 342                                            DWC3_TRB_NUM,
 343                                            (unsigned long *)&dep->trb_pool_dma);
 344         if (!dep->trb_pool) {
 345                 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
 346                                 dep->name);
 347                 return -ENOMEM;
 348         }
 349
 350         return 0;
 351 }
 352
 353 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
 354 {
 355         dma_free_coherent(dep->trb_pool);
 356
 357         dep->trb_pool = NULL;
 358         dep->trb_pool_dma = 0;
 359 }
 360
 361 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
 362 {
 363         struct dwc3_gadget_ep_cmd_params params;
 364         u32                     cmd;
 365
 366         memset(&params, 0x00, sizeof(params));
 367
 368         if (dep->number != 1) {
 369                 cmd = DWC3_DEPCMD_DEPSTARTCFG;
 370                 /* XferRscIdx == 0 for ep0 and 2 for the remaining */
 371                 if (dep->number > 1) {
 372                         if (dwc->start_config_issued)
 373                                 return 0;
 374                         dwc->start_config_issued = true;
 375                         cmd |= DWC3_DEPCMD_PARAM(2);
 376                 }
 377
 378                 return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, &params);
 379         }
 380
 381         return 0;
 382 }
 383
 384 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
 385                 const struct usb_endpoint_descriptor *desc,
 386                 const struct usb_ss_ep_comp_descriptor *comp_desc,
 387                 bool ignore, bool restore)
 388 {
 389         struct dwc3_gadget_ep_cmd_params params;
 390
 391         memset(&params, 0x00, sizeof(params));
 392
 393         params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
 394                 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
 395
 396         /* Burst size is only needed in SuperSpeed mode */
 397         if (dwc->gadget.speed == USB_SPEED_SUPER) {
 398                 u32 burst = dep->endpoint.maxburst - 1;
 399
 400                 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst);
 401         }
 402
 403         if (ignore)
 404                 params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM;
 405
 406         if (restore) {
 407                 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
 408                 params.param2 |= dep->saved_state;
 409         }
 410
 411         params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
 412                 | DWC3_DEPCFG_XFER_NOT_READY_EN;
 413
 414         if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
 415                 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
 416                         | DWC3_DEPCFG_STREAM_EVENT_EN;
 417                 dep->stream_capable = true;
 418         }
 419
 420         if (!usb_endpoint_xfer_control(desc))
 421                 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
 422
 423         /*
 424          * We are doing 1:1 mapping for endpoints, meaning
 425          * Physical Endpoints 2 maps to Logical Endpoint 2 and
 426          * so on. We consider the direction bit as part of the physical
 427          * endpoint number. So USB endpoint 0x81 is 0x03.
 428          */
 429         params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
 430
 431         /*
 432          * We must use the lower 16 TX FIFOs even though
 433          * HW might have more
 434          */
 435         if (dep->direction)
 436                 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
 437
 438         if (desc->bInterval) {
 439                 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
 440                 dep->interval = 1 << (desc->bInterval - 1);
 441         }
 442
 443         return dwc3_send_gadget_ep_cmd(dwc, dep->number,
 444                         DWC3_DEPCMD_SETEPCONFIG, &params);
 445 }
 446
 447 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
 448 {
 449         struct dwc3_gadget_ep_cmd_params params;
 450
 451         memset(&params, 0x00, sizeof(params));
 452
 453         params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
 454
 455         return dwc3_send_gadget_ep_cmd(dwc, dep->number,
 456                         DWC3_DEPCMD_SETTRANSFRESOURCE, &params);
 457 }
 458
 459 /**
 460  * __dwc3_gadget_ep_enable - Initializes a HW endpoint
 461  * @dep: endpoint to be initialized
 462  * @desc: USB Endpoint Descriptor
 463  *
 464  * Caller should take care of locking
 465  */
 466 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
 467                 const struct usb_endpoint_descriptor *desc,
 468                 const struct usb_ss_ep_comp_descriptor *comp_desc,
 469                 bool ignore, bool restore)
 470 {
 471         struct dwc3             *dwc = dep->dwc;
 472         u32                     reg;
 473         int                     ret;
 474
 475         dev_vdbg(dwc->dev, "Enabling %s\n", dep->name);
 476
 477         if (!(dep->flags & DWC3_EP_ENABLED)) {
 478                 ret = dwc3_gadget_start_config(dwc, dep);
 479                 if (ret)
 480                         return ret;
 481         }
 482
 483         ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore,
 484                         restore);
 485         if (ret)
 486                 return ret;
 487
 488         if (!(dep->flags & DWC3_EP_ENABLED)) {
 489                 struct dwc3_trb *trb_st_hw;
 490                 struct dwc3_trb *trb_link;
 491
 492                 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
 493                 if (ret)
 494                         return ret;
 495
 496                 dep->endpoint.desc = desc;
 497                 dep->comp_desc = comp_desc;
 498                 dep->type = usb_endpoint_type(desc);
 499                 dep->flags |= DWC3_EP_ENABLED;
 500
 501                 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 502                 reg |= DWC3_DALEPENA_EP(dep->number);
 503                 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 504
 505                 if (!usb_endpoint_xfer_isoc(desc))
 506                         return 0;
 507
 508                 /* Link TRB for ISOC. The HWO bit is never reset */
 509                 trb_st_hw = &dep->trb_pool[0];
 510
 511                 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
 512                 memset(trb_link, 0, sizeof(*trb_link));
 513
 514                 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 515                 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 516                 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
 517                 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
 518         }
 519
 520         return 0;
 521 }
 522
 523 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
 524 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
 525 {
 526         struct dwc3_request             *req;
 527
 528         if (!list_empty(&dep->req_queued)) {
 529                 dwc3_stop_active_transfer(dwc, dep->number, true);
 530
 531                 /* - giveback all requests to gadget driver */
 532                 while (!list_empty(&dep->req_queued)) {
 533                         req = next_request(&dep->req_queued);
 534
 535                         dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 536                 }
 537         }
 538
 539         while (!list_empty(&dep->request_list)) {
 540                 req = next_request(&dep->request_list);
 541
 542                 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 543         }
 544 }
 545
 546 /**
 547  * __dwc3_gadget_ep_disable - Disables a HW endpoint
 548  * @dep: the endpoint to disable
 549  *
 550  * This function also removes requests which are currently processed ny the
 551  * hardware and those which are not yet scheduled.
 552  * Caller should take care of locking.
 553  */
 554 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
 555 {
 556         struct dwc3             *dwc = dep->dwc;
 557         u32                     reg;
 558
 559         dwc3_remove_requests(dwc, dep);
 560
 561         /* make sure HW endpoint isn't stalled */
 562         if (dep->flags & DWC3_EP_STALL)
 563                 __dwc3_gadget_ep_set_halt(dep, 0, false);
 564
 565         reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 566         reg &= ~DWC3_DALEPENA_EP(dep->number);
 567         dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 568
 569         dep->stream_capable = false;
 570         dep->endpoint.desc = NULL;
 571         dep->comp_desc = NULL;
 572         dep->type = 0;
 573         dep->flags = 0;
 574
 575         return 0;
 576 }
 577
 578 /* -------------------------------------------------------------------------- */
 579
 580 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
 581                 const struct usb_endpoint_descriptor *desc)
 582 {
 583         return -EINVAL;
 584 }
 585
 586 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
 587 {
 588         return -EINVAL;
 589 }
 590
 591 /* -------------------------------------------------------------------------- */
 592
 593 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
 594                 const struct usb_endpoint_descriptor *desc)
 595 {
 596         struct dwc3_ep                  *dep;
 597         unsigned long                   flags;
 598         int                             ret;
 599
 600         if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
 601                 pr_debug("dwc3: invalid parameters\n");
 602                 return -EINVAL;
 603         }
 604
 605         if (!desc->wMaxPacketSize) {
 606                 pr_debug("dwc3: missing wMaxPacketSize\n");
 607                 return -EINVAL;
 608         }
 609
 610         dep = to_dwc3_ep(ep);
 611
 612         if (dep->flags & DWC3_EP_ENABLED) {
 613                 WARN(true, "%s is already enabled\n",
 614                                 dep->name);
 615                 return 0;
 616         }
 617
 618         switch (usb_endpoint_type(desc)) {
 619         case USB_ENDPOINT_XFER_CONTROL:
 620                 strlcat(dep->name, "-control", sizeof(dep->name));
 621                 break;
 622         case USB_ENDPOINT_XFER_ISOC:
 623                 strlcat(dep->name, "-isoc", sizeof(dep->name));
 624                 break;
 625         case USB_ENDPOINT_XFER_BULK:
 626                 strlcat(dep->name, "-bulk", sizeof(dep->name));
 627                 break;
 628         case USB_ENDPOINT_XFER_INT:
 629                 strlcat(dep->name, "-int", sizeof(dep->name));
 630                 break;
 631         default:
 632                 dev_err(dwc->dev, "invalid endpoint transfer type\n");
 633         }
 634
 635         spin_lock_irqsave(&dwc->lock, flags);
 636         ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false);
 637         spin_unlock_irqrestore(&dwc->lock, flags);
 638
 639         return ret;
 640 }
 641
 642 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
 643 {
 644         struct dwc3_ep                  *dep;
 645         unsigned long                   flags;
 646         int                             ret;
 647
 648         if (!ep) {
 649                 pr_debug("dwc3: invalid parameters\n");
 650                 return -EINVAL;
 651         }
 652
 653         dep = to_dwc3_ep(ep);
 654
 655         if (!(dep->flags & DWC3_EP_ENABLED)) {
 656                 WARN(true, "%s is already disabled\n",
 657                                 dep->name);
 658                 return 0;
 659         }
 660
 661         snprintf(dep->name, sizeof(dep->name), "ep%d%s",
 662                         dep->number >> 1,
 663                         (dep->number & 1) ? "in" : "out");
 664
 665         spin_lock_irqsave(&dwc->lock, flags);
 666         ret = __dwc3_gadget_ep_disable(dep);
 667         spin_unlock_irqrestore(&dwc->lock, flags);
 668
 669         return ret;
 670 }
 671
 672 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
 673         gfp_t gfp_flags)
 674 {
 675         struct dwc3_request             *req;
 676         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 677
 678         req = kzalloc(sizeof(*req), gfp_flags);
 679         if (!req)
 680                 return NULL;
 681
 682         req->epnum      = dep->number;
 683         req->dep        = dep;
 684
 685         return &req->request;
 686 }
 687
 688 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
 689                 struct usb_request *request)
 690 {
 691         struct dwc3_request             *req = to_dwc3_request(request);
 692
 693         kfree(req);
 694 }
 695
 696 /**
 697  * dwc3_prepare_one_trb - setup one TRB from one request
 698  * @dep: endpoint for which this request is prepared
 699  * @req: dwc3_request pointer
 700  */
 701 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
 702                 struct dwc3_request *req, dma_addr_t dma,
 703                 unsigned length, unsigned last, unsigned chain, unsigned node)
 704 {
 705         struct dwc3_trb         *trb;
 706
 707         dev_vdbg(dwc->dev, "%s: req %p dma %08llx length %d%s%s\n",
 708                         dep->name, req, (unsigned long long) dma,
 709                         length, last ? " last" : "",
 710                         chain ? " chain" : "");
 711
 712
 713         trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
 714
 715         if (!req->trb) {
 716                 dwc3_gadget_move_request_queued(req);
 717                 req->trb = trb;
 718                 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
 719                 req->start_slot = dep->free_slot & DWC3_TRB_MASK;
 720         }
 721
 722         dep->free_slot++;
 723         /* Skip the LINK-TRB on ISOC */
 724         if (((dep->free_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
 725                         usb_endpoint_xfer_isoc(dep->endpoint.desc))
 726                 dep->free_slot++;
 727
 728         trb->size = DWC3_TRB_SIZE_LENGTH(length);
 729         trb->bpl = lower_32_bits(dma);
 730         trb->bph = upper_32_bits(dma);
 731
 732         switch (usb_endpoint_type(dep->endpoint.desc)) {
 733         case USB_ENDPOINT_XFER_CONTROL:
 734                 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
 735                 break;
 736
 737         case USB_ENDPOINT_XFER_ISOC:
 738                 if (!node)
 739                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
 740                 else
 741                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
 742                 break;
 743
 744         case USB_ENDPOINT_XFER_BULK:
 745         case USB_ENDPOINT_XFER_INT:
 746                 trb->ctrl = DWC3_TRBCTL_NORMAL;
 747                 break;
 748         default:
 749                 /*
 750                  * This is only possible with faulty memory because we
 751                  * checked it already :)
 752                  */
 753                 BUG();
 754         }
 755
 756         if (!req->request.no_interrupt && !chain)
 757                 trb->ctrl |= DWC3_TRB_CTRL_IOC;
 758
 759         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
 760                 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
 761                 trb->ctrl |= DWC3_TRB_CTRL_CSP;
 762         } else if (last) {
 763                 trb->ctrl |= DWC3_TRB_CTRL_LST;
 764         }
 765
 766         if (chain)
 767                 trb->ctrl |= DWC3_TRB_CTRL_CHN;
 768
 769         if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
 770                 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
 771
 772         trb->ctrl |= DWC3_TRB_CTRL_HWO;
 773
 774         dwc3_flush_cache((int)dma, length);
 775         dwc3_flush_cache((int)trb, sizeof(*trb));
 776 }
 777
 778 /*
 779  * dwc3_prepare_trbs - setup TRBs from requests
 780  * @dep: endpoint for which requests are being prepared
 781  * @starting: true if the endpoint is idle and no requests are queued.
 782  *
 783  * The function goes through the requests list and sets up TRBs for the
 784  * transfers. The function returns once there are no more TRBs available or
 785  * it runs out of requests.
 786  */
 787 static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
 788 {
 789         struct dwc3_request     *req, *n;
 790         u32                     trbs_left;
 791         u32                     max;
 792         unsigned int            last_one = 0;
 793
 794         BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
 795
 796         /* the first request must not be queued */
 797         trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
 798
 799         /* Can't wrap around on a non-isoc EP since there's no link TRB */
 800         if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
 801                 max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK);
 802                 if (trbs_left > max)
 803                         trbs_left = max;
 804         }
 805
 806         /*
 807          * If busy & slot are equal than it is either full or empty. If we are
 808          * starting to process requests then we are empty. Otherwise we are
 809          * full and don't do anything
 810          */
 811         if (!trbs_left) {
 812                 if (!starting)
 813                         return;
 814                 trbs_left = DWC3_TRB_NUM;
 815                 /*
 816                  * In case we start from scratch, we queue the ISOC requests
 817                  * starting from slot 1. This is done because we use ring
 818                  * buffer and have no LST bit to stop us. Instead, we place
 819                  * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
 820                  * after the first request so we start at slot 1 and have
 821                  * 7 requests proceed before we hit the first IOC.
 822                  * Other transfer types don't use the ring buffer and are
 823                  * processed from the first TRB until the last one. Since we
 824                  * don't wrap around we have to start at the beginning.
 825                  */
 826                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
 827                         dep->busy_slot = 1;
 828                         dep->free_slot = 1;
 829                 } else {
 830                         dep->busy_slot = 0;
 831                         dep->free_slot = 0;
 832                 }
 833         }
 834
 835         /* The last TRB is a link TRB, not used for xfer */
 836         if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc))
 837                 return;
 838
 839         list_for_each_entry_safe(req, n, &dep->request_list, list) {
 840                 unsigned        length;
 841                 dma_addr_t      dma;
 842                 last_one = false;
 843
 844                 dma = req->request.dma;
 845                 length = req->request.length;
 846                 trbs_left--;
 847
 848                 if (!trbs_left)
 849                         last_one = 1;
 850
 851                 /* Is this the last request? */
 852                 if (list_is_last(&req->list, &dep->request_list))
 853                         last_one = 1;
 854
 855                 dwc3_prepare_one_trb(dep, req, dma, length,
 856                                 last_one, false, 0);
 857
 858                 if (last_one)
 859                         break;
 860         }
 861 }
 862
 863 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
 864                 int start_new)
 865 {
 866         struct dwc3_gadget_ep_cmd_params params;
 867         struct dwc3_request             *req;
 868         struct dwc3                     *dwc = dep->dwc;
 869         int                             ret;
 870         u32                             cmd;
 871
 872         if (start_new && (dep->flags & DWC3_EP_BUSY)) {
 873                 dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name);
 874                 return -EBUSY;
 875         }
 876         dep->flags &= ~DWC3_EP_PENDING_REQUEST;
 877
 878         /*
 879          * If we are getting here after a short-out-packet we don't enqueue any
 880          * new requests as we try to set the IOC bit only on the last request.
 881          */
 882         if (start_new) {
 883                 if (list_empty(&dep->req_queued))
 884                         dwc3_prepare_trbs(dep, start_new);
 885
 886                 /* req points to the first request which will be sent */
 887                 req = next_request(&dep->req_queued);
 888         } else {
 889                 dwc3_prepare_trbs(dep, start_new);
 890
 891                 /*
 892                  * req points to the first request where HWO changed from 0 to 1
 893                  */
 894                 req = next_request(&dep->req_queued);
 895         }
 896         if (!req) {
 897                 dep->flags |= DWC3_EP_PENDING_REQUEST;
 898                 return 0;
 899         }
 900
 901         memset(&params, 0, sizeof(params));
 902
 903         if (start_new) {
 904                 params.param0 = upper_32_bits(req->trb_dma);
 905                 params.param1 = lower_32_bits(req->trb_dma);
 906                 cmd = DWC3_DEPCMD_STARTTRANSFER;
 907         } else {
 908                 cmd = DWC3_DEPCMD_UPDATETRANSFER;
 909         }
 910
 911         cmd |= DWC3_DEPCMD_PARAM(cmd_param);
 912         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
 913         if (ret < 0) {
 914                 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
 915
 916                 /*
 917                  * FIXME we need to iterate over the list of requests
 918                  * here and stop, unmap, free and del each of the linked
 919                  * requests instead of what we do now.
 920                  */
 921                 usb_gadget_unmap_request(&dwc->gadget, &req->request,
 922                                 req->direction);
 923                 list_del(&req->list);
 924                 return ret;
 925         }
 926
 927         dep->flags |= DWC3_EP_BUSY;
 928
 929         if (start_new) {
 930                 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
 931                                 dep->number);
 932                 WARN_ON_ONCE(!dep->resource_index);
 933         }
 934
 935         return 0;
 936 }
 937
 938 static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
 939                 struct dwc3_ep *dep, u32 cur_uf)
 940 {
 941         u32 uf;
 942
 943         if (list_empty(&dep->request_list)) {
 944                 dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n",
 945                         dep->name);
 946                 dep->flags |= DWC3_EP_PENDING_REQUEST;
 947                 return;
 948         }
 949
 950         /* 4 micro frames in the future */
 951         uf = cur_uf + dep->interval * 4;
 952
 953         __dwc3_gadget_kick_transfer(dep, uf, 1);
 954 }
 955
 956 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
 957                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
 958 {
 959         u32 cur_uf, mask;
 960
 961         mask = ~(dep->interval - 1);
 962         cur_uf = event->parameters & mask;
 963
 964         __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
 965 }
 966
 967 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
 968 {
 969         struct dwc3             *dwc = dep->dwc;
 970         int                     ret;
 971
 972         req->request.actual     = 0;
 973         req->request.status     = -EINPROGRESS;
 974         req->direction          = dep->direction;
 975         req->epnum              = dep->number;
 976
 977         /*
 978          * We only add to our list of requests now and
 979          * start consuming the list once we get XferNotReady
 980          * IRQ.
 981          *
 982          * That way, we avoid doing anything that we don't need
 983          * to do now and defer it until the point we receive a
 984          * particular token from the Host side.
 985          *
 986          * This will also avoid Host cancelling URBs due to too
 987          * many NAKs.
 988          */
 989         ret = usb_gadget_map_request(&dwc->gadget, &req->request,
 990                         dep->direction);
 991         if (ret)
 992                 return ret;
 993
 994         list_add_tail(&req->list, &dep->request_list);
 995
 996         /*
 997          * There are a few special cases:
 998          *
 999          * 1. XferNotReady with empty list of requests. We need to kick the
1000          *    transfer here in that situation, otherwise we will be NAKing
1001          *    forever. If we get XferNotReady before gadget driver has a
1002          *    chance to queue a request, we will ACK the IRQ but won't be
1003          *    able to receive the data until the next request is queued.
1004          *    The following code is handling exactly that.
1005          *
1006          */
1007         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
1008                 /*
1009                  * If xfernotready is already elapsed and it is a case
1010                  * of isoc transfer, then issue END TRANSFER, so that
1011                  * you can receive xfernotready again and can have
1012                  * notion of current microframe.
1013                  */
1014                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1015                         if (list_empty(&dep->req_queued)) {
1016                                 dwc3_stop_active_transfer(dwc, dep->number, true);
1017                                 dep->flags = DWC3_EP_ENABLED;
1018                         }
1019                         return 0;
1020                 }
1021
1022                 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1023                 if (ret && ret != -EBUSY)
1024                         dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1025                                         dep->name);
1026                 return ret;
1027         }
1028
1029         /*
1030          * 2. XferInProgress on Isoc EP with an active transfer. We need to
1031          *    kick the transfer here after queuing a request, otherwise the
1032          *    core may not see the modified TRB(s).
1033          */
1034         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1035                         (dep->flags & DWC3_EP_BUSY) &&
1036                         !(dep->flags & DWC3_EP_MISSED_ISOC)) {
1037                 WARN_ON_ONCE(!dep->resource_index);
1038                 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index,
1039                                 false);
1040                 if (ret && ret != -EBUSY)
1041                         dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1042                                         dep->name);
1043                 return ret;
1044         }
1045
1046         /*
1047          * 4. Stream Capable Bulk Endpoints. We need to start the transfer
1048          * right away, otherwise host will not know we have streams to be
1049          * handled.
1050          */
1051         if (dep->stream_capable) {
1052                 int     ret;
1053
1054                 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1055                 if (ret && ret != -EBUSY) {
1056                         dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1057                                         dep->name);
1058                 }
1059         }
1060
1061         return 0;
1062 }
1063
1064 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1065         gfp_t gfp_flags)
1066 {
1067         struct dwc3_request             *req = to_dwc3_request(request);
1068         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1069
1070         unsigned long                   flags;
1071
1072         int                             ret;
1073
1074         spin_lock_irqsave(&dwc->lock, flags);
1075         if (!dep->endpoint.desc) {
1076                 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
1077                                 request, ep->name);
1078                 ret = -ESHUTDOWN;
1079                 goto out;
1080         }
1081
1082         if (req->dep != dep) {
1083                 WARN(true, "request %p belongs to '%s'\n",
1084                                 request, req->dep->name);
1085                 ret = -EINVAL;
1086                 goto out;
1087         }
1088
1089         dev_vdbg(dwc->dev, "queing request %p to %s length %d\n",
1090                         request, ep->name, request->length);
1091
1092         ret = __dwc3_gadget_ep_queue(dep, req);
1093
1094 out:
1095         spin_unlock_irqrestore(&dwc->lock, flags);
1096
1097         return ret;
1098 }
1099
1100 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1101                 struct usb_request *request)
1102 {
1103         struct dwc3_request             *req = to_dwc3_request(request);
1104         struct dwc3_request             *r = NULL;
1105
1106         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1107         struct dwc3                     *dwc = dep->dwc;
1108
1109         unsigned long                   flags;
1110         int                             ret = 0;
1111
1112         spin_lock_irqsave(&dwc->lock, flags);
1113
1114         list_for_each_entry(r, &dep->request_list, list) {
1115                 if (r == req)
1116                         break;
1117         }
1118
1119         if (r != req) {
1120                 list_for_each_entry(r, &dep->req_queued, list) {
1121                         if (r == req)
1122                                 break;
1123                 }
1124                 if (r == req) {
1125                         /* wait until it is processed */
1126                         dwc3_stop_active_transfer(dwc, dep->number, true);
1127                         goto out1;
1128                 }
1129                 dev_err(dwc->dev, "request %p was not queued to %s\n",
1130                                 request, ep->name);
1131                 ret = -EINVAL;
1132                 goto out0;
1133         }
1134
1135 out1:
1136         /* giveback the request */
1137         dwc3_gadget_giveback(dep, req, -ECONNRESET);
1138
1139 out0:
1140         spin_unlock_irqrestore(&dwc->lock, flags);
1141
1142         return ret;
1143 }
1144
1145 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1146 {
1147         struct dwc3_gadget_ep_cmd_params        params;
1148         struct dwc3                             *dwc = dep->dwc;
1149         int                                     ret;
1150
1151         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1152                 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1153                 return -EINVAL;
1154         }
1155
1156         memset(&params, 0x00, sizeof(params));
1157
1158         if (value) {
1159                 if (!protocol && ((dep->direction && dep->flags & DWC3_EP_BUSY) ||
1160                                 (!list_empty(&dep->req_queued) ||
1161                                  !list_empty(&dep->request_list)))) {
1162                         dev_dbg(dwc->dev, "%s: pending request, cannot halt\n",
1163                                         dep->name);
1164                         return -EAGAIN;
1165                 }
1166
1167                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1168                         DWC3_DEPCMD_SETSTALL, &params);
1169                 if (ret)
1170                         dev_err(dwc->dev, "failed to set STALL on %s\n",
1171                                         dep->name);
1172                 else
1173                         dep->flags |= DWC3_EP_STALL;
1174         } else {
1175                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1176                         DWC3_DEPCMD_CLEARSTALL, &params);
1177                 if (ret)
1178                         dev_err(dwc->dev, "failed to clear STALL on %s\n",
1179                                         dep->name);
1180                 else
1181                         dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1182         }
1183
1184         return ret;
1185 }
1186
1187 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1188 {
1189         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1190
1191         unsigned long                   flags;
1192
1193         int                             ret;
1194
1195         spin_lock_irqsave(&dwc->lock, flags);
1196         ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1197         spin_unlock_irqrestore(&dwc->lock, flags);
1198
1199         return ret;
1200 }
1201
1202 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1203 {
1204         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1205         unsigned long                   flags;
1206         int                             ret;
1207
1208         spin_lock_irqsave(&dwc->lock, flags);
1209         dep->flags |= DWC3_EP_WEDGE;
1210
1211         if (dep->number == 0 || dep->number == 1)
1212                 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1213         else
1214                 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1215         spin_unlock_irqrestore(&dwc->lock, flags);
1216
1217         return ret;
1218 }
1219
1220 /* -------------------------------------------------------------------------- */
1221
1222 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1223         .bLength        = USB_DT_ENDPOINT_SIZE,
1224         .bDescriptorType = USB_DT_ENDPOINT,
1225         .bmAttributes   = USB_ENDPOINT_XFER_CONTROL,
1226 };
1227
1228 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1229         .enable         = dwc3_gadget_ep0_enable,
1230         .disable        = dwc3_gadget_ep0_disable,
1231         .alloc_request  = dwc3_gadget_ep_alloc_request,
1232         .free_request   = dwc3_gadget_ep_free_request,
1233         .queue          = dwc3_gadget_ep0_queue,
1234         .dequeue        = dwc3_gadget_ep_dequeue,
1235         .set_halt       = dwc3_gadget_ep0_set_halt,
1236         .set_wedge      = dwc3_gadget_ep_set_wedge,
1237 };
1238
1239 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1240         .enable         = dwc3_gadget_ep_enable,
1241         .disable        = dwc3_gadget_ep_disable,
1242         .alloc_request  = dwc3_gadget_ep_alloc_request,
1243         .free_request   = dwc3_gadget_ep_free_request,
1244         .queue          = dwc3_gadget_ep_queue,
1245         .dequeue        = dwc3_gadget_ep_dequeue,
1246         .set_halt       = dwc3_gadget_ep_set_halt,
1247         .set_wedge      = dwc3_gadget_ep_set_wedge,
1248 };
1249
1250 /* -------------------------------------------------------------------------- */
1251
1252 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1253 {
1254         struct dwc3             *dwc = gadget_to_dwc(g);
1255         u32                     reg;
1256
1257         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1258         return DWC3_DSTS_SOFFN(reg);
1259 }
1260
1261 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1262 {
1263         struct dwc3             *dwc = gadget_to_dwc(g);
1264
1265         unsigned long           timeout;
1266         unsigned long           flags;
1267
1268         u32                     reg;
1269
1270         int                     ret = 0;
1271
1272         u8                      link_state;
1273         u8                      speed;
1274
1275         spin_lock_irqsave(&dwc->lock, flags);
1276
1277         /*
1278          * According to the Databook Remote wakeup request should
1279          * be issued only when the device is in early suspend state.
1280          *
1281          * We can check that via USB Link State bits in DSTS register.
1282          */
1283         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1284
1285         speed = reg & DWC3_DSTS_CONNECTSPD;
1286         if (speed == DWC3_DSTS_SUPERSPEED) {
1287                 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n");
1288                 ret = -EINVAL;
1289                 goto out;
1290         }
1291
1292         link_state = DWC3_DSTS_USBLNKST(reg);
1293
1294         switch (link_state) {
1295         case DWC3_LINK_STATE_RX_DET:    /* in HS, means Early Suspend */
1296         case DWC3_LINK_STATE_U3:        /* in HS, means SUSPEND */
1297                 break;
1298         default:
1299                 dev_dbg(dwc->dev, "can't wakeup from link state %d\n",
1300                                 link_state);
1301                 ret = -EINVAL;
1302                 goto out;
1303         }
1304
1305         ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1306         if (ret < 0) {
1307                 dev_err(dwc->dev, "failed to put link in Recovery\n");
1308                 goto out;
1309         }
1310
1311         /* Recent versions do this automatically */
1312         if (dwc->revision < DWC3_REVISION_194A) {
1313                 /* write zeroes to Link Change Request */
1314                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1315                 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1316                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1317         }
1318
1319         /* poll until Link State changes to ON */
1320         timeout = 1000;
1321
1322         while (timeout--) {
1323                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1324
1325                 /* in HS, means ON */
1326                 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1327                         break;
1328         }
1329
1330         if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1331                 dev_err(dwc->dev, "failed to send remote wakeup\n");
1332                 ret = -EINVAL;
1333         }
1334
1335 out:
1336         spin_unlock_irqrestore(&dwc->lock, flags);
1337
1338         return ret;
1339 }
1340
1341 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1342                 int is_selfpowered)
1343 {
1344         struct dwc3             *dwc = gadget_to_dwc(g);
1345         unsigned long           flags;
1346
1347         spin_lock_irqsave(&dwc->lock, flags);
1348         dwc->is_selfpowered = !!is_selfpowered;
1349         spin_unlock_irqrestore(&dwc->lock, flags);
1350
1351         return 0;
1352 }
1353
1354 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1355 {
1356         u32                     reg;
1357         u32                     timeout = 500;
1358
1359         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1360         if (is_on) {
1361                 if (dwc->revision <= DWC3_REVISION_187A) {
1362                         reg &= ~DWC3_DCTL_TRGTULST_MASK;
1363                         reg |= DWC3_DCTL_TRGTULST_RX_DET;
1364                 }
1365
1366                 if (dwc->revision >= DWC3_REVISION_194A)
1367                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1368                 reg |= DWC3_DCTL_RUN_STOP;
1369
1370                 if (dwc->has_hibernation)
1371                         reg |= DWC3_DCTL_KEEP_CONNECT;
1372
1373                 dwc->pullups_connected = true;
1374         } else {
1375                 reg &= ~DWC3_DCTL_RUN_STOP;
1376
1377                 if (dwc->has_hibernation && !suspend)
1378                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1379
1380                 dwc->pullups_connected = false;
1381         }
1382
1383         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1384
1385         do {
1386                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1387                 if (is_on) {
1388                         if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1389                                 break;
1390                 } else {
1391                         if (reg & DWC3_DSTS_DEVCTRLHLT)
1392                                 break;
1393                 }
1394                 timeout--;
1395                 if (!timeout)
1396                         return -ETIMEDOUT;
1397                 udelay(1);
1398         } while (1);
1399
1400         dev_vdbg(dwc->dev, "gadget %s data soft-%s\n",
1401                         dwc->gadget_driver
1402                         ? dwc->gadget_driver->function : "no-function",
1403                         is_on ? "connect" : "disconnect");
1404
1405         return 0;
1406 }
1407
1408 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1409 {
1410         struct dwc3             *dwc = gadget_to_dwc(g);
1411         unsigned long           flags;
1412         int                     ret;
1413
1414         is_on = !!is_on;
1415
1416         spin_lock_irqsave(&dwc->lock, flags);
1417         ret = dwc3_gadget_run_stop(dwc, is_on, false);
1418         spin_unlock_irqrestore(&dwc->lock, flags);
1419
1420         return ret;
1421 }
1422
1423 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1424 {
1425         u32                     reg;
1426
1427         /* Enable all but Start and End of Frame IRQs */
1428         reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1429                         DWC3_DEVTEN_EVNTOVERFLOWEN |
1430                         DWC3_DEVTEN_CMDCMPLTEN |
1431                         DWC3_DEVTEN_ERRTICERREN |
1432                         DWC3_DEVTEN_WKUPEVTEN |
1433                         DWC3_DEVTEN_ULSTCNGEN |
1434                         DWC3_DEVTEN_CONNECTDONEEN |
1435                         DWC3_DEVTEN_USBRSTEN |
1436                         DWC3_DEVTEN_DISCONNEVTEN);
1437
1438         dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1439 }
1440
1441 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1442 {
1443         /* mask all interrupts */
1444         dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1445 }
1446
1447 static int dwc3_gadget_start(struct usb_gadget *g,
1448                 struct usb_gadget_driver *driver)
1449 {
1450         struct dwc3             *dwc = gadget_to_dwc(g);
1451         struct dwc3_ep          *dep;
1452         unsigned long           flags;
1453         int                     ret = 0;
1454         u32                     reg;
1455
1456         spin_lock_irqsave(&dwc->lock, flags);
1457
1458         if (dwc->gadget_driver) {
1459                 dev_err(dwc->dev, "%s is already bound to %s\n",
1460                                 dwc->gadget.name,
1461                                 dwc->gadget_driver->function);
1462                 ret = -EBUSY;
1463                 goto err1;
1464         }
1465
1466         dwc->gadget_driver      = driver;
1467
1468         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1469         reg &= ~(DWC3_DCFG_SPEED_MASK);
1470
1471         /**
1472          * WORKAROUND: DWC3 revision < 2.20a have an issue
1473          * which would cause metastability state on Run/Stop
1474          * bit if we try to force the IP to USB2-only mode.
1475          *
1476          * Because of that, we cannot configure the IP to any
1477          * speed other than the SuperSpeed
1478          *
1479          * Refers to:
1480          *
1481          * STAR#9000525659: Clock Domain Crossing on DCTL in
1482          * USB 2.0 Mode
1483          */
1484         if (dwc->revision < DWC3_REVISION_220A) {
1485                 reg |= DWC3_DCFG_SUPERSPEED;
1486         } else {
1487                 switch (dwc->maximum_speed) {
1488                 case USB_SPEED_LOW:
1489                         reg |= DWC3_DSTS_LOWSPEED;
1490                         break;
1491                 case USB_SPEED_FULL:
1492                         reg |= DWC3_DSTS_FULLSPEED1;
1493                         break;
1494                 case USB_SPEED_HIGH:
1495                         reg |= DWC3_DSTS_HIGHSPEED;
1496                         break;
1497                 case USB_SPEED_SUPER:   /* FALLTHROUGH */
1498                 case USB_SPEED_UNKNOWN: /* FALTHROUGH */
1499                 default:
1500                         reg |= DWC3_DSTS_SUPERSPEED;
1501                 }
1502         }
1503         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1504
1505         dwc->start_config_issued = false;
1506
1507         /* Start with SuperSpeed Default */
1508         dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1509
1510         dep = dwc->eps[0];
1511         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1512                         false);
1513         if (ret) {
1514                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1515                 goto err2;
1516         }
1517
1518         dep = dwc->eps[1];
1519         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1520                         false);
1521         if (ret) {
1522                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1523                 goto err3;
1524         }
1525
1526         /* begin to receive SETUP packets */
1527         dwc->ep0state = EP0_SETUP_PHASE;
1528         dwc3_ep0_out_start(dwc);
1529
1530         dwc3_gadget_enable_irq(dwc);
1531
1532         spin_unlock_irqrestore(&dwc->lock, flags);
1533
1534         return 0;
1535
1536 err3:
1537         __dwc3_gadget_ep_disable(dwc->eps[0]);
1538
1539 err2:
1540         dwc->gadget_driver = NULL;
1541
1542 err1:
1543         spin_unlock_irqrestore(&dwc->lock, flags);
1544
1545         return ret;
1546 }
1547
1548 static int dwc3_gadget_stop(struct usb_gadget *g)
1549 {
1550         struct dwc3             *dwc = gadget_to_dwc(g);
1551         unsigned long           flags;
1552
1553         spin_lock_irqsave(&dwc->lock, flags);
1554
1555         dwc3_gadget_disable_irq(dwc);
1556         __dwc3_gadget_ep_disable(dwc->eps[0]);
1557         __dwc3_gadget_ep_disable(dwc->eps[1]);
1558
1559         dwc->gadget_driver      = NULL;
1560
1561         spin_unlock_irqrestore(&dwc->lock, flags);
1562
1563         return 0;
1564 }
1565
1566 static const struct usb_gadget_ops dwc3_gadget_ops = {
1567         .get_frame              = dwc3_gadget_get_frame,
1568         .wakeup                 = dwc3_gadget_wakeup,
1569         .set_selfpowered        = dwc3_gadget_set_selfpowered,
1570         .pullup                 = dwc3_gadget_pullup,
1571         .udc_start              = dwc3_gadget_start,
1572         .udc_stop               = dwc3_gadget_stop,
1573 };
1574
1575 /* -------------------------------------------------------------------------- */
1576
1577 static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
1578                 u8 num, u32 direction)
1579 {
1580         struct dwc3_ep                  *dep;
1581         u8                              i;
1582
1583         for (i = 0; i < num; i++) {
1584                 u8 epnum = (i << 1) | (!!direction);
1585
1586                 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1587                 if (!dep)
1588                         return -ENOMEM;
1589
1590                 dep->dwc = dwc;
1591                 dep->number = epnum;
1592                 dep->direction = !!direction;
1593                 dwc->eps[epnum] = dep;
1594
1595                 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1596                                 (epnum & 1) ? "in" : "out");
1597
1598                 dep->endpoint.name = dep->name;
1599
1600                 dev_vdbg(dwc->dev, "initializing %s\n", dep->name);
1601
1602                 if (epnum == 0 || epnum == 1) {
1603                         usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
1604                         dep->endpoint.maxburst = 1;
1605                         dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1606                         if (!epnum)
1607                                 dwc->gadget.ep0 = &dep->endpoint;
1608                 } else {
1609                         int             ret;
1610
1611                         usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
1612                         dep->endpoint.max_streams = 15;
1613                         dep->endpoint.ops = &dwc3_gadget_ep_ops;
1614                         list_add_tail(&dep->endpoint.ep_list,
1615                                         &dwc->gadget.ep_list);
1616
1617                         ret = dwc3_alloc_trb_pool(dep);
1618                         if (ret)
1619                                 return ret;
1620                 }
1621
1622                 INIT_LIST_HEAD(&dep->request_list);
1623                 INIT_LIST_HEAD(&dep->req_queued);
1624         }
1625
1626         return 0;
1627 }
1628
1629 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1630 {
1631         int                             ret;
1632
1633         INIT_LIST_HEAD(&dwc->gadget.ep_list);
1634
1635         ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
1636         if (ret < 0) {
1637                 dev_vdbg(dwc->dev, "failed to allocate OUT endpoints\n");
1638                 return ret;
1639         }
1640
1641         ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
1642         if (ret < 0) {
1643                 dev_vdbg(dwc->dev, "failed to allocate IN endpoints\n");
1644                 return ret;
1645         }
1646
1647         return 0;
1648 }
1649
1650 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1651 {
1652         struct dwc3_ep                  *dep;
1653         u8                              epnum;
1654
1655         for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1656                 dep = dwc->eps[epnum];
1657                 if (!dep)
1658                         continue;
1659                 /*
1660                  * Physical endpoints 0 and 1 are special; they form the
1661                  * bi-directional USB endpoint 0.
1662                  *
1663                  * For those two physical endpoints, we don't allocate a TRB
1664                  * pool nor do we add them the endpoints list. Due to that, we
1665                  * shouldn't do these two operations otherwise we would end up
1666                  * with all sorts of bugs when removing dwc3.ko.
1667                  */
1668                 if (epnum != 0 && epnum != 1) {
1669                         dwc3_free_trb_pool(dep);
1670                         list_del(&dep->endpoint.ep_list);
1671                 }
1672
1673                 kfree(dep);
1674         }
1675 }
1676
1677 /* -------------------------------------------------------------------------- */
1678
1679 static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
1680                 struct dwc3_request *req, struct dwc3_trb *trb,
1681                 const struct dwc3_event_depevt *event, int status)
1682 {
1683         unsigned int            count;
1684         unsigned int            s_pkt = 0;
1685         unsigned int            trb_status;
1686
1687         if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1688                 /*
1689                  * We continue despite the error. There is not much we
1690                  * can do. If we don't clean it up we loop forever. If
1691                  * we skip the TRB then it gets overwritten after a
1692                  * while since we use them in a ring buffer. A BUG()
1693                  * would help. Lets hope that if this occurs, someone
1694                  * fixes the root cause instead of looking away :)
1695                  */
1696                 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1697                                 dep->name, trb);
1698         count = trb->size & DWC3_TRB_SIZE_MASK;
1699
1700         if (dep->direction) {
1701                 if (count) {
1702                         trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1703                         if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
1704                                 dev_dbg(dwc->dev, "incomplete IN transfer %s\n",
1705                                                 dep->name);
1706                                 /*
1707                                  * If missed isoc occurred and there is
1708                                  * no request queued then issue END
1709                                  * TRANSFER, so that core generates
1710                                  * next xfernotready and we will issue
1711                                  * a fresh START TRANSFER.
1712                                  * If there are still queued request
1713                                  * then wait, do not issue either END
1714                                  * or UPDATE TRANSFER, just attach next
1715                                  * request in request_list during
1716                                  * giveback.If any future queued request
1717                                  * is successfully transferred then we
1718                                  * will issue UPDATE TRANSFER for all
1719                                  * request in the request_list.
1720                                  */
1721                                 dep->flags |= DWC3_EP_MISSED_ISOC;
1722                         } else {
1723                                 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1724                                                 dep->name);
1725                                 status = -ECONNRESET;
1726                         }
1727                 } else {
1728                         dep->flags &= ~DWC3_EP_MISSED_ISOC;
1729                 }
1730         } else {
1731                 if (count && (event->status & DEPEVT_STATUS_SHORT))
1732                         s_pkt = 1;
1733         }
1734
1735         /*
1736          * We assume here we will always receive the entire data block
1737          * which we should receive. Meaning, if we program RX to
1738          * receive 4K but we receive only 2K, we assume that's all we
1739          * should receive and we simply bounce the request back to the
1740          * gadget driver for further processing.
1741          */
1742         req->request.actual += req->request.length - count;
1743         if (s_pkt)
1744                 return 1;
1745         if ((event->status & DEPEVT_STATUS_LST) &&
1746                         (trb->ctrl & (DWC3_TRB_CTRL_LST |
1747                                 DWC3_TRB_CTRL_HWO)))
1748                 return 1;
1749         if ((event->status & DEPEVT_STATUS_IOC) &&
1750                         (trb->ctrl & DWC3_TRB_CTRL_IOC))
1751                 return 1;
1752         return 0;
1753 }
1754
1755 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1756                 const struct dwc3_event_depevt *event, int status)
1757 {
1758         struct dwc3_request     *req;
1759         struct dwc3_trb         *trb;
1760         unsigned int            slot;
1761         int                     ret;
1762
1763         do {
1764                 req = next_request(&dep->req_queued);
1765                 if (!req) {
1766                         WARN_ON_ONCE(1);
1767                         return 1;
1768                 }
1769
1770                 slot = req->start_slot;
1771                 if ((slot == DWC3_TRB_NUM - 1) &&
1772                         usb_endpoint_xfer_isoc(dep->endpoint.desc))
1773                         slot++;
1774                 slot %= DWC3_TRB_NUM;
1775                 trb = &dep->trb_pool[slot];
1776
1777                 dwc3_flush_cache((int)trb, sizeof(*trb));
1778                 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
1779                                 event, status);
1780                 if (ret)
1781                         break;
1782
1783                 dwc3_gadget_giveback(dep, req, status);
1784
1785                 if (ret)
1786                         break;
1787         } while (1);
1788
1789         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1790                         list_empty(&dep->req_queued)) {
1791                 if (list_empty(&dep->request_list)) {
1792                         /*
1793                          * If there is no entry in request list then do
1794                          * not issue END TRANSFER now. Just set PENDING
1795                          * flag, so that END TRANSFER is issued when an
1796                          * entry is added into request list.
1797                          */
1798                         dep->flags = DWC3_EP_PENDING_REQUEST;
1799                 } else {
1800                         dwc3_stop_active_transfer(dwc, dep->number, true);
1801                         dep->flags = DWC3_EP_ENABLED;
1802                 }
1803                 return 1;
1804         }
1805
1806         return 1;
1807 }
1808
1809 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
1810                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1811 {
1812         unsigned                status = 0;
1813         int                     clean_busy;
1814
1815         if (event->status & DEPEVT_STATUS_BUSERR)
1816                 status = -ECONNRESET;
1817
1818         clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
1819         if (clean_busy)
1820                 dep->flags &= ~DWC3_EP_BUSY;
1821
1822         /*
1823          * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
1824          * See dwc3_gadget_linksts_change_interrupt() for 1st half.
1825          */
1826         if (dwc->revision < DWC3_REVISION_183A) {
1827                 u32             reg;
1828                 int             i;
1829
1830                 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
1831                         dep = dwc->eps[i];
1832
1833                         if (!(dep->flags & DWC3_EP_ENABLED))
1834                                 continue;
1835
1836                         if (!list_empty(&dep->req_queued))
1837                                 return;
1838                 }
1839
1840                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1841                 reg |= dwc->u1u2;
1842                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1843
1844                 dwc->u1u2 = 0;
1845         }
1846 }
1847
1848 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
1849                 const struct dwc3_event_depevt *event)
1850 {
1851         struct dwc3_ep          *dep;
1852         u8                      epnum = event->endpoint_number;
1853
1854         dep = dwc->eps[epnum];
1855
1856         if (!(dep->flags & DWC3_EP_ENABLED))
1857                 return;
1858
1859         if (epnum == 0 || epnum == 1) {
1860                 dwc3_ep0_interrupt(dwc, event);
1861                 return;
1862         }
1863
1864         switch (event->endpoint_event) {
1865         case DWC3_DEPEVT_XFERCOMPLETE:
1866                 dep->resource_index = 0;
1867
1868                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1869                         dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n",
1870                                         dep->name);
1871                         return;
1872                 }
1873
1874                 dwc3_endpoint_transfer_complete(dwc, dep, event);
1875                 break;
1876         case DWC3_DEPEVT_XFERINPROGRESS:
1877                 dwc3_endpoint_transfer_complete(dwc, dep, event);
1878                 break;
1879         case DWC3_DEPEVT_XFERNOTREADY:
1880                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1881                         dwc3_gadget_start_isoc(dwc, dep, event);
1882                 } else {
1883                         int ret;
1884
1885                         dev_vdbg(dwc->dev, "%s: reason %s\n",
1886                                         dep->name, event->status &
1887                                         DEPEVT_STATUS_TRANSFER_ACTIVE
1888                                         ? "Transfer Active"
1889                                         : "Transfer Not Active");
1890
1891                         ret = __dwc3_gadget_kick_transfer(dep, 0, 1);
1892                         if (!ret || ret == -EBUSY)
1893                                 return;
1894
1895                         dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1896                                         dep->name);
1897                 }
1898
1899                 break;
1900         case DWC3_DEPEVT_STREAMEVT:
1901                 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
1902                         dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
1903                                         dep->name);
1904                         return;
1905                 }
1906
1907                 switch (event->status) {
1908                 case DEPEVT_STREAMEVT_FOUND:
1909                         dev_vdbg(dwc->dev, "Stream %d found and started\n",
1910                                         event->parameters);
1911
1912                         break;
1913                 case DEPEVT_STREAMEVT_NOTFOUND:
1914                         /* FALLTHROUGH */
1915                 default:
1916                         dev_dbg(dwc->dev, "Couldn't find suitable stream\n");
1917                 }
1918                 break;
1919         case DWC3_DEPEVT_RXTXFIFOEVT:
1920                 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name);
1921                 break;
1922         case DWC3_DEPEVT_EPCMDCMPLT:
1923                 dev_vdbg(dwc->dev, "Endpoint Command Complete\n");
1924                 break;
1925         }
1926 }
1927
1928 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
1929 {
1930         if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
1931                 spin_unlock(&dwc->lock);
1932                 dwc->gadget_driver->disconnect(&dwc->gadget);
1933                 spin_lock(&dwc->lock);
1934         }
1935 }
1936
1937 static void dwc3_suspend_gadget(struct dwc3 *dwc)
1938 {
1939         if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
1940                 spin_unlock(&dwc->lock);
1941                 dwc->gadget_driver->suspend(&dwc->gadget);
1942                 spin_lock(&dwc->lock);
1943         }
1944 }
1945
1946 static void dwc3_resume_gadget(struct dwc3 *dwc)
1947 {
1948         if (dwc->gadget_driver && dwc->gadget_driver->resume) {
1949                 spin_unlock(&dwc->lock);
1950                 dwc->gadget_driver->resume(&dwc->gadget);
1951         }
1952 }
1953
1954 static void dwc3_reset_gadget(struct dwc3 *dwc)
1955 {
1956         if (!dwc->gadget_driver)
1957                 return;
1958
1959         if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
1960                 spin_unlock(&dwc->lock);
1961                 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
1962                 spin_lock(&dwc->lock);
1963         }
1964 }
1965
1966 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
1967 {
1968         struct dwc3_ep *dep;
1969         struct dwc3_gadget_ep_cmd_params params;
1970         u32 cmd;
1971         int ret;
1972
1973         dep = dwc->eps[epnum];
1974
1975         if (!dep->resource_index)
1976                 return;
1977
1978         /*
1979          * NOTICE: We are violating what the Databook says about the
1980          * EndTransfer command. Ideally we would _always_ wait for the
1981          * EndTransfer Command Completion IRQ, but that's causing too
1982          * much trouble synchronizing between us and gadget driver.
1983          *
1984          * We have discussed this with the IP Provider and it was
1985          * suggested to giveback all requests here, but give HW some
1986          * extra time to synchronize with the interconnect. We're using
1987          * an arbitraty 100us delay for that.
1988          *
1989          * Note also that a similar handling was tested by Synopsys
1990          * (thanks a lot Paul) and nothing bad has come out of it.
1991          * In short, what we're doing is:
1992          *
1993          * - Issue EndTransfer WITH CMDIOC bit set
1994          * - Wait 100us
1995          */
1996
1997         cmd = DWC3_DEPCMD_ENDTRANSFER;
1998         cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
1999         cmd |= DWC3_DEPCMD_CMDIOC;
2000         cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2001         memset(&params, 0, sizeof(params));
2002         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
2003         WARN_ON_ONCE(ret);
2004         dep->resource_index = 0;
2005         dep->flags &= ~DWC3_EP_BUSY;
2006         udelay(100);
2007 }
2008
2009 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2010 {
2011         u32 epnum;
2012
2013         for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2014                 struct dwc3_ep *dep;
2015
2016                 dep = dwc->eps[epnum];
2017                 if (!dep)
2018                         continue;
2019
2020                 if (!(dep->flags & DWC3_EP_ENABLED))
2021                         continue;
2022
2023                 dwc3_remove_requests(dwc, dep);
2024         }
2025 }
2026
2027 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2028 {
2029         u32 epnum;
2030
2031         for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2032                 struct dwc3_ep *dep;
2033                 struct dwc3_gadget_ep_cmd_params params;
2034                 int ret;
2035
2036                 dep = dwc->eps[epnum];
2037                 if (!dep)
2038                         continue;
2039
2040                 if (!(dep->flags & DWC3_EP_STALL))
2041                         continue;
2042
2043                 dep->flags &= ~DWC3_EP_STALL;
2044
2045                 memset(&params, 0, sizeof(params));
2046                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
2047                                 DWC3_DEPCMD_CLEARSTALL, &params);
2048                 WARN_ON_ONCE(ret);
2049         }
2050 }
2051
2052 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2053 {
2054         int                     reg;
2055
2056         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2057         reg &= ~DWC3_DCTL_INITU1ENA;
2058         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2059
2060         reg &= ~DWC3_DCTL_INITU2ENA;
2061         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2062
2063         dwc3_disconnect_gadget(dwc);
2064         dwc->start_config_issued = false;
2065
2066         dwc->gadget.speed = USB_SPEED_UNKNOWN;
2067         dwc->setup_packet_pending = false;
2068         usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2069 }
2070
2071 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2072 {
2073         u32                     reg;
2074
2075         /*
2076          * WORKAROUND: DWC3 revisions <1.88a have an issue which
2077          * would cause a missing Disconnect Event if there's a
2078          * pending Setup Packet in the FIFO.
2079          *
2080          * There's no suggested workaround on the official Bug
2081          * report, which states that "unless the driver/application
2082          * is doing any special handling of a disconnect event,
2083          * there is no functional issue".
2084          *
2085          * Unfortunately, it turns out that we _do_ some special
2086          * handling of a disconnect event, namely complete all
2087          * pending transfers, notify gadget driver of the
2088          * disconnection, and so on.
2089          *
2090          * Our suggested workaround is to follow the Disconnect
2091          * Event steps here, instead, based on a setup_packet_pending
2092          * flag. Such flag gets set whenever we have a XferNotReady
2093          * event on EP0 and gets cleared on XferComplete for the
2094          * same endpoint.
2095          *
2096          * Refers to:
2097          *
2098          * STAR#9000466709: RTL: Device : Disconnect event not
2099          * generated if setup packet pending in FIFO
2100          */
2101         if (dwc->revision < DWC3_REVISION_188A) {
2102                 if (dwc->setup_packet_pending)
2103                         dwc3_gadget_disconnect_interrupt(dwc);
2104         }
2105
2106         dwc3_reset_gadget(dwc);
2107
2108         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2109         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2110         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2111         dwc->test_mode = false;
2112
2113         dwc3_stop_active_transfers(dwc);
2114         dwc3_clear_stall_all_ep(dwc);
2115         dwc->start_config_issued = false;
2116
2117         /* Reset device address to zero */
2118         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2119         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2120         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2121 }
2122
2123 static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2124 {
2125         u32 reg;
2126         u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2127
2128         /*
2129          * We change the clock only at SS but I dunno why I would want to do
2130          * this. Maybe it becomes part of the power saving plan.
2131          */
2132
2133         if (speed != DWC3_DSTS_SUPERSPEED)
2134                 return;
2135
2136         /*
2137          * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2138          * each time on Connect Done.
2139          */
2140         if (!usb30_clock)
2141                 return;
2142
2143         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2144         reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2145         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2146 }
2147
2148 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2149 {
2150         struct dwc3_ep          *dep;
2151         int                     ret;
2152         u32                     reg;
2153         u8                      speed;
2154
2155         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2156         speed = reg & DWC3_DSTS_CONNECTSPD;
2157         dwc->speed = speed;
2158
2159         dwc3_update_ram_clk_sel(dwc, speed);
2160
2161         switch (speed) {
2162         case DWC3_DCFG_SUPERSPEED:
2163                 /*
2164                  * WORKAROUND: DWC3 revisions <1.90a have an issue which
2165                  * would cause a missing USB3 Reset event.
2166                  *
2167                  * In such situations, we should force a USB3 Reset
2168                  * event by calling our dwc3_gadget_reset_interrupt()
2169                  * routine.
2170                  *
2171                  * Refers to:
2172                  *
2173                  * STAR#9000483510: RTL: SS : USB3 reset event may
2174                  * not be generated always when the link enters poll
2175                  */
2176                 if (dwc->revision < DWC3_REVISION_190A)
2177                         dwc3_gadget_reset_interrupt(dwc);
2178
2179                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2180                 dwc->gadget.ep0->maxpacket = 512;
2181                 dwc->gadget.speed = USB_SPEED_SUPER;
2182                 break;
2183         case DWC3_DCFG_HIGHSPEED:
2184                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2185                 dwc->gadget.ep0->maxpacket = 64;
2186                 dwc->gadget.speed = USB_SPEED_HIGH;
2187                 break;
2188         case DWC3_DCFG_FULLSPEED2:
2189         case DWC3_DCFG_FULLSPEED1:
2190                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2191                 dwc->gadget.ep0->maxpacket = 64;
2192                 dwc->gadget.speed = USB_SPEED_FULL;
2193                 break;
2194         case DWC3_DCFG_LOWSPEED:
2195                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2196                 dwc->gadget.ep0->maxpacket = 8;
2197                 dwc->gadget.speed = USB_SPEED_LOW;
2198                 break;
2199         }
2200
2201         /* Enable USB2 LPM Capability */
2202
2203         if ((dwc->revision > DWC3_REVISION_194A)
2204                         && (speed != DWC3_DCFG_SUPERSPEED)) {
2205                 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2206                 reg |= DWC3_DCFG_LPM_CAP;
2207                 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2208
2209                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2210                 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2211
2212                 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2213
2214                 /*
2215                  * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2216                  * DCFG.LPMCap is set, core responses with an ACK and the
2217                  * BESL value in the LPM token is less than or equal to LPM
2218                  * NYET threshold.
2219                  */
2220                 if (dwc->revision < DWC3_REVISION_240A  && dwc->has_lpm_erratum)
2221                         WARN(true, "LPM Erratum not available on dwc3 revisisions < 2.40a\n");
2222
2223                 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2224                         reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2225
2226                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2227         } else {
2228                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2229                 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2230                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2231         }
2232
2233         dep = dwc->eps[0];
2234         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2235                         false);
2236         if (ret) {
2237                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2238                 return;
2239         }
2240
2241         dep = dwc->eps[1];
2242         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2243                         false);
2244         if (ret) {
2245                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2246                 return;
2247         }
2248
2249         /*
2250          * Configure PHY via GUSB3PIPECTLn if required.
2251          *
2252          * Update GTXFIFOSIZn
2253          *
2254          * In both cases reset values should be sufficient.
2255          */
2256 }
2257
2258 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2259 {
2260         /*
2261          * TODO take core out of low power mode when that's
2262          * implemented.
2263          */
2264
2265         dwc->gadget_driver->resume(&dwc->gadget);
2266 }
2267
2268 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2269                 unsigned int evtinfo)
2270 {
2271         enum dwc3_link_state    next = evtinfo & DWC3_LINK_STATE_MASK;
2272         unsigned int            pwropt;
2273
2274         /*
2275          * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2276          * Hibernation mode enabled which would show up when device detects
2277          * host-initiated U3 exit.
2278          *
2279          * In that case, device will generate a Link State Change Interrupt
2280          * from U3 to RESUME which is only necessary if Hibernation is
2281          * configured in.
2282          *
2283          * There are no functional changes due to such spurious event and we
2284          * just need to ignore it.
2285          *
2286          * Refers to:
2287          *
2288          * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2289          * operational mode
2290          */
2291         pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2292         if ((dwc->revision < DWC3_REVISION_250A) &&
2293                         (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2294                 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2295                                 (next == DWC3_LINK_STATE_RESUME)) {
2296                         dev_vdbg(dwc->dev, "ignoring transition U3 -> Resume\n");
2297                         return;
2298                 }
2299         }
2300
2301         /*
2302          * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2303          * on the link partner, the USB session might do multiple entry/exit
2304          * of low power states before a transfer takes place.
2305          *
2306          * Due to this problem, we might experience lower throughput. The
2307          * suggested workaround is to disable DCTL[12:9] bits if we're
2308          * transitioning from U1/U2 to U0 and enable those bits again
2309          * after a transfer completes and there are no pending transfers
2310          * on any of the enabled endpoints.
2311          *
2312          * This is the first half of that workaround.
2313          *
2314          * Refers to:
2315          *
2316          * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2317          * core send LGO_Ux entering U0
2318          */
2319         if (dwc->revision < DWC3_REVISION_183A) {
2320                 if (next == DWC3_LINK_STATE_U0) {
2321                         u32     u1u2;
2322                         u32     reg;
2323
2324                         switch (dwc->link_state) {
2325                         case DWC3_LINK_STATE_U1:
2326                         case DWC3_LINK_STATE_U2:
2327                                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2328                                 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2329                                                 | DWC3_DCTL_ACCEPTU2ENA
2330                                                 | DWC3_DCTL_INITU1ENA
2331                                                 | DWC3_DCTL_ACCEPTU1ENA);
2332
2333                                 if (!dwc->u1u2)
2334                                         dwc->u1u2 = reg & u1u2;
2335
2336                                 reg &= ~u1u2;
2337
2338                                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2339                                 break;
2340                         default:
2341                                 /* do nothing */
2342                                 break;
2343                         }
2344                 }
2345         }
2346
2347         switch (next) {
2348         case DWC3_LINK_STATE_U1:
2349                 if (dwc->speed == USB_SPEED_SUPER)
2350                         dwc3_suspend_gadget(dwc);
2351                 break;
2352         case DWC3_LINK_STATE_U2:
2353         case DWC3_LINK_STATE_U3:
2354                 dwc3_suspend_gadget(dwc);
2355                 break;
2356         case DWC3_LINK_STATE_RESUME:
2357                 dwc3_resume_gadget(dwc);
2358                 break;
2359         default:
2360                 /* do nothing */
2361                 break;
2362         }
2363
2364         dwc->link_state = next;
2365 }
2366
2367 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2368                 unsigned int evtinfo)
2369 {
2370         unsigned int is_ss = evtinfo & BIT(4);
2371
2372         /**
2373          * WORKAROUND: DWC3 revison 2.20a with hibernation support
2374          * have a known issue which can cause USB CV TD.9.23 to fail
2375          * randomly.
2376          *
2377          * Because of this issue, core could generate bogus hibernation
2378          * events which SW needs to ignore.
2379          *
2380          * Refers to:
2381          *
2382          * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2383          * Device Fallback from SuperSpeed
2384          */
2385         if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2386                 return;
2387
2388         /* enter hibernation here */
2389 }
2390
2391 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2392                 const struct dwc3_event_devt *event)
2393 {
2394         switch (event->type) {
2395         case DWC3_DEVICE_EVENT_DISCONNECT:
2396                 dwc3_gadget_disconnect_interrupt(dwc);
2397                 break;
2398         case DWC3_DEVICE_EVENT_RESET:
2399                 dwc3_gadget_reset_interrupt(dwc);
2400                 break;
2401         case DWC3_DEVICE_EVENT_CONNECT_DONE:
2402                 dwc3_gadget_conndone_interrupt(dwc);
2403                 break;
2404         case DWC3_DEVICE_EVENT_WAKEUP:
2405                 dwc3_gadget_wakeup_interrupt(dwc);
2406                 break;
2407         case DWC3_DEVICE_EVENT_HIBER_REQ:
2408                 if (!dwc->has_hibernation) {
2409                         WARN(1 ,"unexpected hibernation event\n");
2410                         break;
2411                 }
2412                 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2413                 break;
2414         case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2415                 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2416                 break;
2417         case DWC3_DEVICE_EVENT_EOPF:
2418                 dev_vdbg(dwc->dev, "End of Periodic Frame\n");
2419                 break;
2420         case DWC3_DEVICE_EVENT_SOF:
2421                 dev_vdbg(dwc->dev, "Start of Periodic Frame\n");
2422                 break;
2423         case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2424                 dev_vdbg(dwc->dev, "Erratic Error\n");
2425                 break;
2426         case DWC3_DEVICE_EVENT_CMD_CMPL:
2427                 dev_vdbg(dwc->dev, "Command Complete\n");
2428                 break;
2429         case DWC3_DEVICE_EVENT_OVERFLOW:
2430                 dev_vdbg(dwc->dev, "Overflow\n");
2431                 break;
2432         default:
2433                 dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2434         }
2435 }
2436
2437 static void dwc3_process_event_entry(struct dwc3 *dwc,
2438                 const union dwc3_event *event)
2439 {
2440         /* Endpoint IRQ, handle it and return early */
2441         if (event->type.is_devspec == 0) {
2442                 /* depevt */
2443                 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2444         }
2445
2446         switch (event->type.type) {
2447         case DWC3_EVENT_TYPE_DEV:
2448                 dwc3_gadget_interrupt(dwc, &event->devt);
2449                 break;
2450         /* REVISIT what to do with Carkit and I2C events ? */
2451         default:
2452                 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2453         }
2454 }
2455
2456 static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
2457 {
2458         struct dwc3_event_buffer *evt;
2459         irqreturn_t ret = IRQ_NONE;
2460         int left;
2461         u32 reg;
2462
2463         evt = dwc->ev_buffs[buf];
2464         left = evt->count;
2465
2466         if (!(evt->flags & DWC3_EVENT_PENDING))
2467                 return IRQ_NONE;
2468
2469         while (left > 0) {
2470                 union dwc3_event event;
2471
2472                 event.raw = *(u32 *) (evt->buf + evt->lpos);
2473
2474                 dwc3_process_event_entry(dwc, &event);
2475
2476                 /*
2477                  * FIXME we wrap around correctly to the next entry as
2478                  * almost all entries are 4 bytes in size. There is one
2479                  * entry which has 12 bytes which is a regular entry
2480                  * followed by 8 bytes data. ATM I don't know how
2481                  * things are organized if we get next to the a
2482                  * boundary so I worry about that once we try to handle
2483                  * that.
2484                  */
2485                 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2486                 left -= 4;
2487
2488                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4);
2489         }
2490
2491         evt->count = 0;
2492         evt->flags &= ~DWC3_EVENT_PENDING;
2493         ret = IRQ_HANDLED;
2494
2495         /* Unmask interrupt */
2496         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2497         reg &= ~DWC3_GEVNTSIZ_INTMASK;
2498         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
2499
2500         return ret;
2501 }
2502
2503 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc)
2504 {
2505         struct dwc3 *dwc = _dwc;
2506         unsigned long flags;
2507         irqreturn_t ret = IRQ_NONE;
2508         int i;
2509
2510         spin_lock_irqsave(&dwc->lock, flags);
2511
2512         for (i = 0; i < dwc->num_event_buffers; i++)
2513                 ret |= dwc3_process_event_buf(dwc, i);
2514
2515         spin_unlock_irqrestore(&dwc->lock, flags);
2516
2517         return ret;
2518 }
2519
2520 static irqreturn_t dwc3_check_event_buf(struct dwc3 *dwc, u32 buf)
2521 {
2522         struct dwc3_event_buffer *evt;
2523         u32 count;
2524         u32 reg;
2525
2526         evt = dwc->ev_buffs[buf];
2527
2528         count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
2529         count &= DWC3_GEVNTCOUNT_MASK;
2530         if (!count)
2531                 return IRQ_NONE;
2532
2533         evt->count = count;
2534         evt->flags |= DWC3_EVENT_PENDING;
2535
2536         /* Mask interrupt */
2537         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2538         reg |= DWC3_GEVNTSIZ_INTMASK;
2539         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
2540
2541         return IRQ_WAKE_THREAD;
2542 }
2543
2544 static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
2545 {
2546         struct dwc3                     *dwc = _dwc;
2547         int                             i;
2548         irqreturn_t                     ret = IRQ_NONE;
2549
2550         spin_lock(&dwc->lock);
2551
2552         for (i = 0; i < dwc->num_event_buffers; i++) {
2553                 irqreturn_t status;
2554
2555                 status = dwc3_check_event_buf(dwc, i);
2556                 if (status == IRQ_WAKE_THREAD)
2557                         ret = status;
2558         }
2559
2560         spin_unlock(&dwc->lock);
2561
2562         return ret;
2563 }
2564
2565 /**
2566  * dwc3_gadget_init - Initializes gadget related registers
2567  * @dwc: pointer to our controller context structure
2568  *
2569  * Returns 0 on success otherwise negative errno.
2570  */
2571 int dwc3_gadget_init(struct dwc3 *dwc)
2572 {
2573         int                                     ret;
2574
2575         dwc->ctrl_req = dma_alloc_coherent(sizeof(*dwc->ctrl_req),
2576                                         (unsigned long *)&dwc->ctrl_req_addr);
2577         if (!dwc->ctrl_req) {
2578                 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2579                 ret = -ENOMEM;
2580                 goto err0;
2581         }
2582
2583         dwc->ep0_trb = dma_alloc_coherent(sizeof(*dwc->ep0_trb) * 2,
2584                                           (unsigned long *)&dwc->ep0_trb_addr);
2585         if (!dwc->ep0_trb) {
2586                 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2587                 ret = -ENOMEM;
2588                 goto err1;
2589         }
2590
2591         dwc->setup_buf = memalign(CONFIG_SYS_CACHELINE_SIZE,
2592                                   DWC3_EP0_BOUNCE_SIZE);
2593         if (!dwc->setup_buf) {
2594                 ret = -ENOMEM;
2595                 goto err2;
2596         }
2597
2598         dwc->ep0_bounce = dma_alloc_coherent(DWC3_EP0_BOUNCE_SIZE,
2599                                         (unsigned long *)&dwc->ep0_bounce_addr);
2600         if (!dwc->ep0_bounce) {
2601                 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2602                 ret = -ENOMEM;
2603                 goto err3;
2604         }
2605
2606         dwc->gadget.ops                 = &dwc3_gadget_ops;
2607         dwc->gadget.max_speed           = USB_SPEED_SUPER;
2608         dwc->gadget.speed               = USB_SPEED_UNKNOWN;
2609         dwc->gadget.name                = "dwc3-gadget";
2610
2611         /*
2612          * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
2613          * on ep out.
2614          */
2615         dwc->gadget.quirk_ep_out_aligned_size = true;
2616
2617         /*
2618          * REVISIT: Here we should clear all pending IRQs to be
2619          * sure we're starting from a well known location.
2620          */
2621
2622         ret = dwc3_gadget_init_endpoints(dwc);
2623         if (ret)
2624                 goto err4;
2625
2626         ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2627         if (ret) {
2628                 dev_err(dwc->dev, "failed to register udc\n");
2629                 goto err4;
2630         }
2631
2632         return 0;
2633
2634 err4:
2635         dwc3_gadget_free_endpoints(dwc);
2636         dma_free_coherent(dwc->ep0_bounce);
2637
2638 err3:
2639         kfree(dwc->setup_buf);
2640
2641 err2:
2642         dma_free_coherent(dwc->ep0_trb);
2643
2644 err1:
2645         dma_free_coherent(dwc->ctrl_req);
2646
2647 err0:
2648         return ret;
2649 }
2650
2651 /* -------------------------------------------------------------------------- */
2652
2653 void dwc3_gadget_exit(struct dwc3 *dwc)
2654 {
2655         usb_del_gadget_udc(&dwc->gadget);
2656
2657         dwc3_gadget_free_endpoints(dwc);
2658
2659         dma_free_coherent(dwc->ep0_bounce);
2660
2661         kfree(dwc->setup_buf);
2662
2663         dma_free_coherent(dwc->ep0_trb);
2664
2665         dma_free_coherent(dwc->ctrl_req);
2666 }
2667
2668 /**
2669  * dwc3_gadget_uboot_handle_interrupt - handle dwc3 gadget interrupt
2670  * @dwc: struct dwce *
2671  *
2672  * Handles ep0 and gadget interrupt
2673  *
2674  * Should be called from dwc3 core.
2675  */
2676 void dwc3_gadget_uboot_handle_interrupt(struct dwc3 *dwc)
2677 {
2678         dwc3_interrupt(0, dwc);
2679         dwc3_thread_interrupt(0, dwc);
2680 }