2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/kernel.h>
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/spinlock.h>
23 #include <linux/platform_device.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/interrupt.h>
27 #include <linux/list.h>
28 #include <linux/dma-mapping.h>
30 #include <linux/usb/ch9.h>
31 #include <linux/usb/gadget.h>
39 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
40 * @dwc: pointer to our context structure
41 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
43 * Caller should take care of locking. This function will
44 * return 0 on success or -EINVAL if wrong Test Selector
47 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
51 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
52 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
66 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
72 * dwc3_gadget_get_link_state - Gets current state of USB Link
73 * @dwc: pointer to our context structure
75 * Caller should take care of locking. This function will
76 * return the link state on success (>= 0) or -ETIMEDOUT.
78 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
82 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
84 return DWC3_DSTS_USBLNKST(reg);
88 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
89 * @dwc: pointer to our context structure
90 * @state: the state to put link into
92 * Caller should take care of locking. This function will
93 * return 0 on success or -ETIMEDOUT.
95 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
101 * Wait until device controller is ready. Only applies to 1.94a and
104 if (dwc->revision >= DWC3_REVISION_194A) {
106 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
107 if (reg & DWC3_DSTS_DCNRD)
117 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
118 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
120 /* set requested state */
121 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
122 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
125 * The following code is racy when called from dwc3_gadget_wakeup,
126 * and is not needed, at least on newer versions
128 if (dwc->revision >= DWC3_REVISION_194A)
131 /* wait for a change in DSTS */
134 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
136 if (DWC3_DSTS_USBLNKST(reg) == state)
146 * dwc3_ep_inc_trb() - Increment a TRB index.
147 * @index - Pointer to the TRB index to increment.
149 * The index should never point to the link TRB. After incrementing,
150 * if it is point to the link TRB, wrap around to the beginning. The
151 * link TRB is always at the last TRB entry.
153 static void dwc3_ep_inc_trb(u8 *index)
156 if (*index == (DWC3_TRB_NUM - 1))
160 static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
162 dwc3_ep_inc_trb(&dep->trb_enqueue);
165 static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
167 dwc3_ep_inc_trb(&dep->trb_dequeue);
170 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
173 struct dwc3 *dwc = dep->dwc;
175 req->started = false;
176 list_del(&req->list);
180 if (req->request.status == -EINPROGRESS)
181 req->request.status = status;
183 usb_gadget_unmap_request_by_dev(dwc->sysdev,
184 &req->request, req->direction);
186 trace_dwc3_gadget_giveback(req);
188 spin_unlock(&dwc->lock);
189 usb_gadget_giveback_request(&dep->endpoint, &req->request);
190 spin_lock(&dwc->lock);
193 pm_runtime_put(dwc->dev);
196 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
203 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
204 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
207 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
208 if (!(reg & DWC3_DGCMD_CMDACT)) {
209 status = DWC3_DGCMD_STATUS(reg);
221 trace_dwc3_gadget_generic_cmd(cmd, param, status);
226 static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
228 int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
229 struct dwc3_gadget_ep_cmd_params *params)
231 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
232 struct dwc3 *dwc = dep->dwc;
241 * Synopsys Databook 2.60a states, on section 6.3.2.5.[1-8], that if
242 * we're issuing an endpoint command, we must check if
243 * GUSB2PHYCFG.SUSPHY bit is set. If it is, then we need to clear it.
245 * We will also set SUSPHY bit to what it was before returning as stated
246 * by the same section on Synopsys databook.
248 if (dwc->gadget.speed <= USB_SPEED_HIGH) {
249 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
250 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
252 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
253 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
257 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
260 needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 ||
261 dwc->link_state == DWC3_LINK_STATE_U2 ||
262 dwc->link_state == DWC3_LINK_STATE_U3);
264 if (unlikely(needs_wakeup)) {
265 ret = __dwc3_gadget_wakeup(dwc);
266 dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
271 dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
272 dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
273 dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
276 * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're
277 * not relying on XferNotReady, we can make use of a special "No
278 * Response Update Transfer" command where we should clear both CmdAct
281 * With this, we don't need to wait for command completion and can
282 * straight away issue further commands to the endpoint.
284 * NOTICE: We're making an assumption that control endpoints will never
285 * make use of Update Transfer command. This is a safe assumption
286 * because we can never have more than one request at a time with
287 * Control Endpoints. If anybody changes that assumption, this chunk
288 * needs to be updated accordingly.
290 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER &&
291 !usb_endpoint_xfer_isoc(desc))
292 cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT);
294 cmd |= DWC3_DEPCMD_CMDACT;
296 dwc3_writel(dep->regs, DWC3_DEPCMD, cmd);
298 reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
299 if (!(reg & DWC3_DEPCMD_CMDACT)) {
300 cmd_status = DWC3_DEPCMD_STATUS(reg);
302 switch (cmd_status) {
306 case DEPEVT_TRANSFER_NO_RESOURCE:
309 case DEPEVT_TRANSFER_BUS_EXPIRY:
311 * SW issues START TRANSFER command to
312 * isochronous ep with future frame interval. If
313 * future interval time has already passed when
314 * core receives the command, it will respond
315 * with an error status of 'Bus Expiry'.
317 * Instead of always returning -EINVAL, let's
318 * give a hint to the gadget driver that this is
319 * the case by returning -EAGAIN.
324 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
333 cmd_status = -ETIMEDOUT;
336 trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status);
339 switch (DWC3_DEPCMD_CMD(cmd)) {
340 case DWC3_DEPCMD_STARTTRANSFER:
341 dep->flags |= DWC3_EP_TRANSFER_STARTED;
343 case DWC3_DEPCMD_ENDTRANSFER:
344 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
352 if (unlikely(susphy)) {
353 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
354 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
355 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
361 static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
363 struct dwc3 *dwc = dep->dwc;
364 struct dwc3_gadget_ep_cmd_params params;
365 u32 cmd = DWC3_DEPCMD_CLEARSTALL;
368 * As of core revision 2.60a the recommended programming model
369 * is to set the ClearPendIN bit when issuing a Clear Stall EP
370 * command for IN endpoints. This is to prevent an issue where
371 * some (non-compliant) hosts may not send ACK TPs for pending
372 * IN transfers due to a mishandled error condition. Synopsys
375 if (dep->direction && (dwc->revision >= DWC3_REVISION_260A) &&
376 (dwc->gadget.speed >= USB_SPEED_SUPER))
377 cmd |= DWC3_DEPCMD_CLEARPENDIN;
379 memset(¶ms, 0, sizeof(params));
381 return dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
384 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
385 struct dwc3_trb *trb)
387 u32 offset = (char *) trb - (char *) dep->trb_pool;
389 return dep->trb_pool_dma + offset;
392 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
394 struct dwc3 *dwc = dep->dwc;
399 dep->trb_pool = dma_alloc_coherent(dwc->sysdev,
400 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
401 &dep->trb_pool_dma, GFP_KERNEL);
402 if (!dep->trb_pool) {
403 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
411 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
413 struct dwc3 *dwc = dep->dwc;
415 dma_free_coherent(dwc->sysdev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
416 dep->trb_pool, dep->trb_pool_dma);
418 dep->trb_pool = NULL;
419 dep->trb_pool_dma = 0;
422 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep);
425 * dwc3_gadget_start_config - Configure EP resources
426 * @dwc: pointer to our controller context structure
427 * @dep: endpoint that is being enabled
429 * The assignment of transfer resources cannot perfectly follow the
430 * data book due to the fact that the controller driver does not have
431 * all knowledge of the configuration in advance. It is given this
432 * information piecemeal by the composite gadget framework after every
433 * SET_CONFIGURATION and SET_INTERFACE. Trying to follow the databook
434 * programming model in this scenario can cause errors. For two
437 * 1) The databook says to do DEPSTARTCFG for every SET_CONFIGURATION
438 * and SET_INTERFACE (8.1.5). This is incorrect in the scenario of
439 * multiple interfaces.
441 * 2) The databook does not mention doing more DEPXFERCFG for new
442 * endpoint on alt setting (8.1.6).
444 * The following simplified method is used instead:
446 * All hardware endpoints can be assigned a transfer resource and this
447 * setting will stay persistent until either a core reset or
448 * hibernation. So whenever we do a DEPSTARTCFG(0) we can go ahead and
449 * do DEPXFERCFG for every hardware endpoint as well. We are
450 * guaranteed that there are as many transfer resources as endpoints.
452 * This function is called for each endpoint when it is being enabled
453 * but is triggered only when called for EP0-out, which always happens
454 * first, and which should only happen in one of the above conditions.
456 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
458 struct dwc3_gadget_ep_cmd_params params;
466 memset(¶ms, 0x00, sizeof(params));
467 cmd = DWC3_DEPCMD_DEPSTARTCFG;
469 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
473 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
474 struct dwc3_ep *dep = dwc->eps[i];
479 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
487 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
488 bool modify, bool restore)
490 const struct usb_ss_ep_comp_descriptor *comp_desc;
491 const struct usb_endpoint_descriptor *desc;
492 struct dwc3_gadget_ep_cmd_params params;
494 if (dev_WARN_ONCE(dwc->dev, modify && restore,
495 "Can't modify and restore\n"))
498 comp_desc = dep->endpoint.comp_desc;
499 desc = dep->endpoint.desc;
501 memset(¶ms, 0x00, sizeof(params));
503 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
504 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
506 /* Burst size is only needed in SuperSpeed mode */
507 if (dwc->gadget.speed >= USB_SPEED_SUPER) {
508 u32 burst = dep->endpoint.maxburst;
509 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
513 params.param0 |= DWC3_DEPCFG_ACTION_MODIFY;
514 } else if (restore) {
515 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
516 params.param2 |= dep->saved_state;
518 params.param0 |= DWC3_DEPCFG_ACTION_INIT;
521 if (usb_endpoint_xfer_control(desc))
522 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN;
524 if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc))
525 params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN;
527 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
528 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
529 | DWC3_DEPCFG_STREAM_EVENT_EN;
530 dep->stream_capable = true;
533 if (!usb_endpoint_xfer_control(desc))
534 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
537 * We are doing 1:1 mapping for endpoints, meaning
538 * Physical Endpoints 2 maps to Logical Endpoint 2 and
539 * so on. We consider the direction bit as part of the physical
540 * endpoint number. So USB endpoint 0x81 is 0x03.
542 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
545 * We must use the lower 16 TX FIFOs even though
549 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
551 if (desc->bInterval) {
552 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
553 dep->interval = 1 << (desc->bInterval - 1);
556 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, ¶ms);
559 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
561 struct dwc3_gadget_ep_cmd_params params;
563 memset(¶ms, 0x00, sizeof(params));
565 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
567 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
572 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
573 * @dep: endpoint to be initialized
574 * @desc: USB Endpoint Descriptor
576 * Caller should take care of locking
578 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
579 bool modify, bool restore)
581 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
582 struct dwc3 *dwc = dep->dwc;
587 if (!(dep->flags & DWC3_EP_ENABLED)) {
588 ret = dwc3_gadget_start_config(dwc, dep);
593 ret = dwc3_gadget_set_ep_config(dwc, dep, modify, restore);
597 if (!(dep->flags & DWC3_EP_ENABLED)) {
598 struct dwc3_trb *trb_st_hw;
599 struct dwc3_trb *trb_link;
601 dep->type = usb_endpoint_type(desc);
602 dep->flags |= DWC3_EP_ENABLED;
603 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
605 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
606 reg |= DWC3_DALEPENA_EP(dep->number);
607 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
609 init_waitqueue_head(&dep->wait_end_transfer);
611 if (usb_endpoint_xfer_control(desc))
614 /* Initialize the TRB ring */
615 dep->trb_dequeue = 0;
616 dep->trb_enqueue = 0;
617 memset(dep->trb_pool, 0,
618 sizeof(struct dwc3_trb) * DWC3_TRB_NUM);
620 /* Link TRB. The HWO bit is never reset */
621 trb_st_hw = &dep->trb_pool[0];
623 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
624 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
625 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
626 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
627 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
631 * Issue StartTransfer here with no-op TRB so we can always rely on No
632 * Response Update Transfer command.
634 if (usb_endpoint_xfer_bulk(desc)) {
635 struct dwc3_gadget_ep_cmd_params params;
636 struct dwc3_trb *trb;
640 memset(¶ms, 0, sizeof(params));
641 trb = &dep->trb_pool[0];
642 trb_dma = dwc3_trb_dma_offset(dep, trb);
644 params.param0 = upper_32_bits(trb_dma);
645 params.param1 = lower_32_bits(trb_dma);
647 cmd = DWC3_DEPCMD_STARTTRANSFER;
649 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
653 dep->flags |= DWC3_EP_BUSY;
655 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
656 WARN_ON_ONCE(!dep->resource_index);
661 trace_dwc3_gadget_ep_enable(dep);
666 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
667 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
669 struct dwc3_request *req;
671 dwc3_stop_active_transfer(dwc, dep->number, true);
673 /* - giveback all requests to gadget driver */
674 while (!list_empty(&dep->started_list)) {
675 req = next_request(&dep->started_list);
677 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
680 while (!list_empty(&dep->pending_list)) {
681 req = next_request(&dep->pending_list);
683 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
688 * __dwc3_gadget_ep_disable - Disables a HW endpoint
689 * @dep: the endpoint to disable
691 * This function also removes requests which are currently processed ny the
692 * hardware and those which are not yet scheduled.
693 * Caller should take care of locking.
695 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
697 struct dwc3 *dwc = dep->dwc;
700 trace_dwc3_gadget_ep_disable(dep);
702 dwc3_remove_requests(dwc, dep);
704 /* make sure HW endpoint isn't stalled */
705 if (dep->flags & DWC3_EP_STALL)
706 __dwc3_gadget_ep_set_halt(dep, 0, false);
708 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
709 reg &= ~DWC3_DALEPENA_EP(dep->number);
710 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
712 dep->stream_capable = false;
714 dep->flags &= DWC3_EP_END_TRANSFER_PENDING;
716 /* Clear out the ep descriptors for non-ep0 */
717 if (dep->number > 1) {
718 dep->endpoint.comp_desc = NULL;
719 dep->endpoint.desc = NULL;
725 /* -------------------------------------------------------------------------- */
727 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
728 const struct usb_endpoint_descriptor *desc)
733 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
738 /* -------------------------------------------------------------------------- */
740 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
741 const struct usb_endpoint_descriptor *desc)
748 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
749 pr_debug("dwc3: invalid parameters\n");
753 if (!desc->wMaxPacketSize) {
754 pr_debug("dwc3: missing wMaxPacketSize\n");
758 dep = to_dwc3_ep(ep);
761 if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
762 "%s is already enabled\n",
766 spin_lock_irqsave(&dwc->lock, flags);
767 ret = __dwc3_gadget_ep_enable(dep, false, false);
768 spin_unlock_irqrestore(&dwc->lock, flags);
773 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
781 pr_debug("dwc3: invalid parameters\n");
785 dep = to_dwc3_ep(ep);
788 if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
789 "%s is already disabled\n",
793 spin_lock_irqsave(&dwc->lock, flags);
794 ret = __dwc3_gadget_ep_disable(dep);
795 spin_unlock_irqrestore(&dwc->lock, flags);
800 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
803 struct dwc3_request *req;
804 struct dwc3_ep *dep = to_dwc3_ep(ep);
806 req = kzalloc(sizeof(*req), gfp_flags);
810 req->epnum = dep->number;
813 dep->allocated_requests++;
815 trace_dwc3_alloc_request(req);
817 return &req->request;
820 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
821 struct usb_request *request)
823 struct dwc3_request *req = to_dwc3_request(request);
824 struct dwc3_ep *dep = to_dwc3_ep(ep);
826 dep->allocated_requests--;
827 trace_dwc3_free_request(req);
831 static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep);
833 static void __dwc3_prepare_one_trb(struct dwc3_ep *dep, struct dwc3_trb *trb,
834 dma_addr_t dma, unsigned length, unsigned chain, unsigned node,
835 unsigned stream_id, unsigned short_not_ok, unsigned no_interrupt)
837 struct dwc3 *dwc = dep->dwc;
838 struct usb_gadget *gadget = &dwc->gadget;
839 enum usb_device_speed speed = gadget->speed;
841 dwc3_ep_inc_enq(dep);
843 trb->size = DWC3_TRB_SIZE_LENGTH(length);
844 trb->bpl = lower_32_bits(dma);
845 trb->bph = upper_32_bits(dma);
847 switch (usb_endpoint_type(dep->endpoint.desc)) {
848 case USB_ENDPOINT_XFER_CONTROL:
849 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
852 case USB_ENDPOINT_XFER_ISOC:
854 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
856 if (speed == USB_SPEED_HIGH) {
857 struct usb_ep *ep = &dep->endpoint;
858 trb->size |= DWC3_TRB_SIZE_PCM1(ep->mult - 1);
861 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
864 /* always enable Interrupt on Missed ISOC */
865 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
868 case USB_ENDPOINT_XFER_BULK:
869 case USB_ENDPOINT_XFER_INT:
870 trb->ctrl = DWC3_TRBCTL_NORMAL;
874 * This is only possible with faulty memory because we
875 * checked it already :)
877 dev_WARN(dwc->dev, "Unknown endpoint type %d\n",
878 usb_endpoint_type(dep->endpoint.desc));
881 /* always enable Continue on Short Packet */
882 if (usb_endpoint_dir_out(dep->endpoint.desc)) {
883 trb->ctrl |= DWC3_TRB_CTRL_CSP;
886 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
889 if ((!no_interrupt && !chain) ||
890 (dwc3_calc_trbs_left(dep) == 0))
891 trb->ctrl |= DWC3_TRB_CTRL_IOC;
894 trb->ctrl |= DWC3_TRB_CTRL_CHN;
896 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
897 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(stream_id);
899 trb->ctrl |= DWC3_TRB_CTRL_HWO;
901 trace_dwc3_prepare_trb(dep, trb);
905 * dwc3_prepare_one_trb - setup one TRB from one request
906 * @dep: endpoint for which this request is prepared
907 * @req: dwc3_request pointer
908 * @chain: should this TRB be chained to the next?
909 * @node: only for isochronous endpoints. First TRB needs different type.
911 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
912 struct dwc3_request *req, unsigned chain, unsigned node)
914 struct dwc3_trb *trb;
915 unsigned length = req->request.length;
916 unsigned stream_id = req->request.stream_id;
917 unsigned short_not_ok = req->request.short_not_ok;
918 unsigned no_interrupt = req->request.no_interrupt;
919 dma_addr_t dma = req->request.dma;
921 trb = &dep->trb_pool[dep->trb_enqueue];
924 dwc3_gadget_move_started_request(req);
926 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
927 dep->queued_requests++;
930 __dwc3_prepare_one_trb(dep, trb, dma, length, chain, node,
931 stream_id, short_not_ok, no_interrupt);
935 * dwc3_ep_prev_trb() - Returns the previous TRB in the ring
936 * @dep: The endpoint with the TRB ring
937 * @index: The index of the current TRB in the ring
939 * Returns the TRB prior to the one pointed to by the index. If the
940 * index is 0, we will wrap backwards, skip the link TRB, and return
941 * the one just before that.
943 static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
948 tmp = DWC3_TRB_NUM - 1;
950 return &dep->trb_pool[tmp - 1];
953 static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
955 struct dwc3_trb *tmp;
956 struct dwc3 *dwc = dep->dwc;
960 * If enqueue & dequeue are equal than it is either full or empty.
962 * One way to know for sure is if the TRB right before us has HWO bit
963 * set or not. If it has, then we're definitely full and can't fit any
964 * more transfers in our ring.
966 if (dep->trb_enqueue == dep->trb_dequeue) {
967 tmp = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
968 if (dev_WARN_ONCE(dwc->dev, tmp->ctrl & DWC3_TRB_CTRL_HWO,
969 "%s No TRBS left\n", dep->name))
972 return DWC3_TRB_NUM - 1;
975 trbs_left = dep->trb_dequeue - dep->trb_enqueue;
976 trbs_left &= (DWC3_TRB_NUM - 1);
978 if (dep->trb_dequeue < dep->trb_enqueue)
984 static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep,
985 struct dwc3_request *req)
987 struct scatterlist *sg = req->sg;
988 struct scatterlist *s;
991 for_each_sg(sg, s, req->num_pending_sgs, i) {
992 unsigned int length = req->request.length;
993 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
994 unsigned int rem = length % maxp;
995 unsigned chain = true;
1000 if (rem && usb_endpoint_dir_out(dep->endpoint.desc) && !chain) {
1001 struct dwc3 *dwc = dep->dwc;
1002 struct dwc3_trb *trb;
1004 req->unaligned = true;
1006 /* prepare normal TRB */
1007 dwc3_prepare_one_trb(dep, req, true, i);
1009 /* Now prepare one extra TRB to align transfer size */
1010 trb = &dep->trb_pool[dep->trb_enqueue];
1011 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr,
1012 maxp - rem, false, 0,
1013 req->request.stream_id,
1014 req->request.short_not_ok,
1015 req->request.no_interrupt);
1017 dwc3_prepare_one_trb(dep, req, chain, i);
1020 if (!dwc3_calc_trbs_left(dep))
1025 static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep,
1026 struct dwc3_request *req)
1028 unsigned int length = req->request.length;
1029 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1030 unsigned int rem = length % maxp;
1032 if (rem && usb_endpoint_dir_out(dep->endpoint.desc)) {
1033 struct dwc3 *dwc = dep->dwc;
1034 struct dwc3_trb *trb;
1036 req->unaligned = true;
1038 /* prepare normal TRB */
1039 dwc3_prepare_one_trb(dep, req, true, 0);
1041 /* Now prepare one extra TRB to align transfer size */
1042 trb = &dep->trb_pool[dep->trb_enqueue];
1043 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, maxp - rem,
1044 false, 0, req->request.stream_id,
1045 req->request.short_not_ok,
1046 req->request.no_interrupt);
1047 } else if (req->request.zero && req->request.length &&
1048 (IS_ALIGNED(req->request.length,dep->endpoint.maxpacket))) {
1049 struct dwc3 *dwc = dep->dwc;
1050 struct dwc3_trb *trb;
1054 /* prepare normal TRB */
1055 dwc3_prepare_one_trb(dep, req, true, 0);
1057 /* Now prepare one extra TRB to handle ZLP */
1058 trb = &dep->trb_pool[dep->trb_enqueue];
1059 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, 0,
1060 false, 0, req->request.stream_id,
1061 req->request.short_not_ok,
1062 req->request.no_interrupt);
1064 dwc3_prepare_one_trb(dep, req, false, 0);
1069 * dwc3_prepare_trbs - setup TRBs from requests
1070 * @dep: endpoint for which requests are being prepared
1072 * The function goes through the requests list and sets up TRBs for the
1073 * transfers. The function returns once there are no more TRBs available or
1074 * it runs out of requests.
1076 static void dwc3_prepare_trbs(struct dwc3_ep *dep)
1078 struct dwc3_request *req, *n;
1080 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
1082 if (!dwc3_calc_trbs_left(dep))
1086 * We can get in a situation where there's a request in the started list
1087 * but there weren't enough TRBs to fully kick it in the first time
1088 * around, so it has been waiting for more TRBs to be freed up.
1090 * In that case, we should check if we have a request with pending_sgs
1091 * in the started list and prepare TRBs for that request first,
1092 * otherwise we will prepare TRBs completely out of order and that will
1095 list_for_each_entry(req, &dep->started_list, list) {
1096 if (req->num_pending_sgs > 0)
1097 dwc3_prepare_one_trb_sg(dep, req);
1099 if (!dwc3_calc_trbs_left(dep))
1103 list_for_each_entry_safe(req, n, &dep->pending_list, list) {
1104 if (req->num_pending_sgs > 0)
1105 dwc3_prepare_one_trb_sg(dep, req);
1107 dwc3_prepare_one_trb_linear(dep, req);
1109 if (!dwc3_calc_trbs_left(dep))
1114 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param)
1116 struct dwc3_gadget_ep_cmd_params params;
1117 struct dwc3_request *req;
1122 starting = !(dep->flags & DWC3_EP_BUSY);
1124 dwc3_prepare_trbs(dep);
1125 req = next_request(&dep->started_list);
1127 dep->flags |= DWC3_EP_PENDING_REQUEST;
1131 memset(¶ms, 0, sizeof(params));
1134 params.param0 = upper_32_bits(req->trb_dma);
1135 params.param1 = lower_32_bits(req->trb_dma);
1136 cmd = DWC3_DEPCMD_STARTTRANSFER |
1137 DWC3_DEPCMD_PARAM(cmd_param);
1139 cmd = DWC3_DEPCMD_UPDATETRANSFER |
1140 DWC3_DEPCMD_PARAM(dep->resource_index);
1143 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1146 * FIXME we need to iterate over the list of requests
1147 * here and stop, unmap, free and del each of the linked
1148 * requests instead of what we do now.
1151 memset(req->trb, 0, sizeof(struct dwc3_trb));
1152 dep->queued_requests--;
1153 dwc3_gadget_giveback(dep, req, ret);
1157 dep->flags |= DWC3_EP_BUSY;
1160 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
1161 WARN_ON_ONCE(!dep->resource_index);
1167 static int __dwc3_gadget_get_frame(struct dwc3 *dwc)
1171 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1172 return DWC3_DSTS_SOFFN(reg);
1175 static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1176 struct dwc3_ep *dep, u32 cur_uf)
1180 if (list_empty(&dep->pending_list)) {
1181 dev_info(dwc->dev, "%s: ran out of requests\n",
1183 dep->flags |= DWC3_EP_PENDING_REQUEST;
1188 * Schedule the first trb for one interval in the future or at
1189 * least 4 microframes.
1191 uf = cur_uf + max_t(u32, 4, dep->interval);
1193 __dwc3_gadget_kick_transfer(dep, uf);
1196 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1197 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1201 mask = ~(dep->interval - 1);
1202 cur_uf = event->parameters & mask;
1204 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1207 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1209 struct dwc3 *dwc = dep->dwc;
1212 if (!dep->endpoint.desc) {
1213 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
1218 if (WARN(req->dep != dep, "request %p belongs to '%s'\n",
1219 &req->request, req->dep->name)) {
1220 dev_err(dwc->dev, "%s: request %p belongs to '%s'\n",
1221 dep->name, &req->request, req->dep->name);
1225 pm_runtime_get(dwc->dev);
1227 req->request.actual = 0;
1228 req->request.status = -EINPROGRESS;
1229 req->direction = dep->direction;
1230 req->epnum = dep->number;
1232 trace_dwc3_ep_queue(req);
1234 ret = usb_gadget_map_request_by_dev(dwc->sysdev, &req->request,
1239 req->sg = req->request.sg;
1240 req->num_pending_sgs = req->request.num_mapped_sgs;
1242 list_add_tail(&req->list, &dep->pending_list);
1245 * NOTICE: Isochronous endpoints should NEVER be prestarted. We must
1246 * wait for a XferNotReady event so we will know what's the current
1247 * (micro-)frame number.
1249 * Without this trick, we are very, very likely gonna get Bus Expiry
1250 * errors which will force us issue EndTransfer command.
1252 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1253 if ((dep->flags & DWC3_EP_PENDING_REQUEST)) {
1254 if (dep->flags & DWC3_EP_TRANSFER_STARTED) {
1255 dwc3_stop_active_transfer(dwc, dep->number, true);
1256 dep->flags = DWC3_EP_ENABLED;
1260 cur_uf = __dwc3_gadget_get_frame(dwc);
1261 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1262 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
1268 if (!dwc3_calc_trbs_left(dep))
1271 ret = __dwc3_gadget_kick_transfer(dep, 0);
1278 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1281 struct dwc3_request *req = to_dwc3_request(request);
1282 struct dwc3_ep *dep = to_dwc3_ep(ep);
1283 struct dwc3 *dwc = dep->dwc;
1285 unsigned long flags;
1289 spin_lock_irqsave(&dwc->lock, flags);
1290 ret = __dwc3_gadget_ep_queue(dep, req);
1291 spin_unlock_irqrestore(&dwc->lock, flags);
1296 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1297 struct usb_request *request)
1299 struct dwc3_request *req = to_dwc3_request(request);
1300 struct dwc3_request *r = NULL;
1302 struct dwc3_ep *dep = to_dwc3_ep(ep);
1303 struct dwc3 *dwc = dep->dwc;
1305 unsigned long flags;
1308 trace_dwc3_ep_dequeue(req);
1310 spin_lock_irqsave(&dwc->lock, flags);
1312 list_for_each_entry(r, &dep->pending_list, list) {
1318 list_for_each_entry(r, &dep->started_list, list) {
1323 /* wait until it is processed */
1324 dwc3_stop_active_transfer(dwc, dep->number, true);
1327 * If request was already started, this means we had to
1328 * stop the transfer. With that we also need to ignore
1329 * all TRBs used by the request, however TRBs can only
1330 * be modified after completion of END_TRANSFER
1331 * command. So what we do here is that we wait for
1332 * END_TRANSFER completion and only after that, we jump
1333 * over TRBs by clearing HWO and incrementing dequeue
1336 * Note that we have 2 possible types of transfers here:
1338 * i) Linear buffer request
1339 * ii) SG-list based request
1341 * SG-list based requests will have r->num_pending_sgs
1342 * set to a valid number (> 0). Linear requests,
1343 * normally use a single TRB.
1345 * For each of these two cases, if r->unaligned flag is
1346 * set, one extra TRB has been used to align transfer
1347 * size to wMaxPacketSize.
1349 * All of these cases need to be taken into
1350 * consideration so we don't mess up our TRB ring
1353 wait_event_lock_irq(dep->wait_end_transfer,
1354 !(dep->flags & DWC3_EP_END_TRANSFER_PENDING),
1360 if (r->num_pending_sgs) {
1361 struct dwc3_trb *trb;
1364 for (i = 0; i < r->num_pending_sgs; i++) {
1366 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1367 dwc3_ep_inc_deq(dep);
1370 if (r->unaligned || r->zero) {
1371 trb = r->trb + r->num_pending_sgs + 1;
1372 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1373 dwc3_ep_inc_deq(dep);
1376 struct dwc3_trb *trb = r->trb;
1378 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1379 dwc3_ep_inc_deq(dep);
1381 if (r->unaligned || r->zero) {
1383 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1384 dwc3_ep_inc_deq(dep);
1389 dev_err(dwc->dev, "request %p was not queued to %s\n",
1396 /* giveback the request */
1397 dep->queued_requests--;
1398 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1401 spin_unlock_irqrestore(&dwc->lock, flags);
1406 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1408 struct dwc3_gadget_ep_cmd_params params;
1409 struct dwc3 *dwc = dep->dwc;
1412 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1413 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1417 memset(¶ms, 0x00, sizeof(params));
1420 struct dwc3_trb *trb;
1422 unsigned transfer_in_flight;
1425 if (dep->flags & DWC3_EP_STALL)
1428 if (dep->number > 1)
1429 trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
1431 trb = &dwc->ep0_trb[dep->trb_enqueue];
1433 transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO;
1434 started = !list_empty(&dep->started_list);
1436 if (!protocol && ((dep->direction && transfer_in_flight) ||
1437 (!dep->direction && started))) {
1441 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
1444 dev_err(dwc->dev, "failed to set STALL on %s\n",
1447 dep->flags |= DWC3_EP_STALL;
1449 if (!(dep->flags & DWC3_EP_STALL))
1452 ret = dwc3_send_clear_stall_ep_cmd(dep);
1454 dev_err(dwc->dev, "failed to clear STALL on %s\n",
1457 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1463 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1465 struct dwc3_ep *dep = to_dwc3_ep(ep);
1466 struct dwc3 *dwc = dep->dwc;
1468 unsigned long flags;
1472 spin_lock_irqsave(&dwc->lock, flags);
1473 ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1474 spin_unlock_irqrestore(&dwc->lock, flags);
1479 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1481 struct dwc3_ep *dep = to_dwc3_ep(ep);
1482 struct dwc3 *dwc = dep->dwc;
1483 unsigned long flags;
1486 spin_lock_irqsave(&dwc->lock, flags);
1487 dep->flags |= DWC3_EP_WEDGE;
1489 if (dep->number == 0 || dep->number == 1)
1490 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1492 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1493 spin_unlock_irqrestore(&dwc->lock, flags);
1498 /* -------------------------------------------------------------------------- */
1500 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1501 .bLength = USB_DT_ENDPOINT_SIZE,
1502 .bDescriptorType = USB_DT_ENDPOINT,
1503 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1506 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1507 .enable = dwc3_gadget_ep0_enable,
1508 .disable = dwc3_gadget_ep0_disable,
1509 .alloc_request = dwc3_gadget_ep_alloc_request,
1510 .free_request = dwc3_gadget_ep_free_request,
1511 .queue = dwc3_gadget_ep0_queue,
1512 .dequeue = dwc3_gadget_ep_dequeue,
1513 .set_halt = dwc3_gadget_ep0_set_halt,
1514 .set_wedge = dwc3_gadget_ep_set_wedge,
1517 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1518 .enable = dwc3_gadget_ep_enable,
1519 .disable = dwc3_gadget_ep_disable,
1520 .alloc_request = dwc3_gadget_ep_alloc_request,
1521 .free_request = dwc3_gadget_ep_free_request,
1522 .queue = dwc3_gadget_ep_queue,
1523 .dequeue = dwc3_gadget_ep_dequeue,
1524 .set_halt = dwc3_gadget_ep_set_halt,
1525 .set_wedge = dwc3_gadget_ep_set_wedge,
1528 /* -------------------------------------------------------------------------- */
1530 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1532 struct dwc3 *dwc = gadget_to_dwc(g);
1534 return __dwc3_gadget_get_frame(dwc);
1537 static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
1548 * According to the Databook Remote wakeup request should
1549 * be issued only when the device is in early suspend state.
1551 * We can check that via USB Link State bits in DSTS register.
1553 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1555 speed = reg & DWC3_DSTS_CONNECTSPD;
1556 if ((speed == DWC3_DSTS_SUPERSPEED) ||
1557 (speed == DWC3_DSTS_SUPERSPEED_PLUS))
1560 link_state = DWC3_DSTS_USBLNKST(reg);
1562 switch (link_state) {
1563 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1564 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1570 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1572 dev_err(dwc->dev, "failed to put link in Recovery\n");
1576 /* Recent versions do this automatically */
1577 if (dwc->revision < DWC3_REVISION_194A) {
1578 /* write zeroes to Link Change Request */
1579 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1580 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1581 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1584 /* poll until Link State changes to ON */
1588 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1590 /* in HS, means ON */
1591 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1595 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1596 dev_err(dwc->dev, "failed to send remote wakeup\n");
1603 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1605 struct dwc3 *dwc = gadget_to_dwc(g);
1606 unsigned long flags;
1609 spin_lock_irqsave(&dwc->lock, flags);
1610 ret = __dwc3_gadget_wakeup(dwc);
1611 spin_unlock_irqrestore(&dwc->lock, flags);
1616 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1619 struct dwc3 *dwc = gadget_to_dwc(g);
1620 unsigned long flags;
1622 spin_lock_irqsave(&dwc->lock, flags);
1623 g->is_selfpowered = !!is_selfpowered;
1624 spin_unlock_irqrestore(&dwc->lock, flags);
1629 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1634 if (pm_runtime_suspended(dwc->dev))
1637 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1639 if (dwc->revision <= DWC3_REVISION_187A) {
1640 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1641 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1644 if (dwc->revision >= DWC3_REVISION_194A)
1645 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1646 reg |= DWC3_DCTL_RUN_STOP;
1648 if (dwc->has_hibernation)
1649 reg |= DWC3_DCTL_KEEP_CONNECT;
1651 dwc->pullups_connected = true;
1653 reg &= ~DWC3_DCTL_RUN_STOP;
1655 if (dwc->has_hibernation && !suspend)
1656 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1658 dwc->pullups_connected = false;
1661 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1664 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1665 reg &= DWC3_DSTS_DEVCTRLHLT;
1666 } while (--timeout && !(!is_on ^ !reg));
1674 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1676 struct dwc3 *dwc = gadget_to_dwc(g);
1677 unsigned long flags;
1683 * Per databook, when we want to stop the gadget, if a control transfer
1684 * is still in process, complete it and get the core into setup phase.
1686 if (!is_on && dwc->ep0state != EP0_SETUP_PHASE) {
1687 reinit_completion(&dwc->ep0_in_setup);
1689 ret = wait_for_completion_timeout(&dwc->ep0_in_setup,
1690 msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT));
1692 dev_err(dwc->dev, "timed out waiting for SETUP phase\n");
1697 spin_lock_irqsave(&dwc->lock, flags);
1698 ret = dwc3_gadget_run_stop(dwc, is_on, false);
1699 spin_unlock_irqrestore(&dwc->lock, flags);
1704 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1708 /* Enable all but Start and End of Frame IRQs */
1709 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1710 DWC3_DEVTEN_EVNTOVERFLOWEN |
1711 DWC3_DEVTEN_CMDCMPLTEN |
1712 DWC3_DEVTEN_ERRTICERREN |
1713 DWC3_DEVTEN_WKUPEVTEN |
1714 DWC3_DEVTEN_CONNECTDONEEN |
1715 DWC3_DEVTEN_USBRSTEN |
1716 DWC3_DEVTEN_DISCONNEVTEN);
1718 if (dwc->revision < DWC3_REVISION_250A)
1719 reg |= DWC3_DEVTEN_ULSTCNGEN;
1721 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1724 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1726 /* mask all interrupts */
1727 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1730 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1731 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1734 * dwc3_gadget_setup_nump - Calculate and initialize NUMP field of DCFG
1735 * dwc: pointer to our context structure
1737 * The following looks like complex but it's actually very simple. In order to
1738 * calculate the number of packets we can burst at once on OUT transfers, we're
1739 * gonna use RxFIFO size.
1741 * To calculate RxFIFO size we need two numbers:
1742 * MDWIDTH = size, in bits, of the internal memory bus
1743 * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
1745 * Given these two numbers, the formula is simple:
1747 * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
1749 * 24 bytes is for 3x SETUP packets
1750 * 16 bytes is a clock domain crossing tolerance
1752 * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
1754 static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
1761 ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
1762 mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0);
1764 nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
1765 nump = min_t(u32, nump, 16);
1768 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1769 reg &= ~DWC3_DCFG_NUMP_MASK;
1770 reg |= nump << DWC3_DCFG_NUMP_SHIFT;
1771 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1774 static int __dwc3_gadget_start(struct dwc3 *dwc)
1776 struct dwc3_ep *dep;
1781 * Use IMOD if enabled via dwc->imod_interval. Otherwise, if
1782 * the core supports IMOD, disable it.
1784 if (dwc->imod_interval) {
1785 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
1786 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
1787 } else if (dwc3_has_imod(dwc)) {
1788 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), 0);
1791 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1792 reg &= ~(DWC3_DCFG_SPEED_MASK);
1795 * WORKAROUND: DWC3 revision < 2.20a have an issue
1796 * which would cause metastability state on Run/Stop
1797 * bit if we try to force the IP to USB2-only mode.
1799 * Because of that, we cannot configure the IP to any
1800 * speed other than the SuperSpeed
1804 * STAR#9000525659: Clock Domain Crossing on DCTL in
1807 if (dwc->revision < DWC3_REVISION_220A) {
1808 reg |= DWC3_DCFG_SUPERSPEED;
1810 switch (dwc->maximum_speed) {
1812 reg |= DWC3_DCFG_LOWSPEED;
1814 case USB_SPEED_FULL:
1815 reg |= DWC3_DCFG_FULLSPEED;
1817 case USB_SPEED_HIGH:
1818 reg |= DWC3_DCFG_HIGHSPEED;
1820 case USB_SPEED_SUPER_PLUS:
1821 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
1824 dev_err(dwc->dev, "invalid dwc->maximum_speed (%d)\n",
1825 dwc->maximum_speed);
1827 case USB_SPEED_SUPER:
1828 reg |= DWC3_DCFG_SUPERSPEED;
1832 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1835 * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
1836 * field instead of letting dwc3 itself calculate that automatically.
1838 * This way, we maximize the chances that we'll be able to get several
1839 * bursts of data without going through any sort of endpoint throttling.
1841 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1842 reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
1843 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1845 dwc3_gadget_setup_nump(dwc);
1847 /* Start with SuperSpeed Default */
1848 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1851 ret = __dwc3_gadget_ep_enable(dep, false, false);
1853 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1858 ret = __dwc3_gadget_ep_enable(dep, false, false);
1860 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1864 /* begin to receive SETUP packets */
1865 dwc->ep0state = EP0_SETUP_PHASE;
1866 dwc3_ep0_out_start(dwc);
1868 dwc3_gadget_enable_irq(dwc);
1873 __dwc3_gadget_ep_disable(dwc->eps[0]);
1879 static int dwc3_gadget_start(struct usb_gadget *g,
1880 struct usb_gadget_driver *driver)
1882 struct dwc3 *dwc = gadget_to_dwc(g);
1883 unsigned long flags;
1887 irq = dwc->irq_gadget;
1888 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1889 IRQF_SHARED, "dwc3", dwc->ev_buf);
1891 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1896 spin_lock_irqsave(&dwc->lock, flags);
1897 if (dwc->gadget_driver) {
1898 dev_err(dwc->dev, "%s is already bound to %s\n",
1900 dwc->gadget_driver->driver.name);
1905 dwc->gadget_driver = driver;
1907 if (pm_runtime_active(dwc->dev))
1908 __dwc3_gadget_start(dwc);
1910 spin_unlock_irqrestore(&dwc->lock, flags);
1915 spin_unlock_irqrestore(&dwc->lock, flags);
1922 static void __dwc3_gadget_stop(struct dwc3 *dwc)
1924 dwc3_gadget_disable_irq(dwc);
1925 __dwc3_gadget_ep_disable(dwc->eps[0]);
1926 __dwc3_gadget_ep_disable(dwc->eps[1]);
1929 static int dwc3_gadget_stop(struct usb_gadget *g)
1931 struct dwc3 *dwc = gadget_to_dwc(g);
1932 unsigned long flags;
1935 spin_lock_irqsave(&dwc->lock, flags);
1937 if (pm_runtime_suspended(dwc->dev))
1940 __dwc3_gadget_stop(dwc);
1942 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1943 struct dwc3_ep *dep = dwc->eps[epnum];
1948 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
1951 wait_event_lock_irq(dep->wait_end_transfer,
1952 !(dep->flags & DWC3_EP_END_TRANSFER_PENDING),
1957 dwc->gadget_driver = NULL;
1958 spin_unlock_irqrestore(&dwc->lock, flags);
1960 free_irq(dwc->irq_gadget, dwc->ev_buf);
1965 static const struct usb_gadget_ops dwc3_gadget_ops = {
1966 .get_frame = dwc3_gadget_get_frame,
1967 .wakeup = dwc3_gadget_wakeup,
1968 .set_selfpowered = dwc3_gadget_set_selfpowered,
1969 .pullup = dwc3_gadget_pullup,
1970 .udc_start = dwc3_gadget_start,
1971 .udc_stop = dwc3_gadget_stop,
1974 /* -------------------------------------------------------------------------- */
1976 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc, u8 num)
1978 struct dwc3_ep *dep;
1981 INIT_LIST_HEAD(&dwc->gadget.ep_list);
1983 for (epnum = 0; epnum < num; epnum++) {
1984 bool direction = epnum & 1;
1986 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1991 dep->number = epnum;
1992 dep->direction = direction;
1993 dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
1994 dwc->eps[epnum] = dep;
1996 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1997 direction ? "in" : "out");
1999 dep->endpoint.name = dep->name;
2001 if (!(dep->number > 1)) {
2002 dep->endpoint.desc = &dwc3_gadget_ep0_desc;
2003 dep->endpoint.comp_desc = NULL;
2006 spin_lock_init(&dep->lock);
2008 if (epnum == 0 || epnum == 1) {
2009 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
2010 dep->endpoint.maxburst = 1;
2011 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
2013 dwc->gadget.ep0 = &dep->endpoint;
2014 } else if (direction) {
2020 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
2021 /* MDWIDTH is represented in bits, we need it in bytes */
2024 size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(epnum >> 1));
2025 size = DWC3_GTXFIFOSIZ_TXFDEF(size);
2027 /* FIFO Depth is in MDWDITH bytes. Multiply */
2035 * FIFO sizes account an extra MDWIDTH * (num + 1) bytes for
2036 * internal overhead. We don't really know how these are used,
2037 * but documentation say it exists.
2039 size -= mdwidth * (num + 1);
2042 usb_ep_set_maxpacket_limit(&dep->endpoint, size);
2044 dep->endpoint.max_streams = 15;
2045 dep->endpoint.ops = &dwc3_gadget_ep_ops;
2046 list_add_tail(&dep->endpoint.ep_list,
2047 &dwc->gadget.ep_list);
2049 ret = dwc3_alloc_trb_pool(dep);
2055 usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
2056 dep->endpoint.max_streams = 15;
2057 dep->endpoint.ops = &dwc3_gadget_ep_ops;
2058 list_add_tail(&dep->endpoint.ep_list,
2059 &dwc->gadget.ep_list);
2061 ret = dwc3_alloc_trb_pool(dep);
2066 if (epnum == 0 || epnum == 1) {
2067 dep->endpoint.caps.type_control = true;
2069 dep->endpoint.caps.type_iso = true;
2070 dep->endpoint.caps.type_bulk = true;
2071 dep->endpoint.caps.type_int = true;
2074 dep->endpoint.caps.dir_in = direction;
2075 dep->endpoint.caps.dir_out = !direction;
2077 INIT_LIST_HEAD(&dep->pending_list);
2078 INIT_LIST_HEAD(&dep->started_list);
2084 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
2086 struct dwc3_ep *dep;
2089 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2090 dep = dwc->eps[epnum];
2094 * Physical endpoints 0 and 1 are special; they form the
2095 * bi-directional USB endpoint 0.
2097 * For those two physical endpoints, we don't allocate a TRB
2098 * pool nor do we add them the endpoints list. Due to that, we
2099 * shouldn't do these two operations otherwise we would end up
2100 * with all sorts of bugs when removing dwc3.ko.
2102 if (epnum != 0 && epnum != 1) {
2103 dwc3_free_trb_pool(dep);
2104 list_del(&dep->endpoint.ep_list);
2111 /* -------------------------------------------------------------------------- */
2113 static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
2114 struct dwc3_request *req, struct dwc3_trb *trb,
2115 const struct dwc3_event_depevt *event, int status,
2119 unsigned int s_pkt = 0;
2120 unsigned int trb_status;
2122 dwc3_ep_inc_deq(dep);
2124 if (req->trb == trb)
2125 dep->queued_requests--;
2127 trace_dwc3_complete_trb(dep, trb);
2130 * If we're in the middle of series of chained TRBs and we
2131 * receive a short transfer along the way, DWC3 will skip
2132 * through all TRBs including the last TRB in the chain (the
2133 * where CHN bit is zero. DWC3 will also avoid clearing HWO
2134 * bit and SW has to do it manually.
2136 * We're going to do that here to avoid problems of HW trying
2137 * to use bogus TRBs for transfers.
2139 if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO))
2140 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2143 * If we're dealing with unaligned size OUT transfer, we will be left
2144 * with one TRB pending in the ring. We need to manually clear HWO bit
2147 if ((req->zero || req->unaligned) && (trb->ctrl & DWC3_TRB_CTRL_HWO)) {
2148 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2152 count = trb->size & DWC3_TRB_SIZE_MASK;
2153 req->remaining += count;
2155 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
2158 if (dep->direction) {
2160 trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
2161 if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
2163 * If missed isoc occurred and there is
2164 * no request queued then issue END
2165 * TRANSFER, so that core generates
2166 * next xfernotready and we will issue
2167 * a fresh START TRANSFER.
2168 * If there are still queued request
2169 * then wait, do not issue either END
2170 * or UPDATE TRANSFER, just attach next
2171 * request in pending_list during
2172 * giveback.If any future queued request
2173 * is successfully transferred then we
2174 * will issue UPDATE TRANSFER for all
2175 * request in the pending_list.
2177 dep->flags |= DWC3_EP_MISSED_ISOC;
2179 dev_err(dwc->dev, "incomplete IN transfer %s\n",
2181 status = -ECONNRESET;
2184 dep->flags &= ~DWC3_EP_MISSED_ISOC;
2187 if (count && (event->status & DEPEVT_STATUS_SHORT))
2191 if (s_pkt && !chain)
2194 if ((event->status & DEPEVT_STATUS_IOC) &&
2195 (trb->ctrl & DWC3_TRB_CTRL_IOC))
2201 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
2202 const struct dwc3_event_depevt *event, int status)
2204 struct dwc3_request *req, *n;
2205 struct dwc3_trb *trb;
2209 list_for_each_entry_safe(req, n, &dep->started_list, list) {
2213 length = req->request.length;
2214 chain = req->num_pending_sgs > 0;
2216 struct scatterlist *sg = req->sg;
2217 struct scatterlist *s;
2218 unsigned int pending = req->num_pending_sgs;
2221 for_each_sg(sg, s, pending, i) {
2222 trb = &dep->trb_pool[dep->trb_dequeue];
2224 if (trb->ctrl & DWC3_TRB_CTRL_HWO)
2227 req->sg = sg_next(s);
2228 req->num_pending_sgs--;
2230 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2231 event, status, chain);
2236 trb = &dep->trb_pool[dep->trb_dequeue];
2237 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2238 event, status, chain);
2241 if (req->unaligned || req->zero) {
2242 trb = &dep->trb_pool[dep->trb_dequeue];
2243 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2244 event, status, false);
2245 req->unaligned = false;
2249 req->request.actual = length - req->remaining;
2251 if ((req->request.actual < length) && req->num_pending_sgs)
2252 return __dwc3_gadget_kick_transfer(dep, 0);
2254 dwc3_gadget_giveback(dep, req, status);
2257 if ((event->status & DEPEVT_STATUS_IOC) &&
2258 (trb->ctrl & DWC3_TRB_CTRL_IOC))
2265 * Our endpoint might get disabled by another thread during
2266 * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2267 * early on so DWC3_EP_BUSY flag gets cleared
2269 if (!dep->endpoint.desc)
2272 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
2273 list_empty(&dep->started_list)) {
2274 if (list_empty(&dep->pending_list)) {
2276 * If there is no entry in request list then do
2277 * not issue END TRANSFER now. Just set PENDING
2278 * flag, so that END TRANSFER is issued when an
2279 * entry is added into request list.
2281 dep->flags = DWC3_EP_PENDING_REQUEST;
2283 dwc3_stop_active_transfer(dwc, dep->number, true);
2284 dep->flags = DWC3_EP_ENABLED;
2289 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && ioc)
2295 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
2296 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
2298 unsigned status = 0;
2300 u32 is_xfer_complete;
2302 is_xfer_complete = (event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE);
2304 if (event->status & DEPEVT_STATUS_BUSERR)
2305 status = -ECONNRESET;
2307 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
2308 if (clean_busy && (!dep->endpoint.desc || is_xfer_complete ||
2309 usb_endpoint_xfer_isoc(dep->endpoint.desc)))
2310 dep->flags &= ~DWC3_EP_BUSY;
2313 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2314 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2316 if (dwc->revision < DWC3_REVISION_183A) {
2320 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
2323 if (!(dep->flags & DWC3_EP_ENABLED))
2326 if (!list_empty(&dep->started_list))
2330 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2332 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2338 * Our endpoint might get disabled by another thread during
2339 * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2340 * early on so DWC3_EP_BUSY flag gets cleared
2342 if (!dep->endpoint.desc)
2345 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2348 ret = __dwc3_gadget_kick_transfer(dep, 0);
2349 if (!ret || ret == -EBUSY)
2354 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2355 const struct dwc3_event_depevt *event)
2357 struct dwc3_ep *dep;
2358 u8 epnum = event->endpoint_number;
2361 dep = dwc->eps[epnum];
2363 if (!(dep->flags & DWC3_EP_ENABLED)) {
2364 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
2367 /* Handle only EPCMDCMPLT when EP disabled */
2368 if (event->endpoint_event != DWC3_DEPEVT_EPCMDCMPLT)
2372 if (epnum == 0 || epnum == 1) {
2373 dwc3_ep0_interrupt(dwc, event);
2377 switch (event->endpoint_event) {
2378 case DWC3_DEPEVT_XFERCOMPLETE:
2379 dep->resource_index = 0;
2381 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2382 dev_err(dwc->dev, "XferComplete for Isochronous endpoint\n");
2386 dwc3_endpoint_transfer_complete(dwc, dep, event);
2388 case DWC3_DEPEVT_XFERINPROGRESS:
2389 dwc3_endpoint_transfer_complete(dwc, dep, event);
2391 case DWC3_DEPEVT_XFERNOTREADY:
2392 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2393 dwc3_gadget_start_isoc(dwc, dep, event);
2397 ret = __dwc3_gadget_kick_transfer(dep, 0);
2398 if (!ret || ret == -EBUSY)
2403 case DWC3_DEPEVT_STREAMEVT:
2404 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
2405 dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
2410 case DWC3_DEPEVT_EPCMDCMPLT:
2411 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
2413 if (cmd == DWC3_DEPCMD_ENDTRANSFER) {
2414 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
2415 wake_up(&dep->wait_end_transfer);
2418 case DWC3_DEPEVT_RXTXFIFOEVT:
2423 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2425 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2426 spin_unlock(&dwc->lock);
2427 dwc->gadget_driver->disconnect(&dwc->gadget);
2428 spin_lock(&dwc->lock);
2432 static void dwc3_suspend_gadget(struct dwc3 *dwc)
2434 if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
2435 spin_unlock(&dwc->lock);
2436 dwc->gadget_driver->suspend(&dwc->gadget);
2437 spin_lock(&dwc->lock);
2441 static void dwc3_resume_gadget(struct dwc3 *dwc)
2443 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2444 spin_unlock(&dwc->lock);
2445 dwc->gadget_driver->resume(&dwc->gadget);
2446 spin_lock(&dwc->lock);
2450 static void dwc3_reset_gadget(struct dwc3 *dwc)
2452 if (!dwc->gadget_driver)
2455 if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2456 spin_unlock(&dwc->lock);
2457 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
2458 spin_lock(&dwc->lock);
2462 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
2464 struct dwc3_ep *dep;
2465 struct dwc3_gadget_ep_cmd_params params;
2469 dep = dwc->eps[epnum];
2471 if ((dep->flags & DWC3_EP_END_TRANSFER_PENDING) ||
2472 !dep->resource_index)
2476 * NOTICE: We are violating what the Databook says about the
2477 * EndTransfer command. Ideally we would _always_ wait for the
2478 * EndTransfer Command Completion IRQ, but that's causing too
2479 * much trouble synchronizing between us and gadget driver.
2481 * We have discussed this with the IP Provider and it was
2482 * suggested to giveback all requests here, but give HW some
2483 * extra time to synchronize with the interconnect. We're using
2484 * an arbitrary 100us delay for that.
2486 * Note also that a similar handling was tested by Synopsys
2487 * (thanks a lot Paul) and nothing bad has come out of it.
2488 * In short, what we're doing is:
2490 * - Issue EndTransfer WITH CMDIOC bit set
2493 * As of IP version 3.10a of the DWC_usb3 IP, the controller
2494 * supports a mode to work around the above limitation. The
2495 * software can poll the CMDACT bit in the DEPCMD register
2496 * after issuing a EndTransfer command. This mode is enabled
2497 * by writing GUCTL2[14]. This polling is already done in the
2498 * dwc3_send_gadget_ep_cmd() function so if the mode is
2499 * enabled, the EndTransfer command will have completed upon
2500 * returning from this function and we don't need to delay for
2503 * This mode is NOT available on the DWC_usb31 IP.
2506 cmd = DWC3_DEPCMD_ENDTRANSFER;
2507 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2508 cmd |= DWC3_DEPCMD_CMDIOC;
2509 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2510 memset(¶ms, 0, sizeof(params));
2511 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
2513 dep->resource_index = 0;
2514 dep->flags &= ~DWC3_EP_BUSY;
2516 if (dwc3_is_usb31(dwc) || dwc->revision < DWC3_REVISION_310A) {
2517 dep->flags |= DWC3_EP_END_TRANSFER_PENDING;
2522 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2526 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2527 struct dwc3_ep *dep;
2530 dep = dwc->eps[epnum];
2534 if (!(dep->flags & DWC3_EP_STALL))
2537 dep->flags &= ~DWC3_EP_STALL;
2539 ret = dwc3_send_clear_stall_ep_cmd(dep);
2544 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2548 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2549 reg &= ~DWC3_DCTL_INITU1ENA;
2550 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2552 reg &= ~DWC3_DCTL_INITU2ENA;
2553 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2555 dwc3_disconnect_gadget(dwc);
2557 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2558 dwc->setup_packet_pending = false;
2559 usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2561 dwc->connected = false;
2564 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2568 dwc->connected = true;
2571 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2572 * would cause a missing Disconnect Event if there's a
2573 * pending Setup Packet in the FIFO.
2575 * There's no suggested workaround on the official Bug
2576 * report, which states that "unless the driver/application
2577 * is doing any special handling of a disconnect event,
2578 * there is no functional issue".
2580 * Unfortunately, it turns out that we _do_ some special
2581 * handling of a disconnect event, namely complete all
2582 * pending transfers, notify gadget driver of the
2583 * disconnection, and so on.
2585 * Our suggested workaround is to follow the Disconnect
2586 * Event steps here, instead, based on a setup_packet_pending
2587 * flag. Such flag gets set whenever we have a SETUP_PENDING
2588 * status for EP0 TRBs and gets cleared on XferComplete for the
2593 * STAR#9000466709: RTL: Device : Disconnect event not
2594 * generated if setup packet pending in FIFO
2596 if (dwc->revision < DWC3_REVISION_188A) {
2597 if (dwc->setup_packet_pending)
2598 dwc3_gadget_disconnect_interrupt(dwc);
2601 dwc3_reset_gadget(dwc);
2603 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2604 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2605 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2606 dwc->test_mode = false;
2607 dwc3_clear_stall_all_ep(dwc);
2609 /* Reset device address to zero */
2610 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2611 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2612 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2615 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2617 struct dwc3_ep *dep;
2622 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2623 speed = reg & DWC3_DSTS_CONNECTSPD;
2627 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2628 * each time on Connect Done.
2630 * Currently we always use the reset value. If any platform
2631 * wants to set this to a different value, we need to add a
2632 * setting and update GCTL.RAMCLKSEL here.
2636 case DWC3_DSTS_SUPERSPEED_PLUS:
2637 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2638 dwc->gadget.ep0->maxpacket = 512;
2639 dwc->gadget.speed = USB_SPEED_SUPER_PLUS;
2641 case DWC3_DSTS_SUPERSPEED:
2643 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2644 * would cause a missing USB3 Reset event.
2646 * In such situations, we should force a USB3 Reset
2647 * event by calling our dwc3_gadget_reset_interrupt()
2652 * STAR#9000483510: RTL: SS : USB3 reset event may
2653 * not be generated always when the link enters poll
2655 if (dwc->revision < DWC3_REVISION_190A)
2656 dwc3_gadget_reset_interrupt(dwc);
2658 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2659 dwc->gadget.ep0->maxpacket = 512;
2660 dwc->gadget.speed = USB_SPEED_SUPER;
2662 case DWC3_DSTS_HIGHSPEED:
2663 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2664 dwc->gadget.ep0->maxpacket = 64;
2665 dwc->gadget.speed = USB_SPEED_HIGH;
2667 case DWC3_DSTS_FULLSPEED:
2668 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2669 dwc->gadget.ep0->maxpacket = 64;
2670 dwc->gadget.speed = USB_SPEED_FULL;
2672 case DWC3_DSTS_LOWSPEED:
2673 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2674 dwc->gadget.ep0->maxpacket = 8;
2675 dwc->gadget.speed = USB_SPEED_LOW;
2679 /* Enable USB2 LPM Capability */
2681 if ((dwc->revision > DWC3_REVISION_194A) &&
2682 (speed != DWC3_DSTS_SUPERSPEED) &&
2683 (speed != DWC3_DSTS_SUPERSPEED_PLUS)) {
2684 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2685 reg |= DWC3_DCFG_LPM_CAP;
2686 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2688 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2689 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2691 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2694 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2695 * DCFG.LPMCap is set, core responses with an ACK and the
2696 * BESL value in the LPM token is less than or equal to LPM
2699 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2700 && dwc->has_lpm_erratum,
2701 "LPM Erratum not available on dwc3 revisions < 2.40a\n");
2703 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2704 reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2706 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2708 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2709 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2710 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2714 ret = __dwc3_gadget_ep_enable(dep, true, false);
2716 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2721 ret = __dwc3_gadget_ep_enable(dep, true, false);
2723 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2728 * Configure PHY via GUSB3PIPECTLn if required.
2730 * Update GTXFIFOSIZn
2732 * In both cases reset values should be sufficient.
2736 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2739 * TODO take core out of low power mode when that's
2743 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2744 spin_unlock(&dwc->lock);
2745 dwc->gadget_driver->resume(&dwc->gadget);
2746 spin_lock(&dwc->lock);
2750 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2751 unsigned int evtinfo)
2753 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2754 unsigned int pwropt;
2757 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2758 * Hibernation mode enabled which would show up when device detects
2759 * host-initiated U3 exit.
2761 * In that case, device will generate a Link State Change Interrupt
2762 * from U3 to RESUME which is only necessary if Hibernation is
2765 * There are no functional changes due to such spurious event and we
2766 * just need to ignore it.
2770 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2773 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2774 if ((dwc->revision < DWC3_REVISION_250A) &&
2775 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2776 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2777 (next == DWC3_LINK_STATE_RESUME)) {
2783 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2784 * on the link partner, the USB session might do multiple entry/exit
2785 * of low power states before a transfer takes place.
2787 * Due to this problem, we might experience lower throughput. The
2788 * suggested workaround is to disable DCTL[12:9] bits if we're
2789 * transitioning from U1/U2 to U0 and enable those bits again
2790 * after a transfer completes and there are no pending transfers
2791 * on any of the enabled endpoints.
2793 * This is the first half of that workaround.
2797 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2798 * core send LGO_Ux entering U0
2800 if (dwc->revision < DWC3_REVISION_183A) {
2801 if (next == DWC3_LINK_STATE_U0) {
2805 switch (dwc->link_state) {
2806 case DWC3_LINK_STATE_U1:
2807 case DWC3_LINK_STATE_U2:
2808 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2809 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2810 | DWC3_DCTL_ACCEPTU2ENA
2811 | DWC3_DCTL_INITU1ENA
2812 | DWC3_DCTL_ACCEPTU1ENA);
2815 dwc->u1u2 = reg & u1u2;
2819 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2829 case DWC3_LINK_STATE_U1:
2830 if (dwc->speed == USB_SPEED_SUPER)
2831 dwc3_suspend_gadget(dwc);
2833 case DWC3_LINK_STATE_U2:
2834 case DWC3_LINK_STATE_U3:
2835 dwc3_suspend_gadget(dwc);
2837 case DWC3_LINK_STATE_RESUME:
2838 dwc3_resume_gadget(dwc);
2845 dwc->link_state = next;
2848 static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc,
2849 unsigned int evtinfo)
2851 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2853 if (dwc->link_state != next && next == DWC3_LINK_STATE_U3)
2854 dwc3_suspend_gadget(dwc);
2856 dwc->link_state = next;
2859 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2860 unsigned int evtinfo)
2862 unsigned int is_ss = evtinfo & BIT(4);
2865 * WORKAROUND: DWC3 revison 2.20a with hibernation support
2866 * have a known issue which can cause USB CV TD.9.23 to fail
2869 * Because of this issue, core could generate bogus hibernation
2870 * events which SW needs to ignore.
2874 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2875 * Device Fallback from SuperSpeed
2877 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2880 /* enter hibernation here */
2883 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2884 const struct dwc3_event_devt *event)
2886 switch (event->type) {
2887 case DWC3_DEVICE_EVENT_DISCONNECT:
2888 dwc3_gadget_disconnect_interrupt(dwc);
2890 case DWC3_DEVICE_EVENT_RESET:
2891 dwc3_gadget_reset_interrupt(dwc);
2893 case DWC3_DEVICE_EVENT_CONNECT_DONE:
2894 dwc3_gadget_conndone_interrupt(dwc);
2896 case DWC3_DEVICE_EVENT_WAKEUP:
2897 dwc3_gadget_wakeup_interrupt(dwc);
2899 case DWC3_DEVICE_EVENT_HIBER_REQ:
2900 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
2901 "unexpected hibernation event\n"))
2904 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2906 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2907 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2909 case DWC3_DEVICE_EVENT_EOPF:
2910 /* It changed to be suspend event for version 2.30a and above */
2911 if (dwc->revision >= DWC3_REVISION_230A) {
2913 * Ignore suspend event until the gadget enters into
2914 * USB_STATE_CONFIGURED state.
2916 if (dwc->gadget.state >= USB_STATE_CONFIGURED)
2917 dwc3_gadget_suspend_interrupt(dwc,
2921 case DWC3_DEVICE_EVENT_SOF:
2922 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2923 case DWC3_DEVICE_EVENT_CMD_CMPL:
2924 case DWC3_DEVICE_EVENT_OVERFLOW:
2927 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2931 static void dwc3_process_event_entry(struct dwc3 *dwc,
2932 const union dwc3_event *event)
2934 trace_dwc3_event(event->raw, dwc);
2936 /* Endpoint IRQ, handle it and return early */
2937 if (event->type.is_devspec == 0) {
2939 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2942 switch (event->type.type) {
2943 case DWC3_EVENT_TYPE_DEV:
2944 dwc3_gadget_interrupt(dwc, &event->devt);
2946 /* REVISIT what to do with Carkit and I2C events ? */
2948 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2952 static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
2954 struct dwc3 *dwc = evt->dwc;
2955 irqreturn_t ret = IRQ_NONE;
2961 if (!(evt->flags & DWC3_EVENT_PENDING))
2965 union dwc3_event event;
2967 event.raw = *(u32 *) (evt->cache + evt->lpos);
2969 dwc3_process_event_entry(dwc, &event);
2972 * FIXME we wrap around correctly to the next entry as
2973 * almost all entries are 4 bytes in size. There is one
2974 * entry which has 12 bytes which is a regular entry
2975 * followed by 8 bytes data. ATM I don't know how
2976 * things are organized if we get next to the a
2977 * boundary so I worry about that once we try to handle
2980 evt->lpos = (evt->lpos + 4) % evt->length;
2985 evt->flags &= ~DWC3_EVENT_PENDING;
2988 /* Unmask interrupt */
2989 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
2990 reg &= ~DWC3_GEVNTSIZ_INTMASK;
2991 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
2993 if (dwc->imod_interval) {
2994 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
2995 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
3001 static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
3003 struct dwc3_event_buffer *evt = _evt;
3004 struct dwc3 *dwc = evt->dwc;
3005 unsigned long flags;
3006 irqreturn_t ret = IRQ_NONE;
3008 spin_lock_irqsave(&dwc->lock, flags);
3009 ret = dwc3_process_event_buf(evt);
3010 spin_unlock_irqrestore(&dwc->lock, flags);
3015 static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
3017 struct dwc3 *dwc = evt->dwc;
3022 if (pm_runtime_suspended(dwc->dev)) {
3023 pm_runtime_get(dwc->dev);
3024 disable_irq_nosync(dwc->irq_gadget);
3025 dwc->pending_events = true;
3029 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
3030 count &= DWC3_GEVNTCOUNT_MASK;
3035 evt->flags |= DWC3_EVENT_PENDING;
3037 /* Mask interrupt */
3038 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
3039 reg |= DWC3_GEVNTSIZ_INTMASK;
3040 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
3042 amount = min(count, evt->length - evt->lpos);
3043 memcpy(evt->cache + evt->lpos, evt->buf + evt->lpos, amount);
3046 memcpy(evt->cache, evt->buf, count - amount);
3048 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
3050 return IRQ_WAKE_THREAD;
3053 static irqreturn_t dwc3_interrupt(int irq, void *_evt)
3055 struct dwc3_event_buffer *evt = _evt;
3057 return dwc3_check_event_buf(evt);
3060 static int dwc3_gadget_get_irq(struct dwc3 *dwc)
3062 struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
3065 irq = platform_get_irq_byname(dwc3_pdev, "peripheral");
3069 if (irq == -EPROBE_DEFER)
3072 irq = platform_get_irq_byname(dwc3_pdev, "dwc_usb3");
3076 if (irq == -EPROBE_DEFER)
3079 irq = platform_get_irq(dwc3_pdev, 0);
3083 if (irq != -EPROBE_DEFER)
3084 dev_err(dwc->dev, "missing peripheral IRQ\n");
3094 * dwc3_gadget_init - Initializes gadget related registers
3095 * @dwc: pointer to our controller context structure
3097 * Returns 0 on success otherwise negative errno.
3099 int dwc3_gadget_init(struct dwc3 *dwc)
3104 irq = dwc3_gadget_get_irq(dwc);
3110 dwc->irq_gadget = irq;
3112 dwc->ep0_trb = dma_alloc_coherent(dwc->sysdev,
3113 sizeof(*dwc->ep0_trb) * 2,
3114 &dwc->ep0_trb_addr, GFP_KERNEL);
3115 if (!dwc->ep0_trb) {
3116 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
3121 dwc->setup_buf = kzalloc(DWC3_EP0_SETUP_SIZE, GFP_KERNEL);
3122 if (!dwc->setup_buf) {
3127 dwc->bounce = dma_alloc_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE,
3128 &dwc->bounce_addr, GFP_KERNEL);
3134 init_completion(&dwc->ep0_in_setup);
3136 dwc->gadget.ops = &dwc3_gadget_ops;
3137 dwc->gadget.speed = USB_SPEED_UNKNOWN;
3138 dwc->gadget.sg_supported = true;
3139 dwc->gadget.name = "dwc3-gadget";
3140 dwc->gadget.is_otg = dwc->dr_mode == USB_DR_MODE_OTG;
3143 * FIXME We might be setting max_speed to <SUPER, however versions
3144 * <2.20a of dwc3 have an issue with metastability (documented
3145 * elsewhere in this driver) which tells us we can't set max speed to
3146 * anything lower than SUPER.
3148 * Because gadget.max_speed is only used by composite.c and function
3149 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
3150 * to happen so we avoid sending SuperSpeed Capability descriptor
3151 * together with our BOS descriptor as that could confuse host into
3152 * thinking we can handle super speed.
3154 * Note that, in fact, we won't even support GetBOS requests when speed
3155 * is less than super speed because we don't have means, yet, to tell
3156 * composite.c that we are USB 2.0 + LPM ECN.
3158 if (dwc->revision < DWC3_REVISION_220A)
3159 dev_info(dwc->dev, "changing max_speed on rev %08x\n",
3162 dwc->gadget.max_speed = dwc->maximum_speed;
3165 * REVISIT: Here we should clear all pending IRQs to be
3166 * sure we're starting from a well known location.
3169 ret = dwc3_gadget_init_endpoints(dwc, dwc->num_eps);
3173 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
3175 dev_err(dwc->dev, "failed to register udc\n");
3182 dwc3_gadget_free_endpoints(dwc);
3185 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
3189 kfree(dwc->setup_buf);
3192 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
3193 dwc->ep0_trb, dwc->ep0_trb_addr);
3199 /* -------------------------------------------------------------------------- */
3201 void dwc3_gadget_exit(struct dwc3 *dwc)
3203 usb_del_gadget_udc(&dwc->gadget);
3204 dwc3_gadget_free_endpoints(dwc);
3205 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
3207 kfree(dwc->setup_buf);
3208 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
3209 dwc->ep0_trb, dwc->ep0_trb_addr);
3212 int dwc3_gadget_suspend(struct dwc3 *dwc)
3214 if (!dwc->gadget_driver)
3217 dwc3_gadget_run_stop(dwc, false, false);
3218 dwc3_disconnect_gadget(dwc);
3219 __dwc3_gadget_stop(dwc);
3224 int dwc3_gadget_resume(struct dwc3 *dwc)
3228 if (!dwc->gadget_driver)
3231 ret = __dwc3_gadget_start(dwc);
3235 ret = dwc3_gadget_run_stop(dwc, true, false);
3242 __dwc3_gadget_stop(dwc);
3248 void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
3250 if (dwc->pending_events) {
3251 dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf);
3252 dwc->pending_events = false;
3253 enable_irq(dwc->irq_gadget);