2 * Copyright (c) 2011 The Chromium OS Authors.
3 * Copyright (C) 2009 NVIDIA, Corporation
4 * Copyright (C) 2007-2008 SMSC (Steve Glendinning)
6 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/unaligned.h>
14 #include <linux/mii.h>
15 #include "usb_ether.h"
17 /* SMSC LAN95xx based USB 2.0 Ethernet Devices */
20 #define LED_GPIO_CFG (0x24)
21 #define LED_GPIO_CFG_SPD_LED (0x01000000)
22 #define LED_GPIO_CFG_LNK_LED (0x00100000)
23 #define LED_GPIO_CFG_FDX_LED (0x00010000)
25 /* Tx command words */
26 #define TX_CMD_A_FIRST_SEG_ 0x00002000
27 #define TX_CMD_A_LAST_SEG_ 0x00001000
30 #define RX_STS_FL_ 0x3FFF0000 /* Frame Length */
31 #define RX_STS_ES_ 0x00008000 /* Error Summary */
39 #define TX_CFG_ON_ 0x00000004
42 #define HW_CFG_BIR_ 0x00001000
43 #define HW_CFG_RXDOFF_ 0x00000600
44 #define HW_CFG_MEF_ 0x00000020
45 #define HW_CFG_BCE_ 0x00000002
46 #define HW_CFG_LRST_ 0x00000008
49 #define PM_CTL_PHY_RST_ 0x00000010
54 * Hi watermark = 15.5Kb (~10 mtu pkts)
55 * low watermark = 3k (~2 mtu pkts)
56 * backpressure duration = ~ 350us
57 * Apply FC on any frame.
59 #define AFC_CFG_DEFAULT 0x00F830A1
62 #define E2P_CMD_BUSY_ 0x80000000
63 #define E2P_CMD_READ_ 0x00000000
64 #define E2P_CMD_TIMEOUT_ 0x00000400
65 #define E2P_CMD_LOADED_ 0x00000200
66 #define E2P_CMD_ADDR_ 0x000001FF
70 #define BURST_CAP 0x38
72 #define INT_EP_CTL 0x68
73 #define INT_EP_CTL_PHY_INT_ 0x00008000
75 #define BULK_IN_DLY 0x6C
79 #define MAC_CR_MCPAS_ 0x00080000
80 #define MAC_CR_PRMS_ 0x00040000
81 #define MAC_CR_HPFILT_ 0x00002000
82 #define MAC_CR_TXEN_ 0x00000008
83 #define MAC_CR_RXEN_ 0x00000004
89 #define MII_ADDR 0x114
90 #define MII_WRITE_ 0x02
91 #define MII_BUSY_ 0x01
92 #define MII_READ_ 0x00 /* ~of MII Write bit */
94 #define MII_DATA 0x118
101 #define Tx_COE_EN_ 0x00010000
102 #define Rx_COE_EN_ 0x00000001
104 /* Vendor-specific PHY Definitions */
105 #define PHY_INT_SRC 29
107 #define PHY_INT_MASK 30
108 #define PHY_INT_MASK_ANEG_COMP_ ((u16)0x0040)
109 #define PHY_INT_MASK_LINK_DOWN_ ((u16)0x0010)
110 #define PHY_INT_MASK_DEFAULT_ (PHY_INT_MASK_ANEG_COMP_ | \
111 PHY_INT_MASK_LINK_DOWN_)
113 /* USB Vendor Requests */
114 #define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0
115 #define USB_VENDOR_REQUEST_READ_REGISTER 0xA1
117 /* Some extra defines */
118 #define HS_USB_PKT_SIZE 512
119 #define FS_USB_PKT_SIZE 64
120 #define DEFAULT_HS_BURST_CAP_SIZE (16 * 1024 + 5 * HS_USB_PKT_SIZE)
121 #define DEFAULT_FS_BURST_CAP_SIZE (6 * 1024 + 33 * FS_USB_PKT_SIZE)
122 #define DEFAULT_BULK_IN_DELAY 0x00002000
123 #define MAX_SINGLE_PACKET_SIZE 2048
124 #define EEPROM_MAC_OFFSET 0x01
125 #define SMSC95XX_INTERNAL_PHY_ID 1
126 #define ETH_P_8021Q 0x8100 /* 802.1Q VLAN Extended Header */
129 #define SMSC95XX_BASE_NAME "sms"
130 #define USB_CTRL_SET_TIMEOUT 5000
131 #define USB_CTRL_GET_TIMEOUT 5000
132 #define USB_BULK_SEND_TIMEOUT 5000
133 #define USB_BULK_RECV_TIMEOUT 5000
135 #define RX_URB_SIZE 2048
136 #define PHY_CONNECT_TIMEOUT 5000
141 static int curr_eth_dev; /* index for name of next device detected */
144 struct smsc95xx_private {
145 size_t rx_urb_size; /* maximum USB URB size */
146 u32 mac_cr; /* MAC control register value */
147 int have_hwaddr; /* 1 if we have a hardware MAC address */
151 * Smsc95xx infrastructure commands
153 static int smsc95xx_write_reg(struct ueth_data *dev, u32 index, u32 data)
156 ALLOC_CACHE_ALIGN_BUFFER(u32, tmpbuf, 1);
161 len = usb_control_msg(dev->pusb_dev, usb_sndctrlpipe(dev->pusb_dev, 0),
162 USB_VENDOR_REQUEST_WRITE_REGISTER,
163 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
164 00, index, tmpbuf, sizeof(data), USB_CTRL_SET_TIMEOUT);
165 if (len != sizeof(data)) {
166 debug("smsc95xx_write_reg failed: index=%d, data=%d, len=%d",
173 static int smsc95xx_read_reg(struct ueth_data *dev, u32 index, u32 *data)
176 ALLOC_CACHE_ALIGN_BUFFER(u32, tmpbuf, 1);
178 len = usb_control_msg(dev->pusb_dev, usb_rcvctrlpipe(dev->pusb_dev, 0),
179 USB_VENDOR_REQUEST_READ_REGISTER,
180 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
181 00, index, tmpbuf, sizeof(data), USB_CTRL_GET_TIMEOUT);
183 if (len != sizeof(data)) {
184 debug("smsc95xx_read_reg failed: index=%d, len=%d",
193 /* Loop until the read is completed with timeout */
194 static int smsc95xx_phy_wait_not_busy(struct ueth_data *dev)
196 unsigned long start_time = get_timer(0);
200 smsc95xx_read_reg(dev, MII_ADDR, &val);
201 if (!(val & MII_BUSY_))
203 } while (get_timer(start_time) < 1 * 1000 * 1000);
208 static int smsc95xx_mdio_read(struct ueth_data *dev, int phy_id, int idx)
212 /* confirm MII not busy */
213 if (smsc95xx_phy_wait_not_busy(dev)) {
214 debug("MII is busy in smsc95xx_mdio_read\n");
218 /* set the address, index & direction (read from PHY) */
219 addr = (phy_id << 11) | (idx << 6) | MII_READ_;
220 smsc95xx_write_reg(dev, MII_ADDR, addr);
222 if (smsc95xx_phy_wait_not_busy(dev)) {
223 debug("Timed out reading MII reg %02X\n", idx);
227 smsc95xx_read_reg(dev, MII_DATA, &val);
229 return (u16)(val & 0xFFFF);
232 static void smsc95xx_mdio_write(struct ueth_data *dev, int phy_id, int idx,
237 /* confirm MII not busy */
238 if (smsc95xx_phy_wait_not_busy(dev)) {
239 debug("MII is busy in smsc95xx_mdio_write\n");
244 smsc95xx_write_reg(dev, MII_DATA, val);
246 /* set the address, index & direction (write to PHY) */
247 addr = (phy_id << 11) | (idx << 6) | MII_WRITE_;
248 smsc95xx_write_reg(dev, MII_ADDR, addr);
250 if (smsc95xx_phy_wait_not_busy(dev))
251 debug("Timed out writing MII reg %02X\n", idx);
254 static int smsc95xx_eeprom_confirm_not_busy(struct ueth_data *dev)
256 unsigned long start_time = get_timer(0);
260 smsc95xx_read_reg(dev, E2P_CMD, &val);
261 if (!(val & E2P_CMD_BUSY_))
264 } while (get_timer(start_time) < 1 * 1000 * 1000);
266 debug("EEPROM is busy\n");
270 static int smsc95xx_wait_eeprom(struct ueth_data *dev)
272 unsigned long start_time = get_timer(0);
276 smsc95xx_read_reg(dev, E2P_CMD, &val);
277 if (!(val & E2P_CMD_BUSY_) || (val & E2P_CMD_TIMEOUT_))
280 } while (get_timer(start_time) < 1 * 1000 * 1000);
282 if (val & (E2P_CMD_TIMEOUT_ | E2P_CMD_BUSY_)) {
283 debug("EEPROM read operation timeout\n");
289 static int smsc95xx_read_eeprom(struct ueth_data *dev, u32 offset, u32 length,
295 ret = smsc95xx_eeprom_confirm_not_busy(dev);
299 for (i = 0; i < length; i++) {
300 val = E2P_CMD_BUSY_ | E2P_CMD_READ_ | (offset & E2P_CMD_ADDR_);
301 smsc95xx_write_reg(dev, E2P_CMD, val);
303 ret = smsc95xx_wait_eeprom(dev);
307 smsc95xx_read_reg(dev, E2P_DATA, &val);
308 data[i] = val & 0xFF;
315 * mii_nway_restart - restart NWay (autonegotiation) for this interface
317 * Returns 0 on success, negative on error.
319 static int mii_nway_restart(struct ueth_data *dev)
324 /* if autoneg is off, it's an error */
325 bmcr = smsc95xx_mdio_read(dev, dev->phy_id, MII_BMCR);
327 if (bmcr & BMCR_ANENABLE) {
328 bmcr |= BMCR_ANRESTART;
329 smsc95xx_mdio_write(dev, dev->phy_id, MII_BMCR, bmcr);
335 static int smsc95xx_phy_initialize(struct ueth_data *dev)
337 smsc95xx_mdio_write(dev, dev->phy_id, MII_BMCR, BMCR_RESET);
338 smsc95xx_mdio_write(dev, dev->phy_id, MII_ADVERTISE,
339 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP |
340 ADVERTISE_PAUSE_ASYM);
343 smsc95xx_mdio_read(dev, dev->phy_id, PHY_INT_SRC);
345 smsc95xx_mdio_write(dev, dev->phy_id, PHY_INT_MASK,
346 PHY_INT_MASK_DEFAULT_);
347 mii_nway_restart(dev);
349 debug("phy initialised succesfully\n");
353 static int smsc95xx_init_mac_address(struct eth_device *eth,
354 struct ueth_data *dev)
356 /* try reading mac address from EEPROM */
357 if (smsc95xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN,
358 eth->enetaddr) == 0) {
359 if (is_valid_ethaddr(eth->enetaddr)) {
360 /* eeprom values are valid so use them */
361 debug("MAC address read from EEPROM\n");
367 * No eeprom, or eeprom values are invalid. Generating a random MAC
368 * address is not safe. Just return an error.
373 static int smsc95xx_write_hwaddr(struct eth_device *eth)
375 struct ueth_data *dev = (struct ueth_data *)eth->priv;
376 struct smsc95xx_private *priv = dev->dev_priv;
377 u32 addr_lo = __get_unaligned_le32(ð->enetaddr[0]);
378 u32 addr_hi = __get_unaligned_le16(ð->enetaddr[4]);
381 /* set hardware address */
382 debug("** %s()\n", __func__);
383 ret = smsc95xx_write_reg(dev, ADDRL, addr_lo);
387 ret = smsc95xx_write_reg(dev, ADDRH, addr_hi);
391 debug("MAC %pM\n", eth->enetaddr);
392 priv->have_hwaddr = 1;
396 /* Enable or disable Tx & Rx checksum offload engines */
397 static int smsc95xx_set_csums(struct ueth_data *dev,
398 int use_tx_csum, int use_rx_csum)
401 int ret = smsc95xx_read_reg(dev, COE_CR, &read_buf);
406 read_buf |= Tx_COE_EN_;
408 read_buf &= ~Tx_COE_EN_;
411 read_buf |= Rx_COE_EN_;
413 read_buf &= ~Rx_COE_EN_;
415 ret = smsc95xx_write_reg(dev, COE_CR, read_buf);
419 debug("COE_CR = 0x%08x\n", read_buf);
423 static void smsc95xx_set_multicast(struct ueth_data *dev)
425 struct smsc95xx_private *priv = dev->dev_priv;
427 /* No multicast in u-boot */
428 priv->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
431 /* starts the TX path */
432 static void smsc95xx_start_tx_path(struct ueth_data *dev)
434 struct smsc95xx_private *priv = dev->dev_priv;
437 /* Enable Tx at MAC */
438 priv->mac_cr |= MAC_CR_TXEN_;
440 smsc95xx_write_reg(dev, MAC_CR, priv->mac_cr);
442 /* Enable Tx at SCSRs */
443 reg_val = TX_CFG_ON_;
444 smsc95xx_write_reg(dev, TX_CFG, reg_val);
447 /* Starts the Receive path */
448 static void smsc95xx_start_rx_path(struct ueth_data *dev)
450 struct smsc95xx_private *priv = dev->dev_priv;
452 priv->mac_cr |= MAC_CR_RXEN_;
453 smsc95xx_write_reg(dev, MAC_CR, priv->mac_cr);
459 static int smsc95xx_init(struct eth_device *eth, bd_t *bd)
466 struct ueth_data *dev = (struct ueth_data *)eth->priv;
467 struct smsc95xx_private *priv =
468 (struct smsc95xx_private *)dev->dev_priv;
469 #define TIMEOUT_RESOLUTION 50 /* ms */
472 debug("** %s()\n", __func__);
473 dev->phy_id = SMSC95XX_INTERNAL_PHY_ID; /* fixed phy id */
475 write_buf = HW_CFG_LRST_;
476 ret = smsc95xx_write_reg(dev, HW_CFG, write_buf);
482 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
487 } while ((read_buf & HW_CFG_LRST_) && (timeout < 100));
489 if (timeout >= 100) {
490 debug("timeout waiting for completion of Lite Reset\n");
494 write_buf = PM_CTL_PHY_RST_;
495 ret = smsc95xx_write_reg(dev, PM_CTRL, write_buf);
501 ret = smsc95xx_read_reg(dev, PM_CTRL, &read_buf);
506 } while ((read_buf & PM_CTL_PHY_RST_) && (timeout < 100));
507 if (timeout >= 100) {
508 debug("timeout waiting for PHY Reset\n");
511 if (!priv->have_hwaddr && smsc95xx_init_mac_address(eth, dev) == 0)
512 priv->have_hwaddr = 1;
513 if (!priv->have_hwaddr) {
514 puts("Error: SMSC95xx: No MAC address set - set usbethaddr\n");
517 if (smsc95xx_write_hwaddr(eth) < 0)
520 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
523 debug("Read Value from HW_CFG : 0x%08x\n", read_buf);
525 read_buf |= HW_CFG_BIR_;
526 ret = smsc95xx_write_reg(dev, HW_CFG, read_buf);
530 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
533 debug("Read Value from HW_CFG after writing "
534 "HW_CFG_BIR_: 0x%08x\n", read_buf);
537 if (dev->pusb_dev->speed == USB_SPEED_HIGH) {
538 burst_cap = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE;
539 priv->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE;
541 burst_cap = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE;
542 priv->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE;
546 priv->rx_urb_size = MAX_SINGLE_PACKET_SIZE;
548 debug("rx_urb_size=%ld\n", (ulong)priv->rx_urb_size);
550 ret = smsc95xx_write_reg(dev, BURST_CAP, burst_cap);
554 ret = smsc95xx_read_reg(dev, BURST_CAP, &read_buf);
557 debug("Read Value from BURST_CAP after writing: 0x%08x\n", read_buf);
559 read_buf = DEFAULT_BULK_IN_DELAY;
560 ret = smsc95xx_write_reg(dev, BULK_IN_DLY, read_buf);
564 ret = smsc95xx_read_reg(dev, BULK_IN_DLY, &read_buf);
567 debug("Read Value from BULK_IN_DLY after writing: "
568 "0x%08x\n", read_buf);
570 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
573 debug("Read Value from HW_CFG: 0x%08x\n", read_buf);
576 read_buf |= (HW_CFG_MEF_ | HW_CFG_BCE_);
578 read_buf &= ~HW_CFG_RXDOFF_;
580 #define NET_IP_ALIGN 0
581 read_buf |= NET_IP_ALIGN << 9;
583 ret = smsc95xx_write_reg(dev, HW_CFG, read_buf);
587 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
590 debug("Read Value from HW_CFG after writing: 0x%08x\n", read_buf);
592 write_buf = 0xFFFFFFFF;
593 ret = smsc95xx_write_reg(dev, INT_STS, write_buf);
597 ret = smsc95xx_read_reg(dev, ID_REV, &read_buf);
600 debug("ID_REV = 0x%08x\n", read_buf);
602 /* Configure GPIO pins as LED outputs */
603 write_buf = LED_GPIO_CFG_SPD_LED | LED_GPIO_CFG_LNK_LED |
604 LED_GPIO_CFG_FDX_LED;
605 ret = smsc95xx_write_reg(dev, LED_GPIO_CFG, write_buf);
608 debug("LED_GPIO_CFG set\n");
612 ret = smsc95xx_write_reg(dev, FLOW, write_buf);
616 read_buf = AFC_CFG_DEFAULT;
617 ret = smsc95xx_write_reg(dev, AFC_CFG, read_buf);
621 ret = smsc95xx_read_reg(dev, MAC_CR, &priv->mac_cr);
625 /* Init Rx. Set Vlan */
626 write_buf = (u32)ETH_P_8021Q;
627 ret = smsc95xx_write_reg(dev, VLAN1, write_buf);
631 /* Disable checksum offload engines */
632 ret = smsc95xx_set_csums(dev, 0, 0);
634 debug("Failed to set csum offload: %d\n", ret);
637 smsc95xx_set_multicast(dev);
639 if (smsc95xx_phy_initialize(dev) < 0)
641 ret = smsc95xx_read_reg(dev, INT_EP_CTL, &read_buf);
645 /* enable PHY interrupts */
646 read_buf |= INT_EP_CTL_PHY_INT_;
648 ret = smsc95xx_write_reg(dev, INT_EP_CTL, read_buf);
652 smsc95xx_start_tx_path(dev);
653 smsc95xx_start_rx_path(dev);
657 link_detected = smsc95xx_mdio_read(dev, dev->phy_id, MII_BMSR)
659 if (!link_detected) {
661 printf("Waiting for Ethernet connection... ");
662 udelay(TIMEOUT_RESOLUTION * 1000);
663 timeout += TIMEOUT_RESOLUTION;
665 } while (!link_detected && timeout < PHY_CONNECT_TIMEOUT);
670 printf("unable to connect.\n");
676 static int smsc95xx_send(struct eth_device *eth, void* packet, int length)
678 struct ueth_data *dev = (struct ueth_data *)eth->priv;
683 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, msg,
684 PKTSIZE + sizeof(tx_cmd_a) + sizeof(tx_cmd_b));
686 debug("** %s(), len %d, buf %#x\n", __func__, length, (int)msg);
687 if (length > PKTSIZE)
690 tx_cmd_a = (u32)length | TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
691 tx_cmd_b = (u32)length;
692 cpu_to_le32s(&tx_cmd_a);
693 cpu_to_le32s(&tx_cmd_b);
695 /* prepend cmd_a and cmd_b */
696 memcpy(msg, &tx_cmd_a, sizeof(tx_cmd_a));
697 memcpy(msg + sizeof(tx_cmd_a), &tx_cmd_b, sizeof(tx_cmd_b));
698 memcpy(msg + sizeof(tx_cmd_a) + sizeof(tx_cmd_b), (void *)packet,
700 err = usb_bulk_msg(dev->pusb_dev,
701 usb_sndbulkpipe(dev->pusb_dev, dev->ep_out),
703 length + sizeof(tx_cmd_a) + sizeof(tx_cmd_b),
705 USB_BULK_SEND_TIMEOUT);
706 debug("Tx: len = %u, actual = %u, err = %d\n",
707 length + sizeof(tx_cmd_a) + sizeof(tx_cmd_b),
712 static int smsc95xx_recv(struct eth_device *eth)
714 struct ueth_data *dev = (struct ueth_data *)eth->priv;
715 DEFINE_CACHE_ALIGN_BUFFER(unsigned char, recv_buf, RX_URB_SIZE);
716 unsigned char *buf_ptr;
722 debug("** %s()\n", __func__);
723 err = usb_bulk_msg(dev->pusb_dev,
724 usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in),
728 USB_BULK_RECV_TIMEOUT);
729 debug("Rx: len = %u, actual = %u, err = %d\n", RX_URB_SIZE,
732 debug("Rx: failed to receive\n");
735 if (actual_len > RX_URB_SIZE) {
736 debug("Rx: received too many bytes %d\n", actual_len);
741 while (actual_len > 0) {
743 * 1st 4 bytes contain the length of the actual data plus error
744 * info. Extract data length.
746 if (actual_len < sizeof(packet_len)) {
747 debug("Rx: incomplete packet length\n");
750 memcpy(&packet_len, buf_ptr, sizeof(packet_len));
751 le32_to_cpus(&packet_len);
752 if (packet_len & RX_STS_ES_) {
753 debug("Rx: Error header=%#x", packet_len);
756 packet_len = ((packet_len & RX_STS_FL_) >> 16);
758 if (packet_len > actual_len - sizeof(packet_len)) {
759 debug("Rx: too large packet: %d\n", packet_len);
763 /* Notify net stack */
764 net_process_received_packet(buf_ptr + sizeof(packet_len),
767 /* Adjust for next iteration */
768 actual_len -= sizeof(packet_len) + packet_len;
769 buf_ptr += sizeof(packet_len) + packet_len;
770 cur_buf_align = (int)buf_ptr - (int)recv_buf;
772 if (cur_buf_align & 0x03) {
773 int align = 4 - (cur_buf_align & 0x03);
782 static void smsc95xx_halt(struct eth_device *eth)
784 debug("** %s()\n", __func__);
788 * SMSC probing functions
790 void smsc95xx_eth_before_probe(void)
795 struct smsc95xx_dongle {
796 unsigned short vendor;
797 unsigned short product;
800 static const struct smsc95xx_dongle smsc95xx_dongles[] = {
801 { 0x0424, 0xec00 }, /* LAN9512/LAN9514 Ethernet */
802 { 0x0424, 0x9500 }, /* LAN9500 Ethernet */
803 { 0x0424, 0x9730 }, /* LAN9730 Ethernet (HSIC) */
804 { 0x0424, 0x9900 }, /* SMSC9500 USB Ethernet Device (SAL10) */
805 { 0x0424, 0x9e00 }, /* LAN9500A Ethernet */
806 { 0x0000, 0x0000 } /* END - Do not remove */
809 /* Probe to see if a new device is actually an SMSC device */
810 int smsc95xx_eth_probe(struct usb_device *dev, unsigned int ifnum,
811 struct ueth_data *ss)
813 struct usb_interface *iface;
814 struct usb_interface_descriptor *iface_desc;
817 /* let's examine the device now */
818 iface = &dev->config.if_desc[ifnum];
819 iface_desc = &dev->config.if_desc[ifnum].desc;
821 for (i = 0; smsc95xx_dongles[i].vendor != 0; i++) {
822 if (dev->descriptor.idVendor == smsc95xx_dongles[i].vendor &&
823 dev->descriptor.idProduct == smsc95xx_dongles[i].product)
824 /* Found a supported dongle */
827 if (smsc95xx_dongles[i].vendor == 0)
830 /* At this point, we know we've got a live one */
831 debug("\n\nUSB Ethernet device detected\n");
832 memset(ss, '\0', sizeof(struct ueth_data));
834 /* Initialize the ueth_data structure with some useful info */
837 ss->subclass = iface_desc->bInterfaceSubClass;
838 ss->protocol = iface_desc->bInterfaceProtocol;
841 * We are expecting a minimum of 3 endpoints - in, out (bulk), and int.
842 * We will ignore any others.
844 for (i = 0; i < iface_desc->bNumEndpoints; i++) {
845 /* is it an BULK endpoint? */
846 if ((iface->ep_desc[i].bmAttributes &
847 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) {
848 if (iface->ep_desc[i].bEndpointAddress & USB_DIR_IN)
850 iface->ep_desc[i].bEndpointAddress &
851 USB_ENDPOINT_NUMBER_MASK;
854 iface->ep_desc[i].bEndpointAddress &
855 USB_ENDPOINT_NUMBER_MASK;
858 /* is it an interrupt endpoint? */
859 if ((iface->ep_desc[i].bmAttributes &
860 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) {
861 ss->ep_int = iface->ep_desc[i].bEndpointAddress &
862 USB_ENDPOINT_NUMBER_MASK;
863 ss->irqinterval = iface->ep_desc[i].bInterval;
866 debug("Endpoints In %d Out %d Int %d\n",
867 ss->ep_in, ss->ep_out, ss->ep_int);
869 /* Do some basic sanity checks, and bail if we find a problem */
870 if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) ||
871 !ss->ep_in || !ss->ep_out || !ss->ep_int) {
872 debug("Problems with device\n");
875 dev->privptr = (void *)ss;
877 /* alloc driver private */
878 ss->dev_priv = calloc(1, sizeof(struct smsc95xx_private));
885 int smsc95xx_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
886 struct eth_device *eth)
888 debug("** %s()\n", __func__);
890 debug("%s: missing parameter.\n", __func__);
893 sprintf(eth->name, "%s%d", SMSC95XX_BASE_NAME, curr_eth_dev++);
894 eth->init = smsc95xx_init;
895 eth->send = smsc95xx_send;
896 eth->recv = smsc95xx_recv;
897 eth->halt = smsc95xx_halt;
898 eth->write_hwaddr = smsc95xx_write_hwaddr;