drivers/usb/gadget/mv_u3d_core.c

   1 /*
   2  * Copyright (C) 2011 Marvell International Ltd. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  */
   8
   9 #include <linux/module.h>
  10 #include <linux/dma-mapping.h>
  11 #include <linux/dmapool.h>
  12 #include <linux/kernel.h>
  13 #include <linux/delay.h>
  14 #include <linux/ioport.h>
  15 #include <linux/sched.h>
  16 #include <linux/slab.h>
  17 #include <linux/errno.h>
  18 #include <linux/init.h>
  19 #include <linux/timer.h>
  20 #include <linux/list.h>
  21 #include <linux/notifier.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/moduleparam.h>
  24 #include <linux/device.h>
  25 #include <linux/usb/ch9.h>
  26 #include <linux/usb/gadget.h>
  27 #include <linux/pm.h>
  28 #include <linux/io.h>
  29 #include <linux/irq.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/platform_data/mv_usb.h>
  32 #include <linux/clk.h>
  33
  34 #include "mv_u3d.h"
  35
  36 #define DRIVER_DESC             "Marvell PXA USB3.0 Device Controller driver"
  37
  38 static const char driver_name[] = "mv_u3d";
  39 static const char driver_desc[] = DRIVER_DESC;
  40
  41 static void mv_u3d_nuke(struct mv_u3d_ep *ep, int status);
  42 static void mv_u3d_stop_activity(struct mv_u3d *u3d,
  43                         struct usb_gadget_driver *driver);
  44
  45 /* for endpoint 0 operations */
  46 static const struct usb_endpoint_descriptor mv_u3d_ep0_desc = {
  47         .bLength =              USB_DT_ENDPOINT_SIZE,
  48         .bDescriptorType =      USB_DT_ENDPOINT,
  49         .bEndpointAddress =     0,
  50         .bmAttributes =         USB_ENDPOINT_XFER_CONTROL,
  51         .wMaxPacketSize =       MV_U3D_EP0_MAX_PKT_SIZE,
  52 };
  53
  54 static void mv_u3d_ep0_reset(struct mv_u3d *u3d)
  55 {
  56         struct mv_u3d_ep *ep;
  57         u32 epxcr;
  58         int i;
  59
  60         for (i = 0; i < 2; i++) {
  61                 ep = &u3d->eps[i];
  62                 ep->u3d = u3d;
  63
  64                 /* ep0 ep context, ep0 in and out share the same ep context */
  65                 ep->ep_context = &u3d->ep_context[1];
  66         }
  67
  68         /* reset ep state machine */
  69         /* reset ep0 out */
  70         epxcr = ioread32(&u3d->vuc_regs->epcr[0].epxoutcr0);
  71         epxcr |= MV_U3D_EPXCR_EP_INIT;
  72         iowrite32(epxcr, &u3d->vuc_regs->epcr[0].epxoutcr0);
  73         udelay(5);
  74         epxcr &= ~MV_U3D_EPXCR_EP_INIT;
  75         iowrite32(epxcr, &u3d->vuc_regs->epcr[0].epxoutcr0);
  76
  77         epxcr = ((MV_U3D_EP0_MAX_PKT_SIZE
  78                 << MV_U3D_EPXCR_MAX_PACKET_SIZE_SHIFT)
  79                 | (1 << MV_U3D_EPXCR_MAX_BURST_SIZE_SHIFT)
  80                 | (1 << MV_U3D_EPXCR_EP_ENABLE_SHIFT)
  81                 | MV_U3D_EPXCR_EP_TYPE_CONTROL);
  82         iowrite32(epxcr, &u3d->vuc_regs->epcr[0].epxoutcr1);
  83
  84         /* reset ep0 in */
  85         epxcr = ioread32(&u3d->vuc_regs->epcr[0].epxincr0);
  86         epxcr |= MV_U3D_EPXCR_EP_INIT;
  87         iowrite32(epxcr, &u3d->vuc_regs->epcr[0].epxincr0);
  88         udelay(5);
  89         epxcr &= ~MV_U3D_EPXCR_EP_INIT;
  90         iowrite32(epxcr, &u3d->vuc_regs->epcr[0].epxincr0);
  91
  92         epxcr = ((MV_U3D_EP0_MAX_PKT_SIZE
  93                 << MV_U3D_EPXCR_MAX_PACKET_SIZE_SHIFT)
  94                 | (1 << MV_U3D_EPXCR_MAX_BURST_SIZE_SHIFT)
  95                 | (1 << MV_U3D_EPXCR_EP_ENABLE_SHIFT)
  96                 | MV_U3D_EPXCR_EP_TYPE_CONTROL);
  97         iowrite32(epxcr, &u3d->vuc_regs->epcr[0].epxincr1);
  98 }
  99
 100 static void mv_u3d_ep0_stall(struct mv_u3d *u3d)
 101 {
 102         u32 tmp;
 103         dev_dbg(u3d->dev, "%s\n", __func__);
 104
 105         /* set TX and RX to stall */
 106         tmp = ioread32(&u3d->vuc_regs->epcr[0].epxoutcr0);
 107         tmp |= MV_U3D_EPXCR_EP_HALT;
 108         iowrite32(tmp, &u3d->vuc_regs->epcr[0].epxoutcr0);
 109
 110         tmp = ioread32(&u3d->vuc_regs->epcr[0].epxincr0);
 111         tmp |= MV_U3D_EPXCR_EP_HALT;
 112         iowrite32(tmp, &u3d->vuc_regs->epcr[0].epxincr0);
 113
 114         /* update ep0 state */
 115         u3d->ep0_state = MV_U3D_WAIT_FOR_SETUP;
 116         u3d->ep0_dir = MV_U3D_EP_DIR_OUT;
 117 }
 118
 119 static int mv_u3d_process_ep_req(struct mv_u3d *u3d, int index,
 120         struct mv_u3d_req *curr_req)
 121 {
 122         struct mv_u3d_trb       *curr_trb;
 123         dma_addr_t cur_deq_lo;
 124         struct mv_u3d_ep_context        *curr_ep_context;
 125         int trb_complete, actual, remaining_length = 0;
 126         int direction, ep_num;
 127         int retval = 0;
 128         u32 tmp, status, length;
 129
 130         curr_ep_context = &u3d->ep_context[index];
 131         direction = index % 2;
 132         ep_num = index / 2;
 133
 134         trb_complete = 0;
 135         actual = curr_req->req.length;
 136
 137         while (!list_empty(&curr_req->trb_list)) {
 138                 curr_trb = list_entry(curr_req->trb_list.next,
 139                                         struct mv_u3d_trb, trb_list);
 140                 if (!curr_trb->trb_hw->ctrl.own) {
 141                         dev_err(u3d->dev, "%s, TRB own error!\n",
 142                                 u3d->eps[index].name);
 143                         return 1;
 144                 }
 145
 146                 curr_trb->trb_hw->ctrl.own = 0;
 147                 if (direction == MV_U3D_EP_DIR_OUT) {
 148                         tmp = ioread32(&u3d->vuc_regs->rxst[ep_num].statuslo);
 149                         cur_deq_lo =
 150                                 ioread32(&u3d->vuc_regs->rxst[ep_num].curdeqlo);
 151                 } else {
 152                         tmp = ioread32(&u3d->vuc_regs->txst[ep_num].statuslo);
 153                         cur_deq_lo =
 154                                 ioread32(&u3d->vuc_regs->txst[ep_num].curdeqlo);
 155                 }
 156
 157                 status = tmp >> MV_U3D_XFERSTATUS_COMPLETE_SHIFT;
 158                 length = tmp & MV_U3D_XFERSTATUS_TRB_LENGTH_MASK;
 159
 160                 if (status == MV_U3D_COMPLETE_SUCCESS ||
 161                         (status == MV_U3D_COMPLETE_SHORT_PACKET &&
 162                         direction == MV_U3D_EP_DIR_OUT)) {
 163                         remaining_length += length;
 164                         actual -= remaining_length;
 165                 } else {
 166                         dev_err(u3d->dev,
 167                                 "complete_tr error: ep=%d %s: error = 0x%x\n",
 168                                 index >> 1, direction ? "SEND" : "RECV",
 169                                 status);
 170                         retval = -EPROTO;
 171                 }
 172
 173                 list_del_init(&curr_trb->trb_list);
 174         }
 175         if (retval)
 176                 return retval;
 177
 178         curr_req->req.actual = actual;
 179         return 0;
 180 }
 181
 182 /*
 183  * mv_u3d_done() - retire a request; caller blocked irqs
 184  * @status : request status to be set, only works when
 185  * request is still in progress.
 186  */
 187 static
 188 void mv_u3d_done(struct mv_u3d_ep *ep, struct mv_u3d_req *req, int status)
 189         __releases(&ep->udc->lock)
 190         __acquires(&ep->udc->lock)
 191 {
 192         struct mv_u3d *u3d = (struct mv_u3d *)ep->u3d;
 193
 194         dev_dbg(u3d->dev, "mv_u3d_done: remove req->queue\n");
 195         /* Removed the req from ep queue */
 196         list_del_init(&req->queue);
 197
 198         /* req.status should be set as -EINPROGRESS in ep_queue() */
 199         if (req->req.status == -EINPROGRESS)
 200                 req->req.status = status;
 201         else
 202                 status = req->req.status;
 203
 204         /* Free trb for the request */
 205         if (!req->chain)
 206                 dma_pool_free(u3d->trb_pool,
 207                         req->trb_head->trb_hw, req->trb_head->trb_dma);
 208         else {
 209                 dma_unmap_single(ep->u3d->gadget.dev.parent,
 210                         (dma_addr_t)req->trb_head->trb_dma,
 211                         req->trb_count * sizeof(struct mv_u3d_trb_hw),
 212                         DMA_BIDIRECTIONAL);
 213                 kfree(req->trb_head->trb_hw);
 214         }
 215         kfree(req->trb_head);
 216
 217         usb_gadget_unmap_request(&u3d->gadget, &req->req, mv_u3d_ep_dir(ep));
 218
 219         if (status && (status != -ESHUTDOWN)) {
 220                 dev_dbg(u3d->dev, "complete %s req %p stat %d len %u/%u",
 221                         ep->ep.name, &req->req, status,
 222                         req->req.actual, req->req.length);
 223         }
 224
 225         spin_unlock(&ep->u3d->lock);
 226         /*
 227          * complete() is from gadget layer,
 228          * eg fsg->bulk_in_complete()
 229          */
 230         if (req->req.complete)
 231                 req->req.complete(&ep->ep, &req->req);
 232
 233         spin_lock(&ep->u3d->lock);
 234 }
 235
 236 static int mv_u3d_queue_trb(struct mv_u3d_ep *ep, struct mv_u3d_req *req)
 237 {
 238         u32 tmp, direction;
 239         struct mv_u3d *u3d;
 240         struct mv_u3d_ep_context *ep_context;
 241         int retval = 0;
 242
 243         u3d = ep->u3d;
 244         direction = mv_u3d_ep_dir(ep);
 245
 246         /* ep0 in and out share the same ep context slot 1*/
 247         if (ep->ep_num == 0)
 248                 ep_context = &(u3d->ep_context[1]);
 249         else
 250                 ep_context = &(u3d->ep_context[ep->ep_num * 2 + direction]);
 251
 252         /* check if the pipe is empty or not */
 253         if (!list_empty(&ep->queue)) {
 254                 dev_err(u3d->dev, "add trb to non-empty queue!\n");
 255                 retval = -ENOMEM;
 256                 WARN_ON(1);
 257         } else {
 258                 ep_context->rsvd0 = cpu_to_le32(1);
 259                 ep_context->rsvd1 = 0;
 260
 261                 /* Configure the trb address and set the DCS bit.
 262                  * Both DCS bit and own bit in trb should be set.
 263                  */
 264                 ep_context->trb_addr_lo =
 265                         cpu_to_le32(req->trb_head->trb_dma | DCS_ENABLE);
 266                 ep_context->trb_addr_hi = 0;
 267
 268                 /* Ensure that updates to the EP Context will
 269                  * occure before Ring Bell.
 270                  */
 271                 wmb();
 272
 273                 /* ring bell the ep */
 274                 if (ep->ep_num == 0)
 275                         tmp = 0x1;
 276                 else
 277                         tmp = ep->ep_num * 2
 278                                 + ((direction == MV_U3D_EP_DIR_OUT) ? 0 : 1);
 279
 280                 iowrite32(tmp, &u3d->op_regs->doorbell);
 281         }
 282         return retval;
 283 }
 284
 285 static struct mv_u3d_trb *mv_u3d_build_trb_one(struct mv_u3d_req *req,
 286                                 unsigned *length, dma_addr_t *dma)
 287 {
 288         u32 temp;
 289         unsigned int direction;
 290         struct mv_u3d_trb *trb;
 291         struct mv_u3d_trb_hw *trb_hw;
 292         struct mv_u3d *u3d;
 293
 294         /* how big will this transfer be? */
 295         *length = req->req.length - req->req.actual;
 296         BUG_ON(*length > (unsigned)MV_U3D_EP_MAX_LENGTH_TRANSFER);
 297
 298         u3d = req->ep->u3d;
 299
 300         trb = kzalloc(sizeof(*trb), GFP_ATOMIC);
 301         if (!trb) {
 302                 dev_err(u3d->dev, "%s, trb alloc fail\n", __func__);
 303                 return NULL;
 304         }
 305
 306         /*
 307          * Be careful that no _GFP_HIGHMEM is set,
 308          * or we can not use dma_to_virt
 309          * cannot use GFP_KERNEL in spin lock
 310          */
 311         trb_hw = dma_pool_alloc(u3d->trb_pool, GFP_ATOMIC, dma);
 312         if (!trb_hw) {
 313                 dev_err(u3d->dev,
 314                         "%s, dma_pool_alloc fail\n", __func__);
 315                 return NULL;
 316         }
 317         trb->trb_dma = *dma;
 318         trb->trb_hw = trb_hw;
 319
 320         /* initialize buffer page pointers */
 321         temp = (u32)(req->req.dma + req->req.actual);
 322
 323         trb_hw->buf_addr_lo = cpu_to_le32(temp);
 324         trb_hw->buf_addr_hi = 0;
 325         trb_hw->trb_len = cpu_to_le32(*length);
 326         trb_hw->ctrl.own = 1;
 327
 328         if (req->ep->ep_num == 0)
 329                 trb_hw->ctrl.type = TYPE_DATA;
 330         else
 331                 trb_hw->ctrl.type = TYPE_NORMAL;
 332
 333         req->req.actual += *length;
 334
 335         direction = mv_u3d_ep_dir(req->ep);
 336         if (direction == MV_U3D_EP_DIR_IN)
 337                 trb_hw->ctrl.dir = 1;
 338         else
 339                 trb_hw->ctrl.dir = 0;
 340
 341         /* Enable interrupt for the last trb of a request */
 342         if (!req->req.no_interrupt)
 343                 trb_hw->ctrl.ioc = 1;
 344
 345         trb_hw->ctrl.chain = 0;
 346
 347         wmb();
 348         return trb;
 349 }
 350
 351 static int mv_u3d_build_trb_chain(struct mv_u3d_req *req, unsigned *length,
 352                 struct mv_u3d_trb *trb, int *is_last)
 353 {
 354         u32 temp;
 355         unsigned int direction;
 356         struct mv_u3d *u3d;
 357
 358         /* how big will this transfer be? */
 359         *length = min(req->req.length - req->req.actual,
 360                         (unsigned)MV_U3D_EP_MAX_LENGTH_TRANSFER);
 361
 362         u3d = req->ep->u3d;
 363
 364         trb->trb_dma = 0;
 365
 366         /* initialize buffer page pointers */
 367         temp = (u32)(req->req.dma + req->req.actual);
 368
 369         trb->trb_hw->buf_addr_lo = cpu_to_le32(temp);
 370         trb->trb_hw->buf_addr_hi = 0;
 371         trb->trb_hw->trb_len = cpu_to_le32(*length);
 372         trb->trb_hw->ctrl.own = 1;
 373
 374         if (req->ep->ep_num == 0)
 375                 trb->trb_hw->ctrl.type = TYPE_DATA;
 376         else
 377                 trb->trb_hw->ctrl.type = TYPE_NORMAL;
 378
 379         req->req.actual += *length;
 380
 381         direction = mv_u3d_ep_dir(req->ep);
 382         if (direction == MV_U3D_EP_DIR_IN)
 383                 trb->trb_hw->ctrl.dir = 1;
 384         else
 385                 trb->trb_hw->ctrl.dir = 0;
 386
 387         /* zlp is needed if req->req.zero is set */
 388         if (req->req.zero) {
 389                 if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
 390                         *is_last = 1;
 391                 else
 392                         *is_last = 0;
 393         } else if (req->req.length == req->req.actual)
 394                 *is_last = 1;
 395         else
 396                 *is_last = 0;
 397
 398         /* Enable interrupt for the last trb of a request */
 399         if (*is_last && !req->req.no_interrupt)
 400                 trb->trb_hw->ctrl.ioc = 1;
 401
 402         if (*is_last)
 403                 trb->trb_hw->ctrl.chain = 0;
 404         else {
 405                 trb->trb_hw->ctrl.chain = 1;
 406                 dev_dbg(u3d->dev, "chain trb\n");
 407         }
 408
 409         wmb();
 410
 411         return 0;
 412 }
 413
 414 /* generate TRB linked list for a request
 415  * usb controller only supports continous trb chain,
 416  * that trb structure physical address should be continous.
 417  */
 418 static int mv_u3d_req_to_trb(struct mv_u3d_req *req)
 419 {
 420         unsigned count;
 421         int is_last;
 422         struct mv_u3d_trb *trb;
 423         struct mv_u3d_trb_hw *trb_hw;
 424         struct mv_u3d *u3d;
 425         dma_addr_t dma;
 426         unsigned length;
 427         unsigned trb_num;
 428
 429         u3d = req->ep->u3d;
 430
 431         INIT_LIST_HEAD(&req->trb_list);
 432
 433         length = req->req.length - req->req.actual;
 434         /* normally the request transfer length is less than 16KB.
 435          * we use buil_trb_one() to optimize it.
 436          */
 437         if (length <= (unsigned)MV_U3D_EP_MAX_LENGTH_TRANSFER) {
 438                 trb = mv_u3d_build_trb_one(req, &count, &dma);
 439                 list_add_tail(&trb->trb_list, &req->trb_list);
 440                 req->trb_head = trb;
 441                 req->trb_count = 1;
 442                 req->chain = 0;
 443         } else {
 444                 trb_num = length / MV_U3D_EP_MAX_LENGTH_TRANSFER;
 445                 if (length % MV_U3D_EP_MAX_LENGTH_TRANSFER)
 446                         trb_num++;
 447
 448                 trb = kcalloc(trb_num, sizeof(*trb), GFP_ATOMIC);
 449                 if (!trb) {
 450                         dev_err(u3d->dev,
 451                                         "%s, trb alloc fail\n", __func__);
 452                         return -ENOMEM;
 453                 }
 454
 455                 trb_hw = kcalloc(trb_num, sizeof(*trb_hw), GFP_ATOMIC);
 456                 if (!trb_hw) {
 457                         dev_err(u3d->dev,
 458                                         "%s, trb_hw alloc fail\n", __func__);
 459                         return -ENOMEM;
 460                 }
 461
 462                 do {
 463                         trb->trb_hw = trb_hw;
 464                         if (mv_u3d_build_trb_chain(req, &count,
 465                                                 trb, &is_last)) {
 466                                 dev_err(u3d->dev,
 467                                         "%s, mv_u3d_build_trb_chain fail\n",
 468                                         __func__);
 469                                 return -EIO;
 470                         }
 471
 472                         list_add_tail(&trb->trb_list, &req->trb_list);
 473                         req->trb_count++;
 474                         trb++;
 475                         trb_hw++;
 476                 } while (!is_last);
 477
 478                 req->trb_head = list_entry(req->trb_list.next,
 479                                         struct mv_u3d_trb, trb_list);
 480                 req->trb_head->trb_dma = dma_map_single(u3d->gadget.dev.parent,
 481                                         req->trb_head->trb_hw,
 482                                         trb_num * sizeof(*trb_hw),
 483                                         DMA_BIDIRECTIONAL);
 484
 485                 req->chain = 1;
 486         }
 487
 488         return 0;
 489 }
 490
 491 static int
 492 mv_u3d_start_queue(struct mv_u3d_ep *ep)
 493 {
 494         struct mv_u3d *u3d = ep->u3d;
 495         struct mv_u3d_req *req;
 496         int ret;
 497
 498         if (!list_empty(&ep->req_list) && !ep->processing)
 499                 req = list_entry(ep->req_list.next, struct mv_u3d_req, list);
 500         else
 501                 return 0;
 502
 503         ep->processing = 1;
 504
 505         /* set up dma mapping */
 506         ret = usb_gadget_map_request(&u3d->gadget, &req->req,
 507                                         mv_u3d_ep_dir(ep));
 508         if (ret)
 509                 return ret;
 510
 511         req->req.status = -EINPROGRESS;
 512         req->req.actual = 0;
 513         req->trb_count = 0;
 514
 515         /* build trbs and push them to device queue */
 516         if (!mv_u3d_req_to_trb(req)) {
 517                 ret = mv_u3d_queue_trb(ep, req);
 518                 if (ret) {
 519                         ep->processing = 0;
 520                         return ret;
 521                 }
 522         } else {
 523                 ep->processing = 0;
 524                 dev_err(u3d->dev, "%s, mv_u3d_req_to_trb fail\n", __func__);
 525                 return -ENOMEM;
 526         }
 527
 528         /* irq handler advances the queue */
 529         if (req)
 530                 list_add_tail(&req->queue, &ep->queue);
 531
 532         return 0;
 533 }
 534
 535 static int mv_u3d_ep_enable(struct usb_ep *_ep,
 536                 const struct usb_endpoint_descriptor *desc)
 537 {
 538         struct mv_u3d *u3d;
 539         struct mv_u3d_ep *ep;
 540         struct mv_u3d_ep_context *ep_context;
 541         u16 max = 0;
 542         unsigned maxburst = 0;
 543         u32 epxcr, direction;
 544
 545         if (!_ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT)
 546                 return -EINVAL;
 547
 548         ep = container_of(_ep, struct mv_u3d_ep, ep);
 549         u3d = ep->u3d;
 550
 551         if (!u3d->driver || u3d->gadget.speed == USB_SPEED_UNKNOWN)
 552                 return -ESHUTDOWN;
 553
 554         direction = mv_u3d_ep_dir(ep);
 555         max = le16_to_cpu(desc->wMaxPacketSize);
 556
 557         if (!_ep->maxburst)
 558                 _ep->maxburst = 1;
 559         maxburst = _ep->maxburst;
 560
 561         /* Get the endpoint context address */
 562         ep_context = (struct mv_u3d_ep_context *)ep->ep_context;
 563
 564         /* Set the max burst size */
 565         switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
 566         case USB_ENDPOINT_XFER_BULK:
 567                 if (maxburst > 16) {
 568                         dev_dbg(u3d->dev,
 569                                 "max burst should not be greater "
 570                                 "than 16 on bulk ep\n");
 571                         maxburst = 1;
 572                         _ep->maxburst = maxburst;
 573                 }
 574                 dev_dbg(u3d->dev,
 575                         "maxburst: %d on bulk %s\n", maxburst, ep->name);
 576                 break;
 577         case USB_ENDPOINT_XFER_CONTROL:
 578                 /* control transfer only supports maxburst as one */
 579                 maxburst = 1;
 580                 _ep->maxburst = maxburst;
 581                 break;
 582         case USB_ENDPOINT_XFER_INT:
 583                 if (maxburst != 1) {
 584                         dev_dbg(u3d->dev,
 585                                 "max burst should be 1 on int ep "
 586                                 "if transfer size is not 1024\n");
 587                         maxburst = 1;
 588                         _ep->maxburst = maxburst;
 589                 }
 590                 break;
 591         case USB_ENDPOINT_XFER_ISOC:
 592                 if (maxburst != 1) {
 593                         dev_dbg(u3d->dev,
 594                                 "max burst should be 1 on isoc ep "
 595                                 "if transfer size is not 1024\n");
 596                         maxburst = 1;
 597                         _ep->maxburst = maxburst;
 598                 }
 599                 break;
 600         default:
 601                 goto en_done;
 602         }
 603
 604         ep->ep.maxpacket = max;
 605         ep->ep.desc = desc;
 606         ep->enabled = 1;
 607
 608         /* Enable the endpoint for Rx or Tx and set the endpoint type */
 609         if (direction == MV_U3D_EP_DIR_OUT) {
 610                 epxcr = ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxoutcr0);
 611                 epxcr |= MV_U3D_EPXCR_EP_INIT;
 612                 iowrite32(epxcr, &u3d->vuc_regs->epcr[ep->ep_num].epxoutcr0);
 613                 udelay(5);
 614                 epxcr &= ~MV_U3D_EPXCR_EP_INIT;
 615                 iowrite32(epxcr, &u3d->vuc_regs->epcr[ep->ep_num].epxoutcr0);
 616
 617                 epxcr = ((max << MV_U3D_EPXCR_MAX_PACKET_SIZE_SHIFT)
 618                       | ((maxburst - 1) << MV_U3D_EPXCR_MAX_BURST_SIZE_SHIFT)
 619                       | (1 << MV_U3D_EPXCR_EP_ENABLE_SHIFT)
 620                       | (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK));
 621                 iowrite32(epxcr, &u3d->vuc_regs->epcr[ep->ep_num].epxoutcr1);
 622         } else {
 623                 epxcr = ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxincr0);
 624                 epxcr |= MV_U3D_EPXCR_EP_INIT;
 625                 iowrite32(epxcr, &u3d->vuc_regs->epcr[ep->ep_num].epxincr0);
 626                 udelay(5);
 627                 epxcr &= ~MV_U3D_EPXCR_EP_INIT;
 628                 iowrite32(epxcr, &u3d->vuc_regs->epcr[ep->ep_num].epxincr0);
 629
 630                 epxcr = ((max << MV_U3D_EPXCR_MAX_PACKET_SIZE_SHIFT)
 631                       | ((maxburst - 1) << MV_U3D_EPXCR_MAX_BURST_SIZE_SHIFT)
 632                       | (1 << MV_U3D_EPXCR_EP_ENABLE_SHIFT)
 633                       | (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK));
 634                 iowrite32(epxcr, &u3d->vuc_regs->epcr[ep->ep_num].epxincr1);
 635         }
 636
 637         return 0;
 638 en_done:
 639         return -EINVAL;
 640 }
 641
 642 static int  mv_u3d_ep_disable(struct usb_ep *_ep)
 643 {
 644         struct mv_u3d *u3d;
 645         struct mv_u3d_ep *ep;
 646         struct mv_u3d_ep_context *ep_context;
 647         u32 epxcr, direction;
 648
 649         if (!_ep)
 650                 return -EINVAL;
 651
 652         ep = container_of(_ep, struct mv_u3d_ep, ep);
 653         if (!ep->ep.desc)
 654                 return -EINVAL;
 655
 656         u3d = ep->u3d;
 657
 658         /* Get the endpoint context address */
 659         ep_context = ep->ep_context;
 660
 661         direction = mv_u3d_ep_dir(ep);
 662
 663         /* nuke all pending requests (does flush) */
 664         mv_u3d_nuke(ep, -ESHUTDOWN);
 665
 666         /* Disable the endpoint for Rx or Tx and reset the endpoint type */
 667         if (direction == MV_U3D_EP_DIR_OUT) {
 668                 epxcr = ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxoutcr1);
 669                 epxcr &= ~((1 << MV_U3D_EPXCR_EP_ENABLE_SHIFT)
 670                       | USB_ENDPOINT_XFERTYPE_MASK);
 671                 iowrite32(epxcr, &u3d->vuc_regs->epcr[ep->ep_num].epxoutcr1);
 672         } else {
 673                 epxcr = ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxincr1);
 674                 epxcr &= ~((1 << MV_U3D_EPXCR_EP_ENABLE_SHIFT)
 675                       | USB_ENDPOINT_XFERTYPE_MASK);
 676                 iowrite32(epxcr, &u3d->vuc_regs->epcr[ep->ep_num].epxincr1);
 677         }
 678
 679         ep->enabled = 0;
 680
 681         ep->ep.desc = NULL;
 682         return 0;
 683 }
 684
 685 static struct usb_request *
 686 mv_u3d_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
 687 {
 688         struct mv_u3d_req *req = NULL;
 689
 690         req = kzalloc(sizeof *req, gfp_flags);
 691         if (!req)
 692                 return NULL;
 693
 694         INIT_LIST_HEAD(&req->queue);
 695
 696         return &req->req;
 697 }
 698
 699 static void mv_u3d_free_request(struct usb_ep *_ep, struct usb_request *_req)
 700 {
 701         struct mv_u3d_req *req = container_of(_req, struct mv_u3d_req, req);
 702
 703         kfree(req);
 704 }
 705
 706 static void mv_u3d_ep_fifo_flush(struct usb_ep *_ep)
 707 {
 708         struct mv_u3d *u3d;
 709         u32 direction;
 710         struct mv_u3d_ep *ep = container_of(_ep, struct mv_u3d_ep, ep);
 711         unsigned int loops;
 712         u32 tmp;
 713
 714         /* if endpoint is not enabled, cannot flush endpoint */
 715         if (!ep->enabled)
 716                 return;
 717
 718         u3d = ep->u3d;
 719         direction = mv_u3d_ep_dir(ep);
 720
 721         /* ep0 need clear bit after flushing fifo. */
 722         if (!ep->ep_num) {
 723                 if (direction == MV_U3D_EP_DIR_OUT) {
 724                         tmp = ioread32(&u3d->vuc_regs->epcr[0].epxoutcr0);
 725                         tmp |= MV_U3D_EPXCR_EP_FLUSH;
 726                         iowrite32(tmp, &u3d->vuc_regs->epcr[0].epxoutcr0);
 727                         udelay(10);
 728                         tmp &= ~MV_U3D_EPXCR_EP_FLUSH;
 729                         iowrite32(tmp, &u3d->vuc_regs->epcr[0].epxoutcr0);
 730                 } else {
 731                         tmp = ioread32(&u3d->vuc_regs->epcr[0].epxincr0);
 732                         tmp |= MV_U3D_EPXCR_EP_FLUSH;
 733                         iowrite32(tmp, &u3d->vuc_regs->epcr[0].epxincr0);
 734                         udelay(10);
 735                         tmp &= ~MV_U3D_EPXCR_EP_FLUSH;
 736                         iowrite32(tmp, &u3d->vuc_regs->epcr[0].epxincr0);
 737                 }
 738                 return;
 739         }
 740
 741         if (direction == MV_U3D_EP_DIR_OUT) {
 742                 tmp = ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxoutcr0);
 743                 tmp |= MV_U3D_EPXCR_EP_FLUSH;
 744                 iowrite32(tmp, &u3d->vuc_regs->epcr[ep->ep_num].epxoutcr0);
 745
 746                 /* Wait until flushing completed */
 747                 loops = LOOPS(MV_U3D_FLUSH_TIMEOUT);
 748                 while (ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxoutcr0) &
 749                         MV_U3D_EPXCR_EP_FLUSH) {
 750                         /*
 751                          * EP_FLUSH bit should be cleared to indicate this
 752                          * operation is complete
 753                          */
 754                         if (loops == 0) {
 755                                 dev_dbg(u3d->dev,
 756                                     "EP FLUSH TIMEOUT for ep%d%s\n", ep->ep_num,
 757                                     direction ? "in" : "out");
 758                                 return;
 759                         }
 760                         loops--;
 761                         udelay(LOOPS_USEC);
 762                 }
 763         } else {        /* EP_DIR_IN */
 764                 tmp = ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxincr0);
 765                 tmp |= MV_U3D_EPXCR_EP_FLUSH;
 766                 iowrite32(tmp, &u3d->vuc_regs->epcr[ep->ep_num].epxincr0);
 767
 768                 /* Wait until flushing completed */
 769                 loops = LOOPS(MV_U3D_FLUSH_TIMEOUT);
 770                 while (ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxincr0) &
 771                         MV_U3D_EPXCR_EP_FLUSH) {
 772                         /*
 773                         * EP_FLUSH bit should be cleared to indicate this
 774                         * operation is complete
 775                         */
 776                         if (loops == 0) {
 777                                 dev_dbg(u3d->dev,
 778                                     "EP FLUSH TIMEOUT for ep%d%s\n", ep->ep_num,
 779                                     direction ? "in" : "out");
 780                                 return;
 781                         }
 782                         loops--;
 783                         udelay(LOOPS_USEC);
 784                 }
 785         }
 786 }
 787
 788 /* queues (submits) an I/O request to an endpoint */
 789 static int
 790 mv_u3d_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
 791 {
 792         struct mv_u3d_ep *ep;
 793         struct mv_u3d_req *req;
 794         struct mv_u3d *u3d;
 795         unsigned long flags;
 796         int is_first_req = 0;
 797
 798         if (unlikely(!_ep || !_req))
 799                 return -EINVAL;
 800
 801         ep = container_of(_ep, struct mv_u3d_ep, ep);
 802         u3d = ep->u3d;
 803
 804         req = container_of(_req, struct mv_u3d_req, req);
 805
 806         if (!ep->ep_num
 807                 && u3d->ep0_state == MV_U3D_STATUS_STAGE
 808                 && !_req->length) {
 809                 dev_dbg(u3d->dev, "ep0 status stage\n");
 810                 u3d->ep0_state = MV_U3D_WAIT_FOR_SETUP;
 811                 return 0;
 812         }
 813
 814         dev_dbg(u3d->dev, "%s: %s, req: 0x%p\n",
 815                         __func__, _ep->name, req);
 816
 817         /* catch various bogus parameters */
 818         if (!req->req.complete || !req->req.buf
 819                         || !list_empty(&req->queue)) {
 820                 dev_err(u3d->dev,
 821                         "%s, bad params, _req: 0x%p,"
 822                         "req->req.complete: 0x%p, req->req.buf: 0x%p,"
 823                         "list_empty: 0x%x\n",
 824                         __func__, _req,
 825                         req->req.complete, req->req.buf,
 826                         list_empty(&req->queue));
 827                 return -EINVAL;
 828         }
 829         if (unlikely(!ep->ep.desc)) {
 830                 dev_err(u3d->dev, "%s, bad ep\n", __func__);
 831                 return -EINVAL;
 832         }
 833         if (ep->ep.desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
 834                 if (req->req.length > ep->ep.maxpacket)
 835                         return -EMSGSIZE;
 836         }
 837
 838         if (!u3d->driver || u3d->gadget.speed == USB_SPEED_UNKNOWN) {
 839                 dev_err(u3d->dev,
 840                         "bad params of driver/speed\n");
 841                 return -ESHUTDOWN;
 842         }
 843
 844         req->ep = ep;
 845
 846         /* Software list handles usb request. */
 847         spin_lock_irqsave(&ep->req_lock, flags);
 848         is_first_req = list_empty(&ep->req_list);
 849         list_add_tail(&req->list, &ep->req_list);
 850         spin_unlock_irqrestore(&ep->req_lock, flags);
 851         if (!is_first_req) {
 852                 dev_dbg(u3d->dev, "list is not empty\n");
 853                 return 0;
 854         }
 855
 856         dev_dbg(u3d->dev, "call mv_u3d_start_queue from usb_ep_queue\n");
 857         spin_lock_irqsave(&u3d->lock, flags);
 858         mv_u3d_start_queue(ep);
 859         spin_unlock_irqrestore(&u3d->lock, flags);
 860         return 0;
 861 }
 862
 863 /* dequeues (cancels, unlinks) an I/O request from an endpoint */
 864 static int mv_u3d_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
 865 {
 866         struct mv_u3d_ep *ep;
 867         struct mv_u3d_req *req;
 868         struct mv_u3d *u3d;
 869         struct mv_u3d_ep_context *ep_context;
 870         struct mv_u3d_req *next_req;
 871
 872         unsigned long flags;
 873         int ret = 0;
 874
 875         if (!_ep || !_req)
 876                 return -EINVAL;
 877
 878         ep = container_of(_ep, struct mv_u3d_ep, ep);
 879         u3d = ep->u3d;
 880
 881         spin_lock_irqsave(&ep->u3d->lock, flags);
 882
 883         /* make sure it's actually queued on this endpoint */
 884         list_for_each_entry(req, &ep->queue, queue) {
 885                 if (&req->req == _req)
 886                         break;
 887         }
 888         if (&req->req != _req) {
 889                 ret = -EINVAL;
 890                 goto out;
 891         }
 892
 893         /* The request is in progress, or completed but not dequeued */
 894         if (ep->queue.next == &req->queue) {
 895                 _req->status = -ECONNRESET;
 896                 mv_u3d_ep_fifo_flush(_ep);
 897
 898                 /* The request isn't the last request in this ep queue */
 899                 if (req->queue.next != &ep->queue) {
 900                         dev_dbg(u3d->dev,
 901                                 "it is the last request in this ep queue\n");
 902                         ep_context = ep->ep_context;
 903                         next_req = list_entry(req->queue.next,
 904                                         struct mv_u3d_req, queue);
 905
 906                         /* Point first TRB of next request to the EP context. */
 907                         iowrite32((unsigned long) next_req->trb_head,
 908                                         &ep_context->trb_addr_lo);
 909                 } else {
 910                         struct mv_u3d_ep_context *ep_context;
 911                         ep_context = ep->ep_context;
 912                         ep_context->trb_addr_lo = 0;
 913                         ep_context->trb_addr_hi = 0;
 914                 }
 915
 916         } else
 917                 WARN_ON(1);
 918
 919         mv_u3d_done(ep, req, -ECONNRESET);
 920
 921         /* remove the req from the ep req list */
 922         if (!list_empty(&ep->req_list)) {
 923                 struct mv_u3d_req *curr_req;
 924                 curr_req = list_entry(ep->req_list.next,
 925                                         struct mv_u3d_req, list);
 926                 if (curr_req == req) {
 927                         list_del_init(&req->list);
 928                         ep->processing = 0;
 929                 }
 930         }
 931
 932 out:
 933         spin_unlock_irqrestore(&ep->u3d->lock, flags);
 934         return ret;
 935 }
 936
 937 static void
 938 mv_u3d_ep_set_stall(struct mv_u3d *u3d, u8 ep_num, u8 direction, int stall)
 939 {
 940         u32 tmp;
 941         struct mv_u3d_ep *ep = u3d->eps;
 942
 943         dev_dbg(u3d->dev, "%s\n", __func__);
 944         if (direction == MV_U3D_EP_DIR_OUT) {
 945                 tmp = ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxoutcr0);
 946                 if (stall)
 947                         tmp |= MV_U3D_EPXCR_EP_HALT;
 948                 else
 949                         tmp &= ~MV_U3D_EPXCR_EP_HALT;
 950                 iowrite32(tmp, &u3d->vuc_regs->epcr[ep->ep_num].epxoutcr0);
 951         } else {
 952                 tmp = ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxincr0);
 953                 if (stall)
 954                         tmp |= MV_U3D_EPXCR_EP_HALT;
 955                 else
 956                         tmp &= ~MV_U3D_EPXCR_EP_HALT;
 957                 iowrite32(tmp, &u3d->vuc_regs->epcr[ep->ep_num].epxincr0);
 958         }
 959 }
 960
 961 static int mv_u3d_ep_set_halt_wedge(struct usb_ep *_ep, int halt, int wedge)
 962 {
 963         struct mv_u3d_ep *ep;
 964         unsigned long flags = 0;
 965         int status = 0;
 966         struct mv_u3d *u3d;
 967
 968         ep = container_of(_ep, struct mv_u3d_ep, ep);
 969         u3d = ep->u3d;
 970         if (!ep->ep.desc) {
 971                 status = -EINVAL;
 972                 goto out;
 973         }
 974
 975         if (ep->ep.desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
 976                 status = -EOPNOTSUPP;
 977                 goto out;
 978         }
 979
 980         /*
 981          * Attempt to halt IN ep will fail if any transfer requests
 982          * are still queue
 983          */
 984         if (halt && (mv_u3d_ep_dir(ep) == MV_U3D_EP_DIR_IN)
 985                         && !list_empty(&ep->queue)) {
 986                 status = -EAGAIN;
 987                 goto out;
 988         }
 989
 990         spin_lock_irqsave(&ep->u3d->lock, flags);
 991         mv_u3d_ep_set_stall(u3d, ep->ep_num, mv_u3d_ep_dir(ep), halt);
 992         if (halt && wedge)
 993                 ep->wedge = 1;
 994         else if (!halt)
 995                 ep->wedge = 0;
 996         spin_unlock_irqrestore(&ep->u3d->lock, flags);
 997
 998         if (ep->ep_num == 0)
 999                 u3d->ep0_dir = MV_U3D_EP_DIR_OUT;
1000 out:
1001         return status;
1002 }
1003
1004 static int mv_u3d_ep_set_halt(struct usb_ep *_ep, int halt)
1005 {
1006         return mv_u3d_ep_set_halt_wedge(_ep, halt, 0);
1007 }
1008
1009 static int mv_u3d_ep_set_wedge(struct usb_ep *_ep)
1010 {
1011         return mv_u3d_ep_set_halt_wedge(_ep, 1, 1);
1012 }
1013
1014 static struct usb_ep_ops mv_u3d_ep_ops = {
1015         .enable         = mv_u3d_ep_enable,
1016         .disable        = mv_u3d_ep_disable,
1017
1018         .alloc_request  = mv_u3d_alloc_request,
1019         .free_request   = mv_u3d_free_request,
1020
1021         .queue          = mv_u3d_ep_queue,
1022         .dequeue        = mv_u3d_ep_dequeue,
1023
1024         .set_wedge      = mv_u3d_ep_set_wedge,
1025         .set_halt       = mv_u3d_ep_set_halt,
1026         .fifo_flush     = mv_u3d_ep_fifo_flush,
1027 };
1028
1029 static void mv_u3d_controller_stop(struct mv_u3d *u3d)
1030 {
1031         u32 tmp;
1032
1033         if (!u3d->clock_gating && u3d->vbus_valid_detect)
1034                 iowrite32(MV_U3D_INTR_ENABLE_VBUS_VALID,
1035                                 &u3d->vuc_regs->intrenable);
1036         else
1037                 iowrite32(0, &u3d->vuc_regs->intrenable);
1038         iowrite32(~0x0, &u3d->vuc_regs->endcomplete);
1039         iowrite32(~0x0, &u3d->vuc_regs->trbunderrun);
1040         iowrite32(~0x0, &u3d->vuc_regs->trbcomplete);
1041         iowrite32(~0x0, &u3d->vuc_regs->linkchange);
1042         iowrite32(0x1, &u3d->vuc_regs->setuplock);
1043
1044         /* Reset the RUN bit in the command register to stop USB */
1045         tmp = ioread32(&u3d->op_regs->usbcmd);
1046         tmp &= ~MV_U3D_CMD_RUN_STOP;
1047         iowrite32(tmp, &u3d->op_regs->usbcmd);
1048         dev_dbg(u3d->dev, "after u3d_stop, USBCMD 0x%x\n",
1049                 ioread32(&u3d->op_regs->usbcmd));
1050 }
1051
1052 static void mv_u3d_controller_start(struct mv_u3d *u3d)
1053 {
1054         u32 usbintr;
1055         u32 temp;
1056
1057         /* enable link LTSSM state machine */
1058         temp = ioread32(&u3d->vuc_regs->ltssm);
1059         temp |= MV_U3D_LTSSM_PHY_INIT_DONE;
1060         iowrite32(temp, &u3d->vuc_regs->ltssm);
1061
1062         /* Enable interrupts */
1063         usbintr = MV_U3D_INTR_ENABLE_LINK_CHG | MV_U3D_INTR_ENABLE_TXDESC_ERR |
1064                 MV_U3D_INTR_ENABLE_RXDESC_ERR | MV_U3D_INTR_ENABLE_TX_COMPLETE |
1065                 MV_U3D_INTR_ENABLE_RX_COMPLETE | MV_U3D_INTR_ENABLE_SETUP |
1066                 (u3d->vbus_valid_detect ? MV_U3D_INTR_ENABLE_VBUS_VALID : 0);
1067         iowrite32(usbintr, &u3d->vuc_regs->intrenable);
1068
1069         /* Enable ctrl ep */
1070         iowrite32(0x1, &u3d->vuc_regs->ctrlepenable);
1071
1072         /* Set the Run bit in the command register */
1073         iowrite32(MV_U3D_CMD_RUN_STOP, &u3d->op_regs->usbcmd);
1074         dev_dbg(u3d->dev, "after u3d_start, USBCMD 0x%x\n",
1075                 ioread32(&u3d->op_regs->usbcmd));
1076 }
1077
1078 static int mv_u3d_controller_reset(struct mv_u3d *u3d)
1079 {
1080         unsigned int loops;
1081         u32 tmp;
1082
1083         /* Stop the controller */
1084         tmp = ioread32(&u3d->op_regs->usbcmd);
1085         tmp &= ~MV_U3D_CMD_RUN_STOP;
1086         iowrite32(tmp, &u3d->op_regs->usbcmd);
1087
1088         /* Reset the controller to get default values */
1089         iowrite32(MV_U3D_CMD_CTRL_RESET, &u3d->op_regs->usbcmd);
1090
1091         /* wait for reset to complete */
1092         loops = LOOPS(MV_U3D_RESET_TIMEOUT);
1093         while (ioread32(&u3d->op_regs->usbcmd) & MV_U3D_CMD_CTRL_RESET) {
1094                 if (loops == 0) {
1095                         dev_err(u3d->dev,
1096                                 "Wait for RESET completed TIMEOUT\n");
1097                         return -ETIMEDOUT;
1098                 }
1099                 loops--;
1100                 udelay(LOOPS_USEC);
1101         }
1102
1103         /* Configure the Endpoint Context Address */
1104         iowrite32(u3d->ep_context_dma, &u3d->op_regs->dcbaapl);
1105         iowrite32(0, &u3d->op_regs->dcbaaph);
1106
1107         return 0;
1108 }
1109
1110 static int mv_u3d_enable(struct mv_u3d *u3d)
1111 {
1112         struct mv_usb_platform_data *pdata = dev_get_platdata(u3d->dev);
1113         int retval;
1114
1115         if (u3d->active)
1116                 return 0;
1117
1118         if (!u3d->clock_gating) {
1119                 u3d->active = 1;
1120                 return 0;
1121         }
1122
1123         dev_dbg(u3d->dev, "enable u3d\n");
1124         clk_enable(u3d->clk);
1125         if (pdata->phy_init) {
1126                 retval = pdata->phy_init(u3d->phy_regs);
1127                 if (retval) {
1128                         dev_err(u3d->dev,
1129                                 "init phy error %d\n", retval);
1130                         clk_disable(u3d->clk);
1131                         return retval;
1132                 }
1133         }
1134         u3d->active = 1;
1135
1136         return 0;
1137 }
1138
1139 static void mv_u3d_disable(struct mv_u3d *u3d)
1140 {
1141         struct mv_usb_platform_data *pdata = dev_get_platdata(u3d->dev);
1142         if (u3d->clock_gating && u3d->active) {
1143                 dev_dbg(u3d->dev, "disable u3d\n");
1144                 if (pdata->phy_deinit)
1145                         pdata->phy_deinit(u3d->phy_regs);
1146                 clk_disable(u3d->clk);
1147                 u3d->active = 0;
1148         }
1149 }
1150
1151 static int mv_u3d_vbus_session(struct usb_gadget *gadget, int is_active)
1152 {
1153         struct mv_u3d *u3d;
1154         unsigned long flags;
1155         int retval = 0;
1156
1157         u3d = container_of(gadget, struct mv_u3d, gadget);
1158
1159         spin_lock_irqsave(&u3d->lock, flags);
1160
1161         u3d->vbus_active = (is_active != 0);
1162         dev_dbg(u3d->dev, "%s: softconnect %d, vbus_active %d\n",
1163                 __func__, u3d->softconnect, u3d->vbus_active);
1164         /*
1165          * 1. external VBUS detect: we can disable/enable clock on demand.
1166          * 2. UDC VBUS detect: we have to enable clock all the time.
1167          * 3. No VBUS detect: we have to enable clock all the time.
1168          */
1169         if (u3d->driver && u3d->softconnect && u3d->vbus_active) {
1170                 retval = mv_u3d_enable(u3d);
1171                 if (retval == 0) {
1172                         /*
1173                          * after clock is disabled, we lost all the register
1174                          *  context. We have to re-init registers
1175                          */
1176                         mv_u3d_controller_reset(u3d);
1177                         mv_u3d_ep0_reset(u3d);
1178                         mv_u3d_controller_start(u3d);
1179                 }
1180         } else if (u3d->driver && u3d->softconnect) {
1181                 if (!u3d->active)
1182                         goto out;
1183
1184                 /* stop all the transfer in queue*/
1185                 mv_u3d_stop_activity(u3d, u3d->driver);
1186                 mv_u3d_controller_stop(u3d);
1187                 mv_u3d_disable(u3d);
1188         }
1189
1190 out:
1191         spin_unlock_irqrestore(&u3d->lock, flags);
1192         return retval;
1193 }
1194
1195 /* constrain controller's VBUS power usage
1196  * This call is used by gadget drivers during SET_CONFIGURATION calls,
1197  * reporting how much power the device may consume.  For example, this
1198  * could affect how quickly batteries are recharged.
1199  *
1200  * Returns zero on success, else negative errno.
1201  */
1202 static int mv_u3d_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1203 {
1204         struct mv_u3d *u3d = container_of(gadget, struct mv_u3d, gadget);
1205
1206         u3d->power = mA;
1207
1208         return 0;
1209 }
1210
1211 static int mv_u3d_pullup(struct usb_gadget *gadget, int is_on)
1212 {
1213         struct mv_u3d *u3d = container_of(gadget, struct mv_u3d, gadget);
1214         unsigned long flags;
1215         int retval = 0;
1216
1217         spin_lock_irqsave(&u3d->lock, flags);
1218
1219         dev_dbg(u3d->dev, "%s: softconnect %d, vbus_active %d\n",
1220                 __func__, u3d->softconnect, u3d->vbus_active);
1221         u3d->softconnect = (is_on != 0);
1222         if (u3d->driver && u3d->softconnect && u3d->vbus_active) {
1223                 retval = mv_u3d_enable(u3d);
1224                 if (retval == 0) {
1225                         /*
1226                          * after clock is disabled, we lost all the register
1227                          *  context. We have to re-init registers
1228                          */
1229                         mv_u3d_controller_reset(u3d);
1230                         mv_u3d_ep0_reset(u3d);
1231                         mv_u3d_controller_start(u3d);
1232                 }
1233         } else if (u3d->driver && u3d->vbus_active) {
1234                 /* stop all the transfer in queue*/
1235                 mv_u3d_stop_activity(u3d, u3d->driver);
1236                 mv_u3d_controller_stop(u3d);
1237                 mv_u3d_disable(u3d);
1238         }
1239
1240         spin_unlock_irqrestore(&u3d->lock, flags);
1241
1242         return retval;
1243 }
1244
1245 static int mv_u3d_start(struct usb_gadget *g,
1246                 struct usb_gadget_driver *driver)
1247 {
1248         struct mv_u3d *u3d = container_of(g, struct mv_u3d, gadget);
1249         struct mv_usb_platform_data *pdata = dev_get_platdata(u3d->dev);
1250         unsigned long flags;
1251
1252         if (u3d->driver)
1253                 return -EBUSY;
1254
1255         spin_lock_irqsave(&u3d->lock, flags);
1256
1257         if (!u3d->clock_gating) {
1258                 clk_enable(u3d->clk);
1259                 if (pdata->phy_init)
1260                         pdata->phy_init(u3d->phy_regs);
1261         }
1262
1263         /* hook up the driver ... */
1264         driver->driver.bus = NULL;
1265         u3d->driver = driver;
1266
1267         u3d->ep0_dir = USB_DIR_OUT;
1268
1269         spin_unlock_irqrestore(&u3d->lock, flags);
1270
1271         u3d->vbus_valid_detect = 1;
1272
1273         return 0;
1274 }
1275
1276 static int mv_u3d_stop(struct usb_gadget *g,
1277                 struct usb_gadget_driver *driver)
1278 {
1279         struct mv_u3d *u3d = container_of(g, struct mv_u3d, gadget);
1280         struct mv_usb_platform_data *pdata = dev_get_platdata(u3d->dev);
1281         unsigned long flags;
1282
1283         u3d->vbus_valid_detect = 0;
1284         spin_lock_irqsave(&u3d->lock, flags);
1285
1286         /* enable clock to access controller register */
1287         clk_enable(u3d->clk);
1288         if (pdata->phy_init)
1289                 pdata->phy_init(u3d->phy_regs);
1290
1291         mv_u3d_controller_stop(u3d);
1292         /* stop all usb activities */
1293         u3d->gadget.speed = USB_SPEED_UNKNOWN;
1294         mv_u3d_stop_activity(u3d, driver);
1295         mv_u3d_disable(u3d);
1296
1297         if (pdata->phy_deinit)
1298                 pdata->phy_deinit(u3d->phy_regs);
1299         clk_disable(u3d->clk);
1300
1301         spin_unlock_irqrestore(&u3d->lock, flags);
1302
1303         u3d->driver = NULL;
1304
1305         return 0;
1306 }
1307
1308 /* device controller usb_gadget_ops structure */
1309 static const struct usb_gadget_ops mv_u3d_ops = {
1310         /* notify controller that VBUS is powered or not */
1311         .vbus_session   = mv_u3d_vbus_session,
1312
1313         /* constrain controller's VBUS power usage */
1314         .vbus_draw      = mv_u3d_vbus_draw,
1315
1316         .pullup         = mv_u3d_pullup,
1317         .udc_start      = mv_u3d_start,
1318         .udc_stop       = mv_u3d_stop,
1319 };
1320
1321 static int mv_u3d_eps_init(struct mv_u3d *u3d)
1322 {
1323         struct mv_u3d_ep        *ep;
1324         char name[14];
1325         int i;
1326
1327         /* initialize ep0, ep0 in/out use eps[1] */
1328         ep = &u3d->eps[1];
1329         ep->u3d = u3d;
1330         strncpy(ep->name, "ep0", sizeof(ep->name));
1331         ep->ep.name = ep->name;
1332         ep->ep.ops = &mv_u3d_ep_ops;
1333         ep->wedge = 0;
1334         ep->ep.maxpacket = MV_U3D_EP0_MAX_PKT_SIZE;
1335         ep->ep_num = 0;
1336         ep->ep.desc = &mv_u3d_ep0_desc;
1337         INIT_LIST_HEAD(&ep->queue);
1338         INIT_LIST_HEAD(&ep->req_list);
1339         ep->ep_type = USB_ENDPOINT_XFER_CONTROL;
1340
1341         /* add ep0 ep_context */
1342         ep->ep_context = &u3d->ep_context[1];
1343
1344         /* initialize other endpoints */
1345         for (i = 2; i < u3d->max_eps * 2; i++) {
1346                 ep = &u3d->eps[i];
1347                 if (i & 1) {
1348                         snprintf(name, sizeof(name), "ep%din", i >> 1);
1349                         ep->direction = MV_U3D_EP_DIR_IN;
1350                 } else {
1351                         snprintf(name, sizeof(name), "ep%dout", i >> 1);
1352                         ep->direction = MV_U3D_EP_DIR_OUT;
1353                 }
1354                 ep->u3d = u3d;
1355                 strncpy(ep->name, name, sizeof(ep->name));
1356                 ep->ep.name = ep->name;
1357
1358                 ep->ep.ops = &mv_u3d_ep_ops;
1359                 ep->ep.maxpacket = (unsigned short) ~0;
1360                 ep->ep_num = i / 2;
1361
1362                 INIT_LIST_HEAD(&ep->queue);
1363                 list_add_tail(&ep->ep.ep_list, &u3d->gadget.ep_list);
1364
1365                 INIT_LIST_HEAD(&ep->req_list);
1366                 spin_lock_init(&ep->req_lock);
1367                 ep->ep_context = &u3d->ep_context[i];
1368         }
1369
1370         return 0;
1371 }
1372
1373 /* delete all endpoint requests, called with spinlock held */
1374 static void mv_u3d_nuke(struct mv_u3d_ep *ep, int status)
1375 {
1376         /* endpoint fifo flush */
1377         mv_u3d_ep_fifo_flush(&ep->ep);
1378
1379         while (!list_empty(&ep->queue)) {
1380                 struct mv_u3d_req *req = NULL;
1381                 req = list_entry(ep->queue.next, struct mv_u3d_req, queue);
1382                 mv_u3d_done(ep, req, status);
1383         }
1384 }
1385
1386 /* stop all USB activities */
1387 static
1388 void mv_u3d_stop_activity(struct mv_u3d *u3d, struct usb_gadget_driver *driver)
1389 {
1390         struct mv_u3d_ep        *ep;
1391
1392         mv_u3d_nuke(&u3d->eps[1], -ESHUTDOWN);
1393
1394         list_for_each_entry(ep, &u3d->gadget.ep_list, ep.ep_list) {
1395                 mv_u3d_nuke(ep, -ESHUTDOWN);
1396         }
1397
1398         /* report disconnect; the driver is already quiesced */
1399         if (driver) {
1400                 spin_unlock(&u3d->lock);
1401                 driver->disconnect(&u3d->gadget);
1402                 spin_lock(&u3d->lock);
1403         }
1404 }
1405
1406 static void mv_u3d_irq_process_error(struct mv_u3d *u3d)
1407 {
1408         /* Increment the error count */
1409         u3d->errors++;
1410         dev_err(u3d->dev, "%s\n", __func__);
1411 }
1412
1413 static void mv_u3d_irq_process_link_change(struct mv_u3d *u3d)
1414 {
1415         u32 linkchange;
1416
1417         linkchange = ioread32(&u3d->vuc_regs->linkchange);
1418         iowrite32(linkchange, &u3d->vuc_regs->linkchange);
1419
1420         dev_dbg(u3d->dev, "linkchange: 0x%x\n", linkchange);
1421
1422         if (linkchange & MV_U3D_LINK_CHANGE_LINK_UP) {
1423                 dev_dbg(u3d->dev, "link up: ltssm state: 0x%x\n",
1424                         ioread32(&u3d->vuc_regs->ltssmstate));
1425
1426                 u3d->usb_state = USB_STATE_DEFAULT;
1427                 u3d->ep0_dir = MV_U3D_EP_DIR_OUT;
1428                 u3d->ep0_state = MV_U3D_WAIT_FOR_SETUP;
1429
1430                 /* set speed */
1431                 u3d->gadget.speed = USB_SPEED_SUPER;
1432         }
1433
1434         if (linkchange & MV_U3D_LINK_CHANGE_SUSPEND) {
1435                 dev_dbg(u3d->dev, "link suspend\n");
1436                 u3d->resume_state = u3d->usb_state;
1437                 u3d->usb_state = USB_STATE_SUSPENDED;
1438         }
1439
1440         if (linkchange & MV_U3D_LINK_CHANGE_RESUME) {
1441                 dev_dbg(u3d->dev, "link resume\n");
1442                 u3d->usb_state = u3d->resume_state;
1443                 u3d->resume_state = 0;
1444         }
1445
1446         if (linkchange & MV_U3D_LINK_CHANGE_WRESET) {
1447                 dev_dbg(u3d->dev, "warm reset\n");
1448                 u3d->usb_state = USB_STATE_POWERED;
1449         }
1450
1451         if (linkchange & MV_U3D_LINK_CHANGE_HRESET) {
1452                 dev_dbg(u3d->dev, "hot reset\n");
1453                 u3d->usb_state = USB_STATE_DEFAULT;
1454         }
1455
1456         if (linkchange & MV_U3D_LINK_CHANGE_INACT)
1457                 dev_dbg(u3d->dev, "inactive\n");
1458
1459         if (linkchange & MV_U3D_LINK_CHANGE_DISABLE_AFTER_U0)
1460                 dev_dbg(u3d->dev, "ss.disabled\n");
1461
1462         if (linkchange & MV_U3D_LINK_CHANGE_VBUS_INVALID) {
1463                 dev_dbg(u3d->dev, "vbus invalid\n");
1464                 u3d->usb_state = USB_STATE_ATTACHED;
1465                 u3d->vbus_valid_detect = 1;
1466                 /* if external vbus detect is not supported,
1467                  * we handle it here.
1468                  */
1469                 if (!u3d->vbus) {
1470                         spin_unlock(&u3d->lock);
1471                         mv_u3d_vbus_session(&u3d->gadget, 0);
1472                         spin_lock(&u3d->lock);
1473                 }
1474         }
1475 }
1476
1477 static void mv_u3d_ch9setaddress(struct mv_u3d *u3d,
1478                                 struct usb_ctrlrequest *setup)
1479 {
1480         u32 tmp;
1481
1482         if (u3d->usb_state != USB_STATE_DEFAULT) {
1483                 dev_err(u3d->dev,
1484                         "%s, cannot setaddr in this state (%d)\n",
1485                         __func__, u3d->usb_state);
1486                 goto err;
1487         }
1488
1489         u3d->dev_addr = (u8)setup->wValue;
1490
1491         dev_dbg(u3d->dev, "%s: 0x%x\n", __func__, u3d->dev_addr);
1492
1493         if (u3d->dev_addr > 127) {
1494                 dev_err(u3d->dev,
1495                         "%s, u3d address is wrong (out of range)\n", __func__);
1496                 u3d->dev_addr = 0;
1497                 goto err;
1498         }
1499
1500         /* update usb state */
1501         u3d->usb_state = USB_STATE_ADDRESS;
1502
1503         /* set the new address */
1504         tmp = ioread32(&u3d->vuc_regs->devaddrtiebrkr);
1505         tmp &= ~0x7F;
1506         tmp |= (u32)u3d->dev_addr;
1507         iowrite32(tmp, &u3d->vuc_regs->devaddrtiebrkr);
1508
1509         return;
1510 err:
1511         mv_u3d_ep0_stall(u3d);
1512 }
1513
1514 static int mv_u3d_is_set_configuration(struct usb_ctrlrequest *setup)
1515 {
1516         if ((setup->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
1517                 if (setup->bRequest == USB_REQ_SET_CONFIGURATION)
1518                         return 1;
1519
1520         return 0;
1521 }
1522
1523 static void mv_u3d_handle_setup_packet(struct mv_u3d *u3d, u8 ep_num,
1524         struct usb_ctrlrequest *setup)
1525         __releases(&u3c->lock)
1526         __acquires(&u3c->lock)
1527 {
1528         bool delegate = false;
1529
1530         mv_u3d_nuke(&u3d->eps[ep_num * 2 + MV_U3D_EP_DIR_IN], -ESHUTDOWN);
1531
1532         dev_dbg(u3d->dev, "SETUP %02x.%02x v%04x i%04x l%04x\n",
1533                         setup->bRequestType, setup->bRequest,
1534                         setup->wValue, setup->wIndex, setup->wLength);
1535
1536         /* We process some stardard setup requests here */
1537         if ((setup->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1538                 switch (setup->bRequest) {
1539                 case USB_REQ_GET_STATUS:
1540                         delegate = true;
1541                         break;
1542
1543                 case USB_REQ_SET_ADDRESS:
1544                         mv_u3d_ch9setaddress(u3d, setup);
1545                         break;
1546
1547                 case USB_REQ_CLEAR_FEATURE:
1548                         delegate = true;
1549                         break;
1550
1551                 case USB_REQ_SET_FEATURE:
1552                         delegate = true;
1553                         break;
1554
1555                 default:
1556                         delegate = true;
1557                 }
1558         } else
1559                 delegate = true;
1560
1561         /* delegate USB standard requests to the gadget driver */
1562         if (delegate == true) {
1563                 /* USB requests handled by gadget */
1564                 if (setup->wLength) {
1565                         /* DATA phase from gadget, STATUS phase from u3d */
1566                         u3d->ep0_dir = (setup->bRequestType & USB_DIR_IN)
1567                                         ? MV_U3D_EP_DIR_IN : MV_U3D_EP_DIR_OUT;
1568                         spin_unlock(&u3d->lock);
1569                         if (u3d->driver->setup(&u3d->gadget,
1570                                 &u3d->local_setup_buff) < 0) {
1571                                 dev_err(u3d->dev, "setup error!\n");
1572                                 mv_u3d_ep0_stall(u3d);
1573                         }
1574                         spin_lock(&u3d->lock);
1575                 } else {
1576                         /* no DATA phase, STATUS phase from gadget */
1577                         u3d->ep0_dir = MV_U3D_EP_DIR_IN;
1578                         u3d->ep0_state = MV_U3D_STATUS_STAGE;
1579                         spin_unlock(&u3d->lock);
1580                         if (u3d->driver->setup(&u3d->gadget,
1581                                 &u3d->local_setup_buff) < 0)
1582                                 mv_u3d_ep0_stall(u3d);
1583                         spin_lock(&u3d->lock);
1584                 }
1585
1586                 if (mv_u3d_is_set_configuration(setup)) {
1587                         dev_dbg(u3d->dev, "u3d configured\n");
1588                         u3d->usb_state = USB_STATE_CONFIGURED;
1589                 }
1590         }
1591 }
1592
1593 static void mv_u3d_get_setup_data(struct mv_u3d *u3d, u8 ep_num, u8 *buffer_ptr)
1594 {
1595         struct mv_u3d_ep_context *epcontext;
1596
1597         epcontext = &u3d->ep_context[ep_num * 2 + MV_U3D_EP_DIR_IN];
1598
1599         /* Copy the setup packet to local buffer */
1600         memcpy(buffer_ptr, (u8 *) &epcontext->setup_buffer, 8);
1601 }
1602
1603 static void mv_u3d_irq_process_setup(struct mv_u3d *u3d)
1604 {
1605         u32 tmp, i;
1606         /* Process all Setup packet received interrupts */
1607         tmp = ioread32(&u3d->vuc_regs->setuplock);
1608         if (tmp) {
1609                 for (i = 0; i < u3d->max_eps; i++) {
1610                         if (tmp & (1 << i)) {
1611                                 mv_u3d_get_setup_data(u3d, i,
1612                                         (u8 *)(&u3d->local_setup_buff));
1613                                 mv_u3d_handle_setup_packet(u3d, i,
1614                                         &u3d->local_setup_buff);
1615                         }
1616                 }
1617         }
1618
1619         iowrite32(tmp, &u3d->vuc_regs->setuplock);
1620 }
1621
1622 static void mv_u3d_irq_process_tr_complete(struct mv_u3d *u3d)
1623 {
1624         u32 tmp, bit_pos;
1625         int i, ep_num = 0, direction = 0;
1626         struct mv_u3d_ep        *curr_ep;
1627         struct mv_u3d_req *curr_req, *temp_req;
1628         int status;
1629
1630         tmp = ioread32(&u3d->vuc_regs->endcomplete);
1631
1632         dev_dbg(u3d->dev, "tr_complete: ep: 0x%x\n", tmp);
1633         if (!tmp)
1634                 return;
1635         iowrite32(tmp, &u3d->vuc_regs->endcomplete);
1636
1637         for (i = 0; i < u3d->max_eps * 2; i++) {
1638                 ep_num = i >> 1;
1639                 direction = i % 2;
1640
1641                 bit_pos = 1 << (ep_num + 16 * direction);
1642
1643                 if (!(bit_pos & tmp))
1644                         continue;
1645
1646                 if (i == 0)
1647                         curr_ep = &u3d->eps[1];
1648                 else
1649                         curr_ep = &u3d->eps[i];
1650
1651                 /* remove req out of ep request list after completion */
1652                 dev_dbg(u3d->dev, "tr comp: check req_list\n");
1653                 spin_lock(&curr_ep->req_lock);
1654                 if (!list_empty(&curr_ep->req_list)) {
1655                         struct mv_u3d_req *req;
1656                         req = list_entry(curr_ep->req_list.next,
1657                                                 struct mv_u3d_req, list);
1658                         list_del_init(&req->list);
1659                         curr_ep->processing = 0;
1660                 }
1661                 spin_unlock(&curr_ep->req_lock);
1662
1663                 /* process the req queue until an uncomplete request */
1664                 list_for_each_entry_safe(curr_req, temp_req,
1665                         &curr_ep->queue, queue) {
1666                         status = mv_u3d_process_ep_req(u3d, i, curr_req);
1667                         if (status)
1668                                 break;
1669                         /* write back status to req */
1670                         curr_req->req.status = status;
1671
1672                         /* ep0 request completion */
1673                         if (ep_num == 0) {
1674                                 mv_u3d_done(curr_ep, curr_req, 0);
1675                                 break;
1676                         } else {
1677                                 mv_u3d_done(curr_ep, curr_req, status);
1678                         }
1679                 }
1680
1681                 dev_dbg(u3d->dev, "call mv_u3d_start_queue from ep complete\n");
1682                 mv_u3d_start_queue(curr_ep);
1683         }
1684 }
1685
1686 static irqreturn_t mv_u3d_irq(int irq, void *dev)
1687 {
1688         struct mv_u3d *u3d = (struct mv_u3d *)dev;
1689         u32 status, intr;
1690         u32 bridgesetting;
1691         u32 trbunderrun;
1692
1693         spin_lock(&u3d->lock);
1694
1695         status = ioread32(&u3d->vuc_regs->intrcause);
1696         intr = ioread32(&u3d->vuc_regs->intrenable);
1697         status &= intr;
1698
1699         if (status == 0) {
1700                 spin_unlock(&u3d->lock);
1701                 dev_err(u3d->dev, "irq error!\n");
1702                 return IRQ_NONE;
1703         }
1704
1705         if (status & MV_U3D_USBINT_VBUS_VALID) {
1706                 bridgesetting = ioread32(&u3d->vuc_regs->bridgesetting);
1707                 if (bridgesetting & MV_U3D_BRIDGE_SETTING_VBUS_VALID) {
1708                         /* write vbus valid bit of bridge setting to clear */
1709                         bridgesetting = MV_U3D_BRIDGE_SETTING_VBUS_VALID;
1710                         iowrite32(bridgesetting, &u3d->vuc_regs->bridgesetting);
1711                         dev_dbg(u3d->dev, "vbus valid\n");
1712
1713                         u3d->usb_state = USB_STATE_POWERED;
1714                         u3d->vbus_valid_detect = 0;
1715                         /* if external vbus detect is not supported,
1716                          * we handle it here.
1717                          */
1718                         if (!u3d->vbus) {
1719                                 spin_unlock(&u3d->lock);
1720                                 mv_u3d_vbus_session(&u3d->gadget, 1);
1721                                 spin_lock(&u3d->lock);
1722                         }
1723                 } else
1724                         dev_err(u3d->dev, "vbus bit is not set\n");
1725         }
1726
1727         /* RX data is already in the 16KB FIFO.*/
1728         if (status & MV_U3D_USBINT_UNDER_RUN) {
1729                 trbunderrun = ioread32(&u3d->vuc_regs->trbunderrun);
1730                 dev_err(u3d->dev, "under run, ep%d\n", trbunderrun);
1731                 iowrite32(trbunderrun, &u3d->vuc_regs->trbunderrun);
1732                 mv_u3d_irq_process_error(u3d);
1733         }
1734
1735         if (status & (MV_U3D_USBINT_RXDESC_ERR | MV_U3D_USBINT_TXDESC_ERR)) {
1736                 /* write one to clear */
1737                 iowrite32(status & (MV_U3D_USBINT_RXDESC_ERR
1738                         | MV_U3D_USBINT_TXDESC_ERR),
1739                         &u3d->vuc_regs->intrcause);
1740                 dev_err(u3d->dev, "desc err 0x%x\n", status);
1741                 mv_u3d_irq_process_error(u3d);
1742         }
1743
1744         if (status & MV_U3D_USBINT_LINK_CHG)
1745                 mv_u3d_irq_process_link_change(u3d);
1746
1747         if (status & MV_U3D_USBINT_TX_COMPLETE)
1748                 mv_u3d_irq_process_tr_complete(u3d);
1749
1750         if (status & MV_U3D_USBINT_RX_COMPLETE)
1751                 mv_u3d_irq_process_tr_complete(u3d);
1752
1753         if (status & MV_U3D_USBINT_SETUP)
1754                 mv_u3d_irq_process_setup(u3d);
1755
1756         spin_unlock(&u3d->lock);
1757         return IRQ_HANDLED;
1758 }
1759
1760 static int mv_u3d_remove(struct platform_device *dev)
1761 {
1762         struct mv_u3d *u3d = platform_get_drvdata(dev);
1763
1764         BUG_ON(u3d == NULL);
1765
1766         usb_del_gadget_udc(&u3d->gadget);
1767
1768         /* free memory allocated in probe */
1769         if (u3d->trb_pool)
1770                 dma_pool_destroy(u3d->trb_pool);
1771
1772         if (u3d->ep_context)
1773                 dma_free_coherent(&dev->dev, u3d->ep_context_size,
1774                         u3d->ep_context, u3d->ep_context_dma);
1775
1776         kfree(u3d->eps);
1777
1778         if (u3d->irq)
1779                 free_irq(u3d->irq, u3d);
1780
1781         if (u3d->cap_regs)
1782                 iounmap(u3d->cap_regs);
1783         u3d->cap_regs = NULL;
1784
1785         kfree(u3d->status_req);
1786
1787         clk_put(u3d->clk);
1788
1789         kfree(u3d);
1790
1791         return 0;
1792 }
1793
1794 static int mv_u3d_probe(struct platform_device *dev)
1795 {
1796         struct mv_u3d *u3d = NULL;
1797         struct mv_usb_platform_data *pdata = dev_get_platdata(&dev->dev);
1798         int retval = 0;
1799         struct resource *r;
1800         size_t size;
1801
1802         if (!dev_get_platdata(&dev->dev)) {
1803                 dev_err(&dev->dev, "missing platform_data\n");
1804                 retval = -ENODEV;
1805                 goto err_pdata;
1806         }
1807
1808         u3d = kzalloc(sizeof(*u3d), GFP_KERNEL);
1809         if (!u3d) {
1810                 dev_err(&dev->dev, "failed to allocate memory for u3d\n");
1811                 retval = -ENOMEM;
1812                 goto err_alloc_private;
1813         }
1814
1815         spin_lock_init(&u3d->lock);
1816
1817         platform_set_drvdata(dev, u3d);
1818
1819         u3d->dev = &dev->dev;
1820         u3d->vbus = pdata->vbus;
1821
1822         u3d->clk = clk_get(&dev->dev, NULL);
1823         if (IS_ERR(u3d->clk)) {
1824                 retval = PTR_ERR(u3d->clk);
1825                 goto err_get_clk;
1826         }
1827
1828         r = platform_get_resource_byname(dev, IORESOURCE_MEM, "capregs");
1829         if (!r) {
1830                 dev_err(&dev->dev, "no I/O memory resource defined\n");
1831                 retval = -ENODEV;
1832                 goto err_get_cap_regs;
1833         }
1834
1835         u3d->cap_regs = (struct mv_u3d_cap_regs __iomem *)
1836                 ioremap(r->start, resource_size(r));
1837         if (!u3d->cap_regs) {
1838                 dev_err(&dev->dev, "failed to map I/O memory\n");
1839                 retval = -EBUSY;
1840                 goto err_map_cap_regs;
1841         } else {
1842                 dev_dbg(&dev->dev, "cap_regs address: 0x%lx/0x%lx\n",
1843                         (unsigned long) r->start,
1844                         (unsigned long) u3d->cap_regs);
1845         }
1846
1847         /* we will access controller register, so enable the u3d controller */
1848         clk_enable(u3d->clk);
1849
1850         if (pdata->phy_init) {
1851                 retval = pdata->phy_init(u3d->phy_regs);
1852                 if (retval) {
1853                         dev_err(&dev->dev, "init phy error %d\n", retval);
1854                         goto err_u3d_enable;
1855                 }
1856         }
1857
1858         u3d->op_regs = (struct mv_u3d_op_regs __iomem *)(u3d->cap_regs
1859                 + MV_U3D_USB3_OP_REGS_OFFSET);
1860
1861         u3d->vuc_regs = (struct mv_u3d_vuc_regs __iomem *)(u3d->cap_regs
1862                 + ioread32(&u3d->cap_regs->vuoff));
1863
1864         u3d->max_eps = 16;
1865
1866         /*
1867          * some platform will use usb to download image, it may not disconnect
1868          * usb gadget before loading kernel. So first stop u3d here.
1869          */
1870         mv_u3d_controller_stop(u3d);
1871         iowrite32(0xFFFFFFFF, &u3d->vuc_regs->intrcause);
1872
1873         if (pdata->phy_deinit)
1874                 pdata->phy_deinit(u3d->phy_regs);
1875         clk_disable(u3d->clk);
1876
1877         size = u3d->max_eps * sizeof(struct mv_u3d_ep_context) * 2;
1878         size = (size + MV_U3D_EP_CONTEXT_ALIGNMENT - 1)
1879                 & ~(MV_U3D_EP_CONTEXT_ALIGNMENT - 1);
1880         u3d->ep_context = dma_alloc_coherent(&dev->dev, size,
1881                                         &u3d->ep_context_dma, GFP_KERNEL);
1882         if (!u3d->ep_context) {
1883                 dev_err(&dev->dev, "allocate ep context memory failed\n");
1884                 retval = -ENOMEM;
1885                 goto err_alloc_ep_context;
1886         }
1887         u3d->ep_context_size = size;
1888
1889         /* create TRB dma_pool resource */
1890         u3d->trb_pool = dma_pool_create("u3d_trb",
1891                         &dev->dev,
1892                         sizeof(struct mv_u3d_trb_hw),
1893                         MV_U3D_TRB_ALIGNMENT,
1894                         MV_U3D_DMA_BOUNDARY);
1895
1896         if (!u3d->trb_pool) {
1897                 retval = -ENOMEM;
1898                 goto err_alloc_trb_pool;
1899         }
1900
1901         size = u3d->max_eps * sizeof(struct mv_u3d_ep) * 2;
1902         u3d->eps = kzalloc(size, GFP_KERNEL);
1903         if (!u3d->eps) {
1904                 dev_err(&dev->dev, "allocate ep memory failed\n");
1905                 retval = -ENOMEM;
1906                 goto err_alloc_eps;
1907         }
1908
1909         /* initialize ep0 status request structure */
1910         u3d->status_req = kzalloc(sizeof(struct mv_u3d_req) + 8, GFP_KERNEL);
1911         if (!u3d->status_req) {
1912                 dev_err(&dev->dev, "allocate status_req memory failed\n");
1913                 retval = -ENOMEM;
1914                 goto err_alloc_status_req;
1915         }
1916         INIT_LIST_HEAD(&u3d->status_req->queue);
1917
1918         /* allocate a small amount of memory to get valid address */
1919         u3d->status_req->req.buf = (char *)u3d->status_req
1920                                         + sizeof(struct mv_u3d_req);
1921         u3d->status_req->req.dma = virt_to_phys(u3d->status_req->req.buf);
1922
1923         u3d->resume_state = USB_STATE_NOTATTACHED;
1924         u3d->usb_state = USB_STATE_ATTACHED;
1925         u3d->ep0_dir = MV_U3D_EP_DIR_OUT;
1926         u3d->remote_wakeup = 0;
1927
1928         r = platform_get_resource(dev, IORESOURCE_IRQ, 0);
1929         if (!r) {
1930                 dev_err(&dev->dev, "no IRQ resource defined\n");
1931                 retval = -ENODEV;
1932                 goto err_get_irq;
1933         }
1934         u3d->irq = r->start;
1935         if (request_irq(u3d->irq, mv_u3d_irq,
1936                 IRQF_DISABLED | IRQF_SHARED, driver_name, u3d)) {
1937                 u3d->irq = 0;
1938                 dev_err(&dev->dev, "Request irq %d for u3d failed\n",
1939                         u3d->irq);
1940                 retval = -ENODEV;
1941                 goto err_request_irq;
1942         }
1943
1944         /* initialize gadget structure */
1945         u3d->gadget.ops = &mv_u3d_ops;  /* usb_gadget_ops */
1946         u3d->gadget.ep0 = &u3d->eps[1].ep;      /* gadget ep0 */
1947         INIT_LIST_HEAD(&u3d->gadget.ep_list);   /* ep_list */
1948         u3d->gadget.speed = USB_SPEED_UNKNOWN;  /* speed */
1949
1950         /* the "gadget" abstracts/virtualizes the controller */
1951         u3d->gadget.name = driver_name;         /* gadget name */
1952
1953         mv_u3d_eps_init(u3d);
1954
1955         /* external vbus detection */
1956         if (u3d->vbus) {
1957                 u3d->clock_gating = 1;
1958                 dev_err(&dev->dev, "external vbus detection\n");
1959         }
1960
1961         if (!u3d->clock_gating)
1962                 u3d->vbus_active = 1;
1963
1964         /* enable usb3 controller vbus detection */
1965         u3d->vbus_valid_detect = 1;
1966
1967         retval = usb_add_gadget_udc(&dev->dev, &u3d->gadget);
1968         if (retval)
1969                 goto err_unregister;
1970
1971         dev_dbg(&dev->dev, "successful probe usb3 device %s clock gating.\n",
1972                 u3d->clock_gating ? "with" : "without");
1973
1974         return 0;
1975
1976 err_unregister:
1977         free_irq(u3d->irq, u3d);
1978 err_request_irq:
1979 err_get_irq:
1980         kfree(u3d->status_req);
1981 err_alloc_status_req:
1982         kfree(u3d->eps);
1983 err_alloc_eps:
1984         dma_pool_destroy(u3d->trb_pool);
1985 err_alloc_trb_pool:
1986         dma_free_coherent(&dev->dev, u3d->ep_context_size,
1987                 u3d->ep_context, u3d->ep_context_dma);
1988 err_alloc_ep_context:
1989         if (pdata->phy_deinit)
1990                 pdata->phy_deinit(u3d->phy_regs);
1991         clk_disable(u3d->clk);
1992 err_u3d_enable:
1993         iounmap(u3d->cap_regs);
1994 err_map_cap_regs:
1995 err_get_cap_regs:
1996 err_get_clk:
1997         clk_put(u3d->clk);
1998         kfree(u3d);
1999 err_alloc_private:
2000 err_pdata:
2001         return retval;
2002 }
2003
2004 #ifdef CONFIG_PM_SLEEP
2005 static int mv_u3d_suspend(struct device *dev)
2006 {
2007         struct mv_u3d *u3d = dev_get_drvdata(dev);
2008
2009         /*
2010          * only cable is unplugged, usb can suspend.
2011          * So do not care about clock_gating == 1, it is handled by
2012          * vbus session.
2013          */
2014         if (!u3d->clock_gating) {
2015                 mv_u3d_controller_stop(u3d);
2016
2017                 spin_lock_irq(&u3d->lock);
2018                 /* stop all usb activities */
2019                 mv_u3d_stop_activity(u3d, u3d->driver);
2020                 spin_unlock_irq(&u3d->lock);
2021
2022                 mv_u3d_disable(u3d);
2023         }
2024
2025         return 0;
2026 }
2027
2028 static int mv_u3d_resume(struct device *dev)
2029 {
2030         struct mv_u3d *u3d = dev_get_drvdata(dev);
2031         int retval;
2032
2033         if (!u3d->clock_gating) {
2034                 retval = mv_u3d_enable(u3d);
2035                 if (retval)
2036                         return retval;
2037
2038                 if (u3d->driver && u3d->softconnect) {
2039                         mv_u3d_controller_reset(u3d);
2040                         mv_u3d_ep0_reset(u3d);
2041                         mv_u3d_controller_start(u3d);
2042                 }
2043         }
2044
2045         return 0;
2046 }
2047 #endif
2048
2049 static SIMPLE_DEV_PM_OPS(mv_u3d_pm_ops, mv_u3d_suspend, mv_u3d_resume);
2050
2051 static void mv_u3d_shutdown(struct platform_device *dev)
2052 {
2053         struct mv_u3d *u3d = platform_get_drvdata(dev);
2054         u32 tmp;
2055
2056         tmp = ioread32(&u3d->op_regs->usbcmd);
2057         tmp &= ~MV_U3D_CMD_RUN_STOP;
2058         iowrite32(tmp, &u3d->op_regs->usbcmd);
2059 }
2060
2061 static struct platform_driver mv_u3d_driver = {
2062         .probe          = mv_u3d_probe,
2063         .remove         = mv_u3d_remove,
2064         .shutdown       = mv_u3d_shutdown,
2065         .driver         = {
2066                 .owner  = THIS_MODULE,
2067                 .name   = "mv-u3d",
2068                 .pm     = &mv_u3d_pm_ops,
2069         },
2070 };
2071
2072 module_platform_driver(mv_u3d_driver);
2073 MODULE_ALIAS("platform:mv-u3d");
2074 MODULE_DESCRIPTION(DRIVER_DESC);
2075 MODULE_AUTHOR("Yu Xu <yuxu@marvell.com>");
2076 MODULE_LICENSE("GPL");