drivers/usb/gadget/mv_udc_core.c

   1 /*
   2  * Copyright (C) 2011 Marvell International Ltd. All rights reserved.
   3  * Author: Chao Xie <chao.xie@marvell.com>
   4  *         Neil Zhang <zhangwm@marvell.com>
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/pci.h>
  14 #include <linux/dma-mapping.h>
  15 #include <linux/dmapool.h>
  16 #include <linux/kernel.h>
  17 #include <linux/delay.h>
  18 #include <linux/ioport.h>
  19 #include <linux/sched.h>
  20 #include <linux/slab.h>
  21 #include <linux/errno.h>
  22 #include <linux/init.h>
  23 #include <linux/timer.h>
  24 #include <linux/list.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/moduleparam.h>
  27 #include <linux/device.h>
  28 #include <linux/usb/ch9.h>
  29 #include <linux/usb/gadget.h>
  30 #include <linux/usb/otg.h>
  31 #include <linux/pm.h>
  32 #include <linux/io.h>
  33 #include <linux/irq.h>
  34 #include <linux/platform_device.h>
  35 #include <linux/clk.h>
  36 #include <linux/platform_data/mv_usb.h>
  37 #include <asm/system.h>
  38 #include <asm/unaligned.h>
  39
  40 #include "mv_udc.h"
  41
  42 #define DRIVER_DESC             "Marvell PXA USB Device Controller driver"
  43 #define DRIVER_VERSION          "8 Nov 2010"
  44
  45 #define ep_dir(ep)      (((ep)->ep_num == 0) ? \
  46                                 ((ep)->udc->ep0_dir) : ((ep)->direction))
  47
  48 /* timeout value -- usec */
  49 #define RESET_TIMEOUT           10000
  50 #define FLUSH_TIMEOUT           10000
  51 #define EPSTATUS_TIMEOUT        10000
  52 #define PRIME_TIMEOUT           10000
  53 #define READSAFE_TIMEOUT        1000
  54 #define DTD_TIMEOUT             1000
  55
  56 #define LOOPS_USEC_SHIFT        4
  57 #define LOOPS_USEC              (1 << LOOPS_USEC_SHIFT)
  58 #define LOOPS(timeout)          ((timeout) >> LOOPS_USEC_SHIFT)
  59
  60 static DECLARE_COMPLETION(release_done);
  61
  62 static const char driver_name[] = "mv_udc";
  63 static const char driver_desc[] = DRIVER_DESC;
  64
  65 /* controller device global variable */
  66 static struct mv_udc    *the_controller;
  67 int mv_usb_otgsc;
  68
  69 static void nuke(struct mv_ep *ep, int status);
  70 static void stop_activity(struct mv_udc *udc, struct usb_gadget_driver *driver);
  71
  72 /* for endpoint 0 operations */
  73 static const struct usb_endpoint_descriptor mv_ep0_desc = {
  74         .bLength =              USB_DT_ENDPOINT_SIZE,
  75         .bDescriptorType =      USB_DT_ENDPOINT,
  76         .bEndpointAddress =     0,
  77         .bmAttributes =         USB_ENDPOINT_XFER_CONTROL,
  78         .wMaxPacketSize =       EP0_MAX_PKT_SIZE,
  79 };
  80
  81 static void ep0_reset(struct mv_udc *udc)
  82 {
  83         struct mv_ep *ep;
  84         u32 epctrlx;
  85         int i = 0;
  86
  87         /* ep0 in and out */
  88         for (i = 0; i < 2; i++) {
  89                 ep = &udc->eps[i];
  90                 ep->udc = udc;
  91
  92                 /* ep0 dQH */
  93                 ep->dqh = &udc->ep_dqh[i];
  94
  95                 /* configure ep0 endpoint capabilities in dQH */
  96                 ep->dqh->max_packet_length =
  97                         (EP0_MAX_PKT_SIZE << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
  98                         | EP_QUEUE_HEAD_IOS;
  99
 100                 ep->dqh->next_dtd_ptr = EP_QUEUE_HEAD_NEXT_TERMINATE;
 101
 102                 epctrlx = readl(&udc->op_regs->epctrlx[0]);
 103                 if (i) {        /* TX */
 104                         epctrlx |= EPCTRL_TX_ENABLE
 105                                 | (USB_ENDPOINT_XFER_CONTROL
 106                                         << EPCTRL_TX_EP_TYPE_SHIFT);
 107
 108                 } else {        /* RX */
 109                         epctrlx |= EPCTRL_RX_ENABLE
 110                                 | (USB_ENDPOINT_XFER_CONTROL
 111                                         << EPCTRL_RX_EP_TYPE_SHIFT);
 112                 }
 113
 114                 writel(epctrlx, &udc->op_regs->epctrlx[0]);
 115         }
 116 }
 117
 118 /* protocol ep0 stall, will automatically be cleared on new transaction */
 119 static void ep0_stall(struct mv_udc *udc)
 120 {
 121         u32     epctrlx;
 122
 123         /* set TX and RX to stall */
 124         epctrlx = readl(&udc->op_regs->epctrlx[0]);
 125         epctrlx |= EPCTRL_RX_EP_STALL | EPCTRL_TX_EP_STALL;
 126         writel(epctrlx, &udc->op_regs->epctrlx[0]);
 127
 128         /* update ep0 state */
 129         udc->ep0_state = WAIT_FOR_SETUP;
 130         udc->ep0_dir = EP_DIR_OUT;
 131 }
 132
 133 static int process_ep_req(struct mv_udc *udc, int index,
 134         struct mv_req *curr_req)
 135 {
 136         struct mv_dtd   *curr_dtd;
 137         struct mv_dqh   *curr_dqh;
 138         int td_complete, actual, remaining_length;
 139         int i, direction;
 140         int retval = 0;
 141         u32 errors;
 142         u32 bit_pos;
 143
 144         curr_dqh = &udc->ep_dqh[index];
 145         direction = index % 2;
 146
 147         curr_dtd = curr_req->head;
 148         td_complete = 0;
 149         actual = curr_req->req.length;
 150
 151         for (i = 0; i < curr_req->dtd_count; i++) {
 152                 if (curr_dtd->size_ioc_sts & DTD_STATUS_ACTIVE) {
 153                         dev_dbg(&udc->dev->dev, "%s, dTD not completed\n",
 154                                 udc->eps[index].name);
 155                         return 1;
 156                 }
 157
 158                 errors = curr_dtd->size_ioc_sts & DTD_ERROR_MASK;
 159                 if (!errors) {
 160                         remaining_length =
 161                                 (curr_dtd->size_ioc_sts & DTD_PACKET_SIZE)
 162                                         >> DTD_LENGTH_BIT_POS;
 163                         actual -= remaining_length;
 164
 165                         if (remaining_length) {
 166                                 if (direction) {
 167                                         dev_dbg(&udc->dev->dev,
 168                                                 "TX dTD remains data\n");
 169                                         retval = -EPROTO;
 170                                         break;
 171                                 } else
 172                                         break;
 173                         }
 174                 } else {
 175                         dev_info(&udc->dev->dev,
 176                                 "complete_tr error: ep=%d %s: error = 0x%x\n",
 177                                 index >> 1, direction ? "SEND" : "RECV",
 178                                 errors);
 179                         if (errors & DTD_STATUS_HALTED) {
 180                                 /* Clear the errors and Halt condition */
 181                                 curr_dqh->size_ioc_int_sts &= ~errors;
 182                                 retval = -EPIPE;
 183                         } else if (errors & DTD_STATUS_DATA_BUFF_ERR) {
 184                                 retval = -EPROTO;
 185                         } else if (errors & DTD_STATUS_TRANSACTION_ERR) {
 186                                 retval = -EILSEQ;
 187                         }
 188                 }
 189                 if (i != curr_req->dtd_count - 1)
 190                         curr_dtd = (struct mv_dtd *)curr_dtd->next_dtd_virt;
 191         }
 192         if (retval)
 193                 return retval;
 194
 195         if (direction == EP_DIR_OUT)
 196                 bit_pos = 1 << curr_req->ep->ep_num;
 197         else
 198                 bit_pos = 1 << (16 + curr_req->ep->ep_num);
 199
 200         while ((curr_dqh->curr_dtd_ptr == curr_dtd->td_dma)) {
 201                 if (curr_dtd->dtd_next == EP_QUEUE_HEAD_NEXT_TERMINATE) {
 202                         while (readl(&udc->op_regs->epstatus) & bit_pos)
 203                                 udelay(1);
 204                         break;
 205                 }
 206                 udelay(1);
 207         }
 208
 209         curr_req->req.actual = actual;
 210
 211         return 0;
 212 }
 213
 214 /*
 215  * done() - retire a request; caller blocked irqs
 216  * @status : request status to be set, only works when
 217  * request is still in progress.
 218  */
 219 static void done(struct mv_ep *ep, struct mv_req *req, int status)
 220 {
 221         struct mv_udc *udc = NULL;
 222         unsigned char stopped = ep->stopped;
 223         struct mv_dtd *curr_td, *next_td;
 224         int j;
 225
 226         udc = (struct mv_udc *)ep->udc;
 227         /* Removed the req from fsl_ep->queue */
 228         list_del_init(&req->queue);
 229
 230         /* req.status should be set as -EINPROGRESS in ep_queue() */
 231         if (req->req.status == -EINPROGRESS)
 232                 req->req.status = status;
 233         else
 234                 status = req->req.status;
 235
 236         /* Free dtd for the request */
 237         next_td = req->head;
 238         for (j = 0; j < req->dtd_count; j++) {
 239                 curr_td = next_td;
 240                 if (j != req->dtd_count - 1)
 241                         next_td = curr_td->next_dtd_virt;
 242                 dma_pool_free(udc->dtd_pool, curr_td, curr_td->td_dma);
 243         }
 244
 245         if (req->mapped) {
 246                 dma_unmap_single(ep->udc->gadget.dev.parent,
 247                         req->req.dma, req->req.length,
 248                         ((ep_dir(ep) == EP_DIR_IN) ?
 249                                 DMA_TO_DEVICE : DMA_FROM_DEVICE));
 250                 req->req.dma = DMA_ADDR_INVALID;
 251                 req->mapped = 0;
 252         } else
 253                 dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
 254                         req->req.dma, req->req.length,
 255                         ((ep_dir(ep) == EP_DIR_IN) ?
 256                                 DMA_TO_DEVICE : DMA_FROM_DEVICE));
 257
 258         if (status && (status != -ESHUTDOWN))
 259                 dev_info(&udc->dev->dev, "complete %s req %p stat %d len %u/%u",
 260                         ep->ep.name, &req->req, status,
 261                         req->req.actual, req->req.length);
 262
 263         ep->stopped = 1;
 264
 265         spin_unlock(&ep->udc->lock);
 266         /*
 267          * complete() is from gadget layer,
 268          * eg fsg->bulk_in_complete()
 269          */
 270         if (req->req.complete)
 271                 req->req.complete(&ep->ep, &req->req);
 272
 273         spin_lock(&ep->udc->lock);
 274         ep->stopped = stopped;
 275 }
 276
 277 static int queue_dtd(struct mv_ep *ep, struct mv_req *req)
 278 {
 279         struct mv_udc *udc;
 280         struct mv_dqh *dqh;
 281         u32 bit_pos, direction;
 282         u32 usbcmd, epstatus;
 283         unsigned int loops;
 284         int retval = 0;
 285
 286         udc = ep->udc;
 287         direction = ep_dir(ep);
 288         dqh = &(udc->ep_dqh[ep->ep_num * 2 + direction]);
 289         bit_pos = 1 << (((direction == EP_DIR_OUT) ? 0 : 16) + ep->ep_num);
 290
 291         /* check if the pipe is empty */
 292         if (!(list_empty(&ep->queue))) {
 293                 struct mv_req *lastreq;
 294                 lastreq = list_entry(ep->queue.prev, struct mv_req, queue);
 295                 lastreq->tail->dtd_next =
 296                         req->head->td_dma & EP_QUEUE_HEAD_NEXT_POINTER_MASK;
 297
 298                 wmb();
 299
 300                 if (readl(&udc->op_regs->epprime) & bit_pos)
 301                         goto done;
 302
 303                 loops = LOOPS(READSAFE_TIMEOUT);
 304                 while (1) {
 305                         /* start with setting the semaphores */
 306                         usbcmd = readl(&udc->op_regs->usbcmd);
 307                         usbcmd |= USBCMD_ATDTW_TRIPWIRE_SET;
 308                         writel(usbcmd, &udc->op_regs->usbcmd);
 309
 310                         /* read the endpoint status */
 311                         epstatus = readl(&udc->op_regs->epstatus) & bit_pos;
 312
 313                         /*
 314                          * Reread the ATDTW semaphore bit to check if it is
 315                          * cleared. When hardware see a hazard, it will clear
 316                          * the bit or else we remain set to 1 and we can
 317                          * proceed with priming of endpoint if not already
 318                          * primed.
 319                          */
 320                         if (readl(&udc->op_regs->usbcmd)
 321                                 & USBCMD_ATDTW_TRIPWIRE_SET)
 322                                 break;
 323
 324                         loops--;
 325                         if (loops == 0) {
 326                                 dev_err(&udc->dev->dev,
 327                                         "Timeout for ATDTW_TRIPWIRE...\n");
 328                                 retval = -ETIME;
 329                                 goto done;
 330                         }
 331                         udelay(LOOPS_USEC);
 332                 }
 333
 334                 /* Clear the semaphore */
 335                 usbcmd = readl(&udc->op_regs->usbcmd);
 336                 usbcmd &= USBCMD_ATDTW_TRIPWIRE_CLEAR;
 337                 writel(usbcmd, &udc->op_regs->usbcmd);
 338
 339                 if (epstatus)
 340                         goto done;
 341         }
 342
 343         /* Write dQH next pointer and terminate bit to 0 */
 344         dqh->next_dtd_ptr = req->head->td_dma
 345                                 & EP_QUEUE_HEAD_NEXT_POINTER_MASK;
 346
 347         /* clear active and halt bit, in case set from a previous error */
 348         dqh->size_ioc_int_sts &= ~(DTD_STATUS_ACTIVE | DTD_STATUS_HALTED);
 349
 350         /* Ensure that updates to the QH will occure before priming. */
 351         wmb();
 352
 353         /* Prime the Endpoint */
 354         writel(bit_pos, &udc->op_regs->epprime);
 355
 356 done:
 357         return retval;
 358 }
 359
 360
 361 static struct mv_dtd *build_dtd(struct mv_req *req, unsigned *length,
 362                 dma_addr_t *dma, int *is_last)
 363 {
 364         u32 temp;
 365         struct mv_dtd *dtd;
 366         struct mv_udc *udc;
 367
 368         /* how big will this transfer be? */
 369         *length = min(req->req.length - req->req.actual,
 370                         (unsigned)EP_MAX_LENGTH_TRANSFER);
 371
 372         udc = req->ep->udc;
 373
 374         /*
 375          * Be careful that no _GFP_HIGHMEM is set,
 376          * or we can not use dma_to_virt
 377          */
 378         dtd = dma_pool_alloc(udc->dtd_pool, GFP_KERNEL, dma);
 379         if (dtd == NULL)
 380                 return dtd;
 381
 382         dtd->td_dma = *dma;
 383         /* initialize buffer page pointers */
 384         temp = (u32)(req->req.dma + req->req.actual);
 385         dtd->buff_ptr0 = cpu_to_le32(temp);
 386         temp &= ~0xFFF;
 387         dtd->buff_ptr1 = cpu_to_le32(temp + 0x1000);
 388         dtd->buff_ptr2 = cpu_to_le32(temp + 0x2000);
 389         dtd->buff_ptr3 = cpu_to_le32(temp + 0x3000);
 390         dtd->buff_ptr4 = cpu_to_le32(temp + 0x4000);
 391
 392         req->req.actual += *length;
 393
 394         /* zlp is needed if req->req.zero is set */
 395         if (req->req.zero) {
 396                 if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
 397                         *is_last = 1;
 398                 else
 399                         *is_last = 0;
 400         } else if (req->req.length == req->req.actual)
 401                 *is_last = 1;
 402         else
 403                 *is_last = 0;
 404
 405         /* Fill in the transfer size; set active bit */
 406         temp = ((*length << DTD_LENGTH_BIT_POS) | DTD_STATUS_ACTIVE);
 407
 408         /* Enable interrupt for the last dtd of a request */
 409         if (*is_last && !req->req.no_interrupt)
 410                 temp |= DTD_IOC;
 411
 412         dtd->size_ioc_sts = temp;
 413
 414         mb();
 415
 416         return dtd;
 417 }
 418
 419 /* generate dTD linked list for a request */
 420 static int req_to_dtd(struct mv_req *req)
 421 {
 422         unsigned count;
 423         int is_last, is_first = 1;
 424         struct mv_dtd *dtd, *last_dtd = NULL;
 425         struct mv_udc *udc;
 426         dma_addr_t dma;
 427
 428         udc = req->ep->udc;
 429
 430         do {
 431                 dtd = build_dtd(req, &count, &dma, &is_last);
 432                 if (dtd == NULL)
 433                         return -ENOMEM;
 434
 435                 if (is_first) {
 436                         is_first = 0;
 437                         req->head = dtd;
 438                 } else {
 439                         last_dtd->dtd_next = dma;
 440                         last_dtd->next_dtd_virt = dtd;
 441                 }
 442                 last_dtd = dtd;
 443                 req->dtd_count++;
 444         } while (!is_last);
 445
 446         /* set terminate bit to 1 for the last dTD */
 447         dtd->dtd_next = DTD_NEXT_TERMINATE;
 448
 449         req->tail = dtd;
 450
 451         return 0;
 452 }
 453
 454 static int mv_ep_enable(struct usb_ep *_ep,
 455                 const struct usb_endpoint_descriptor *desc)
 456 {
 457         struct mv_udc *udc;
 458         struct mv_ep *ep;
 459         struct mv_dqh *dqh;
 460         u16 max = 0;
 461         u32 bit_pos, epctrlx, direction;
 462         unsigned char zlt = 0, ios = 0, mult = 0;
 463         unsigned long flags;
 464
 465         ep = container_of(_ep, struct mv_ep, ep);
 466         udc = ep->udc;
 467
 468         if (!_ep || !desc || ep->desc
 469                         || desc->bDescriptorType != USB_DT_ENDPOINT)
 470                 return -EINVAL;
 471
 472         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
 473                 return -ESHUTDOWN;
 474
 475         direction = ep_dir(ep);
 476         max = usb_endpoint_maxp(desc);
 477
 478         /*
 479          * disable HW zero length termination select
 480          * driver handles zero length packet through req->req.zero
 481          */
 482         zlt = 1;
 483
 484         bit_pos = 1 << ((direction == EP_DIR_OUT ? 0 : 16) + ep->ep_num);
 485
 486         /* Check if the Endpoint is Primed */
 487         if ((readl(&udc->op_regs->epprime) & bit_pos)
 488                 || (readl(&udc->op_regs->epstatus) & bit_pos)) {
 489                 dev_info(&udc->dev->dev,
 490                         "ep=%d %s: Init ERROR: ENDPTPRIME=0x%x,"
 491                         " ENDPTSTATUS=0x%x, bit_pos=0x%x\n",
 492                         (unsigned)ep->ep_num, direction ? "SEND" : "RECV",
 493                         (unsigned)readl(&udc->op_regs->epprime),
 494                         (unsigned)readl(&udc->op_regs->epstatus),
 495                         (unsigned)bit_pos);
 496                 goto en_done;
 497         }
 498         /* Set the max packet length, interrupt on Setup and Mult fields */
 499         switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
 500         case USB_ENDPOINT_XFER_BULK:
 501                 zlt = 1;
 502                 mult = 0;
 503                 break;
 504         case USB_ENDPOINT_XFER_CONTROL:
 505                 ios = 1;
 506         case USB_ENDPOINT_XFER_INT:
 507                 mult = 0;
 508                 break;
 509         case USB_ENDPOINT_XFER_ISOC:
 510                 /* Calculate transactions needed for high bandwidth iso */
 511                 mult = (unsigned char)(1 + ((max >> 11) & 0x03));
 512                 max = max & 0x7ff;      /* bit 0~10 */
 513                 /* 3 transactions at most */
 514                 if (mult > 3)
 515                         goto en_done;
 516                 break;
 517         default:
 518                 goto en_done;
 519         }
 520
 521         spin_lock_irqsave(&udc->lock, flags);
 522         /* Get the endpoint queue head address */
 523         dqh = ep->dqh;
 524         dqh->max_packet_length = (max << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
 525                 | (mult << EP_QUEUE_HEAD_MULT_POS)
 526                 | (zlt ? EP_QUEUE_HEAD_ZLT_SEL : 0)
 527                 | (ios ? EP_QUEUE_HEAD_IOS : 0);
 528         dqh->next_dtd_ptr = 1;
 529         dqh->size_ioc_int_sts = 0;
 530
 531         ep->ep.maxpacket = max;
 532         ep->desc = desc;
 533         ep->stopped = 0;
 534
 535         /* Enable the endpoint for Rx or Tx and set the endpoint type */
 536         epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
 537         if (direction == EP_DIR_IN) {
 538                 epctrlx &= ~EPCTRL_TX_ALL_MASK;
 539                 epctrlx |= EPCTRL_TX_ENABLE | EPCTRL_TX_DATA_TOGGLE_RST
 540                         | ((desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK)
 541                                 << EPCTRL_TX_EP_TYPE_SHIFT);
 542         } else {
 543                 epctrlx &= ~EPCTRL_RX_ALL_MASK;
 544                 epctrlx |= EPCTRL_RX_ENABLE | EPCTRL_RX_DATA_TOGGLE_RST
 545                         | ((desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK)
 546                                 << EPCTRL_RX_EP_TYPE_SHIFT);
 547         }
 548         writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
 549
 550         /*
 551          * Implement Guideline (GL# USB-7) The unused endpoint type must
 552          * be programmed to bulk.
 553          */
 554         epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
 555         if ((epctrlx & EPCTRL_RX_ENABLE) == 0) {
 556                 epctrlx |= (USB_ENDPOINT_XFER_BULK
 557                                 << EPCTRL_RX_EP_TYPE_SHIFT);
 558                 writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
 559         }
 560
 561         epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
 562         if ((epctrlx & EPCTRL_TX_ENABLE) == 0) {
 563                 epctrlx |= (USB_ENDPOINT_XFER_BULK
 564                                 << EPCTRL_TX_EP_TYPE_SHIFT);
 565                 writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
 566         }
 567
 568         spin_unlock_irqrestore(&udc->lock, flags);
 569
 570         return 0;
 571 en_done:
 572         return -EINVAL;
 573 }
 574
 575 static int  mv_ep_disable(struct usb_ep *_ep)
 576 {
 577         struct mv_udc *udc;
 578         struct mv_ep *ep;
 579         struct mv_dqh *dqh;
 580         u32 bit_pos, epctrlx, direction;
 581         unsigned long flags;
 582
 583         ep = container_of(_ep, struct mv_ep, ep);
 584         if ((_ep == NULL) || !ep->desc)
 585                 return -EINVAL;
 586
 587         udc = ep->udc;
 588
 589         /* Get the endpoint queue head address */
 590         dqh = ep->dqh;
 591
 592         spin_lock_irqsave(&udc->lock, flags);
 593
 594         direction = ep_dir(ep);
 595         bit_pos = 1 << ((direction == EP_DIR_OUT ? 0 : 16) + ep->ep_num);
 596
 597         /* Reset the max packet length and the interrupt on Setup */
 598         dqh->max_packet_length = 0;
 599
 600         /* Disable the endpoint for Rx or Tx and reset the endpoint type */
 601         epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
 602         epctrlx &= ~((direction == EP_DIR_IN)
 603                         ? (EPCTRL_TX_ENABLE | EPCTRL_TX_TYPE)
 604                         : (EPCTRL_RX_ENABLE | EPCTRL_RX_TYPE));
 605         writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
 606
 607         /* nuke all pending requests (does flush) */
 608         nuke(ep, -ESHUTDOWN);
 609
 610         ep->desc = NULL;
 611         ep->stopped = 1;
 612
 613         spin_unlock_irqrestore(&udc->lock, flags);
 614
 615         return 0;
 616 }
 617
 618 static struct usb_request *
 619 mv_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
 620 {
 621         struct mv_req *req = NULL;
 622
 623         req = kzalloc(sizeof *req, gfp_flags);
 624         if (!req)
 625                 return NULL;
 626
 627         req->req.dma = DMA_ADDR_INVALID;
 628         INIT_LIST_HEAD(&req->queue);
 629
 630         return &req->req;
 631 }
 632
 633 static void mv_free_request(struct usb_ep *_ep, struct usb_request *_req)
 634 {
 635         struct mv_req *req = NULL;
 636
 637         req = container_of(_req, struct mv_req, req);
 638
 639         if (_req)
 640                 kfree(req);
 641 }
 642
 643 static void mv_ep_fifo_flush(struct usb_ep *_ep)
 644 {
 645         struct mv_udc *udc;
 646         u32 bit_pos, direction;
 647         struct mv_ep *ep;
 648         unsigned int loops;
 649
 650         if (!_ep)
 651                 return;
 652
 653         ep = container_of(_ep, struct mv_ep, ep);
 654         if (!ep->desc)
 655                 return;
 656
 657         udc = ep->udc;
 658         direction = ep_dir(ep);
 659
 660         if (ep->ep_num == 0)
 661                 bit_pos = (1 << 16) | 1;
 662         else if (direction == EP_DIR_OUT)
 663                 bit_pos = 1 << ep->ep_num;
 664         else
 665                 bit_pos = 1 << (16 + ep->ep_num);
 666
 667         loops = LOOPS(EPSTATUS_TIMEOUT);
 668         do {
 669                 unsigned int inter_loops;
 670
 671                 if (loops == 0) {
 672                         dev_err(&udc->dev->dev,
 673                                 "TIMEOUT for ENDPTSTATUS=0x%x, bit_pos=0x%x\n",
 674                                 (unsigned)readl(&udc->op_regs->epstatus),
 675                                 (unsigned)bit_pos);
 676                         return;
 677                 }
 678                 /* Write 1 to the Flush register */
 679                 writel(bit_pos, &udc->op_regs->epflush);
 680
 681                 /* Wait until flushing completed */
 682                 inter_loops = LOOPS(FLUSH_TIMEOUT);
 683                 while (readl(&udc->op_regs->epflush)) {
 684                         /*
 685                          * ENDPTFLUSH bit should be cleared to indicate this
 686                          * operation is complete
 687                          */
 688                         if (inter_loops == 0) {
 689                                 dev_err(&udc->dev->dev,
 690                                         "TIMEOUT for ENDPTFLUSH=0x%x,"
 691                                         "bit_pos=0x%x\n",
 692                                         (unsigned)readl(&udc->op_regs->epflush),
 693                                         (unsigned)bit_pos);
 694                                 return;
 695                         }
 696                         inter_loops--;
 697                         udelay(LOOPS_USEC);
 698                 }
 699                 loops--;
 700         } while (readl(&udc->op_regs->epstatus) & bit_pos);
 701 }
 702
 703 /* queues (submits) an I/O request to an endpoint */
 704 static int
 705 mv_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
 706 {
 707         struct mv_ep *ep = container_of(_ep, struct mv_ep, ep);
 708         struct mv_req *req = container_of(_req, struct mv_req, req);
 709         struct mv_udc *udc = ep->udc;
 710         unsigned long flags;
 711
 712         /* catch various bogus parameters */
 713         if (!_req || !req->req.complete || !req->req.buf
 714                         || !list_empty(&req->queue)) {
 715                 dev_err(&udc->dev->dev, "%s, bad params", __func__);
 716                 return -EINVAL;
 717         }
 718         if (unlikely(!_ep || !ep->desc)) {
 719                 dev_err(&udc->dev->dev, "%s, bad ep", __func__);
 720                 return -EINVAL;
 721         }
 722         if (ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
 723                 if (req->req.length > ep->ep.maxpacket)
 724                         return -EMSGSIZE;
 725         }
 726
 727         udc = ep->udc;
 728         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
 729                 return -ESHUTDOWN;
 730
 731         req->ep = ep;
 732
 733         /* map virtual address to hardware */
 734         if (req->req.dma == DMA_ADDR_INVALID) {
 735                 req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
 736                                         req->req.buf,
 737                                         req->req.length, ep_dir(ep)
 738                                                 ? DMA_TO_DEVICE
 739                                                 : DMA_FROM_DEVICE);
 740                 req->mapped = 1;
 741         } else {
 742                 dma_sync_single_for_device(ep->udc->gadget.dev.parent,
 743                                         req->req.dma, req->req.length,
 744                                         ep_dir(ep)
 745                                                 ? DMA_TO_DEVICE
 746                                                 : DMA_FROM_DEVICE);
 747                 req->mapped = 0;
 748         }
 749
 750         req->req.status = -EINPROGRESS;
 751         req->req.actual = 0;
 752         req->dtd_count = 0;
 753
 754         spin_lock_irqsave(&udc->lock, flags);
 755
 756         /* build dtds and push them to device queue */
 757         if (!req_to_dtd(req)) {
 758                 int retval;
 759                 retval = queue_dtd(ep, req);
 760                 if (retval) {
 761                         spin_unlock_irqrestore(&udc->lock, flags);
 762                         return retval;
 763                 }
 764         } else {
 765                 spin_unlock_irqrestore(&udc->lock, flags);
 766                 return -ENOMEM;
 767         }
 768
 769         /* Update ep0 state */
 770         if (ep->ep_num == 0)
 771                 udc->ep0_state = DATA_STATE_XMIT;
 772
 773         /* irq handler advances the queue */
 774         if (req != NULL)
 775                 list_add_tail(&req->queue, &ep->queue);
 776         spin_unlock_irqrestore(&udc->lock, flags);
 777
 778         return 0;
 779 }
 780
 781 /* dequeues (cancels, unlinks) an I/O request from an endpoint */
 782 static int mv_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
 783 {
 784         struct mv_ep *ep = container_of(_ep, struct mv_ep, ep);
 785         struct mv_req *req;
 786         struct mv_udc *udc = ep->udc;
 787         unsigned long flags;
 788         int stopped, ret = 0;
 789         u32 epctrlx;
 790
 791         if (!_ep || !_req)
 792                 return -EINVAL;
 793
 794         spin_lock_irqsave(&ep->udc->lock, flags);
 795         stopped = ep->stopped;
 796
 797         /* Stop the ep before we deal with the queue */
 798         ep->stopped = 1;
 799         epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
 800         if (ep_dir(ep) == EP_DIR_IN)
 801                 epctrlx &= ~EPCTRL_TX_ENABLE;
 802         else
 803                 epctrlx &= ~EPCTRL_RX_ENABLE;
 804         writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
 805
 806         /* make sure it's actually queued on this endpoint */
 807         list_for_each_entry(req, &ep->queue, queue) {
 808                 if (&req->req == _req)
 809                         break;
 810         }
 811         if (&req->req != _req) {
 812                 ret = -EINVAL;
 813                 goto out;
 814         }
 815
 816         /* The request is in progress, or completed but not dequeued */
 817         if (ep->queue.next == &req->queue) {
 818                 _req->status = -ECONNRESET;
 819                 mv_ep_fifo_flush(_ep);  /* flush current transfer */
 820
 821                 /* The request isn't the last request in this ep queue */
 822                 if (req->queue.next != &ep->queue) {
 823                         struct mv_dqh *qh;
 824                         struct mv_req *next_req;
 825
 826                         qh = ep->dqh;
 827                         next_req = list_entry(req->queue.next, struct mv_req,
 828                                         queue);
 829
 830                         /* Point the QH to the first TD of next request */
 831                         writel((u32) next_req->head, &qh->curr_dtd_ptr);
 832                 } else {
 833                         struct mv_dqh *qh;
 834
 835                         qh = ep->dqh;
 836                         qh->next_dtd_ptr = 1;
 837                         qh->size_ioc_int_sts = 0;
 838                 }
 839
 840                 /* The request hasn't been processed, patch up the TD chain */
 841         } else {
 842                 struct mv_req *prev_req;
 843
 844                 prev_req = list_entry(req->queue.prev, struct mv_req, queue);
 845                 writel(readl(&req->tail->dtd_next),
 846                                 &prev_req->tail->dtd_next);
 847
 848         }
 849
 850         done(ep, req, -ECONNRESET);
 851
 852         /* Enable EP */
 853 out:
 854         epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
 855         if (ep_dir(ep) == EP_DIR_IN)
 856                 epctrlx |= EPCTRL_TX_ENABLE;
 857         else
 858                 epctrlx |= EPCTRL_RX_ENABLE;
 859         writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
 860         ep->stopped = stopped;
 861
 862         spin_unlock_irqrestore(&ep->udc->lock, flags);
 863         return ret;
 864 }
 865
 866 static void ep_set_stall(struct mv_udc *udc, u8 ep_num, u8 direction, int stall)
 867 {
 868         u32 epctrlx;
 869
 870         epctrlx = readl(&udc->op_regs->epctrlx[ep_num]);
 871
 872         if (stall) {
 873                 if (direction == EP_DIR_IN)
 874                         epctrlx |= EPCTRL_TX_EP_STALL;
 875                 else
 876                         epctrlx |= EPCTRL_RX_EP_STALL;
 877         } else {
 878                 if (direction == EP_DIR_IN) {
 879                         epctrlx &= ~EPCTRL_TX_EP_STALL;
 880                         epctrlx |= EPCTRL_TX_DATA_TOGGLE_RST;
 881                 } else {
 882                         epctrlx &= ~EPCTRL_RX_EP_STALL;
 883                         epctrlx |= EPCTRL_RX_DATA_TOGGLE_RST;
 884                 }
 885         }
 886         writel(epctrlx, &udc->op_regs->epctrlx[ep_num]);
 887 }
 888
 889 static int ep_is_stall(struct mv_udc *udc, u8 ep_num, u8 direction)
 890 {
 891         u32 epctrlx;
 892
 893         epctrlx = readl(&udc->op_regs->epctrlx[ep_num]);
 894
 895         if (direction == EP_DIR_OUT)
 896                 return (epctrlx & EPCTRL_RX_EP_STALL) ? 1 : 0;
 897         else
 898                 return (epctrlx & EPCTRL_TX_EP_STALL) ? 1 : 0;
 899 }
 900
 901 static int mv_ep_set_halt_wedge(struct usb_ep *_ep, int halt, int wedge)
 902 {
 903         struct mv_ep *ep;
 904         unsigned long flags = 0;
 905         int status = 0;
 906         struct mv_udc *udc;
 907
 908         ep = container_of(_ep, struct mv_ep, ep);
 909         udc = ep->udc;
 910         if (!_ep || !ep->desc) {
 911                 status = -EINVAL;
 912                 goto out;
 913         }
 914
 915         if (ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
 916                 status = -EOPNOTSUPP;
 917                 goto out;
 918         }
 919
 920         /*
 921          * Attempt to halt IN ep will fail if any transfer requests
 922          * are still queue
 923          */
 924         if (halt && (ep_dir(ep) == EP_DIR_IN) && !list_empty(&ep->queue)) {
 925                 status = -EAGAIN;
 926                 goto out;
 927         }
 928
 929         spin_lock_irqsave(&ep->udc->lock, flags);
 930         ep_set_stall(udc, ep->ep_num, ep_dir(ep), halt);
 931         if (halt && wedge)
 932                 ep->wedge = 1;
 933         else if (!halt)
 934                 ep->wedge = 0;
 935         spin_unlock_irqrestore(&ep->udc->lock, flags);
 936
 937         if (ep->ep_num == 0) {
 938                 udc->ep0_state = WAIT_FOR_SETUP;
 939                 udc->ep0_dir = EP_DIR_OUT;
 940         }
 941 out:
 942         return status;
 943 }
 944
 945 static int mv_ep_set_halt(struct usb_ep *_ep, int halt)
 946 {
 947         return mv_ep_set_halt_wedge(_ep, halt, 0);
 948 }
 949
 950 static int mv_ep_set_wedge(struct usb_ep *_ep)
 951 {
 952         return mv_ep_set_halt_wedge(_ep, 1, 1);
 953 }
 954
 955 static struct usb_ep_ops mv_ep_ops = {
 956         .enable         = mv_ep_enable,
 957         .disable        = mv_ep_disable,
 958
 959         .alloc_request  = mv_alloc_request,
 960         .free_request   = mv_free_request,
 961
 962         .queue          = mv_ep_queue,
 963         .dequeue        = mv_ep_dequeue,
 964
 965         .set_wedge      = mv_ep_set_wedge,
 966         .set_halt       = mv_ep_set_halt,
 967         .fifo_flush     = mv_ep_fifo_flush,     /* flush fifo */
 968 };
 969
 970 static void udc_clock_enable(struct mv_udc *udc)
 971 {
 972         unsigned int i;
 973
 974         for (i = 0; i < udc->clknum; i++)
 975                 clk_enable(udc->clk[i]);
 976 }
 977
 978 static void udc_clock_disable(struct mv_udc *udc)
 979 {
 980         unsigned int i;
 981
 982         for (i = 0; i < udc->clknum; i++)
 983                 clk_disable(udc->clk[i]);
 984 }
 985
 986 static void udc_stop(struct mv_udc *udc)
 987 {
 988         u32 tmp;
 989
 990         /* Disable interrupts */
 991         tmp = readl(&udc->op_regs->usbintr);
 992         tmp &= ~(USBINTR_INT_EN | USBINTR_ERR_INT_EN |
 993                 USBINTR_PORT_CHANGE_DETECT_EN | USBINTR_RESET_EN);
 994         writel(tmp, &udc->op_regs->usbintr);
 995
 996         udc->stopped = 1;
 997
 998         /* Reset the Run the bit in the command register to stop VUSB */
 999         tmp = readl(&udc->op_regs->usbcmd);
1000         tmp &= ~USBCMD_RUN_STOP;
1001         writel(tmp, &udc->op_regs->usbcmd);
1002 }
1003
1004 static void udc_start(struct mv_udc *udc)
1005 {
1006         u32 usbintr;
1007
1008         usbintr = USBINTR_INT_EN | USBINTR_ERR_INT_EN
1009                 | USBINTR_PORT_CHANGE_DETECT_EN
1010                 | USBINTR_RESET_EN | USBINTR_DEVICE_SUSPEND;
1011         /* Enable interrupts */
1012         writel(usbintr, &udc->op_regs->usbintr);
1013
1014         udc->stopped = 0;
1015
1016         /* Set the Run bit in the command register */
1017         writel(USBCMD_RUN_STOP, &udc->op_regs->usbcmd);
1018 }
1019
1020 static int udc_reset(struct mv_udc *udc)
1021 {
1022         unsigned int loops;
1023         u32 tmp, portsc;
1024
1025         /* Stop the controller */
1026         tmp = readl(&udc->op_regs->usbcmd);
1027         tmp &= ~USBCMD_RUN_STOP;
1028         writel(tmp, &udc->op_regs->usbcmd);
1029
1030         /* Reset the controller to get default values */
1031         writel(USBCMD_CTRL_RESET, &udc->op_regs->usbcmd);
1032
1033         /* wait for reset to complete */
1034         loops = LOOPS(RESET_TIMEOUT);
1035         while (readl(&udc->op_regs->usbcmd) & USBCMD_CTRL_RESET) {
1036                 if (loops == 0) {
1037                         dev_err(&udc->dev->dev,
1038                                 "Wait for RESET completed TIMEOUT\n");
1039                         return -ETIMEDOUT;
1040                 }
1041                 loops--;
1042                 udelay(LOOPS_USEC);
1043         }
1044
1045         /* set controller to device mode */
1046         tmp = readl(&udc->op_regs->usbmode);
1047         tmp |= USBMODE_CTRL_MODE_DEVICE;
1048
1049         /* turn setup lockout off, require setup tripwire in usbcmd */
1050         tmp |= USBMODE_SETUP_LOCK_OFF | USBMODE_STREAM_DISABLE;
1051
1052         writel(tmp, &udc->op_regs->usbmode);
1053
1054         writel(0x0, &udc->op_regs->epsetupstat);
1055
1056         /* Configure the Endpoint List Address */
1057         writel(udc->ep_dqh_dma & USB_EP_LIST_ADDRESS_MASK,
1058                 &udc->op_regs->eplistaddr);
1059
1060         portsc = readl(&udc->op_regs->portsc[0]);
1061         if (readl(&udc->cap_regs->hcsparams) & HCSPARAMS_PPC)
1062                 portsc &= (~PORTSCX_W1C_BITS | ~PORTSCX_PORT_POWER);
1063
1064         if (udc->force_fs)
1065                 portsc |= PORTSCX_FORCE_FULL_SPEED_CONNECT;
1066         else
1067                 portsc &= (~PORTSCX_FORCE_FULL_SPEED_CONNECT);
1068
1069         writel(portsc, &udc->op_regs->portsc[0]);
1070
1071         tmp = readl(&udc->op_regs->epctrlx[0]);
1072         tmp &= ~(EPCTRL_TX_EP_STALL | EPCTRL_RX_EP_STALL);
1073         writel(tmp, &udc->op_regs->epctrlx[0]);
1074
1075         return 0;
1076 }
1077
1078 static int mv_udc_enable_internal(struct mv_udc *udc)
1079 {
1080         int retval;
1081
1082         if (udc->active)
1083                 return 0;
1084
1085         dev_dbg(&udc->dev->dev, "enable udc\n");
1086         udc_clock_enable(udc);
1087         if (udc->pdata->phy_init) {
1088                 retval = udc->pdata->phy_init(udc->phy_regs);
1089                 if (retval) {
1090                         dev_err(&udc->dev->dev,
1091                                 "init phy error %d\n", retval);
1092                         udc_clock_disable(udc);
1093                         return retval;
1094                 }
1095         }
1096         udc->active = 1;
1097
1098         return 0;
1099 }
1100
1101 static int mv_udc_enable(struct mv_udc *udc)
1102 {
1103         if (udc->clock_gating)
1104                 return mv_udc_enable_internal(udc);
1105
1106         return 0;
1107 }
1108
1109 static void mv_udc_disable_internal(struct mv_udc *udc)
1110 {
1111         if (udc->active) {
1112                 dev_dbg(&udc->dev->dev, "disable udc\n");
1113                 if (udc->pdata->phy_deinit)
1114                         udc->pdata->phy_deinit(udc->phy_regs);
1115                 udc_clock_disable(udc);
1116                 udc->active = 0;
1117         }
1118 }
1119
1120 static void mv_udc_disable(struct mv_udc *udc)
1121 {
1122         if (udc->clock_gating)
1123                 mv_udc_disable_internal(udc);
1124 }
1125
1126 static int mv_udc_get_frame(struct usb_gadget *gadget)
1127 {
1128         struct mv_udc *udc;
1129         u16     retval;
1130
1131         if (!gadget)
1132                 return -ENODEV;
1133
1134         udc = container_of(gadget, struct mv_udc, gadget);
1135
1136         retval = readl(&udc->op_regs->frindex) & USB_FRINDEX_MASKS;
1137
1138         return retval;
1139 }
1140
1141 /* Tries to wake up the host connected to this gadget */
1142 static int mv_udc_wakeup(struct usb_gadget *gadget)
1143 {
1144         struct mv_udc *udc = container_of(gadget, struct mv_udc, gadget);
1145         u32 portsc;
1146
1147         /* Remote wakeup feature not enabled by host */
1148         if (!udc->remote_wakeup)
1149                 return -ENOTSUPP;
1150
1151         portsc = readl(&udc->op_regs->portsc);
1152         /* not suspended? */
1153         if (!(portsc & PORTSCX_PORT_SUSPEND))
1154                 return 0;
1155         /* trigger force resume */
1156         portsc |= PORTSCX_PORT_FORCE_RESUME;
1157         writel(portsc, &udc->op_regs->portsc[0]);
1158         return 0;
1159 }
1160
1161 static int mv_udc_vbus_session(struct usb_gadget *gadget, int is_active)
1162 {
1163         struct mv_udc *udc;
1164         unsigned long flags;
1165         int retval = 0;
1166
1167         udc = container_of(gadget, struct mv_udc, gadget);
1168         spin_lock_irqsave(&udc->lock, flags);
1169
1170         udc->vbus_active = (is_active != 0);
1171
1172         dev_dbg(&udc->dev->dev, "%s: softconnect %d, vbus_active %d\n",
1173                 __func__, udc->softconnect, udc->vbus_active);
1174
1175         if (udc->driver && udc->softconnect && udc->vbus_active) {
1176                 retval = mv_udc_enable(udc);
1177                 if (retval == 0) {
1178                         /* Clock is disabled, need re-init registers */
1179                         udc_reset(udc);
1180                         ep0_reset(udc);
1181                         udc_start(udc);
1182                 }
1183         } else if (udc->driver && udc->softconnect) {
1184                 /* stop all the transfer in queue*/
1185                 stop_activity(udc, udc->driver);
1186                 udc_stop(udc);
1187                 mv_udc_disable(udc);
1188         }
1189
1190         spin_unlock_irqrestore(&udc->lock, flags);
1191         return retval;
1192 }
1193
1194 static int mv_udc_pullup(struct usb_gadget *gadget, int is_on)
1195 {
1196         struct mv_udc *udc;
1197         unsigned long flags;
1198         int retval = 0;
1199
1200         udc = container_of(gadget, struct mv_udc, gadget);
1201         spin_lock_irqsave(&udc->lock, flags);
1202
1203         udc->softconnect = (is_on != 0);
1204
1205         dev_dbg(&udc->dev->dev, "%s: softconnect %d, vbus_active %d\n",
1206                         __func__, udc->softconnect, udc->vbus_active);
1207
1208         if (udc->driver && udc->softconnect && udc->vbus_active) {
1209                 retval = mv_udc_enable(udc);
1210                 if (retval == 0) {
1211                         /* Clock is disabled, need re-init registers */
1212                         udc_reset(udc);
1213                         ep0_reset(udc);
1214                         udc_start(udc);
1215                 }
1216         } else if (udc->driver && udc->vbus_active) {
1217                 /* stop all the transfer in queue*/
1218                 stop_activity(udc, udc->driver);
1219                 udc_stop(udc);
1220                 mv_udc_disable(udc);
1221         }
1222
1223         spin_unlock_irqrestore(&udc->lock, flags);
1224         return retval;
1225 }
1226
1227 static int mv_udc_start(struct usb_gadget_driver *driver,
1228                 int (*bind)(struct usb_gadget *));
1229 static int mv_udc_stop(struct usb_gadget_driver *driver);
1230 /* device controller usb_gadget_ops structure */
1231 static const struct usb_gadget_ops mv_ops = {
1232
1233         /* returns the current frame number */
1234         .get_frame      = mv_udc_get_frame,
1235
1236         /* tries to wake up the host connected to this gadget */
1237         .wakeup         = mv_udc_wakeup,
1238
1239         /* notify controller that VBUS is powered or not */
1240         .vbus_session   = mv_udc_vbus_session,
1241
1242         /* D+ pullup, software-controlled connect/disconnect to USB host */
1243         .pullup         = mv_udc_pullup,
1244         .start          = mv_udc_start,
1245         .stop           = mv_udc_stop,
1246 };
1247
1248 static int eps_init(struct mv_udc *udc)
1249 {
1250         struct mv_ep    *ep;
1251         char name[14];
1252         int i;
1253
1254         /* initialize ep0 */
1255         ep = &udc->eps[0];
1256         ep->udc = udc;
1257         strncpy(ep->name, "ep0", sizeof(ep->name));
1258         ep->ep.name = ep->name;
1259         ep->ep.ops = &mv_ep_ops;
1260         ep->wedge = 0;
1261         ep->stopped = 0;
1262         ep->ep.maxpacket = EP0_MAX_PKT_SIZE;
1263         ep->ep_num = 0;
1264         ep->desc = &mv_ep0_desc;
1265         INIT_LIST_HEAD(&ep->queue);
1266
1267         ep->ep_type = USB_ENDPOINT_XFER_CONTROL;
1268
1269         /* initialize other endpoints */
1270         for (i = 2; i < udc->max_eps * 2; i++) {
1271                 ep = &udc->eps[i];
1272                 if (i % 2) {
1273                         snprintf(name, sizeof(name), "ep%din", i / 2);
1274                         ep->direction = EP_DIR_IN;
1275                 } else {
1276                         snprintf(name, sizeof(name), "ep%dout", i / 2);
1277                         ep->direction = EP_DIR_OUT;
1278                 }
1279                 ep->udc = udc;
1280                 strncpy(ep->name, name, sizeof(ep->name));
1281                 ep->ep.name = ep->name;
1282
1283                 ep->ep.ops = &mv_ep_ops;
1284                 ep->stopped = 0;
1285                 ep->ep.maxpacket = (unsigned short) ~0;
1286                 ep->ep_num = i / 2;
1287
1288                 INIT_LIST_HEAD(&ep->queue);
1289                 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
1290
1291                 ep->dqh = &udc->ep_dqh[i];
1292         }
1293
1294         return 0;
1295 }
1296
1297 /* delete all endpoint requests, called with spinlock held */
1298 static void nuke(struct mv_ep *ep, int status)
1299 {
1300         /* called with spinlock held */
1301         ep->stopped = 1;
1302
1303         /* endpoint fifo flush */
1304         mv_ep_fifo_flush(&ep->ep);
1305
1306         while (!list_empty(&ep->queue)) {
1307                 struct mv_req *req = NULL;
1308                 req = list_entry(ep->queue.next, struct mv_req, queue);
1309                 done(ep, req, status);
1310         }
1311 }
1312
1313 /* stop all USB activities */
1314 static void stop_activity(struct mv_udc *udc, struct usb_gadget_driver *driver)
1315 {
1316         struct mv_ep    *ep;
1317
1318         nuke(&udc->eps[0], -ESHUTDOWN);
1319
1320         list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
1321                 nuke(ep, -ESHUTDOWN);
1322         }
1323
1324         /* report disconnect; the driver is already quiesced */
1325         if (driver) {
1326                 spin_unlock(&udc->lock);
1327                 driver->disconnect(&udc->gadget);
1328                 spin_lock(&udc->lock);
1329         }
1330 }
1331
1332 static int mv_udc_start(struct usb_gadget_driver *driver,
1333                 int (*bind)(struct usb_gadget *))
1334 {
1335         struct mv_udc *udc = the_controller;
1336         int retval = 0;
1337         unsigned long flags;
1338
1339         if (!udc)
1340                 return -ENODEV;
1341
1342         if (udc->driver)
1343                 return -EBUSY;
1344
1345         spin_lock_irqsave(&udc->lock, flags);
1346
1347         /* hook up the driver ... */
1348         driver->driver.bus = NULL;
1349         udc->driver = driver;
1350         udc->gadget.dev.driver = &driver->driver;
1351
1352         udc->usb_state = USB_STATE_ATTACHED;
1353         udc->ep0_state = WAIT_FOR_SETUP;
1354         udc->ep0_dir = EP_DIR_OUT;
1355
1356         spin_unlock_irqrestore(&udc->lock, flags);
1357
1358         retval = bind(&udc->gadget);
1359         if (retval) {
1360                 dev_err(&udc->dev->dev, "bind to driver %s --> %d\n",
1361                                 driver->driver.name, retval);
1362                 udc->driver = NULL;
1363                 udc->gadget.dev.driver = NULL;
1364                 return retval;
1365         }
1366
1367         if (udc->transceiver) {
1368                 retval = otg_set_peripheral(udc->transceiver, &udc->gadget);
1369                 if (retval) {
1370                         dev_err(&udc->dev->dev,
1371                                 "unable to register peripheral to otg\n");
1372                         if (driver->unbind) {
1373                                 driver->unbind(&udc->gadget);
1374                                 udc->gadget.dev.driver = NULL;
1375                                 udc->driver = NULL;
1376                         }
1377                         return retval;
1378                 }
1379         }
1380
1381         /* pullup is always on */
1382         mv_udc_pullup(&udc->gadget, 1);
1383
1384         /* When boot with cable attached, there will be no vbus irq occurred */
1385         if (udc->qwork)
1386                 queue_work(udc->qwork, &udc->vbus_work);
1387
1388         return 0;
1389 }
1390
1391 static int mv_udc_stop(struct usb_gadget_driver *driver)
1392 {
1393         struct mv_udc *udc = the_controller;
1394         unsigned long flags;
1395
1396         if (!udc)
1397                 return -ENODEV;
1398
1399         spin_lock_irqsave(&udc->lock, flags);
1400
1401         mv_udc_enable(udc);
1402         udc_stop(udc);
1403
1404         /* stop all usb activities */
1405         udc->gadget.speed = USB_SPEED_UNKNOWN;
1406         stop_activity(udc, driver);
1407         mv_udc_disable(udc);
1408
1409         spin_unlock_irqrestore(&udc->lock, flags);
1410
1411         /* unbind gadget driver */
1412         driver->unbind(&udc->gadget);
1413         udc->gadget.dev.driver = NULL;
1414         udc->driver = NULL;
1415
1416         return 0;
1417 }
1418
1419 static void mv_set_ptc(struct mv_udc *udc, u32 mode)
1420 {
1421         u32 portsc;
1422
1423         portsc = readl(&udc->op_regs->portsc[0]);
1424         portsc |= mode << 16;
1425         writel(portsc, &udc->op_regs->portsc[0]);
1426 }
1427
1428 static void prime_status_complete(struct usb_ep *ep, struct usb_request *_req)
1429 {
1430         struct mv_udc *udc = the_controller;
1431         struct mv_req *req = container_of(_req, struct mv_req, req);
1432         unsigned long flags;
1433
1434         dev_info(&udc->dev->dev, "switch to test mode %d\n", req->test_mode);
1435
1436         spin_lock_irqsave(&udc->lock, flags);
1437         if (req->test_mode) {
1438                 mv_set_ptc(udc, req->test_mode);
1439                 req->test_mode = 0;
1440         }
1441         spin_unlock_irqrestore(&udc->lock, flags);
1442 }
1443
1444 static int
1445 udc_prime_status(struct mv_udc *udc, u8 direction, u16 status, bool empty)
1446 {
1447         int retval = 0;
1448         struct mv_req *req;
1449         struct mv_ep *ep;
1450
1451         ep = &udc->eps[0];
1452         udc->ep0_dir = direction;
1453         udc->ep0_state = WAIT_FOR_OUT_STATUS;
1454
1455         req = udc->status_req;
1456
1457         /* fill in the reqest structure */
1458         if (empty == false) {
1459                 *((u16 *) req->req.buf) = cpu_to_le16(status);
1460                 req->req.length = 2;
1461         } else
1462                 req->req.length = 0;
1463
1464         req->ep = ep;
1465         req->req.status = -EINPROGRESS;
1466         req->req.actual = 0;
1467         if (udc->test_mode) {
1468                 req->req.complete = prime_status_complete;
1469                 req->test_mode = udc->test_mode;
1470                 udc->test_mode = 0;
1471         } else
1472                 req->req.complete = NULL;
1473         req->dtd_count = 0;
1474
1475         if (req->req.dma == DMA_ADDR_INVALID) {
1476                 req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
1477                                 req->req.buf, req->req.length,
1478                                 ep_dir(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1479                 req->mapped = 1;
1480         }
1481
1482         /* prime the data phase */
1483         if (!req_to_dtd(req))
1484                 retval = queue_dtd(ep, req);
1485         else{   /* no mem */
1486                 retval = -ENOMEM;
1487                 goto out;
1488         }
1489
1490         if (retval) {
1491                 dev_err(&udc->dev->dev, "response error on GET_STATUS request\n");
1492                 goto out;
1493         }
1494
1495         list_add_tail(&req->queue, &ep->queue);
1496
1497         return 0;
1498 out:
1499         return retval;
1500 }
1501
1502 static void mv_udc_testmode(struct mv_udc *udc, u16 index)
1503 {
1504         if (index <= TEST_FORCE_EN) {
1505                 udc->test_mode = index;
1506                 if (udc_prime_status(udc, EP_DIR_IN, 0, true))
1507                         ep0_stall(udc);
1508         } else
1509                 dev_err(&udc->dev->dev,
1510                         "This test mode(%d) is not supported\n", index);
1511 }
1512
1513 static void ch9setaddress(struct mv_udc *udc, struct usb_ctrlrequest *setup)
1514 {
1515         udc->dev_addr = (u8)setup->wValue;
1516
1517         /* update usb state */
1518         udc->usb_state = USB_STATE_ADDRESS;
1519
1520         if (udc_prime_status(udc, EP_DIR_IN, 0, true))
1521                 ep0_stall(udc);
1522 }
1523
1524 static void ch9getstatus(struct mv_udc *udc, u8 ep_num,
1525         struct usb_ctrlrequest *setup)
1526 {
1527         u16 status = 0;
1528         int retval;
1529
1530         if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK))
1531                 != (USB_DIR_IN | USB_TYPE_STANDARD))
1532                 return;
1533
1534         if ((setup->bRequestType & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
1535                 status = 1 << USB_DEVICE_SELF_POWERED;
1536                 status |= udc->remote_wakeup << USB_DEVICE_REMOTE_WAKEUP;
1537         } else if ((setup->bRequestType & USB_RECIP_MASK)
1538                         == USB_RECIP_INTERFACE) {
1539                 /* get interface status */
1540                 status = 0;
1541         } else if ((setup->bRequestType & USB_RECIP_MASK)
1542                         == USB_RECIP_ENDPOINT) {
1543                 u8 ep_num, direction;
1544
1545                 ep_num = setup->wIndex & USB_ENDPOINT_NUMBER_MASK;
1546                 direction = (setup->wIndex & USB_ENDPOINT_DIR_MASK)
1547                                 ? EP_DIR_IN : EP_DIR_OUT;
1548                 status = ep_is_stall(udc, ep_num, direction)
1549                                 << USB_ENDPOINT_HALT;
1550         }
1551
1552         retval = udc_prime_status(udc, EP_DIR_IN, status, false);
1553         if (retval)
1554                 ep0_stall(udc);
1555         else
1556                 udc->ep0_state = DATA_STATE_XMIT;
1557 }
1558
1559 static void ch9clearfeature(struct mv_udc *udc, struct usb_ctrlrequest *setup)
1560 {
1561         u8 ep_num;
1562         u8 direction;
1563         struct mv_ep *ep;
1564
1565         if ((setup->bRequestType & (USB_TYPE_MASK | USB_RECIP_MASK))
1566                 == ((USB_TYPE_STANDARD | USB_RECIP_DEVICE))) {
1567                 switch (setup->wValue) {
1568                 case USB_DEVICE_REMOTE_WAKEUP:
1569                         udc->remote_wakeup = 0;
1570                         break;
1571                 default:
1572                         goto out;
1573                 }
1574         } else if ((setup->bRequestType & (USB_TYPE_MASK | USB_RECIP_MASK))
1575                 == ((USB_TYPE_STANDARD | USB_RECIP_ENDPOINT))) {
1576                 switch (setup->wValue) {
1577                 case USB_ENDPOINT_HALT:
1578                         ep_num = setup->wIndex & USB_ENDPOINT_NUMBER_MASK;
1579                         direction = (setup->wIndex & USB_ENDPOINT_DIR_MASK)
1580                                 ? EP_DIR_IN : EP_DIR_OUT;
1581                         if (setup->wValue != 0 || setup->wLength != 0
1582                                 || ep_num > udc->max_eps)
1583                                 goto out;
1584                         ep = &udc->eps[ep_num * 2 + direction];
1585                         if (ep->wedge == 1)
1586                                 break;
1587                         spin_unlock(&udc->lock);
1588                         ep_set_stall(udc, ep_num, direction, 0);
1589                         spin_lock(&udc->lock);
1590                         break;
1591                 default:
1592                         goto out;
1593                 }
1594         } else
1595                 goto out;
1596
1597         if (udc_prime_status(udc, EP_DIR_IN, 0, true))
1598                 ep0_stall(udc);
1599 out:
1600         return;
1601 }
1602
1603 static void ch9setfeature(struct mv_udc *udc, struct usb_ctrlrequest *setup)
1604 {
1605         u8 ep_num;
1606         u8 direction;
1607
1608         if ((setup->bRequestType & (USB_TYPE_MASK | USB_RECIP_MASK))
1609                 == ((USB_TYPE_STANDARD | USB_RECIP_DEVICE))) {
1610                 switch (setup->wValue) {
1611                 case USB_DEVICE_REMOTE_WAKEUP:
1612                         udc->remote_wakeup = 1;
1613                         break;
1614                 case USB_DEVICE_TEST_MODE:
1615                         if (setup->wIndex & 0xFF
1616                                 ||  udc->gadget.speed != USB_SPEED_HIGH)
1617                                 ep0_stall(udc);
1618
1619                         if (udc->usb_state != USB_STATE_CONFIGURED
1620                                 && udc->usb_state != USB_STATE_ADDRESS
1621                                 && udc->usb_state != USB_STATE_DEFAULT)
1622                                 ep0_stall(udc);
1623
1624                         mv_udc_testmode(udc, (setup->wIndex >> 8));
1625                         goto out;
1626                 default:
1627                         goto out;
1628                 }
1629         } else if ((setup->bRequestType & (USB_TYPE_MASK | USB_RECIP_MASK))
1630                 == ((USB_TYPE_STANDARD | USB_RECIP_ENDPOINT))) {
1631                 switch (setup->wValue) {
1632                 case USB_ENDPOINT_HALT:
1633                         ep_num = setup->wIndex & USB_ENDPOINT_NUMBER_MASK;
1634                         direction = (setup->wIndex & USB_ENDPOINT_DIR_MASK)
1635                                 ? EP_DIR_IN : EP_DIR_OUT;
1636                         if (setup->wValue != 0 || setup->wLength != 0
1637                                 || ep_num > udc->max_eps)
1638                                 goto out;
1639                         spin_unlock(&udc->lock);
1640                         ep_set_stall(udc, ep_num, direction, 1);
1641                         spin_lock(&udc->lock);
1642                         break;
1643                 default:
1644                         goto out;
1645                 }
1646         } else
1647                 goto out;
1648
1649         if (udc_prime_status(udc, EP_DIR_IN, 0, true))
1650                 ep0_stall(udc);
1651 out:
1652         return;
1653 }
1654
1655 static void handle_setup_packet(struct mv_udc *udc, u8 ep_num,
1656         struct usb_ctrlrequest *setup)
1657 {
1658         bool delegate = false;
1659
1660         nuke(&udc->eps[ep_num * 2 + EP_DIR_OUT], -ESHUTDOWN);
1661
1662         dev_dbg(&udc->dev->dev, "SETUP %02x.%02x v%04x i%04x l%04x\n",
1663                         setup->bRequestType, setup->bRequest,
1664                         setup->wValue, setup->wIndex, setup->wLength);
1665         /* We process some stardard setup requests here */
1666         if ((setup->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1667                 switch (setup->bRequest) {
1668                 case USB_REQ_GET_STATUS:
1669                         ch9getstatus(udc, ep_num, setup);
1670                         break;
1671
1672                 case USB_REQ_SET_ADDRESS:
1673                         ch9setaddress(udc, setup);
1674                         break;
1675
1676                 case USB_REQ_CLEAR_FEATURE:
1677                         ch9clearfeature(udc, setup);
1678                         break;
1679
1680                 case USB_REQ_SET_FEATURE:
1681                         ch9setfeature(udc, setup);
1682                         break;
1683
1684                 default:
1685                         delegate = true;
1686                 }
1687         } else
1688                 delegate = true;
1689
1690         /* delegate USB standard requests to the gadget driver */
1691         if (delegate == true) {
1692                 /* USB requests handled by gadget */
1693                 if (setup->wLength) {
1694                         /* DATA phase from gadget, STATUS phase from udc */
1695                         udc->ep0_dir = (setup->bRequestType & USB_DIR_IN)
1696                                         ?  EP_DIR_IN : EP_DIR_OUT;
1697                         spin_unlock(&udc->lock);
1698                         if (udc->driver->setup(&udc->gadget,
1699                                 &udc->local_setup_buff) < 0)
1700                                 ep0_stall(udc);
1701                         spin_lock(&udc->lock);
1702                         udc->ep0_state = (setup->bRequestType & USB_DIR_IN)
1703                                         ?  DATA_STATE_XMIT : DATA_STATE_RECV;
1704                 } else {
1705                         /* no DATA phase, IN STATUS phase from gadget */
1706                         udc->ep0_dir = EP_DIR_IN;
1707                         spin_unlock(&udc->lock);
1708                         if (udc->driver->setup(&udc->gadget,
1709                                 &udc->local_setup_buff) < 0)
1710                                 ep0_stall(udc);
1711                         spin_lock(&udc->lock);
1712                         udc->ep0_state = WAIT_FOR_OUT_STATUS;
1713                 }
1714         }
1715 }
1716
1717 /* complete DATA or STATUS phase of ep0 prime status phase if needed */
1718 static void ep0_req_complete(struct mv_udc *udc,
1719         struct mv_ep *ep0, struct mv_req *req)
1720 {
1721         u32 new_addr;
1722
1723         if (udc->usb_state == USB_STATE_ADDRESS) {
1724                 /* set the new address */
1725                 new_addr = (u32)udc->dev_addr;
1726                 writel(new_addr << USB_DEVICE_ADDRESS_BIT_SHIFT,
1727                         &udc->op_regs->deviceaddr);
1728         }
1729
1730         done(ep0, req, 0);
1731
1732         switch (udc->ep0_state) {
1733         case DATA_STATE_XMIT:
1734                 /* receive status phase */
1735                 if (udc_prime_status(udc, EP_DIR_OUT, 0, true))
1736                         ep0_stall(udc);
1737                 break;
1738         case DATA_STATE_RECV:
1739                 /* send status phase */
1740                 if (udc_prime_status(udc, EP_DIR_IN, 0 , true))
1741                         ep0_stall(udc);
1742                 break;
1743         case WAIT_FOR_OUT_STATUS:
1744                 udc->ep0_state = WAIT_FOR_SETUP;
1745                 break;
1746         case WAIT_FOR_SETUP:
1747                 dev_err(&udc->dev->dev, "unexpect ep0 packets\n");
1748                 break;
1749         default:
1750                 ep0_stall(udc);
1751                 break;
1752         }
1753 }
1754
1755 static void get_setup_data(struct mv_udc *udc, u8 ep_num, u8 *buffer_ptr)
1756 {
1757         u32 temp;
1758         struct mv_dqh *dqh;
1759
1760         dqh = &udc->ep_dqh[ep_num * 2 + EP_DIR_OUT];
1761
1762         /* Clear bit in ENDPTSETUPSTAT */
1763         writel((1 << ep_num), &udc->op_regs->epsetupstat);
1764
1765         /* while a hazard exists when setup package arrives */
1766         do {
1767                 /* Set Setup Tripwire */
1768                 temp = readl(&udc->op_regs->usbcmd);
1769                 writel(temp | USBCMD_SETUP_TRIPWIRE_SET, &udc->op_regs->usbcmd);
1770
1771                 /* Copy the setup packet to local buffer */
1772                 memcpy(buffer_ptr, (u8 *) dqh->setup_buffer, 8);
1773         } while (!(readl(&udc->op_regs->usbcmd) & USBCMD_SETUP_TRIPWIRE_SET));
1774
1775         /* Clear Setup Tripwire */
1776         temp = readl(&udc->op_regs->usbcmd);
1777         writel(temp & ~USBCMD_SETUP_TRIPWIRE_SET, &udc->op_regs->usbcmd);
1778 }
1779
1780 static void irq_process_tr_complete(struct mv_udc *udc)
1781 {
1782         u32 tmp, bit_pos;
1783         int i, ep_num = 0, direction = 0;
1784         struct mv_ep    *curr_ep;
1785         struct mv_req *curr_req, *temp_req;
1786         int status;
1787
1788         /*
1789          * We use separate loops for ENDPTSETUPSTAT and ENDPTCOMPLETE
1790          * because the setup packets are to be read ASAP
1791          */
1792
1793         /* Process all Setup packet received interrupts */
1794         tmp = readl(&udc->op_regs->epsetupstat);
1795
1796         if (tmp) {
1797                 for (i = 0; i < udc->max_eps; i++) {
1798                         if (tmp & (1 << i)) {
1799                                 get_setup_data(udc, i,
1800                                         (u8 *)(&udc->local_setup_buff));
1801                                 handle_setup_packet(udc, i,
1802                                         &udc->local_setup_buff);
1803                         }
1804                 }
1805         }
1806
1807         /* Don't clear the endpoint setup status register here.
1808          * It is cleared as a setup packet is read out of the buffer
1809          */
1810
1811         /* Process non-setup transaction complete interrupts */
1812         tmp = readl(&udc->op_regs->epcomplete);
1813
1814         if (!tmp)
1815                 return;
1816
1817         writel(tmp, &udc->op_regs->epcomplete);
1818
1819         for (i = 0; i < udc->max_eps * 2; i++) {
1820                 ep_num = i >> 1;
1821                 direction = i % 2;
1822
1823                 bit_pos = 1 << (ep_num + 16 * direction);
1824
1825                 if (!(bit_pos & tmp))
1826                         continue;
1827
1828                 if (i == 1)
1829                         curr_ep = &udc->eps[0];
1830                 else
1831                         curr_ep = &udc->eps[i];
1832                 /* process the req queue until an uncomplete request */
1833                 list_for_each_entry_safe(curr_req, temp_req,
1834                         &curr_ep->queue, queue) {
1835                         status = process_ep_req(udc, i, curr_req);
1836                         if (status)
1837                                 break;
1838
1839                         /* write back status to req */
1840                         curr_req->req.status = status;
1841
1842                         /* ep0 request completion */
1843                         if (ep_num == 0) {
1844                                 ep0_req_complete(udc, curr_ep, curr_req);
1845                                 break;
1846                         } else {
1847                                 done(curr_ep, curr_req, status);
1848                         }
1849                 }
1850         }
1851 }
1852
1853 void irq_process_reset(struct mv_udc *udc)
1854 {
1855         u32 tmp;
1856         unsigned int loops;
1857
1858         udc->ep0_dir = EP_DIR_OUT;
1859         udc->ep0_state = WAIT_FOR_SETUP;
1860         udc->remote_wakeup = 0;         /* default to 0 on reset */
1861
1862         /* The address bits are past bit 25-31. Set the address */
1863         tmp = readl(&udc->op_regs->deviceaddr);
1864         tmp &= ~(USB_DEVICE_ADDRESS_MASK);
1865         writel(tmp, &udc->op_regs->deviceaddr);
1866
1867         /* Clear all the setup token semaphores */
1868         tmp = readl(&udc->op_regs->epsetupstat);
1869         writel(tmp, &udc->op_regs->epsetupstat);
1870
1871         /* Clear all the endpoint complete status bits */
1872         tmp = readl(&udc->op_regs->epcomplete);
1873         writel(tmp, &udc->op_regs->epcomplete);
1874
1875         /* wait until all endptprime bits cleared */
1876         loops = LOOPS(PRIME_TIMEOUT);
1877         while (readl(&udc->op_regs->epprime) & 0xFFFFFFFF) {
1878                 if (loops == 0) {
1879                         dev_err(&udc->dev->dev,
1880                                 "Timeout for ENDPTPRIME = 0x%x\n",
1881                                 readl(&udc->op_regs->epprime));
1882                         break;
1883                 }
1884                 loops--;
1885                 udelay(LOOPS_USEC);
1886         }
1887
1888         /* Write 1s to the Flush register */
1889         writel((u32)~0, &udc->op_regs->epflush);
1890
1891         if (readl(&udc->op_regs->portsc[0]) & PORTSCX_PORT_RESET) {
1892                 dev_info(&udc->dev->dev, "usb bus reset\n");
1893                 udc->usb_state = USB_STATE_DEFAULT;
1894                 /* reset all the queues, stop all USB activities */
1895                 stop_activity(udc, udc->driver);
1896         } else {
1897                 dev_info(&udc->dev->dev, "USB reset portsc 0x%x\n",
1898                         readl(&udc->op_regs->portsc));
1899
1900                 /*
1901                  * re-initialize
1902                  * controller reset
1903                  */
1904                 udc_reset(udc);
1905
1906                 /* reset all the queues, stop all USB activities */
1907                 stop_activity(udc, udc->driver);
1908
1909                 /* reset ep0 dQH and endptctrl */
1910                 ep0_reset(udc);
1911
1912                 /* enable interrupt and set controller to run state */
1913                 udc_start(udc);
1914
1915                 udc->usb_state = USB_STATE_ATTACHED;
1916         }
1917 }
1918
1919 static void handle_bus_resume(struct mv_udc *udc)
1920 {
1921         udc->usb_state = udc->resume_state;
1922         udc->resume_state = 0;
1923
1924         /* report resume to the driver */
1925         if (udc->driver) {
1926                 if (udc->driver->resume) {
1927                         spin_unlock(&udc->lock);
1928                         udc->driver->resume(&udc->gadget);
1929                         spin_lock(&udc->lock);
1930                 }
1931         }
1932 }
1933
1934 static void irq_process_suspend(struct mv_udc *udc)
1935 {
1936         udc->resume_state = udc->usb_state;
1937         udc->usb_state = USB_STATE_SUSPENDED;
1938
1939         if (udc->driver->suspend) {
1940                 spin_unlock(&udc->lock);
1941                 udc->driver->suspend(&udc->gadget);
1942                 spin_lock(&udc->lock);
1943         }
1944 }
1945
1946 static void irq_process_port_change(struct mv_udc *udc)
1947 {
1948         u32 portsc;
1949
1950         portsc = readl(&udc->op_regs->portsc[0]);
1951         if (!(portsc & PORTSCX_PORT_RESET)) {
1952                 /* Get the speed */
1953                 u32 speed = portsc & PORTSCX_PORT_SPEED_MASK;
1954                 switch (speed) {
1955                 case PORTSCX_PORT_SPEED_HIGH:
1956                         udc->gadget.speed = USB_SPEED_HIGH;
1957                         break;
1958                 case PORTSCX_PORT_SPEED_FULL:
1959                         udc->gadget.speed = USB_SPEED_FULL;
1960                         break;
1961                 case PORTSCX_PORT_SPEED_LOW:
1962                         udc->gadget.speed = USB_SPEED_LOW;
1963                         break;
1964                 default:
1965                         udc->gadget.speed = USB_SPEED_UNKNOWN;
1966                         break;
1967                 }
1968         }
1969
1970         if (portsc & PORTSCX_PORT_SUSPEND) {
1971                 udc->resume_state = udc->usb_state;
1972                 udc->usb_state = USB_STATE_SUSPENDED;
1973                 if (udc->driver->suspend) {
1974                         spin_unlock(&udc->lock);
1975                         udc->driver->suspend(&udc->gadget);
1976                         spin_lock(&udc->lock);
1977                 }
1978         }
1979
1980         if (!(portsc & PORTSCX_PORT_SUSPEND)
1981                 && udc->usb_state == USB_STATE_SUSPENDED) {
1982                 handle_bus_resume(udc);
1983         }
1984
1985         if (!udc->resume_state)
1986                 udc->usb_state = USB_STATE_DEFAULT;
1987 }
1988
1989 static void irq_process_error(struct mv_udc *udc)
1990 {
1991         /* Increment the error count */
1992         udc->errors++;
1993 }
1994
1995 static irqreturn_t mv_udc_irq(int irq, void *dev)
1996 {
1997         struct mv_udc *udc = (struct mv_udc *)dev;
1998         u32 status, intr;
1999
2000         /* Disable ISR when stopped bit is set */
2001         if (udc->stopped)
2002                 return IRQ_NONE;
2003
2004         spin_lock(&udc->lock);
2005
2006         status = readl(&udc->op_regs->usbsts);
2007         intr = readl(&udc->op_regs->usbintr);
2008         status &= intr;
2009
2010         if (status == 0) {
2011                 spin_unlock(&udc->lock);
2012                 return IRQ_NONE;
2013         }
2014
2015         /* Clear all the interrupts occurred */
2016         writel(status, &udc->op_regs->usbsts);
2017
2018         if (status & USBSTS_ERR)
2019                 irq_process_error(udc);
2020
2021         if (status & USBSTS_RESET)
2022                 irq_process_reset(udc);
2023
2024         if (status & USBSTS_PORT_CHANGE)
2025                 irq_process_port_change(udc);
2026
2027         if (status & USBSTS_INT)
2028                 irq_process_tr_complete(udc);
2029
2030         if (status & USBSTS_SUSPEND)
2031                 irq_process_suspend(udc);
2032
2033         spin_unlock(&udc->lock);
2034
2035         return IRQ_HANDLED;
2036 }
2037
2038 static irqreturn_t mv_udc_vbus_irq(int irq, void *dev)
2039 {
2040         struct mv_udc *udc = (struct mv_udc *)dev;
2041
2042         /* polling VBUS and init phy may cause too much time*/
2043         if (udc->qwork)
2044                 queue_work(udc->qwork, &udc->vbus_work);
2045
2046         return IRQ_HANDLED;
2047 }
2048
2049 static void mv_udc_vbus_work(struct work_struct *work)
2050 {
2051         struct mv_udc *udc;
2052         unsigned int vbus;
2053
2054         udc = container_of(work, struct mv_udc, vbus_work);
2055         if (!udc->pdata->vbus)
2056                 return;
2057
2058         vbus = udc->pdata->vbus->poll();
2059         dev_info(&udc->dev->dev, "vbus is %d\n", vbus);
2060
2061         if (vbus == VBUS_HIGH)
2062                 mv_udc_vbus_session(&udc->gadget, 1);
2063         else if (vbus == VBUS_LOW)
2064                 mv_udc_vbus_session(&udc->gadget, 0);
2065 }
2066
2067 /* release device structure */
2068 static void gadget_release(struct device *_dev)
2069 {
2070         struct mv_udc *udc = the_controller;
2071
2072         complete(udc->done);
2073 }
2074
2075 static int __devexit mv_udc_remove(struct platform_device *dev)
2076 {
2077         struct mv_udc *udc = the_controller;
2078         int clk_i;
2079
2080         usb_del_gadget_udc(&udc->gadget);
2081
2082         if (udc->qwork) {
2083                 flush_workqueue(udc->qwork);
2084                 destroy_workqueue(udc->qwork);
2085         }
2086
2087         /*
2088          * If we have transceiver inited,
2089          * then vbus irq will not be requested in udc driver.
2090          */
2091         if (udc->pdata && udc->pdata->vbus
2092                 && udc->clock_gating && udc->transceiver == NULL)
2093                 free_irq(udc->pdata->vbus->irq, &dev->dev);
2094
2095         /* free memory allocated in probe */
2096         if (udc->dtd_pool)
2097                 dma_pool_destroy(udc->dtd_pool);
2098
2099         if (udc->ep_dqh)
2100                 dma_free_coherent(&dev->dev, udc->ep_dqh_size,
2101                         udc->ep_dqh, udc->ep_dqh_dma);
2102
2103         kfree(udc->eps);
2104
2105         if (udc->irq)
2106                 free_irq(udc->irq, &dev->dev);
2107
2108         mv_udc_disable(udc);
2109
2110         if (udc->cap_regs)
2111                 iounmap(udc->cap_regs);
2112         udc->cap_regs = NULL;
2113
2114         if (udc->phy_regs)
2115                 iounmap((void *)udc->phy_regs);
2116         udc->phy_regs = 0;
2117
2118         if (udc->status_req) {
2119                 kfree(udc->status_req->req.buf);
2120                 kfree(udc->status_req);
2121         }
2122
2123         for (clk_i = 0; clk_i <= udc->clknum; clk_i++)
2124                 clk_put(udc->clk[clk_i]);
2125
2126         device_unregister(&udc->gadget.dev);
2127
2128         /* free dev, wait for the release() finished */
2129         wait_for_completion(udc->done);
2130         kfree(udc);
2131
2132         the_controller = NULL;
2133
2134         return 0;
2135 }
2136
2137 static int __devinit mv_udc_probe(struct platform_device *dev)
2138 {
2139         struct mv_usb_platform_data *pdata = dev->dev.platform_data;
2140         struct mv_udc *udc;
2141         int retval = 0;
2142         int clk_i = 0;
2143         struct resource *r;
2144         size_t size;
2145
2146         if (pdata == NULL) {
2147                 dev_err(&dev->dev, "missing platform_data\n");
2148                 return -ENODEV;
2149         }
2150
2151         size = sizeof(*udc) + sizeof(struct clk *) * pdata->clknum;
2152         udc = kzalloc(size, GFP_KERNEL);
2153         if (udc == NULL) {
2154                 dev_err(&dev->dev, "failed to allocate memory for udc\n");
2155                 return -ENOMEM;
2156         }
2157
2158         the_controller = udc;
2159         udc->done = &release_done;
2160         udc->pdata = dev->dev.platform_data;
2161         spin_lock_init(&udc->lock);
2162
2163         udc->dev = dev;
2164
2165 #ifdef CONFIG_USB_OTG_UTILS
2166         if (pdata->mode == MV_USB_MODE_OTG)
2167                 udc->transceiver = otg_get_transceiver();
2168 #endif
2169
2170         udc->clknum = pdata->clknum;
2171         for (clk_i = 0; clk_i < udc->clknum; clk_i++) {
2172                 udc->clk[clk_i] = clk_get(&dev->dev, pdata->clkname[clk_i]);
2173                 if (IS_ERR(udc->clk[clk_i])) {
2174                         retval = PTR_ERR(udc->clk[clk_i]);
2175                         goto err_put_clk;
2176                 }
2177         }
2178
2179         r = platform_get_resource_byname(udc->dev, IORESOURCE_MEM, "capregs");
2180         if (r == NULL) {
2181                 dev_err(&dev->dev, "no I/O memory resource defined\n");
2182                 retval = -ENODEV;
2183                 goto err_put_clk;
2184         }
2185
2186         udc->cap_regs = (struct mv_cap_regs __iomem *)
2187                 ioremap(r->start, resource_size(r));
2188         if (udc->cap_regs == NULL) {
2189                 dev_err(&dev->dev, "failed to map I/O memory\n");
2190                 retval = -EBUSY;
2191                 goto err_put_clk;
2192         }
2193
2194         r = platform_get_resource_byname(udc->dev, IORESOURCE_MEM, "phyregs");
2195         if (r == NULL) {
2196                 dev_err(&dev->dev, "no phy I/O memory resource defined\n");
2197                 retval = -ENODEV;
2198                 goto err_iounmap_capreg;
2199         }
2200
2201         udc->phy_regs = (unsigned int)ioremap(r->start, resource_size(r));
2202         if (udc->phy_regs == 0) {
2203                 dev_err(&dev->dev, "failed to map phy I/O memory\n");
2204                 retval = -EBUSY;
2205                 goto err_iounmap_capreg;
2206         }
2207
2208         /* we will acces controller register, so enable the clk */
2209         retval = mv_udc_enable_internal(udc);
2210         if (retval)
2211                 goto err_iounmap_phyreg;
2212
2213         udc->op_regs = (struct mv_op_regs __iomem *)((u32)udc->cap_regs
2214                 + (readl(&udc->cap_regs->caplength_hciversion)
2215                         & CAPLENGTH_MASK));
2216         udc->max_eps = readl(&udc->cap_regs->dccparams) & DCCPARAMS_DEN_MASK;
2217
2218         /*
2219          * some platform will use usb to download image, it may not disconnect
2220          * usb gadget before loading kernel. So first stop udc here.
2221          */
2222         udc_stop(udc);
2223         writel(0xFFFFFFFF, &udc->op_regs->usbsts);
2224
2225         size = udc->max_eps * sizeof(struct mv_dqh) *2;
2226         size = (size + DQH_ALIGNMENT - 1) & ~(DQH_ALIGNMENT - 1);
2227         udc->ep_dqh = dma_alloc_coherent(&dev->dev, size,
2228                                         &udc->ep_dqh_dma, GFP_KERNEL);
2229
2230         if (udc->ep_dqh == NULL) {
2231                 dev_err(&dev->dev, "allocate dQH memory failed\n");
2232                 retval = -ENOMEM;
2233                 goto err_disable_clock;
2234         }
2235         udc->ep_dqh_size = size;
2236
2237         /* create dTD dma_pool resource */
2238         udc->dtd_pool = dma_pool_create("mv_dtd",
2239                         &dev->dev,
2240                         sizeof(struct mv_dtd),
2241                         DTD_ALIGNMENT,
2242                         DMA_BOUNDARY);
2243
2244         if (!udc->dtd_pool) {
2245                 retval = -ENOMEM;
2246                 goto err_free_dma;
2247         }
2248
2249         size = udc->max_eps * sizeof(struct mv_ep) *2;
2250         udc->eps = kzalloc(size, GFP_KERNEL);
2251         if (udc->eps == NULL) {
2252                 dev_err(&dev->dev, "allocate ep memory failed\n");
2253                 retval = -ENOMEM;
2254                 goto err_destroy_dma;
2255         }
2256
2257         /* initialize ep0 status request structure */
2258         udc->status_req = kzalloc(sizeof(struct mv_req), GFP_KERNEL);
2259         if (!udc->status_req) {
2260                 dev_err(&dev->dev, "allocate status_req memory failed\n");
2261                 retval = -ENOMEM;
2262                 goto err_free_eps;
2263         }
2264         INIT_LIST_HEAD(&udc->status_req->queue);
2265
2266         /* allocate a small amount of memory to get valid address */
2267         udc->status_req->req.buf = kzalloc(8, GFP_KERNEL);
2268         udc->status_req->req.dma = DMA_ADDR_INVALID;
2269
2270         udc->resume_state = USB_STATE_NOTATTACHED;
2271         udc->usb_state = USB_STATE_POWERED;
2272         udc->ep0_dir = EP_DIR_OUT;
2273         udc->remote_wakeup = 0;
2274
2275         r = platform_get_resource(udc->dev, IORESOURCE_IRQ, 0);
2276         if (r == NULL) {
2277                 dev_err(&dev->dev, "no IRQ resource defined\n");
2278                 retval = -ENODEV;
2279                 goto err_free_status_req;
2280         }
2281         udc->irq = r->start;
2282         if (request_irq(udc->irq, mv_udc_irq,
2283                 IRQF_SHARED, driver_name, udc)) {
2284                 dev_err(&dev->dev, "Request irq %d for UDC failed\n",
2285                         udc->irq);
2286                 retval = -ENODEV;
2287                 goto err_free_status_req;
2288         }
2289
2290         /* initialize gadget structure */
2291         udc->gadget.ops = &mv_ops;      /* usb_gadget_ops */
2292         udc->gadget.ep0 = &udc->eps[0].ep;      /* gadget ep0 */
2293         INIT_LIST_HEAD(&udc->gadget.ep_list);   /* ep_list */
2294         udc->gadget.speed = USB_SPEED_UNKNOWN;  /* speed */
2295         udc->gadget.max_speed = USB_SPEED_HIGH; /* support dual speed */
2296
2297         /* the "gadget" abstracts/virtualizes the controller */
2298         dev_set_name(&udc->gadget.dev, "gadget");
2299         udc->gadget.dev.parent = &dev->dev;
2300         udc->gadget.dev.dma_mask = dev->dev.dma_mask;
2301         udc->gadget.dev.release = gadget_release;
2302         udc->gadget.name = driver_name;         /* gadget name */
2303
2304         retval = device_register(&udc->gadget.dev);
2305         if (retval)
2306                 goto err_free_irq;
2307
2308         eps_init(udc);
2309
2310         /* VBUS detect: we can disable/enable clock on demand.*/
2311         if (udc->transceiver)
2312                 udc->clock_gating = 1;
2313         else if (pdata->vbus) {
2314                 udc->clock_gating = 1;
2315                 retval = request_threaded_irq(pdata->vbus->irq, NULL,
2316                                 mv_udc_vbus_irq, IRQF_ONESHOT, "vbus", udc);
2317                 if (retval) {
2318                         dev_info(&dev->dev,
2319                                 "Can not request irq for VBUS, "
2320                                 "disable clock gating\n");
2321                         udc->clock_gating = 0;
2322                 }
2323
2324                 udc->qwork = create_singlethread_workqueue("mv_udc_queue");
2325                 if (!udc->qwork) {
2326                         dev_err(&dev->dev, "cannot create workqueue\n");
2327                         retval = -ENOMEM;
2328                         goto err_unregister;
2329                 }
2330
2331                 INIT_WORK(&udc->vbus_work, mv_udc_vbus_work);
2332         }
2333
2334         /*
2335          * When clock gating is supported, we can disable clk and phy.
2336          * If not, it means that VBUS detection is not supported, we
2337          * have to enable vbus active all the time to let controller work.
2338          */
2339         if (udc->clock_gating)
2340                 mv_udc_disable_internal(udc);
2341         else
2342                 udc->vbus_active = 1;
2343
2344         retval = usb_add_gadget_udc(&dev->dev, &udc->gadget);
2345         if (retval)
2346                 goto err_unregister;
2347
2348         dev_info(&dev->dev, "successful probe UDC device %s clock gating.\n",
2349                 udc->clock_gating ? "with" : "without");
2350
2351         return 0;
2352
2353 err_unregister:
2354         if (udc->pdata && udc->pdata->vbus
2355                 && udc->clock_gating && udc->transceiver == NULL)
2356                 free_irq(pdata->vbus->irq, &dev->dev);
2357         device_unregister(&udc->gadget.dev);
2358 err_free_irq:
2359         free_irq(udc->irq, &dev->dev);
2360 err_free_status_req:
2361         kfree(udc->status_req->req.buf);
2362         kfree(udc->status_req);
2363 err_free_eps:
2364         kfree(udc->eps);
2365 err_destroy_dma:
2366         dma_pool_destroy(udc->dtd_pool);
2367 err_free_dma:
2368         dma_free_coherent(&dev->dev, udc->ep_dqh_size,
2369                         udc->ep_dqh, udc->ep_dqh_dma);
2370 err_disable_clock:
2371         mv_udc_disable_internal(udc);
2372 err_iounmap_phyreg:
2373         iounmap((void *)udc->phy_regs);
2374 err_iounmap_capreg:
2375         iounmap(udc->cap_regs);
2376 err_put_clk:
2377         for (clk_i--; clk_i >= 0; clk_i--)
2378                 clk_put(udc->clk[clk_i]);
2379         the_controller = NULL;
2380         kfree(udc);
2381         return retval;
2382 }
2383
2384 #ifdef CONFIG_PM
2385 static int mv_udc_suspend(struct device *_dev)
2386 {
2387         struct mv_udc *udc = the_controller;
2388
2389         /* if OTG is enabled, the following will be done in OTG driver*/
2390         if (udc->transceiver)
2391                 return 0;
2392
2393         if (udc->pdata->vbus && udc->pdata->vbus->poll)
2394                 if (udc->pdata->vbus->poll() == VBUS_HIGH) {
2395                         dev_info(&udc->dev->dev, "USB cable is connected!\n");
2396                         return -EAGAIN;
2397                 }
2398
2399         /*
2400          * only cable is unplugged, udc can suspend.
2401          * So do not care about clock_gating == 1.
2402          */
2403         if (!udc->clock_gating) {
2404                 udc_stop(udc);
2405
2406                 spin_lock_irq(&udc->lock);
2407                 /* stop all usb activities */
2408                 stop_activity(udc, udc->driver);
2409                 spin_unlock_irq(&udc->lock);
2410
2411                 mv_udc_disable_internal(udc);
2412         }
2413
2414         return 0;
2415 }
2416
2417 static int mv_udc_resume(struct device *_dev)
2418 {
2419         struct mv_udc *udc = the_controller;
2420         int retval;
2421
2422         /* if OTG is enabled, the following will be done in OTG driver*/
2423         if (udc->transceiver)
2424                 return 0;
2425
2426         if (!udc->clock_gating) {
2427                 retval = mv_udc_enable_internal(udc);
2428                 if (retval)
2429                         return retval;
2430
2431                 if (udc->driver && udc->softconnect) {
2432                         udc_reset(udc);
2433                         ep0_reset(udc);
2434                         udc_start(udc);
2435                 }
2436         }
2437
2438         return 0;
2439 }
2440
2441 static const struct dev_pm_ops mv_udc_pm_ops = {
2442         .suspend        = mv_udc_suspend,
2443         .resume         = mv_udc_resume,
2444 };
2445 #endif
2446
2447 static void mv_udc_shutdown(struct platform_device *dev)
2448 {
2449         struct mv_udc *udc = the_controller;
2450         u32 mode;
2451
2452         /* reset controller mode to IDLE */
2453         mode = readl(&udc->op_regs->usbmode);
2454         mode &= ~3;
2455         writel(mode, &udc->op_regs->usbmode);
2456 }
2457
2458 static struct platform_driver udc_driver = {
2459         .probe          = mv_udc_probe,
2460         .remove         = __exit_p(mv_udc_remove),
2461         .shutdown       = mv_udc_shutdown,
2462         .driver         = {
2463                 .owner  = THIS_MODULE,
2464                 .name   = "pxa-u2o",
2465 #ifdef CONFIG_PM
2466                 .pm     = &mv_udc_pm_ops,
2467 #endif
2468         },
2469 };
2470 MODULE_ALIAS("platform:pxa-u2o");
2471
2472 MODULE_DESCRIPTION(DRIVER_DESC);
2473 MODULE_AUTHOR("Chao Xie <chao.xie@marvell.com>");
2474 MODULE_VERSION(DRIVER_VERSION);
2475 MODULE_LICENSE("GPL");
2476
2477
2478 static int __init init(void)
2479 {
2480         return platform_driver_register(&udc_driver);
2481 }
2482 module_init(init);
2483
2484
2485 static void __exit cleanup(void)
2486 {
2487         platform_driver_unregister(&udc_driver);
2488 }
2489 module_exit(cleanup);
2490