2 * Copyright (C) 2011 Marvell International Ltd. All rights reserved.
3 * Author: Chao Xie <chao.xie@marvell.com>
4 * Neil Zhang <zhangwm@marvell.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
12 #include <linux/module.h>
13 #include <linux/pci.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/dmapool.h>
16 #include <linux/kernel.h>
17 #include <linux/delay.h>
18 #include <linux/ioport.h>
19 #include <linux/sched.h>
20 #include <linux/slab.h>
21 #include <linux/errno.h>
22 #include <linux/err.h>
23 #include <linux/init.h>
24 #include <linux/timer.h>
25 #include <linux/list.h>
26 #include <linux/interrupt.h>
27 #include <linux/moduleparam.h>
28 #include <linux/device.h>
29 #include <linux/usb/ch9.h>
30 #include <linux/usb/gadget.h>
31 #include <linux/usb/otg.h>
34 #include <linux/irq.h>
35 #include <linux/platform_device.h>
36 #include <linux/clk.h>
37 #include <linux/platform_data/mv_usb.h>
38 #include <asm/unaligned.h>
42 #define DRIVER_DESC "Marvell PXA USB Device Controller driver"
43 #define DRIVER_VERSION "8 Nov 2010"
45 #define ep_dir(ep) (((ep)->ep_num == 0) ? \
46 ((ep)->udc->ep0_dir) : ((ep)->direction))
48 /* timeout value -- usec */
49 #define RESET_TIMEOUT 10000
50 #define FLUSH_TIMEOUT 10000
51 #define EPSTATUS_TIMEOUT 10000
52 #define PRIME_TIMEOUT 10000
53 #define READSAFE_TIMEOUT 1000
55 #define LOOPS_USEC_SHIFT 1
56 #define LOOPS_USEC (1 << LOOPS_USEC_SHIFT)
57 #define LOOPS(timeout) ((timeout) >> LOOPS_USEC_SHIFT)
59 static DECLARE_COMPLETION(release_done);
61 static const char driver_name[] = "mv_udc";
62 static const char driver_desc[] = DRIVER_DESC;
64 static void nuke(struct mv_ep *ep, int status);
65 static void stop_activity(struct mv_udc *udc, struct usb_gadget_driver *driver);
67 /* for endpoint 0 operations */
68 static const struct usb_endpoint_descriptor mv_ep0_desc = {
69 .bLength = USB_DT_ENDPOINT_SIZE,
70 .bDescriptorType = USB_DT_ENDPOINT,
71 .bEndpointAddress = 0,
72 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
73 .wMaxPacketSize = EP0_MAX_PKT_SIZE,
76 static void ep0_reset(struct mv_udc *udc)
83 for (i = 0; i < 2; i++) {
88 ep->dqh = &udc->ep_dqh[i];
90 /* configure ep0 endpoint capabilities in dQH */
91 ep->dqh->max_packet_length =
92 (EP0_MAX_PKT_SIZE << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
95 ep->dqh->next_dtd_ptr = EP_QUEUE_HEAD_NEXT_TERMINATE;
97 epctrlx = readl(&udc->op_regs->epctrlx[0]);
99 epctrlx |= EPCTRL_TX_ENABLE
100 | (USB_ENDPOINT_XFER_CONTROL
101 << EPCTRL_TX_EP_TYPE_SHIFT);
104 epctrlx |= EPCTRL_RX_ENABLE
105 | (USB_ENDPOINT_XFER_CONTROL
106 << EPCTRL_RX_EP_TYPE_SHIFT);
109 writel(epctrlx, &udc->op_regs->epctrlx[0]);
113 /* protocol ep0 stall, will automatically be cleared on new transaction */
114 static void ep0_stall(struct mv_udc *udc)
118 /* set TX and RX to stall */
119 epctrlx = readl(&udc->op_regs->epctrlx[0]);
120 epctrlx |= EPCTRL_RX_EP_STALL | EPCTRL_TX_EP_STALL;
121 writel(epctrlx, &udc->op_regs->epctrlx[0]);
123 /* update ep0 state */
124 udc->ep0_state = WAIT_FOR_SETUP;
125 udc->ep0_dir = EP_DIR_OUT;
128 static int process_ep_req(struct mv_udc *udc, int index,
129 struct mv_req *curr_req)
131 struct mv_dtd *curr_dtd;
132 struct mv_dqh *curr_dqh;
133 int td_complete, actual, remaining_length;
139 curr_dqh = &udc->ep_dqh[index];
140 direction = index % 2;
142 curr_dtd = curr_req->head;
144 actual = curr_req->req.length;
146 for (i = 0; i < curr_req->dtd_count; i++) {
147 if (curr_dtd->size_ioc_sts & DTD_STATUS_ACTIVE) {
148 dev_dbg(&udc->dev->dev, "%s, dTD not completed\n",
149 udc->eps[index].name);
153 errors = curr_dtd->size_ioc_sts & DTD_ERROR_MASK;
156 (curr_dtd->size_ioc_sts & DTD_PACKET_SIZE)
157 >> DTD_LENGTH_BIT_POS;
158 actual -= remaining_length;
160 if (remaining_length) {
162 dev_dbg(&udc->dev->dev,
163 "TX dTD remains data\n");
170 dev_info(&udc->dev->dev,
171 "complete_tr error: ep=%d %s: error = 0x%x\n",
172 index >> 1, direction ? "SEND" : "RECV",
174 if (errors & DTD_STATUS_HALTED) {
175 /* Clear the errors and Halt condition */
176 curr_dqh->size_ioc_int_sts &= ~errors;
178 } else if (errors & DTD_STATUS_DATA_BUFF_ERR) {
180 } else if (errors & DTD_STATUS_TRANSACTION_ERR) {
184 if (i != curr_req->dtd_count - 1)
185 curr_dtd = (struct mv_dtd *)curr_dtd->next_dtd_virt;
190 if (direction == EP_DIR_OUT)
191 bit_pos = 1 << curr_req->ep->ep_num;
193 bit_pos = 1 << (16 + curr_req->ep->ep_num);
195 while ((curr_dqh->curr_dtd_ptr == curr_dtd->td_dma)) {
196 if (curr_dtd->dtd_next == EP_QUEUE_HEAD_NEXT_TERMINATE) {
197 while (readl(&udc->op_regs->epstatus) & bit_pos)
204 curr_req->req.actual = actual;
210 * done() - retire a request; caller blocked irqs
211 * @status : request status to be set, only works when
212 * request is still in progress.
214 static void done(struct mv_ep *ep, struct mv_req *req, int status)
216 struct mv_udc *udc = NULL;
217 unsigned char stopped = ep->stopped;
218 struct mv_dtd *curr_td, *next_td;
221 udc = (struct mv_udc *)ep->udc;
222 /* Removed the req from fsl_ep->queue */
223 list_del_init(&req->queue);
225 /* req.status should be set as -EINPROGRESS in ep_queue() */
226 if (req->req.status == -EINPROGRESS)
227 req->req.status = status;
229 status = req->req.status;
231 /* Free dtd for the request */
233 for (j = 0; j < req->dtd_count; j++) {
235 if (j != req->dtd_count - 1)
236 next_td = curr_td->next_dtd_virt;
237 dma_pool_free(udc->dtd_pool, curr_td, curr_td->td_dma);
241 dma_unmap_single(ep->udc->gadget.dev.parent,
242 req->req.dma, req->req.length,
243 ((ep_dir(ep) == EP_DIR_IN) ?
244 DMA_TO_DEVICE : DMA_FROM_DEVICE));
245 req->req.dma = DMA_ADDR_INVALID;
248 dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
249 req->req.dma, req->req.length,
250 ((ep_dir(ep) == EP_DIR_IN) ?
251 DMA_TO_DEVICE : DMA_FROM_DEVICE));
253 if (status && (status != -ESHUTDOWN))
254 dev_info(&udc->dev->dev, "complete %s req %p stat %d len %u/%u",
255 ep->ep.name, &req->req, status,
256 req->req.actual, req->req.length);
260 spin_unlock(&ep->udc->lock);
262 * complete() is from gadget layer,
263 * eg fsg->bulk_in_complete()
265 if (req->req.complete)
266 req->req.complete(&ep->ep, &req->req);
268 spin_lock(&ep->udc->lock);
269 ep->stopped = stopped;
272 static int queue_dtd(struct mv_ep *ep, struct mv_req *req)
276 u32 bit_pos, direction;
277 u32 usbcmd, epstatus;
282 direction = ep_dir(ep);
283 dqh = &(udc->ep_dqh[ep->ep_num * 2 + direction]);
284 bit_pos = 1 << (((direction == EP_DIR_OUT) ? 0 : 16) + ep->ep_num);
286 /* check if the pipe is empty */
287 if (!(list_empty(&ep->queue))) {
288 struct mv_req *lastreq;
289 lastreq = list_entry(ep->queue.prev, struct mv_req, queue);
290 lastreq->tail->dtd_next =
291 req->head->td_dma & EP_QUEUE_HEAD_NEXT_POINTER_MASK;
295 if (readl(&udc->op_regs->epprime) & bit_pos)
298 loops = LOOPS(READSAFE_TIMEOUT);
300 /* start with setting the semaphores */
301 usbcmd = readl(&udc->op_regs->usbcmd);
302 usbcmd |= USBCMD_ATDTW_TRIPWIRE_SET;
303 writel(usbcmd, &udc->op_regs->usbcmd);
305 /* read the endpoint status */
306 epstatus = readl(&udc->op_regs->epstatus) & bit_pos;
309 * Reread the ATDTW semaphore bit to check if it is
310 * cleared. When hardware see a hazard, it will clear
311 * the bit or else we remain set to 1 and we can
312 * proceed with priming of endpoint if not already
315 if (readl(&udc->op_regs->usbcmd)
316 & USBCMD_ATDTW_TRIPWIRE_SET)
321 dev_err(&udc->dev->dev,
322 "Timeout for ATDTW_TRIPWIRE...\n");
329 /* Clear the semaphore */
330 usbcmd = readl(&udc->op_regs->usbcmd);
331 usbcmd &= USBCMD_ATDTW_TRIPWIRE_CLEAR;
332 writel(usbcmd, &udc->op_regs->usbcmd);
338 /* Write dQH next pointer and terminate bit to 0 */
339 dqh->next_dtd_ptr = req->head->td_dma
340 & EP_QUEUE_HEAD_NEXT_POINTER_MASK;
342 /* clear active and halt bit, in case set from a previous error */
343 dqh->size_ioc_int_sts &= ~(DTD_STATUS_ACTIVE | DTD_STATUS_HALTED);
345 /* Ensure that updates to the QH will occure before priming. */
348 /* Prime the Endpoint */
349 writel(bit_pos, &udc->op_regs->epprime);
355 static struct mv_dtd *build_dtd(struct mv_req *req, unsigned *length,
356 dma_addr_t *dma, int *is_last)
363 /* how big will this transfer be? */
364 if (usb_endpoint_xfer_isoc(req->ep->ep.desc)) {
366 mult = (dqh->max_packet_length >> EP_QUEUE_HEAD_MULT_POS)
368 *length = min(req->req.length - req->req.actual,
369 (unsigned)(mult * req->ep->ep.maxpacket));
371 *length = min(req->req.length - req->req.actual,
372 (unsigned)EP_MAX_LENGTH_TRANSFER);
377 * Be careful that no _GFP_HIGHMEM is set,
378 * or we can not use dma_to_virt
380 dtd = dma_pool_alloc(udc->dtd_pool, GFP_ATOMIC, dma);
385 /* initialize buffer page pointers */
386 temp = (u32)(req->req.dma + req->req.actual);
387 dtd->buff_ptr0 = cpu_to_le32(temp);
389 dtd->buff_ptr1 = cpu_to_le32(temp + 0x1000);
390 dtd->buff_ptr2 = cpu_to_le32(temp + 0x2000);
391 dtd->buff_ptr3 = cpu_to_le32(temp + 0x3000);
392 dtd->buff_ptr4 = cpu_to_le32(temp + 0x4000);
394 req->req.actual += *length;
396 /* zlp is needed if req->req.zero is set */
398 if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
402 } else if (req->req.length == req->req.actual)
407 /* Fill in the transfer size; set active bit */
408 temp = ((*length << DTD_LENGTH_BIT_POS) | DTD_STATUS_ACTIVE);
410 /* Enable interrupt for the last dtd of a request */
411 if (*is_last && !req->req.no_interrupt)
416 dtd->size_ioc_sts = temp;
423 /* generate dTD linked list for a request */
424 static int req_to_dtd(struct mv_req *req)
427 int is_last, is_first = 1;
428 struct mv_dtd *dtd, *last_dtd = NULL;
435 dtd = build_dtd(req, &count, &dma, &is_last);
443 last_dtd->dtd_next = dma;
444 last_dtd->next_dtd_virt = dtd;
450 /* set terminate bit to 1 for the last dTD */
451 dtd->dtd_next = DTD_NEXT_TERMINATE;
458 static int mv_ep_enable(struct usb_ep *_ep,
459 const struct usb_endpoint_descriptor *desc)
465 u32 bit_pos, epctrlx, direction;
466 unsigned char zlt = 0, ios = 0, mult = 0;
469 ep = container_of(_ep, struct mv_ep, ep);
473 || desc->bDescriptorType != USB_DT_ENDPOINT)
476 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
479 direction = ep_dir(ep);
480 max = usb_endpoint_maxp(desc);
483 * disable HW zero length termination select
484 * driver handles zero length packet through req->req.zero
488 bit_pos = 1 << ((direction == EP_DIR_OUT ? 0 : 16) + ep->ep_num);
490 /* Check if the Endpoint is Primed */
491 if ((readl(&udc->op_regs->epprime) & bit_pos)
492 || (readl(&udc->op_regs->epstatus) & bit_pos)) {
493 dev_info(&udc->dev->dev,
494 "ep=%d %s: Init ERROR: ENDPTPRIME=0x%x,"
495 " ENDPTSTATUS=0x%x, bit_pos=0x%x\n",
496 (unsigned)ep->ep_num, direction ? "SEND" : "RECV",
497 (unsigned)readl(&udc->op_regs->epprime),
498 (unsigned)readl(&udc->op_regs->epstatus),
502 /* Set the max packet length, interrupt on Setup and Mult fields */
503 switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
504 case USB_ENDPOINT_XFER_BULK:
508 case USB_ENDPOINT_XFER_CONTROL:
510 case USB_ENDPOINT_XFER_INT:
513 case USB_ENDPOINT_XFER_ISOC:
514 /* Calculate transactions needed for high bandwidth iso */
515 mult = (unsigned char)(1 + ((max >> 11) & 0x03));
516 max = max & 0x7ff; /* bit 0~10 */
517 /* 3 transactions at most */
525 spin_lock_irqsave(&udc->lock, flags);
526 /* Get the endpoint queue head address */
528 dqh->max_packet_length = (max << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
529 | (mult << EP_QUEUE_HEAD_MULT_POS)
530 | (zlt ? EP_QUEUE_HEAD_ZLT_SEL : 0)
531 | (ios ? EP_QUEUE_HEAD_IOS : 0);
532 dqh->next_dtd_ptr = 1;
533 dqh->size_ioc_int_sts = 0;
535 ep->ep.maxpacket = max;
539 /* Enable the endpoint for Rx or Tx and set the endpoint type */
540 epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
541 if (direction == EP_DIR_IN) {
542 epctrlx &= ~EPCTRL_TX_ALL_MASK;
543 epctrlx |= EPCTRL_TX_ENABLE | EPCTRL_TX_DATA_TOGGLE_RST
544 | ((desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK)
545 << EPCTRL_TX_EP_TYPE_SHIFT);
547 epctrlx &= ~EPCTRL_RX_ALL_MASK;
548 epctrlx |= EPCTRL_RX_ENABLE | EPCTRL_RX_DATA_TOGGLE_RST
549 | ((desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK)
550 << EPCTRL_RX_EP_TYPE_SHIFT);
552 writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
555 * Implement Guideline (GL# USB-7) The unused endpoint type must
556 * be programmed to bulk.
558 epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
559 if ((epctrlx & EPCTRL_RX_ENABLE) == 0) {
560 epctrlx |= (USB_ENDPOINT_XFER_BULK
561 << EPCTRL_RX_EP_TYPE_SHIFT);
562 writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
565 epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
566 if ((epctrlx & EPCTRL_TX_ENABLE) == 0) {
567 epctrlx |= (USB_ENDPOINT_XFER_BULK
568 << EPCTRL_TX_EP_TYPE_SHIFT);
569 writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
572 spin_unlock_irqrestore(&udc->lock, flags);
579 static int mv_ep_disable(struct usb_ep *_ep)
584 u32 bit_pos, epctrlx, direction;
587 ep = container_of(_ep, struct mv_ep, ep);
588 if ((_ep == NULL) || !ep->ep.desc)
593 /* Get the endpoint queue head address */
596 spin_lock_irqsave(&udc->lock, flags);
598 direction = ep_dir(ep);
599 bit_pos = 1 << ((direction == EP_DIR_OUT ? 0 : 16) + ep->ep_num);
601 /* Reset the max packet length and the interrupt on Setup */
602 dqh->max_packet_length = 0;
604 /* Disable the endpoint for Rx or Tx and reset the endpoint type */
605 epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
606 epctrlx &= ~((direction == EP_DIR_IN)
607 ? (EPCTRL_TX_ENABLE | EPCTRL_TX_TYPE)
608 : (EPCTRL_RX_ENABLE | EPCTRL_RX_TYPE));
609 writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
611 /* nuke all pending requests (does flush) */
612 nuke(ep, -ESHUTDOWN);
617 spin_unlock_irqrestore(&udc->lock, flags);
622 static struct usb_request *
623 mv_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
625 struct mv_req *req = NULL;
627 req = kzalloc(sizeof *req, gfp_flags);
631 req->req.dma = DMA_ADDR_INVALID;
632 INIT_LIST_HEAD(&req->queue);
637 static void mv_free_request(struct usb_ep *_ep, struct usb_request *_req)
639 struct mv_req *req = NULL;
641 req = container_of(_req, struct mv_req, req);
647 static void mv_ep_fifo_flush(struct usb_ep *_ep)
650 u32 bit_pos, direction;
657 ep = container_of(_ep, struct mv_ep, ep);
662 direction = ep_dir(ep);
665 bit_pos = (1 << 16) | 1;
666 else if (direction == EP_DIR_OUT)
667 bit_pos = 1 << ep->ep_num;
669 bit_pos = 1 << (16 + ep->ep_num);
671 loops = LOOPS(EPSTATUS_TIMEOUT);
673 unsigned int inter_loops;
676 dev_err(&udc->dev->dev,
677 "TIMEOUT for ENDPTSTATUS=0x%x, bit_pos=0x%x\n",
678 (unsigned)readl(&udc->op_regs->epstatus),
682 /* Write 1 to the Flush register */
683 writel(bit_pos, &udc->op_regs->epflush);
685 /* Wait until flushing completed */
686 inter_loops = LOOPS(FLUSH_TIMEOUT);
687 while (readl(&udc->op_regs->epflush)) {
689 * ENDPTFLUSH bit should be cleared to indicate this
690 * operation is complete
692 if (inter_loops == 0) {
693 dev_err(&udc->dev->dev,
694 "TIMEOUT for ENDPTFLUSH=0x%x,"
696 (unsigned)readl(&udc->op_regs->epflush),
704 } while (readl(&udc->op_regs->epstatus) & bit_pos);
707 /* queues (submits) an I/O request to an endpoint */
709 mv_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
711 struct mv_ep *ep = container_of(_ep, struct mv_ep, ep);
712 struct mv_req *req = container_of(_req, struct mv_req, req);
713 struct mv_udc *udc = ep->udc;
717 /* catch various bogus parameters */
718 if (!_req || !req->req.complete || !req->req.buf
719 || !list_empty(&req->queue)) {
720 dev_err(&udc->dev->dev, "%s, bad params", __func__);
723 if (unlikely(!_ep || !ep->ep.desc)) {
724 dev_err(&udc->dev->dev, "%s, bad ep", __func__);
729 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
734 /* map virtual address to hardware */
735 if (req->req.dma == DMA_ADDR_INVALID) {
736 req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
738 req->req.length, ep_dir(ep)
743 dma_sync_single_for_device(ep->udc->gadget.dev.parent,
744 req->req.dma, req->req.length,
751 req->req.status = -EINPROGRESS;
755 spin_lock_irqsave(&udc->lock, flags);
757 /* build dtds and push them to device queue */
758 if (!req_to_dtd(req)) {
759 retval = queue_dtd(ep, req);
761 spin_unlock_irqrestore(&udc->lock, flags);
762 dev_err(&udc->dev->dev, "Failed to queue dtd\n");
766 spin_unlock_irqrestore(&udc->lock, flags);
767 dev_err(&udc->dev->dev, "Failed to dma_pool_alloc\n");
772 /* Update ep0 state */
774 udc->ep0_state = DATA_STATE_XMIT;
776 /* irq handler advances the queue */
777 list_add_tail(&req->queue, &ep->queue);
778 spin_unlock_irqrestore(&udc->lock, flags);
784 dma_unmap_single(ep->udc->gadget.dev.parent,
785 req->req.dma, req->req.length,
786 ((ep_dir(ep) == EP_DIR_IN) ?
787 DMA_TO_DEVICE : DMA_FROM_DEVICE));
788 req->req.dma = DMA_ADDR_INVALID;
791 dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
792 req->req.dma, req->req.length,
793 ((ep_dir(ep) == EP_DIR_IN) ?
794 DMA_TO_DEVICE : DMA_FROM_DEVICE));
799 static void mv_prime_ep(struct mv_ep *ep, struct mv_req *req)
801 struct mv_dqh *dqh = ep->dqh;
804 /* Write dQH next pointer and terminate bit to 0 */
805 dqh->next_dtd_ptr = req->head->td_dma
806 & EP_QUEUE_HEAD_NEXT_POINTER_MASK;
808 /* clear active and halt bit, in case set from a previous error */
809 dqh->size_ioc_int_sts &= ~(DTD_STATUS_ACTIVE | DTD_STATUS_HALTED);
811 /* Ensure that updates to the QH will occure before priming. */
814 bit_pos = 1 << (((ep_dir(ep) == EP_DIR_OUT) ? 0 : 16) + ep->ep_num);
816 /* Prime the Endpoint */
817 writel(bit_pos, &ep->udc->op_regs->epprime);
820 /* dequeues (cancels, unlinks) an I/O request from an endpoint */
821 static int mv_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
823 struct mv_ep *ep = container_of(_ep, struct mv_ep, ep);
825 struct mv_udc *udc = ep->udc;
827 int stopped, ret = 0;
833 spin_lock_irqsave(&ep->udc->lock, flags);
834 stopped = ep->stopped;
836 /* Stop the ep before we deal with the queue */
838 epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
839 if (ep_dir(ep) == EP_DIR_IN)
840 epctrlx &= ~EPCTRL_TX_ENABLE;
842 epctrlx &= ~EPCTRL_RX_ENABLE;
843 writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
845 /* make sure it's actually queued on this endpoint */
846 list_for_each_entry(req, &ep->queue, queue) {
847 if (&req->req == _req)
850 if (&req->req != _req) {
855 /* The request is in progress, or completed but not dequeued */
856 if (ep->queue.next == &req->queue) {
857 _req->status = -ECONNRESET;
858 mv_ep_fifo_flush(_ep); /* flush current transfer */
860 /* The request isn't the last request in this ep queue */
861 if (req->queue.next != &ep->queue) {
862 struct mv_req *next_req;
864 next_req = list_entry(req->queue.next,
865 struct mv_req, queue);
867 /* Point the QH to the first TD of next request */
868 mv_prime_ep(ep, next_req);
873 qh->next_dtd_ptr = 1;
874 qh->size_ioc_int_sts = 0;
877 /* The request hasn't been processed, patch up the TD chain */
879 struct mv_req *prev_req;
881 prev_req = list_entry(req->queue.prev, struct mv_req, queue);
882 writel(readl(&req->tail->dtd_next),
883 &prev_req->tail->dtd_next);
887 done(ep, req, -ECONNRESET);
891 epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
892 if (ep_dir(ep) == EP_DIR_IN)
893 epctrlx |= EPCTRL_TX_ENABLE;
895 epctrlx |= EPCTRL_RX_ENABLE;
896 writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
897 ep->stopped = stopped;
899 spin_unlock_irqrestore(&ep->udc->lock, flags);
903 static void ep_set_stall(struct mv_udc *udc, u8 ep_num, u8 direction, int stall)
907 epctrlx = readl(&udc->op_regs->epctrlx[ep_num]);
910 if (direction == EP_DIR_IN)
911 epctrlx |= EPCTRL_TX_EP_STALL;
913 epctrlx |= EPCTRL_RX_EP_STALL;
915 if (direction == EP_DIR_IN) {
916 epctrlx &= ~EPCTRL_TX_EP_STALL;
917 epctrlx |= EPCTRL_TX_DATA_TOGGLE_RST;
919 epctrlx &= ~EPCTRL_RX_EP_STALL;
920 epctrlx |= EPCTRL_RX_DATA_TOGGLE_RST;
923 writel(epctrlx, &udc->op_regs->epctrlx[ep_num]);
926 static int ep_is_stall(struct mv_udc *udc, u8 ep_num, u8 direction)
930 epctrlx = readl(&udc->op_regs->epctrlx[ep_num]);
932 if (direction == EP_DIR_OUT)
933 return (epctrlx & EPCTRL_RX_EP_STALL) ? 1 : 0;
935 return (epctrlx & EPCTRL_TX_EP_STALL) ? 1 : 0;
938 static int mv_ep_set_halt_wedge(struct usb_ep *_ep, int halt, int wedge)
941 unsigned long flags = 0;
945 ep = container_of(_ep, struct mv_ep, ep);
947 if (!_ep || !ep->ep.desc) {
952 if (ep->ep.desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
953 status = -EOPNOTSUPP;
958 * Attempt to halt IN ep will fail if any transfer requests
961 if (halt && (ep_dir(ep) == EP_DIR_IN) && !list_empty(&ep->queue)) {
966 spin_lock_irqsave(&ep->udc->lock, flags);
967 ep_set_stall(udc, ep->ep_num, ep_dir(ep), halt);
972 spin_unlock_irqrestore(&ep->udc->lock, flags);
974 if (ep->ep_num == 0) {
975 udc->ep0_state = WAIT_FOR_SETUP;
976 udc->ep0_dir = EP_DIR_OUT;
982 static int mv_ep_set_halt(struct usb_ep *_ep, int halt)
984 return mv_ep_set_halt_wedge(_ep, halt, 0);
987 static int mv_ep_set_wedge(struct usb_ep *_ep)
989 return mv_ep_set_halt_wedge(_ep, 1, 1);
992 static struct usb_ep_ops mv_ep_ops = {
993 .enable = mv_ep_enable,
994 .disable = mv_ep_disable,
996 .alloc_request = mv_alloc_request,
997 .free_request = mv_free_request,
999 .queue = mv_ep_queue,
1000 .dequeue = mv_ep_dequeue,
1002 .set_wedge = mv_ep_set_wedge,
1003 .set_halt = mv_ep_set_halt,
1004 .fifo_flush = mv_ep_fifo_flush, /* flush fifo */
1007 static void udc_clock_enable(struct mv_udc *udc)
1011 for (i = 0; i < udc->clknum; i++)
1012 clk_prepare_enable(udc->clk[i]);
1015 static void udc_clock_disable(struct mv_udc *udc)
1019 for (i = 0; i < udc->clknum; i++)
1020 clk_disable_unprepare(udc->clk[i]);
1023 static void udc_stop(struct mv_udc *udc)
1027 /* Disable interrupts */
1028 tmp = readl(&udc->op_regs->usbintr);
1029 tmp &= ~(USBINTR_INT_EN | USBINTR_ERR_INT_EN |
1030 USBINTR_PORT_CHANGE_DETECT_EN | USBINTR_RESET_EN);
1031 writel(tmp, &udc->op_regs->usbintr);
1035 /* Reset the Run the bit in the command register to stop VUSB */
1036 tmp = readl(&udc->op_regs->usbcmd);
1037 tmp &= ~USBCMD_RUN_STOP;
1038 writel(tmp, &udc->op_regs->usbcmd);
1041 static void udc_start(struct mv_udc *udc)
1045 usbintr = USBINTR_INT_EN | USBINTR_ERR_INT_EN
1046 | USBINTR_PORT_CHANGE_DETECT_EN
1047 | USBINTR_RESET_EN | USBINTR_DEVICE_SUSPEND;
1048 /* Enable interrupts */
1049 writel(usbintr, &udc->op_regs->usbintr);
1053 /* Set the Run bit in the command register */
1054 writel(USBCMD_RUN_STOP, &udc->op_regs->usbcmd);
1057 static int udc_reset(struct mv_udc *udc)
1062 /* Stop the controller */
1063 tmp = readl(&udc->op_regs->usbcmd);
1064 tmp &= ~USBCMD_RUN_STOP;
1065 writel(tmp, &udc->op_regs->usbcmd);
1067 /* Reset the controller to get default values */
1068 writel(USBCMD_CTRL_RESET, &udc->op_regs->usbcmd);
1070 /* wait for reset to complete */
1071 loops = LOOPS(RESET_TIMEOUT);
1072 while (readl(&udc->op_regs->usbcmd) & USBCMD_CTRL_RESET) {
1074 dev_err(&udc->dev->dev,
1075 "Wait for RESET completed TIMEOUT\n");
1082 /* set controller to device mode */
1083 tmp = readl(&udc->op_regs->usbmode);
1084 tmp |= USBMODE_CTRL_MODE_DEVICE;
1086 /* turn setup lockout off, require setup tripwire in usbcmd */
1087 tmp |= USBMODE_SETUP_LOCK_OFF;
1089 writel(tmp, &udc->op_regs->usbmode);
1091 writel(0x0, &udc->op_regs->epsetupstat);
1093 /* Configure the Endpoint List Address */
1094 writel(udc->ep_dqh_dma & USB_EP_LIST_ADDRESS_MASK,
1095 &udc->op_regs->eplistaddr);
1097 portsc = readl(&udc->op_regs->portsc[0]);
1098 if (readl(&udc->cap_regs->hcsparams) & HCSPARAMS_PPC)
1099 portsc &= (~PORTSCX_W1C_BITS | ~PORTSCX_PORT_POWER);
1102 portsc |= PORTSCX_FORCE_FULL_SPEED_CONNECT;
1104 portsc &= (~PORTSCX_FORCE_FULL_SPEED_CONNECT);
1106 writel(portsc, &udc->op_regs->portsc[0]);
1108 tmp = readl(&udc->op_regs->epctrlx[0]);
1109 tmp &= ~(EPCTRL_TX_EP_STALL | EPCTRL_RX_EP_STALL);
1110 writel(tmp, &udc->op_regs->epctrlx[0]);
1115 static int mv_udc_enable_internal(struct mv_udc *udc)
1122 dev_dbg(&udc->dev->dev, "enable udc\n");
1123 udc_clock_enable(udc);
1124 if (udc->pdata->phy_init) {
1125 retval = udc->pdata->phy_init(udc->phy_regs);
1127 dev_err(&udc->dev->dev,
1128 "init phy error %d\n", retval);
1129 udc_clock_disable(udc);
1138 static int mv_udc_enable(struct mv_udc *udc)
1140 if (udc->clock_gating)
1141 return mv_udc_enable_internal(udc);
1146 static void mv_udc_disable_internal(struct mv_udc *udc)
1149 dev_dbg(&udc->dev->dev, "disable udc\n");
1150 if (udc->pdata->phy_deinit)
1151 udc->pdata->phy_deinit(udc->phy_regs);
1152 udc_clock_disable(udc);
1157 static void mv_udc_disable(struct mv_udc *udc)
1159 if (udc->clock_gating)
1160 mv_udc_disable_internal(udc);
1163 static int mv_udc_get_frame(struct usb_gadget *gadget)
1171 udc = container_of(gadget, struct mv_udc, gadget);
1173 retval = readl(&udc->op_regs->frindex) & USB_FRINDEX_MASKS;
1178 /* Tries to wake up the host connected to this gadget */
1179 static int mv_udc_wakeup(struct usb_gadget *gadget)
1181 struct mv_udc *udc = container_of(gadget, struct mv_udc, gadget);
1184 /* Remote wakeup feature not enabled by host */
1185 if (!udc->remote_wakeup)
1188 portsc = readl(&udc->op_regs->portsc);
1189 /* not suspended? */
1190 if (!(portsc & PORTSCX_PORT_SUSPEND))
1192 /* trigger force resume */
1193 portsc |= PORTSCX_PORT_FORCE_RESUME;
1194 writel(portsc, &udc->op_regs->portsc[0]);
1198 static int mv_udc_vbus_session(struct usb_gadget *gadget, int is_active)
1201 unsigned long flags;
1204 udc = container_of(gadget, struct mv_udc, gadget);
1205 spin_lock_irqsave(&udc->lock, flags);
1207 udc->vbus_active = (is_active != 0);
1209 dev_dbg(&udc->dev->dev, "%s: softconnect %d, vbus_active %d\n",
1210 __func__, udc->softconnect, udc->vbus_active);
1212 if (udc->driver && udc->softconnect && udc->vbus_active) {
1213 retval = mv_udc_enable(udc);
1215 /* Clock is disabled, need re-init registers */
1220 } else if (udc->driver && udc->softconnect) {
1224 /* stop all the transfer in queue*/
1225 stop_activity(udc, udc->driver);
1227 mv_udc_disable(udc);
1231 spin_unlock_irqrestore(&udc->lock, flags);
1235 static int mv_udc_pullup(struct usb_gadget *gadget, int is_on)
1238 unsigned long flags;
1241 udc = container_of(gadget, struct mv_udc, gadget);
1242 spin_lock_irqsave(&udc->lock, flags);
1244 udc->softconnect = (is_on != 0);
1246 dev_dbg(&udc->dev->dev, "%s: softconnect %d, vbus_active %d\n",
1247 __func__, udc->softconnect, udc->vbus_active);
1249 if (udc->driver && udc->softconnect && udc->vbus_active) {
1250 retval = mv_udc_enable(udc);
1252 /* Clock is disabled, need re-init registers */
1257 } else if (udc->driver && udc->vbus_active) {
1258 /* stop all the transfer in queue*/
1259 stop_activity(udc, udc->driver);
1261 mv_udc_disable(udc);
1264 spin_unlock_irqrestore(&udc->lock, flags);
1268 static int mv_udc_start(struct usb_gadget *, struct usb_gadget_driver *);
1269 static int mv_udc_stop(struct usb_gadget *, struct usb_gadget_driver *);
1270 /* device controller usb_gadget_ops structure */
1271 static const struct usb_gadget_ops mv_ops = {
1273 /* returns the current frame number */
1274 .get_frame = mv_udc_get_frame,
1276 /* tries to wake up the host connected to this gadget */
1277 .wakeup = mv_udc_wakeup,
1279 /* notify controller that VBUS is powered or not */
1280 .vbus_session = mv_udc_vbus_session,
1282 /* D+ pullup, software-controlled connect/disconnect to USB host */
1283 .pullup = mv_udc_pullup,
1284 .udc_start = mv_udc_start,
1285 .udc_stop = mv_udc_stop,
1288 static int eps_init(struct mv_udc *udc)
1294 /* initialize ep0 */
1297 strncpy(ep->name, "ep0", sizeof(ep->name));
1298 ep->ep.name = ep->name;
1299 ep->ep.ops = &mv_ep_ops;
1302 ep->ep.maxpacket = EP0_MAX_PKT_SIZE;
1304 ep->ep.desc = &mv_ep0_desc;
1305 INIT_LIST_HEAD(&ep->queue);
1307 ep->ep_type = USB_ENDPOINT_XFER_CONTROL;
1309 /* initialize other endpoints */
1310 for (i = 2; i < udc->max_eps * 2; i++) {
1313 snprintf(name, sizeof(name), "ep%din", i / 2);
1314 ep->direction = EP_DIR_IN;
1316 snprintf(name, sizeof(name), "ep%dout", i / 2);
1317 ep->direction = EP_DIR_OUT;
1320 strncpy(ep->name, name, sizeof(ep->name));
1321 ep->ep.name = ep->name;
1323 ep->ep.ops = &mv_ep_ops;
1325 ep->ep.maxpacket = (unsigned short) ~0;
1328 INIT_LIST_HEAD(&ep->queue);
1329 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
1331 ep->dqh = &udc->ep_dqh[i];
1337 /* delete all endpoint requests, called with spinlock held */
1338 static void nuke(struct mv_ep *ep, int status)
1340 /* called with spinlock held */
1343 /* endpoint fifo flush */
1344 mv_ep_fifo_flush(&ep->ep);
1346 while (!list_empty(&ep->queue)) {
1347 struct mv_req *req = NULL;
1348 req = list_entry(ep->queue.next, struct mv_req, queue);
1349 done(ep, req, status);
1353 /* stop all USB activities */
1354 static void stop_activity(struct mv_udc *udc, struct usb_gadget_driver *driver)
1358 nuke(&udc->eps[0], -ESHUTDOWN);
1360 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
1361 nuke(ep, -ESHUTDOWN);
1364 /* report disconnect; the driver is already quiesced */
1366 spin_unlock(&udc->lock);
1367 driver->disconnect(&udc->gadget);
1368 spin_lock(&udc->lock);
1372 static int mv_udc_start(struct usb_gadget *gadget,
1373 struct usb_gadget_driver *driver)
1377 unsigned long flags;
1379 udc = container_of(gadget, struct mv_udc, gadget);
1384 spin_lock_irqsave(&udc->lock, flags);
1386 /* hook up the driver ... */
1387 driver->driver.bus = NULL;
1388 udc->driver = driver;
1389 udc->gadget.dev.driver = &driver->driver;
1391 udc->usb_state = USB_STATE_ATTACHED;
1392 udc->ep0_state = WAIT_FOR_SETUP;
1393 udc->ep0_dir = EP_DIR_OUT;
1395 spin_unlock_irqrestore(&udc->lock, flags);
1397 if (udc->transceiver) {
1398 retval = otg_set_peripheral(udc->transceiver->otg,
1401 dev_err(&udc->dev->dev,
1402 "unable to register peripheral to otg\n");
1404 udc->gadget.dev.driver = NULL;
1409 /* pullup is always on */
1410 mv_udc_pullup(&udc->gadget, 1);
1412 /* When boot with cable attached, there will be no vbus irq occurred */
1414 queue_work(udc->qwork, &udc->vbus_work);
1419 static int mv_udc_stop(struct usb_gadget *gadget,
1420 struct usb_gadget_driver *driver)
1423 unsigned long flags;
1425 udc = container_of(gadget, struct mv_udc, gadget);
1427 spin_lock_irqsave(&udc->lock, flags);
1432 /* stop all usb activities */
1433 udc->gadget.speed = USB_SPEED_UNKNOWN;
1434 stop_activity(udc, driver);
1435 mv_udc_disable(udc);
1437 spin_unlock_irqrestore(&udc->lock, flags);
1439 /* unbind gadget driver */
1440 udc->gadget.dev.driver = NULL;
1446 static void mv_set_ptc(struct mv_udc *udc, u32 mode)
1450 portsc = readl(&udc->op_regs->portsc[0]);
1451 portsc |= mode << 16;
1452 writel(portsc, &udc->op_regs->portsc[0]);
1455 static void prime_status_complete(struct usb_ep *ep, struct usb_request *_req)
1457 struct mv_ep *mvep = container_of(ep, struct mv_ep, ep);
1458 struct mv_req *req = container_of(_req, struct mv_req, req);
1460 unsigned long flags;
1464 dev_info(&udc->dev->dev, "switch to test mode %d\n", req->test_mode);
1466 spin_lock_irqsave(&udc->lock, flags);
1467 if (req->test_mode) {
1468 mv_set_ptc(udc, req->test_mode);
1471 spin_unlock_irqrestore(&udc->lock, flags);
1475 udc_prime_status(struct mv_udc *udc, u8 direction, u16 status, bool empty)
1482 udc->ep0_dir = direction;
1483 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1485 req = udc->status_req;
1487 /* fill in the reqest structure */
1488 if (empty == false) {
1489 *((u16 *) req->req.buf) = cpu_to_le16(status);
1490 req->req.length = 2;
1492 req->req.length = 0;
1495 req->req.status = -EINPROGRESS;
1496 req->req.actual = 0;
1497 if (udc->test_mode) {
1498 req->req.complete = prime_status_complete;
1499 req->test_mode = udc->test_mode;
1502 req->req.complete = NULL;
1505 if (req->req.dma == DMA_ADDR_INVALID) {
1506 req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
1507 req->req.buf, req->req.length,
1508 ep_dir(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1512 /* prime the data phase */
1513 if (!req_to_dtd(req)) {
1514 retval = queue_dtd(ep, req);
1516 dev_err(&udc->dev->dev,
1517 "Failed to queue dtd when prime status\n");
1520 } else{ /* no mem */
1522 dev_err(&udc->dev->dev,
1523 "Failed to dma_pool_alloc when prime status\n");
1527 list_add_tail(&req->queue, &ep->queue);
1532 dma_unmap_single(ep->udc->gadget.dev.parent,
1533 req->req.dma, req->req.length,
1534 ((ep_dir(ep) == EP_DIR_IN) ?
1535 DMA_TO_DEVICE : DMA_FROM_DEVICE));
1536 req->req.dma = DMA_ADDR_INVALID;
1543 static void mv_udc_testmode(struct mv_udc *udc, u16 index)
1545 if (index <= TEST_FORCE_EN) {
1546 udc->test_mode = index;
1547 if (udc_prime_status(udc, EP_DIR_IN, 0, true))
1550 dev_err(&udc->dev->dev,
1551 "This test mode(%d) is not supported\n", index);
1554 static void ch9setaddress(struct mv_udc *udc, struct usb_ctrlrequest *setup)
1556 udc->dev_addr = (u8)setup->wValue;
1558 /* update usb state */
1559 udc->usb_state = USB_STATE_ADDRESS;
1561 if (udc_prime_status(udc, EP_DIR_IN, 0, true))
1565 static void ch9getstatus(struct mv_udc *udc, u8 ep_num,
1566 struct usb_ctrlrequest *setup)
1571 if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK))
1572 != (USB_DIR_IN | USB_TYPE_STANDARD))
1575 if ((setup->bRequestType & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
1576 status = 1 << USB_DEVICE_SELF_POWERED;
1577 status |= udc->remote_wakeup << USB_DEVICE_REMOTE_WAKEUP;
1578 } else if ((setup->bRequestType & USB_RECIP_MASK)
1579 == USB_RECIP_INTERFACE) {
1580 /* get interface status */
1582 } else if ((setup->bRequestType & USB_RECIP_MASK)
1583 == USB_RECIP_ENDPOINT) {
1584 u8 ep_num, direction;
1586 ep_num = setup->wIndex & USB_ENDPOINT_NUMBER_MASK;
1587 direction = (setup->wIndex & USB_ENDPOINT_DIR_MASK)
1588 ? EP_DIR_IN : EP_DIR_OUT;
1589 status = ep_is_stall(udc, ep_num, direction)
1590 << USB_ENDPOINT_HALT;
1593 retval = udc_prime_status(udc, EP_DIR_IN, status, false);
1597 udc->ep0_state = DATA_STATE_XMIT;
1600 static void ch9clearfeature(struct mv_udc *udc, struct usb_ctrlrequest *setup)
1606 if ((setup->bRequestType & (USB_TYPE_MASK | USB_RECIP_MASK))
1607 == ((USB_TYPE_STANDARD | USB_RECIP_DEVICE))) {
1608 switch (setup->wValue) {
1609 case USB_DEVICE_REMOTE_WAKEUP:
1610 udc->remote_wakeup = 0;
1615 } else if ((setup->bRequestType & (USB_TYPE_MASK | USB_RECIP_MASK))
1616 == ((USB_TYPE_STANDARD | USB_RECIP_ENDPOINT))) {
1617 switch (setup->wValue) {
1618 case USB_ENDPOINT_HALT:
1619 ep_num = setup->wIndex & USB_ENDPOINT_NUMBER_MASK;
1620 direction = (setup->wIndex & USB_ENDPOINT_DIR_MASK)
1621 ? EP_DIR_IN : EP_DIR_OUT;
1622 if (setup->wValue != 0 || setup->wLength != 0
1623 || ep_num > udc->max_eps)
1625 ep = &udc->eps[ep_num * 2 + direction];
1628 spin_unlock(&udc->lock);
1629 ep_set_stall(udc, ep_num, direction, 0);
1630 spin_lock(&udc->lock);
1638 if (udc_prime_status(udc, EP_DIR_IN, 0, true))
1644 static void ch9setfeature(struct mv_udc *udc, struct usb_ctrlrequest *setup)
1649 if ((setup->bRequestType & (USB_TYPE_MASK | USB_RECIP_MASK))
1650 == ((USB_TYPE_STANDARD | USB_RECIP_DEVICE))) {
1651 switch (setup->wValue) {
1652 case USB_DEVICE_REMOTE_WAKEUP:
1653 udc->remote_wakeup = 1;
1655 case USB_DEVICE_TEST_MODE:
1656 if (setup->wIndex & 0xFF
1657 || udc->gadget.speed != USB_SPEED_HIGH)
1660 if (udc->usb_state != USB_STATE_CONFIGURED
1661 && udc->usb_state != USB_STATE_ADDRESS
1662 && udc->usb_state != USB_STATE_DEFAULT)
1665 mv_udc_testmode(udc, (setup->wIndex >> 8));
1670 } else if ((setup->bRequestType & (USB_TYPE_MASK | USB_RECIP_MASK))
1671 == ((USB_TYPE_STANDARD | USB_RECIP_ENDPOINT))) {
1672 switch (setup->wValue) {
1673 case USB_ENDPOINT_HALT:
1674 ep_num = setup->wIndex & USB_ENDPOINT_NUMBER_MASK;
1675 direction = (setup->wIndex & USB_ENDPOINT_DIR_MASK)
1676 ? EP_DIR_IN : EP_DIR_OUT;
1677 if (setup->wValue != 0 || setup->wLength != 0
1678 || ep_num > udc->max_eps)
1680 spin_unlock(&udc->lock);
1681 ep_set_stall(udc, ep_num, direction, 1);
1682 spin_lock(&udc->lock);
1690 if (udc_prime_status(udc, EP_DIR_IN, 0, true))
1696 static void handle_setup_packet(struct mv_udc *udc, u8 ep_num,
1697 struct usb_ctrlrequest *setup)
1699 bool delegate = false;
1701 nuke(&udc->eps[ep_num * 2 + EP_DIR_OUT], -ESHUTDOWN);
1703 dev_dbg(&udc->dev->dev, "SETUP %02x.%02x v%04x i%04x l%04x\n",
1704 setup->bRequestType, setup->bRequest,
1705 setup->wValue, setup->wIndex, setup->wLength);
1706 /* We process some stardard setup requests here */
1707 if ((setup->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1708 switch (setup->bRequest) {
1709 case USB_REQ_GET_STATUS:
1710 ch9getstatus(udc, ep_num, setup);
1713 case USB_REQ_SET_ADDRESS:
1714 ch9setaddress(udc, setup);
1717 case USB_REQ_CLEAR_FEATURE:
1718 ch9clearfeature(udc, setup);
1721 case USB_REQ_SET_FEATURE:
1722 ch9setfeature(udc, setup);
1731 /* delegate USB standard requests to the gadget driver */
1732 if (delegate == true) {
1733 /* USB requests handled by gadget */
1734 if (setup->wLength) {
1735 /* DATA phase from gadget, STATUS phase from udc */
1736 udc->ep0_dir = (setup->bRequestType & USB_DIR_IN)
1737 ? EP_DIR_IN : EP_DIR_OUT;
1738 spin_unlock(&udc->lock);
1739 if (udc->driver->setup(&udc->gadget,
1740 &udc->local_setup_buff) < 0)
1742 spin_lock(&udc->lock);
1743 udc->ep0_state = (setup->bRequestType & USB_DIR_IN)
1744 ? DATA_STATE_XMIT : DATA_STATE_RECV;
1746 /* no DATA phase, IN STATUS phase from gadget */
1747 udc->ep0_dir = EP_DIR_IN;
1748 spin_unlock(&udc->lock);
1749 if (udc->driver->setup(&udc->gadget,
1750 &udc->local_setup_buff) < 0)
1752 spin_lock(&udc->lock);
1753 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1758 /* complete DATA or STATUS phase of ep0 prime status phase if needed */
1759 static void ep0_req_complete(struct mv_udc *udc,
1760 struct mv_ep *ep0, struct mv_req *req)
1764 if (udc->usb_state == USB_STATE_ADDRESS) {
1765 /* set the new address */
1766 new_addr = (u32)udc->dev_addr;
1767 writel(new_addr << USB_DEVICE_ADDRESS_BIT_SHIFT,
1768 &udc->op_regs->deviceaddr);
1773 switch (udc->ep0_state) {
1774 case DATA_STATE_XMIT:
1775 /* receive status phase */
1776 if (udc_prime_status(udc, EP_DIR_OUT, 0, true))
1779 case DATA_STATE_RECV:
1780 /* send status phase */
1781 if (udc_prime_status(udc, EP_DIR_IN, 0 , true))
1784 case WAIT_FOR_OUT_STATUS:
1785 udc->ep0_state = WAIT_FOR_SETUP;
1787 case WAIT_FOR_SETUP:
1788 dev_err(&udc->dev->dev, "unexpect ep0 packets\n");
1796 static void get_setup_data(struct mv_udc *udc, u8 ep_num, u8 *buffer_ptr)
1801 dqh = &udc->ep_dqh[ep_num * 2 + EP_DIR_OUT];
1803 /* Clear bit in ENDPTSETUPSTAT */
1804 writel((1 << ep_num), &udc->op_regs->epsetupstat);
1806 /* while a hazard exists when setup package arrives */
1808 /* Set Setup Tripwire */
1809 temp = readl(&udc->op_regs->usbcmd);
1810 writel(temp | USBCMD_SETUP_TRIPWIRE_SET, &udc->op_regs->usbcmd);
1812 /* Copy the setup packet to local buffer */
1813 memcpy(buffer_ptr, (u8 *) dqh->setup_buffer, 8);
1814 } while (!(readl(&udc->op_regs->usbcmd) & USBCMD_SETUP_TRIPWIRE_SET));
1816 /* Clear Setup Tripwire */
1817 temp = readl(&udc->op_regs->usbcmd);
1818 writel(temp & ~USBCMD_SETUP_TRIPWIRE_SET, &udc->op_regs->usbcmd);
1821 static void irq_process_tr_complete(struct mv_udc *udc)
1824 int i, ep_num = 0, direction = 0;
1825 struct mv_ep *curr_ep;
1826 struct mv_req *curr_req, *temp_req;
1830 * We use separate loops for ENDPTSETUPSTAT and ENDPTCOMPLETE
1831 * because the setup packets are to be read ASAP
1834 /* Process all Setup packet received interrupts */
1835 tmp = readl(&udc->op_regs->epsetupstat);
1838 for (i = 0; i < udc->max_eps; i++) {
1839 if (tmp & (1 << i)) {
1840 get_setup_data(udc, i,
1841 (u8 *)(&udc->local_setup_buff));
1842 handle_setup_packet(udc, i,
1843 &udc->local_setup_buff);
1848 /* Don't clear the endpoint setup status register here.
1849 * It is cleared as a setup packet is read out of the buffer
1852 /* Process non-setup transaction complete interrupts */
1853 tmp = readl(&udc->op_regs->epcomplete);
1858 writel(tmp, &udc->op_regs->epcomplete);
1860 for (i = 0; i < udc->max_eps * 2; i++) {
1864 bit_pos = 1 << (ep_num + 16 * direction);
1866 if (!(bit_pos & tmp))
1870 curr_ep = &udc->eps[0];
1872 curr_ep = &udc->eps[i];
1873 /* process the req queue until an uncomplete request */
1874 list_for_each_entry_safe(curr_req, temp_req,
1875 &curr_ep->queue, queue) {
1876 status = process_ep_req(udc, i, curr_req);
1880 /* write back status to req */
1881 curr_req->req.status = status;
1883 /* ep0 request completion */
1885 ep0_req_complete(udc, curr_ep, curr_req);
1888 done(curr_ep, curr_req, status);
1894 void irq_process_reset(struct mv_udc *udc)
1899 udc->ep0_dir = EP_DIR_OUT;
1900 udc->ep0_state = WAIT_FOR_SETUP;
1901 udc->remote_wakeup = 0; /* default to 0 on reset */
1903 /* The address bits are past bit 25-31. Set the address */
1904 tmp = readl(&udc->op_regs->deviceaddr);
1905 tmp &= ~(USB_DEVICE_ADDRESS_MASK);
1906 writel(tmp, &udc->op_regs->deviceaddr);
1908 /* Clear all the setup token semaphores */
1909 tmp = readl(&udc->op_regs->epsetupstat);
1910 writel(tmp, &udc->op_regs->epsetupstat);
1912 /* Clear all the endpoint complete status bits */
1913 tmp = readl(&udc->op_regs->epcomplete);
1914 writel(tmp, &udc->op_regs->epcomplete);
1916 /* wait until all endptprime bits cleared */
1917 loops = LOOPS(PRIME_TIMEOUT);
1918 while (readl(&udc->op_regs->epprime) & 0xFFFFFFFF) {
1920 dev_err(&udc->dev->dev,
1921 "Timeout for ENDPTPRIME = 0x%x\n",
1922 readl(&udc->op_regs->epprime));
1929 /* Write 1s to the Flush register */
1930 writel((u32)~0, &udc->op_regs->epflush);
1932 if (readl(&udc->op_regs->portsc[0]) & PORTSCX_PORT_RESET) {
1933 dev_info(&udc->dev->dev, "usb bus reset\n");
1934 udc->usb_state = USB_STATE_DEFAULT;
1935 /* reset all the queues, stop all USB activities */
1936 stop_activity(udc, udc->driver);
1938 dev_info(&udc->dev->dev, "USB reset portsc 0x%x\n",
1939 readl(&udc->op_regs->portsc));
1947 /* reset all the queues, stop all USB activities */
1948 stop_activity(udc, udc->driver);
1950 /* reset ep0 dQH and endptctrl */
1953 /* enable interrupt and set controller to run state */
1956 udc->usb_state = USB_STATE_ATTACHED;
1960 static void handle_bus_resume(struct mv_udc *udc)
1962 udc->usb_state = udc->resume_state;
1963 udc->resume_state = 0;
1965 /* report resume to the driver */
1967 if (udc->driver->resume) {
1968 spin_unlock(&udc->lock);
1969 udc->driver->resume(&udc->gadget);
1970 spin_lock(&udc->lock);
1975 static void irq_process_suspend(struct mv_udc *udc)
1977 udc->resume_state = udc->usb_state;
1978 udc->usb_state = USB_STATE_SUSPENDED;
1980 if (udc->driver->suspend) {
1981 spin_unlock(&udc->lock);
1982 udc->driver->suspend(&udc->gadget);
1983 spin_lock(&udc->lock);
1987 static void irq_process_port_change(struct mv_udc *udc)
1991 portsc = readl(&udc->op_regs->portsc[0]);
1992 if (!(portsc & PORTSCX_PORT_RESET)) {
1994 u32 speed = portsc & PORTSCX_PORT_SPEED_MASK;
1996 case PORTSCX_PORT_SPEED_HIGH:
1997 udc->gadget.speed = USB_SPEED_HIGH;
1999 case PORTSCX_PORT_SPEED_FULL:
2000 udc->gadget.speed = USB_SPEED_FULL;
2002 case PORTSCX_PORT_SPEED_LOW:
2003 udc->gadget.speed = USB_SPEED_LOW;
2006 udc->gadget.speed = USB_SPEED_UNKNOWN;
2011 if (portsc & PORTSCX_PORT_SUSPEND) {
2012 udc->resume_state = udc->usb_state;
2013 udc->usb_state = USB_STATE_SUSPENDED;
2014 if (udc->driver->suspend) {
2015 spin_unlock(&udc->lock);
2016 udc->driver->suspend(&udc->gadget);
2017 spin_lock(&udc->lock);
2021 if (!(portsc & PORTSCX_PORT_SUSPEND)
2022 && udc->usb_state == USB_STATE_SUSPENDED) {
2023 handle_bus_resume(udc);
2026 if (!udc->resume_state)
2027 udc->usb_state = USB_STATE_DEFAULT;
2030 static void irq_process_error(struct mv_udc *udc)
2032 /* Increment the error count */
2036 static irqreturn_t mv_udc_irq(int irq, void *dev)
2038 struct mv_udc *udc = (struct mv_udc *)dev;
2041 /* Disable ISR when stopped bit is set */
2045 spin_lock(&udc->lock);
2047 status = readl(&udc->op_regs->usbsts);
2048 intr = readl(&udc->op_regs->usbintr);
2052 spin_unlock(&udc->lock);
2056 /* Clear all the interrupts occurred */
2057 writel(status, &udc->op_regs->usbsts);
2059 if (status & USBSTS_ERR)
2060 irq_process_error(udc);
2062 if (status & USBSTS_RESET)
2063 irq_process_reset(udc);
2065 if (status & USBSTS_PORT_CHANGE)
2066 irq_process_port_change(udc);
2068 if (status & USBSTS_INT)
2069 irq_process_tr_complete(udc);
2071 if (status & USBSTS_SUSPEND)
2072 irq_process_suspend(udc);
2074 spin_unlock(&udc->lock);
2079 static irqreturn_t mv_udc_vbus_irq(int irq, void *dev)
2081 struct mv_udc *udc = (struct mv_udc *)dev;
2083 /* polling VBUS and init phy may cause too much time*/
2085 queue_work(udc->qwork, &udc->vbus_work);
2090 static void mv_udc_vbus_work(struct work_struct *work)
2095 udc = container_of(work, struct mv_udc, vbus_work);
2096 if (!udc->pdata->vbus)
2099 vbus = udc->pdata->vbus->poll();
2100 dev_info(&udc->dev->dev, "vbus is %d\n", vbus);
2102 if (vbus == VBUS_HIGH)
2103 mv_udc_vbus_session(&udc->gadget, 1);
2104 else if (vbus == VBUS_LOW)
2105 mv_udc_vbus_session(&udc->gadget, 0);
2108 /* release device structure */
2109 static void gadget_release(struct device *_dev)
2113 udc = dev_get_drvdata(_dev);
2115 complete(udc->done);
2118 static int mv_udc_remove(struct platform_device *pdev)
2122 udc = platform_get_drvdata(pdev);
2124 usb_del_gadget_udc(&udc->gadget);
2127 flush_workqueue(udc->qwork);
2128 destroy_workqueue(udc->qwork);
2131 /* free memory allocated in probe */
2133 dma_pool_destroy(udc->dtd_pool);
2136 dma_free_coherent(&pdev->dev, udc->ep_dqh_size,
2137 udc->ep_dqh, udc->ep_dqh_dma);
2139 mv_udc_disable(udc);
2141 device_unregister(&udc->gadget.dev);
2143 /* free dev, wait for the release() finished */
2144 wait_for_completion(udc->done);
2149 static int mv_udc_probe(struct platform_device *pdev)
2151 struct mv_usb_platform_data *pdata = pdev->dev.platform_data;
2158 if (pdata == NULL) {
2159 dev_err(&pdev->dev, "missing platform_data\n");
2163 size = sizeof(*udc) + sizeof(struct clk *) * pdata->clknum;
2164 udc = devm_kzalloc(&pdev->dev, size, GFP_KERNEL);
2166 dev_err(&pdev->dev, "failed to allocate memory for udc\n");
2170 udc->done = &release_done;
2171 udc->pdata = pdev->dev.platform_data;
2172 spin_lock_init(&udc->lock);
2176 #ifdef CONFIG_USB_OTG_UTILS
2177 if (pdata->mode == MV_USB_MODE_OTG) {
2178 udc->transceiver = devm_usb_get_phy(&pdev->dev,
2180 if (IS_ERR_OR_NULL(udc->transceiver)) {
2181 udc->transceiver = NULL;
2187 udc->clknum = pdata->clknum;
2188 for (clk_i = 0; clk_i < udc->clknum; clk_i++) {
2189 udc->clk[clk_i] = devm_clk_get(&pdev->dev,
2190 pdata->clkname[clk_i]);
2191 if (IS_ERR(udc->clk[clk_i])) {
2192 retval = PTR_ERR(udc->clk[clk_i]);
2197 r = platform_get_resource_byname(udc->dev, IORESOURCE_MEM, "capregs");
2199 dev_err(&pdev->dev, "no I/O memory resource defined\n");
2203 udc->cap_regs = (struct mv_cap_regs __iomem *)
2204 devm_ioremap(&pdev->dev, r->start, resource_size(r));
2205 if (udc->cap_regs == NULL) {
2206 dev_err(&pdev->dev, "failed to map I/O memory\n");
2210 r = platform_get_resource_byname(udc->dev, IORESOURCE_MEM, "phyregs");
2212 dev_err(&pdev->dev, "no phy I/O memory resource defined\n");
2216 udc->phy_regs = ioremap(r->start, resource_size(r));
2217 if (udc->phy_regs == NULL) {
2218 dev_err(&pdev->dev, "failed to map phy I/O memory\n");
2222 /* we will acces controller register, so enable the clk */
2223 retval = mv_udc_enable_internal(udc);
2228 (struct mv_op_regs __iomem *)((unsigned long)udc->cap_regs
2229 + (readl(&udc->cap_regs->caplength_hciversion)
2231 udc->max_eps = readl(&udc->cap_regs->dccparams) & DCCPARAMS_DEN_MASK;
2234 * some platform will use usb to download image, it may not disconnect
2235 * usb gadget before loading kernel. So first stop udc here.
2238 writel(0xFFFFFFFF, &udc->op_regs->usbsts);
2240 size = udc->max_eps * sizeof(struct mv_dqh) *2;
2241 size = (size + DQH_ALIGNMENT - 1) & ~(DQH_ALIGNMENT - 1);
2242 udc->ep_dqh = dma_alloc_coherent(&pdev->dev, size,
2243 &udc->ep_dqh_dma, GFP_KERNEL);
2245 if (udc->ep_dqh == NULL) {
2246 dev_err(&pdev->dev, "allocate dQH memory failed\n");
2248 goto err_disable_clock;
2250 udc->ep_dqh_size = size;
2252 /* create dTD dma_pool resource */
2253 udc->dtd_pool = dma_pool_create("mv_dtd",
2255 sizeof(struct mv_dtd),
2259 if (!udc->dtd_pool) {
2264 size = udc->max_eps * sizeof(struct mv_ep) *2;
2265 udc->eps = devm_kzalloc(&pdev->dev, size, GFP_KERNEL);
2266 if (udc->eps == NULL) {
2267 dev_err(&pdev->dev, "allocate ep memory failed\n");
2269 goto err_destroy_dma;
2272 /* initialize ep0 status request structure */
2273 udc->status_req = devm_kzalloc(&pdev->dev, sizeof(struct mv_req),
2275 if (!udc->status_req) {
2276 dev_err(&pdev->dev, "allocate status_req memory failed\n");
2278 goto err_destroy_dma;
2280 INIT_LIST_HEAD(&udc->status_req->queue);
2282 /* allocate a small amount of memory to get valid address */
2283 udc->status_req->req.buf = kzalloc(8, GFP_KERNEL);
2284 udc->status_req->req.dma = DMA_ADDR_INVALID;
2286 udc->resume_state = USB_STATE_NOTATTACHED;
2287 udc->usb_state = USB_STATE_POWERED;
2288 udc->ep0_dir = EP_DIR_OUT;
2289 udc->remote_wakeup = 0;
2291 r = platform_get_resource(udc->dev, IORESOURCE_IRQ, 0);
2293 dev_err(&pdev->dev, "no IRQ resource defined\n");
2295 goto err_destroy_dma;
2297 udc->irq = r->start;
2298 if (devm_request_irq(&pdev->dev, udc->irq, mv_udc_irq,
2299 IRQF_SHARED, driver_name, udc)) {
2300 dev_err(&pdev->dev, "Request irq %d for UDC failed\n",
2303 goto err_destroy_dma;
2306 /* initialize gadget structure */
2307 udc->gadget.ops = &mv_ops; /* usb_gadget_ops */
2308 udc->gadget.ep0 = &udc->eps[0].ep; /* gadget ep0 */
2309 INIT_LIST_HEAD(&udc->gadget.ep_list); /* ep_list */
2310 udc->gadget.speed = USB_SPEED_UNKNOWN; /* speed */
2311 udc->gadget.max_speed = USB_SPEED_HIGH; /* support dual speed */
2313 /* the "gadget" abstracts/virtualizes the controller */
2314 dev_set_name(&udc->gadget.dev, "gadget");
2315 udc->gadget.dev.parent = &pdev->dev;
2316 udc->gadget.dev.dma_mask = pdev->dev.dma_mask;
2317 udc->gadget.dev.release = gadget_release;
2318 udc->gadget.name = driver_name; /* gadget name */
2320 retval = device_register(&udc->gadget.dev);
2322 goto err_destroy_dma;
2326 /* VBUS detect: we can disable/enable clock on demand.*/
2327 if (udc->transceiver)
2328 udc->clock_gating = 1;
2329 else if (pdata->vbus) {
2330 udc->clock_gating = 1;
2331 retval = devm_request_threaded_irq(&pdev->dev,
2332 pdata->vbus->irq, NULL,
2333 mv_udc_vbus_irq, IRQF_ONESHOT, "vbus", udc);
2335 dev_info(&pdev->dev,
2336 "Can not request irq for VBUS, "
2337 "disable clock gating\n");
2338 udc->clock_gating = 0;
2341 udc->qwork = create_singlethread_workqueue("mv_udc_queue");
2343 dev_err(&pdev->dev, "cannot create workqueue\n");
2345 goto err_unregister;
2348 INIT_WORK(&udc->vbus_work, mv_udc_vbus_work);
2352 * When clock gating is supported, we can disable clk and phy.
2353 * If not, it means that VBUS detection is not supported, we
2354 * have to enable vbus active all the time to let controller work.
2356 if (udc->clock_gating)
2357 mv_udc_disable_internal(udc);
2359 udc->vbus_active = 1;
2361 retval = usb_add_gadget_udc(&pdev->dev, &udc->gadget);
2363 goto err_create_workqueue;
2365 platform_set_drvdata(pdev, udc);
2366 dev_info(&pdev->dev, "successful probe UDC device %s clock gating.\n",
2367 udc->clock_gating ? "with" : "without");
2371 err_create_workqueue:
2372 destroy_workqueue(udc->qwork);
2374 device_unregister(&udc->gadget.dev);
2376 dma_pool_destroy(udc->dtd_pool);
2378 dma_free_coherent(&pdev->dev, udc->ep_dqh_size,
2379 udc->ep_dqh, udc->ep_dqh_dma);
2381 mv_udc_disable_internal(udc);
2387 static int mv_udc_suspend(struct device *dev)
2391 udc = dev_get_drvdata(dev);
2393 /* if OTG is enabled, the following will be done in OTG driver*/
2394 if (udc->transceiver)
2397 if (udc->pdata->vbus && udc->pdata->vbus->poll)
2398 if (udc->pdata->vbus->poll() == VBUS_HIGH) {
2399 dev_info(&udc->dev->dev, "USB cable is connected!\n");
2404 * only cable is unplugged, udc can suspend.
2405 * So do not care about clock_gating == 1.
2407 if (!udc->clock_gating) {
2410 spin_lock_irq(&udc->lock);
2411 /* stop all usb activities */
2412 stop_activity(udc, udc->driver);
2413 spin_unlock_irq(&udc->lock);
2415 mv_udc_disable_internal(udc);
2421 static int mv_udc_resume(struct device *dev)
2426 udc = dev_get_drvdata(dev);
2428 /* if OTG is enabled, the following will be done in OTG driver*/
2429 if (udc->transceiver)
2432 if (!udc->clock_gating) {
2433 retval = mv_udc_enable_internal(udc);
2437 if (udc->driver && udc->softconnect) {
2447 static const struct dev_pm_ops mv_udc_pm_ops = {
2448 .suspend = mv_udc_suspend,
2449 .resume = mv_udc_resume,
2453 static void mv_udc_shutdown(struct platform_device *pdev)
2458 udc = platform_get_drvdata(pdev);
2459 /* reset controller mode to IDLE */
2461 mode = readl(&udc->op_regs->usbmode);
2463 writel(mode, &udc->op_regs->usbmode);
2464 mv_udc_disable(udc);
2467 static struct platform_driver udc_driver = {
2468 .probe = mv_udc_probe,
2469 .remove = mv_udc_remove,
2470 .shutdown = mv_udc_shutdown,
2472 .owner = THIS_MODULE,
2475 .pm = &mv_udc_pm_ops,
2480 module_platform_driver(udc_driver);
2481 MODULE_ALIAS("platform:mv-udc");
2482 MODULE_DESCRIPTION(DRIVER_DESC);
2483 MODULE_AUTHOR("Chao Xie <chao.xie@marvell.com>");
2484 MODULE_VERSION(DRIVER_VERSION);
2485 MODULE_LICENSE("GPL");