2 * omap_udc.c -- for OMAP full speed udc; most chips support OTG.
4 * Copyright (C) 2004 Texas Instruments, Inc.
5 * Copyright (C) 2004-2005 David Brownell
7 * OMAP2 & DMA support by Kyungmin Park <kyungmin.park@samsung.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/ioport.h>
21 #include <linux/types.h>
22 #include <linux/errno.h>
23 #include <linux/delay.h>
24 #include <linux/slab.h>
25 #include <linux/init.h>
26 #include <linux/timer.h>
27 #include <linux/list.h>
28 #include <linux/interrupt.h>
29 #include <linux/proc_fs.h>
31 #include <linux/moduleparam.h>
32 #include <linux/platform_device.h>
33 #include <linux/usb/ch9.h>
34 #include <linux/usb/gadget.h>
35 #include <linux/usb/otg.h>
36 #include <linux/dma-mapping.h>
37 #include <linux/clk.h>
38 #include <linux/prefetch.h>
40 #include <asm/byteorder.h>
43 #include <asm/unaligned.h>
44 #include <asm/mach-types.h>
53 /* bulk DMA seems to be behaving for both IN and OUT */
59 #define DRIVER_DESC "OMAP UDC driver"
60 #define DRIVER_VERSION "4 October 2004"
62 #define DMA_ADDR_INVALID (~(dma_addr_t)0)
64 #define OMAP2_DMA_CH(ch) (((ch) - 1) << 1)
65 #define OMAP24XX_DMA(name, ch) (OMAP24XX_DMA_##name + OMAP2_DMA_CH(ch))
68 * The OMAP UDC needs _very_ early endpoint setup: before enabling the
69 * D+ pullup to allow enumeration. That's too early for the gadget
70 * framework to use from usb_endpoint_enable(), which happens after
71 * enumeration as part of activating an interface. (But if we add an
72 * optional new "UDC not yet running" state to the gadget driver model,
73 * even just during driver binding, the endpoint autoconfig logic is the
74 * natural spot to manufacture new endpoints.)
76 * So instead of using endpoint enable calls to control the hardware setup,
77 * this driver defines a "fifo mode" parameter. It's used during driver
78 * initialization to choose among a set of pre-defined endpoint configs.
79 * See omap_udc_setup() for available modes, or to add others. That code
80 * lives in an init section, so use this driver as a module if you need
81 * to change the fifo mode after the kernel boots.
83 * Gadget drivers normally ignore endpoints they don't care about, and
84 * won't include them in configuration descriptors. That means only
85 * misbehaving hosts would even notice they exist.
88 static unsigned fifo_mode = 3;
90 static unsigned fifo_mode = 0;
93 /* "modprobe omap_udc fifo_mode=42", or else as a kernel
94 * boot parameter "omap_udc:fifo_mode=42"
96 module_param (fifo_mode, uint, 0);
97 MODULE_PARM_DESC (fifo_mode, "endpoint configuration");
100 static bool use_dma = 1;
102 /* "modprobe omap_udc use_dma=y", or else as a kernel
103 * boot parameter "omap_udc:use_dma=y"
105 module_param (use_dma, bool, 0);
106 MODULE_PARM_DESC (use_dma, "enable/disable DMA");
109 /* save a bit of code */
111 #endif /* !USE_DMA */
114 static const char driver_name [] = "omap_udc";
115 static const char driver_desc [] = DRIVER_DESC;
117 /*-------------------------------------------------------------------------*/
119 /* there's a notion of "current endpoint" for modifying endpoint
120 * state, and PIO access to its FIFO.
123 static void use_ep(struct omap_ep *ep, u16 select)
125 u16 num = ep->bEndpointAddress & 0x0f;
127 if (ep->bEndpointAddress & USB_DIR_IN)
129 omap_writew(num | select, UDC_EP_NUM);
130 /* when select, MUST deselect later !! */
133 static inline void deselect_ep(void)
137 w = omap_readw(UDC_EP_NUM);
139 omap_writew(w, UDC_EP_NUM);
140 /* 6 wait states before TX will happen */
143 static void dma_channel_claim(struct omap_ep *ep, unsigned preferred);
145 /*-------------------------------------------------------------------------*/
147 static int omap_ep_enable(struct usb_ep *_ep,
148 const struct usb_endpoint_descriptor *desc)
150 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
151 struct omap_udc *udc;
155 /* catch various bogus parameters */
156 if (!_ep || !desc || ep->desc
157 || desc->bDescriptorType != USB_DT_ENDPOINT
158 || ep->bEndpointAddress != desc->bEndpointAddress
159 || ep->maxpacket < usb_endpoint_maxp(desc)) {
160 DBG("%s, bad ep or descriptor\n", __func__);
163 maxp = usb_endpoint_maxp(desc);
164 if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
165 && maxp != ep->maxpacket)
166 || usb_endpoint_maxp(desc) > ep->maxpacket
167 || !desc->wMaxPacketSize) {
168 DBG("%s, bad %s maxpacket\n", __func__, _ep->name);
173 if ((desc->bmAttributes == USB_ENDPOINT_XFER_ISOC
174 && desc->bInterval != 1)) {
175 /* hardware wants period = 1; USB allows 2^(Interval-1) */
176 DBG("%s, unsupported ISO period %dms\n", _ep->name,
177 1 << (desc->bInterval - 1));
181 if (desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
182 DBG("%s, ISO nyet\n", _ep->name);
187 /* xfer types must match, except that interrupt ~= bulk */
188 if (ep->bmAttributes != desc->bmAttributes
189 && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
190 && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
191 DBG("%s, %s type mismatch\n", __func__, _ep->name);
196 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) {
197 DBG("%s, bogus device state\n", __func__);
201 spin_lock_irqsave(&udc->lock, flags);
206 ep->ep.maxpacket = maxp;
208 /* set endpoint to initial state */
212 use_ep(ep, UDC_EP_SEL);
213 omap_writew(udc->clr_halt, UDC_CTRL);
217 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
218 list_add(&ep->iso, &udc->iso);
220 /* maybe assign a DMA channel to this endpoint */
221 if (use_dma && desc->bmAttributes == USB_ENDPOINT_XFER_BULK)
222 /* FIXME ISO can dma, but prefers first channel */
223 dma_channel_claim(ep, 0);
225 /* PIO OUT may RX packets */
226 if (desc->bmAttributes != USB_ENDPOINT_XFER_ISOC
228 && !(ep->bEndpointAddress & USB_DIR_IN)) {
229 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
230 ep->ackwait = 1 + ep->double_buf;
233 spin_unlock_irqrestore(&udc->lock, flags);
234 VDBG("%s enabled\n", _ep->name);
238 static void nuke(struct omap_ep *, int status);
240 static int omap_ep_disable(struct usb_ep *_ep)
242 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
245 if (!_ep || !ep->desc) {
246 DBG("%s, %s not enabled\n", __func__,
247 _ep ? ep->ep.name : NULL);
251 spin_lock_irqsave(&ep->udc->lock, flags);
254 nuke (ep, -ESHUTDOWN);
255 ep->ep.maxpacket = ep->maxpacket;
257 omap_writew(UDC_SET_HALT, UDC_CTRL);
258 list_del_init(&ep->iso);
259 del_timer(&ep->timer);
261 spin_unlock_irqrestore(&ep->udc->lock, flags);
263 VDBG("%s disabled\n", _ep->name);
267 /*-------------------------------------------------------------------------*/
269 static struct usb_request *
270 omap_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
272 struct omap_req *req;
274 req = kzalloc(sizeof(*req), gfp_flags);
276 req->req.dma = DMA_ADDR_INVALID;
277 INIT_LIST_HEAD (&req->queue);
283 omap_free_request(struct usb_ep *ep, struct usb_request *_req)
285 struct omap_req *req = container_of(_req, struct omap_req, req);
291 /*-------------------------------------------------------------------------*/
294 done(struct omap_ep *ep, struct omap_req *req, int status)
296 unsigned stopped = ep->stopped;
298 list_del_init(&req->queue);
300 if (req->req.status == -EINPROGRESS)
301 req->req.status = status;
303 status = req->req.status;
305 if (use_dma && ep->has_dma) {
307 dma_unmap_single(ep->udc->gadget.dev.parent,
308 req->req.dma, req->req.length,
309 (ep->bEndpointAddress & USB_DIR_IN)
312 req->req.dma = DMA_ADDR_INVALID;
315 dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
316 req->req.dma, req->req.length,
317 (ep->bEndpointAddress & USB_DIR_IN)
323 if (status && status != -ESHUTDOWN)
325 VDBG("complete %s req %p stat %d len %u/%u\n",
326 ep->ep.name, &req->req, status,
327 req->req.actual, req->req.length);
329 /* don't modify queue heads during completion callback */
331 spin_unlock(&ep->udc->lock);
332 req->req.complete(&ep->ep, &req->req);
333 spin_lock(&ep->udc->lock);
334 ep->stopped = stopped;
337 /*-------------------------------------------------------------------------*/
339 #define UDC_FIFO_FULL (UDC_NON_ISO_FIFO_FULL | UDC_ISO_FIFO_FULL)
340 #define UDC_FIFO_UNWRITABLE (UDC_EP_HALTED | UDC_FIFO_FULL)
342 #define FIFO_EMPTY (UDC_NON_ISO_FIFO_EMPTY | UDC_ISO_FIFO_EMPTY)
343 #define FIFO_UNREADABLE (UDC_EP_HALTED | FIFO_EMPTY)
346 write_packet(u8 *buf, struct omap_req *req, unsigned max)
351 len = min(req->req.length - req->req.actual, max);
352 req->req.actual += len;
355 if (likely((((int)buf) & 1) == 0)) {
358 omap_writew(*wp++, UDC_DATA);
364 omap_writeb(*buf++, UDC_DATA);
368 // FIXME change r/w fifo calling convention
371 // return: 0 = still running, 1 = completed, negative = errno
372 static int write_fifo(struct omap_ep *ep, struct omap_req *req)
379 buf = req->req.buf + req->req.actual;
382 /* PIO-IN isn't double buffered except for iso */
383 ep_stat = omap_readw(UDC_STAT_FLG);
384 if (ep_stat & UDC_FIFO_UNWRITABLE)
387 count = ep->ep.maxpacket;
388 count = write_packet(buf, req, count);
389 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
392 /* last packet is often short (sometimes a zlp) */
393 if (count != ep->ep.maxpacket)
395 else if (req->req.length == req->req.actual
401 /* NOTE: requests complete when all IN data is in a
402 * FIFO (or sometimes later, if a zlp was needed).
403 * Use usb_ep_fifo_status() where needed.
411 read_packet(u8 *buf, struct omap_req *req, unsigned avail)
416 len = min(req->req.length - req->req.actual, avail);
417 req->req.actual += len;
420 if (likely((((int)buf) & 1) == 0)) {
423 *wp++ = omap_readw(UDC_DATA);
429 *buf++ = omap_readb(UDC_DATA);
433 // return: 0 = still running, 1 = queue empty, negative = errno
434 static int read_fifo(struct omap_ep *ep, struct omap_req *req)
437 unsigned count, avail;
440 buf = req->req.buf + req->req.actual;
444 u16 ep_stat = omap_readw(UDC_STAT_FLG);
447 if (ep_stat & FIFO_EMPTY) {
452 if (ep_stat & UDC_EP_HALTED)
455 if (ep_stat & UDC_FIFO_FULL)
456 avail = ep->ep.maxpacket;
458 avail = omap_readw(UDC_RXFSTAT);
459 ep->fnf = ep->double_buf;
461 count = read_packet(buf, req, avail);
463 /* partial packet reads may not be errors */
464 if (count < ep->ep.maxpacket) {
466 /* overflowed this request? flush extra data */
467 if (count != avail) {
468 req->req.status = -EOVERFLOW;
471 omap_readw(UDC_DATA);
473 } else if (req->req.length == req->req.actual)
478 if (!ep->bEndpointAddress)
487 /*-------------------------------------------------------------------------*/
489 static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start)
493 /* IN-DMA needs this on fault/cancel paths, so 15xx misreports
494 * the last transfer's bytecount by more than a FIFO's worth.
496 if (cpu_is_omap15xx())
499 end = omap_get_dma_src_pos(ep->lch);
500 if (end == ep->dma_counter)
503 end |= start & (0xffff << 16);
509 static u16 dma_dest_len(struct omap_ep *ep, dma_addr_t start)
513 end = omap_get_dma_dst_pos(ep->lch);
514 if (end == ep->dma_counter)
517 end |= start & (0xffff << 16);
518 if (cpu_is_omap15xx())
526 /* Each USB transfer request using DMA maps to one or more DMA transfers.
527 * When DMA completion isn't request completion, the UDC continues with
528 * the next DMA transfer for that USB transfer.
531 static void next_in_dma(struct omap_ep *ep, struct omap_req *req)
534 unsigned length = req->req.length - req->req.actual;
535 const int sync_mode = cpu_is_omap15xx()
536 ? OMAP_DMA_SYNC_FRAME
537 : OMAP_DMA_SYNC_ELEMENT;
540 if (cpu_is_omap24xx())
541 dma_trigger = OMAP24XX_DMA(USB_W2FC_TX0, ep->dma_channel);
543 /* measure length in either bytes or packets */
544 if ((cpu_is_omap16xx() && length <= UDC_TXN_TSC)
545 || (cpu_is_omap24xx() && length < ep->maxpacket)
546 || (cpu_is_omap15xx() && length < ep->maxpacket)) {
547 txdma_ctrl = UDC_TXN_EOT | length;
548 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8,
549 length, 1, sync_mode, dma_trigger, 0);
551 length = min(length / ep->maxpacket,
552 (unsigned) UDC_TXN_TSC + 1);
554 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
555 ep->ep.maxpacket >> 1, length, sync_mode,
557 length *= ep->maxpacket;
559 omap_set_dma_src_params(ep->lch, OMAP_DMA_PORT_EMIFF,
560 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
563 omap_start_dma(ep->lch);
564 ep->dma_counter = omap_get_dma_src_pos(ep->lch);
565 w = omap_readw(UDC_DMA_IRQ_EN);
566 w |= UDC_TX_DONE_IE(ep->dma_channel);
567 omap_writew(w, UDC_DMA_IRQ_EN);
568 omap_writew(UDC_TXN_START | txdma_ctrl, UDC_TXDMA(ep->dma_channel));
569 req->dma_bytes = length;
572 static void finish_in_dma(struct omap_ep *ep, struct omap_req *req, int status)
577 req->req.actual += req->dma_bytes;
579 /* return if this request needs to send data or zlp */
580 if (req->req.actual < req->req.length)
583 && req->dma_bytes != 0
584 && (req->req.actual % ep->maxpacket) == 0)
587 req->req.actual += dma_src_len(ep, req->req.dma
591 omap_stop_dma(ep->lch);
592 w = omap_readw(UDC_DMA_IRQ_EN);
593 w &= ~UDC_TX_DONE_IE(ep->dma_channel);
594 omap_writew(w, UDC_DMA_IRQ_EN);
595 done(ep, req, status);
598 static void next_out_dma(struct omap_ep *ep, struct omap_req *req)
600 unsigned packets = req->req.length - req->req.actual;
604 if (cpu_is_omap24xx())
605 dma_trigger = OMAP24XX_DMA(USB_W2FC_RX0, ep->dma_channel);
607 /* NOTE: we filtered out "short reads" before, so we know
608 * the buffer has only whole numbers of packets.
609 * except MODE SELECT(6) sent the 24 bytes data in OMAP24XX DMA mode
611 if (cpu_is_omap24xx() && packets < ep->maxpacket) {
612 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8,
613 packets, 1, OMAP_DMA_SYNC_ELEMENT,
615 req->dma_bytes = packets;
617 /* set up this DMA transfer, enable the fifo, start */
618 packets /= ep->ep.maxpacket;
619 packets = min(packets, (unsigned)UDC_RXN_TC + 1);
620 req->dma_bytes = packets * ep->ep.maxpacket;
621 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
622 ep->ep.maxpacket >> 1, packets,
623 OMAP_DMA_SYNC_ELEMENT,
626 omap_set_dma_dest_params(ep->lch, OMAP_DMA_PORT_EMIFF,
627 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
629 ep->dma_counter = omap_get_dma_dst_pos(ep->lch);
631 omap_writew(UDC_RXN_STOP | (packets - 1), UDC_RXDMA(ep->dma_channel));
632 w = omap_readw(UDC_DMA_IRQ_EN);
633 w |= UDC_RX_EOT_IE(ep->dma_channel);
634 omap_writew(w, UDC_DMA_IRQ_EN);
635 omap_writew(ep->bEndpointAddress & 0xf, UDC_EP_NUM);
636 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
638 omap_start_dma(ep->lch);
642 finish_out_dma(struct omap_ep *ep, struct omap_req *req, int status, int one)
647 ep->dma_counter = (u16) (req->req.dma + req->req.actual);
648 count = dma_dest_len(ep, req->req.dma + req->req.actual);
649 count += req->req.actual;
652 if (count <= req->req.length)
653 req->req.actual = count;
655 if (count != req->dma_bytes || status)
656 omap_stop_dma(ep->lch);
658 /* if this wasn't short, request may need another transfer */
659 else if (req->req.actual < req->req.length)
663 w = omap_readw(UDC_DMA_IRQ_EN);
664 w &= ~UDC_RX_EOT_IE(ep->dma_channel);
665 omap_writew(w, UDC_DMA_IRQ_EN);
666 done(ep, req, status);
669 static void dma_irq(struct omap_udc *udc, u16 irq_src)
671 u16 dman_stat = omap_readw(UDC_DMAN_STAT);
673 struct omap_req *req;
675 /* IN dma: tx to host */
676 if (irq_src & UDC_TXN_DONE) {
677 ep = &udc->ep[16 + UDC_DMA_TX_SRC(dman_stat)];
679 /* can see TXN_DONE after dma abort */
680 if (!list_empty(&ep->queue)) {
681 req = container_of(ep->queue.next,
682 struct omap_req, queue);
683 finish_in_dma(ep, req, 0);
685 omap_writew(UDC_TXN_DONE, UDC_IRQ_SRC);
687 if (!list_empty (&ep->queue)) {
688 req = container_of(ep->queue.next,
689 struct omap_req, queue);
690 next_in_dma(ep, req);
694 /* OUT dma: rx from host */
695 if (irq_src & UDC_RXN_EOT) {
696 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
698 /* can see RXN_EOT after dma abort */
699 if (!list_empty(&ep->queue)) {
700 req = container_of(ep->queue.next,
701 struct omap_req, queue);
702 finish_out_dma(ep, req, 0, dman_stat & UDC_DMA_RX_SB);
704 omap_writew(UDC_RXN_EOT, UDC_IRQ_SRC);
706 if (!list_empty (&ep->queue)) {
707 req = container_of(ep->queue.next,
708 struct omap_req, queue);
709 next_out_dma(ep, req);
713 if (irq_src & UDC_RXN_CNT) {
714 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
716 /* omap15xx does this unasked... */
717 VDBG("%s, RX_CNT irq?\n", ep->ep.name);
718 omap_writew(UDC_RXN_CNT, UDC_IRQ_SRC);
722 static void dma_error(int lch, u16 ch_status, void *data)
724 struct omap_ep *ep = data;
726 /* if ch_status & OMAP_DMA_DROP_IRQ ... */
727 /* if ch_status & OMAP1_DMA_TOUT_IRQ ... */
728 ERR("%s dma error, lch %d status %02x\n", ep->ep.name, lch, ch_status);
730 /* complete current transfer ... */
733 static void dma_channel_claim(struct omap_ep *ep, unsigned channel)
736 int status, restart, is_in;
739 is_in = ep->bEndpointAddress & USB_DIR_IN;
741 reg = omap_readw(UDC_TXDMA_CFG);
743 reg = omap_readw(UDC_RXDMA_CFG);
744 reg |= UDC_DMA_REQ; /* "pulse" activated */
748 if (channel == 0 || channel > 3) {
749 if ((reg & 0x0f00) == 0)
751 else if ((reg & 0x00f0) == 0)
753 else if ((reg & 0x000f) == 0) /* preferred for ISO */
760 reg |= (0x0f & ep->bEndpointAddress) << (4 * (channel - 1));
761 ep->dma_channel = channel;
764 if (cpu_is_omap24xx())
765 dma_channel = OMAP24XX_DMA(USB_W2FC_TX0, channel);
767 dma_channel = OMAP_DMA_USB_W2FC_TX0 - 1 + channel;
768 status = omap_request_dma(dma_channel,
769 ep->ep.name, dma_error, ep, &ep->lch);
771 omap_writew(reg, UDC_TXDMA_CFG);
773 omap_set_dma_src_burst_mode(ep->lch,
774 OMAP_DMA_DATA_BURST_4);
775 omap_set_dma_src_data_pack(ep->lch, 1);
777 omap_set_dma_dest_params(ep->lch,
779 OMAP_DMA_AMODE_CONSTANT,
784 if (cpu_is_omap24xx())
785 dma_channel = OMAP24XX_DMA(USB_W2FC_RX0, channel);
787 dma_channel = OMAP_DMA_USB_W2FC_RX0 - 1 + channel;
789 status = omap_request_dma(dma_channel,
790 ep->ep.name, dma_error, ep, &ep->lch);
792 omap_writew(reg, UDC_RXDMA_CFG);
794 omap_set_dma_src_params(ep->lch,
796 OMAP_DMA_AMODE_CONSTANT,
800 omap_set_dma_dest_burst_mode(ep->lch,
801 OMAP_DMA_DATA_BURST_4);
802 omap_set_dma_dest_data_pack(ep->lch, 1);
809 omap_disable_dma_irq(ep->lch, OMAP_DMA_BLOCK_IRQ);
811 /* channel type P: hw synch (fifo) */
812 if (cpu_class_is_omap1() && !cpu_is_omap15xx())
813 omap_set_dma_channel_mode(ep->lch, OMAP_DMA_LCH_P);
817 /* restart any queue, even if the claim failed */
818 restart = !ep->stopped && !list_empty(&ep->queue);
821 DBG("%s no dma channel: %d%s\n", ep->ep.name, status,
822 restart ? " (restart)" : "");
824 DBG("%s claimed %cxdma%d lch %d%s\n", ep->ep.name,
826 ep->dma_channel - 1, ep->lch,
827 restart ? " (restart)" : "");
830 struct omap_req *req;
831 req = container_of(ep->queue.next, struct omap_req, queue);
833 (is_in ? next_in_dma : next_out_dma)(ep, req);
835 use_ep(ep, UDC_EP_SEL);
836 (is_in ? write_fifo : read_fifo)(ep, req);
839 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
840 ep->ackwait = 1 + ep->double_buf;
842 /* IN: 6 wait states before it'll tx */
847 static void dma_channel_release(struct omap_ep *ep)
849 int shift = 4 * (ep->dma_channel - 1);
850 u16 mask = 0x0f << shift;
851 struct omap_req *req;
854 /* abort any active usb transfer request */
855 if (!list_empty(&ep->queue))
856 req = container_of(ep->queue.next, struct omap_req, queue);
860 active = omap_get_dma_active_status(ep->lch);
862 DBG("%s release %s %cxdma%d %p\n", ep->ep.name,
863 active ? "active" : "idle",
864 (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
865 ep->dma_channel - 1, req);
867 /* NOTE: re-setting RX_REQ/TX_REQ because of a chip bug (before
868 * OMAP 1710 ES2.0) where reading the DMA_CFG can clear them.
871 /* wait till current packet DMA finishes, and fifo empties */
872 if (ep->bEndpointAddress & USB_DIR_IN) {
873 omap_writew((omap_readw(UDC_TXDMA_CFG) & ~mask) | UDC_DMA_REQ,
877 finish_in_dma(ep, req, -ECONNRESET);
879 /* clear FIFO; hosts probably won't empty it */
880 use_ep(ep, UDC_EP_SEL);
881 omap_writew(UDC_CLR_EP, UDC_CTRL);
884 while (omap_readw(UDC_TXDMA_CFG) & mask)
887 omap_writew((omap_readw(UDC_RXDMA_CFG) & ~mask) | UDC_DMA_REQ,
890 /* dma empties the fifo */
891 while (omap_readw(UDC_RXDMA_CFG) & mask)
894 finish_out_dma(ep, req, -ECONNRESET, 0);
896 omap_free_dma(ep->lch);
899 /* has_dma still set, till endpoint is fully quiesced */
903 /*-------------------------------------------------------------------------*/
906 omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
908 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
909 struct omap_req *req = container_of(_req, struct omap_req, req);
910 struct omap_udc *udc;
914 /* catch various bogus parameters */
915 if (!_req || !req->req.complete || !req->req.buf
916 || !list_empty(&req->queue)) {
917 DBG("%s, bad params\n", __func__);
920 if (!_ep || (!ep->desc && ep->bEndpointAddress)) {
921 DBG("%s, bad ep\n", __func__);
924 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
925 if (req->req.length > ep->ep.maxpacket)
930 /* this isn't bogus, but OMAP DMA isn't the only hardware to
931 * have a hard time with partial packet reads... reject it.
932 * Except OMAP2 can handle the small packets.
936 && ep->bEndpointAddress != 0
937 && (ep->bEndpointAddress & USB_DIR_IN) == 0
938 && !cpu_class_is_omap2()
939 && (req->req.length % ep->ep.maxpacket) != 0) {
940 DBG("%s, no partial packet OUT reads\n", __func__);
945 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
948 if (use_dma && ep->has_dma) {
949 if (req->req.dma == DMA_ADDR_INVALID) {
950 req->req.dma = dma_map_single(
951 ep->udc->gadget.dev.parent,
954 (ep->bEndpointAddress & USB_DIR_IN)
959 dma_sync_single_for_device(
960 ep->udc->gadget.dev.parent,
961 req->req.dma, req->req.length,
962 (ep->bEndpointAddress & USB_DIR_IN)
969 VDBG("%s queue req %p, len %d buf %p\n",
970 ep->ep.name, _req, _req->length, _req->buf);
972 spin_lock_irqsave(&udc->lock, flags);
974 req->req.status = -EINPROGRESS;
977 /* maybe kickstart non-iso i/o queues */
981 w = omap_readw(UDC_IRQ_EN);
983 omap_writew(w, UDC_IRQ_EN);
984 } else if (list_empty(&ep->queue) && !ep->stopped && !ep->ackwait) {
987 if (ep->bEndpointAddress == 0) {
988 if (!udc->ep0_pending || !list_empty (&ep->queue)) {
989 spin_unlock_irqrestore(&udc->lock, flags);
993 /* empty DATA stage? */
995 if (!req->req.length) {
997 /* chip became CONFIGURED or ADDRESSED
998 * earlier; drivers may already have queued
999 * requests to non-control endpoints
1001 if (udc->ep0_set_config) {
1002 u16 irq_en = omap_readw(UDC_IRQ_EN);
1004 irq_en |= UDC_DS_CHG_IE | UDC_EP0_IE;
1005 if (!udc->ep0_reset_config)
1006 irq_en |= UDC_EPN_RX_IE
1008 omap_writew(irq_en, UDC_IRQ_EN);
1011 /* STATUS for zero length DATA stages is
1012 * always an IN ... even for IN transfers,
1013 * a weird case which seem to stall OMAP.
1015 omap_writew(UDC_EP_SEL | UDC_EP_DIR, UDC_EP_NUM);
1016 omap_writew(UDC_CLR_EP, UDC_CTRL);
1017 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1018 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1021 udc->ep0_pending = 0;
1025 /* non-empty DATA stage */
1027 omap_writew(UDC_EP_SEL | UDC_EP_DIR, UDC_EP_NUM);
1031 omap_writew(UDC_EP_SEL, UDC_EP_NUM);
1034 is_in = ep->bEndpointAddress & USB_DIR_IN;
1036 use_ep(ep, UDC_EP_SEL);
1037 /* if ISO: SOF IRQs must be enabled/disabled! */
1041 (is_in ? next_in_dma : next_out_dma)(ep, req);
1043 if ((is_in ? write_fifo : read_fifo)(ep, req) == 1)
1047 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1048 ep->ackwait = 1 + ep->double_buf;
1050 /* IN: 6 wait states before it'll tx */
1055 /* irq handler advances the queue */
1057 list_add_tail(&req->queue, &ep->queue);
1058 spin_unlock_irqrestore(&udc->lock, flags);
1063 static int omap_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1065 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
1066 struct omap_req *req;
1067 unsigned long flags;
1072 spin_lock_irqsave(&ep->udc->lock, flags);
1074 /* make sure it's actually queued on this endpoint */
1075 list_for_each_entry (req, &ep->queue, queue) {
1076 if (&req->req == _req)
1079 if (&req->req != _req) {
1080 spin_unlock_irqrestore(&ep->udc->lock, flags);
1084 if (use_dma && ep->dma_channel && ep->queue.next == &req->queue) {
1085 int channel = ep->dma_channel;
1087 /* releasing the channel cancels the request,
1088 * reclaiming the channel restarts the queue
1090 dma_channel_release(ep);
1091 dma_channel_claim(ep, channel);
1093 done(ep, req, -ECONNRESET);
1094 spin_unlock_irqrestore(&ep->udc->lock, flags);
1098 /*-------------------------------------------------------------------------*/
1100 static int omap_ep_set_halt(struct usb_ep *_ep, int value)
1102 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
1103 unsigned long flags;
1104 int status = -EOPNOTSUPP;
1106 spin_lock_irqsave(&ep->udc->lock, flags);
1108 /* just use protocol stalls for ep0; real halts are annoying */
1109 if (ep->bEndpointAddress == 0) {
1110 if (!ep->udc->ep0_pending)
1113 if (ep->udc->ep0_set_config) {
1114 WARNING("error changing config?\n");
1115 omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1117 omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1118 ep->udc->ep0_pending = 0;
1123 /* otherwise, all active non-ISO endpoints can halt */
1124 } else if (ep->bmAttributes != USB_ENDPOINT_XFER_ISOC && ep->desc) {
1126 /* IN endpoints must already be idle */
1127 if ((ep->bEndpointAddress & USB_DIR_IN)
1128 && !list_empty(&ep->queue)) {
1136 if (use_dma && ep->dma_channel
1137 && !list_empty(&ep->queue)) {
1138 channel = ep->dma_channel;
1139 dma_channel_release(ep);
1143 use_ep(ep, UDC_EP_SEL);
1144 if (omap_readw(UDC_STAT_FLG) & UDC_NON_ISO_FIFO_EMPTY) {
1145 omap_writew(UDC_SET_HALT, UDC_CTRL);
1152 dma_channel_claim(ep, channel);
1155 omap_writew(ep->udc->clr_halt, UDC_CTRL);
1157 if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1158 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1159 ep->ackwait = 1 + ep->double_buf;
1164 VDBG("%s %s halt stat %d\n", ep->ep.name,
1165 value ? "set" : "clear", status);
1167 spin_unlock_irqrestore(&ep->udc->lock, flags);
1171 static struct usb_ep_ops omap_ep_ops = {
1172 .enable = omap_ep_enable,
1173 .disable = omap_ep_disable,
1175 .alloc_request = omap_alloc_request,
1176 .free_request = omap_free_request,
1178 .queue = omap_ep_queue,
1179 .dequeue = omap_ep_dequeue,
1181 .set_halt = omap_ep_set_halt,
1182 // fifo_status ... report bytes in fifo
1183 // fifo_flush ... flush fifo
1186 /*-------------------------------------------------------------------------*/
1188 static int omap_get_frame(struct usb_gadget *gadget)
1190 u16 sof = omap_readw(UDC_SOF);
1191 return (sof & UDC_TS_OK) ? (sof & UDC_TS) : -EL2NSYNC;
1194 static int omap_wakeup(struct usb_gadget *gadget)
1196 struct omap_udc *udc;
1197 unsigned long flags;
1198 int retval = -EHOSTUNREACH;
1200 udc = container_of(gadget, struct omap_udc, gadget);
1202 spin_lock_irqsave(&udc->lock, flags);
1203 if (udc->devstat & UDC_SUS) {
1204 /* NOTE: OTG spec erratum says that OTG devices may
1205 * issue wakeups without host enable.
1207 if (udc->devstat & (UDC_B_HNP_ENABLE|UDC_R_WK_OK)) {
1208 DBG("remote wakeup...\n");
1209 omap_writew(UDC_RMT_WKP, UDC_SYSCON2);
1213 /* NOTE: non-OTG systems may use SRP TOO... */
1214 } else if (!(udc->devstat & UDC_ATT)) {
1215 if (udc->transceiver)
1216 retval = otg_start_srp(udc->transceiver->otg);
1218 spin_unlock_irqrestore(&udc->lock, flags);
1224 omap_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered)
1226 struct omap_udc *udc;
1227 unsigned long flags;
1230 udc = container_of(gadget, struct omap_udc, gadget);
1231 spin_lock_irqsave(&udc->lock, flags);
1232 syscon1 = omap_readw(UDC_SYSCON1);
1234 syscon1 |= UDC_SELF_PWR;
1236 syscon1 &= ~UDC_SELF_PWR;
1237 omap_writew(syscon1, UDC_SYSCON1);
1238 spin_unlock_irqrestore(&udc->lock, flags);
1243 static int can_pullup(struct omap_udc *udc)
1245 return udc->driver && udc->softconnect && udc->vbus_active;
1248 static void pullup_enable(struct omap_udc *udc)
1252 w = omap_readw(UDC_SYSCON1);
1254 omap_writew(w, UDC_SYSCON1);
1255 if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) {
1258 l = omap_readl(OTG_CTRL);
1260 omap_writel(l, OTG_CTRL);
1262 omap_writew(UDC_DS_CHG_IE, UDC_IRQ_EN);
1265 static void pullup_disable(struct omap_udc *udc)
1269 if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) {
1272 l = omap_readl(OTG_CTRL);
1274 omap_writel(l, OTG_CTRL);
1276 omap_writew(UDC_DS_CHG_IE, UDC_IRQ_EN);
1277 w = omap_readw(UDC_SYSCON1);
1278 w &= ~UDC_PULLUP_EN;
1279 omap_writew(w, UDC_SYSCON1);
1282 static struct omap_udc *udc;
1284 static void omap_udc_enable_clock(int enable)
1286 if (udc == NULL || udc->dc_clk == NULL || udc->hhc_clk == NULL)
1290 clk_enable(udc->dc_clk);
1291 clk_enable(udc->hhc_clk);
1294 clk_disable(udc->hhc_clk);
1295 clk_disable(udc->dc_clk);
1300 * Called by whatever detects VBUS sessions: external transceiver
1301 * driver, or maybe GPIO0 VBUS IRQ. May request 48 MHz clock.
1303 static int omap_vbus_session(struct usb_gadget *gadget, int is_active)
1305 struct omap_udc *udc;
1306 unsigned long flags;
1309 udc = container_of(gadget, struct omap_udc, gadget);
1310 spin_lock_irqsave(&udc->lock, flags);
1311 VDBG("VBUS %s\n", is_active ? "on" : "off");
1312 udc->vbus_active = (is_active != 0);
1313 if (cpu_is_omap15xx()) {
1314 /* "software" detect, ignored if !VBUS_MODE_1510 */
1315 l = omap_readl(FUNC_MUX_CTRL_0);
1317 l |= VBUS_CTRL_1510;
1319 l &= ~VBUS_CTRL_1510;
1320 omap_writel(l, FUNC_MUX_CTRL_0);
1322 if (udc->dc_clk != NULL && is_active) {
1323 if (!udc->clk_requested) {
1324 omap_udc_enable_clock(1);
1325 udc->clk_requested = 1;
1328 if (can_pullup(udc))
1331 pullup_disable(udc);
1332 if (udc->dc_clk != NULL && !is_active) {
1333 if (udc->clk_requested) {
1334 omap_udc_enable_clock(0);
1335 udc->clk_requested = 0;
1338 spin_unlock_irqrestore(&udc->lock, flags);
1342 static int omap_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1344 struct omap_udc *udc;
1346 udc = container_of(gadget, struct omap_udc, gadget);
1347 if (udc->transceiver)
1348 return usb_phy_set_power(udc->transceiver, mA);
1352 static int omap_pullup(struct usb_gadget *gadget, int is_on)
1354 struct omap_udc *udc;
1355 unsigned long flags;
1357 udc = container_of(gadget, struct omap_udc, gadget);
1358 spin_lock_irqsave(&udc->lock, flags);
1359 udc->softconnect = (is_on != 0);
1360 if (can_pullup(udc))
1363 pullup_disable(udc);
1364 spin_unlock_irqrestore(&udc->lock, flags);
1368 static int omap_udc_start(struct usb_gadget_driver *driver,
1369 int (*bind)(struct usb_gadget *));
1370 static int omap_udc_stop(struct usb_gadget_driver *driver);
1372 static struct usb_gadget_ops omap_gadget_ops = {
1373 .get_frame = omap_get_frame,
1374 .wakeup = omap_wakeup,
1375 .set_selfpowered = omap_set_selfpowered,
1376 .vbus_session = omap_vbus_session,
1377 .vbus_draw = omap_vbus_draw,
1378 .pullup = omap_pullup,
1379 .start = omap_udc_start,
1380 .stop = omap_udc_stop,
1383 /*-------------------------------------------------------------------------*/
1385 /* dequeue ALL requests; caller holds udc->lock */
1386 static void nuke(struct omap_ep *ep, int status)
1388 struct omap_req *req;
1392 if (use_dma && ep->dma_channel)
1393 dma_channel_release(ep);
1396 omap_writew(UDC_CLR_EP, UDC_CTRL);
1397 if (ep->bEndpointAddress && ep->bmAttributes != USB_ENDPOINT_XFER_ISOC)
1398 omap_writew(UDC_SET_HALT, UDC_CTRL);
1400 while (!list_empty(&ep->queue)) {
1401 req = list_entry(ep->queue.next, struct omap_req, queue);
1402 done(ep, req, status);
1406 /* caller holds udc->lock */
1407 static void udc_quiesce(struct omap_udc *udc)
1411 udc->gadget.speed = USB_SPEED_UNKNOWN;
1412 nuke(&udc->ep[0], -ESHUTDOWN);
1413 list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list)
1414 nuke(ep, -ESHUTDOWN);
1417 /*-------------------------------------------------------------------------*/
1419 static void update_otg(struct omap_udc *udc)
1423 if (!gadget_is_otg(&udc->gadget))
1426 if (omap_readl(OTG_CTRL) & OTG_ID)
1427 devstat = omap_readw(UDC_DEVSTAT);
1431 udc->gadget.b_hnp_enable = !!(devstat & UDC_B_HNP_ENABLE);
1432 udc->gadget.a_hnp_support = !!(devstat & UDC_A_HNP_SUPPORT);
1433 udc->gadget.a_alt_hnp_support = !!(devstat & UDC_A_ALT_HNP_SUPPORT);
1435 /* Enable HNP early, avoiding races on suspend irq path.
1436 * ASSUMES OTG state machine B_BUS_REQ input is true.
1438 if (udc->gadget.b_hnp_enable) {
1441 l = omap_readl(OTG_CTRL);
1442 l |= OTG_B_HNPEN | OTG_B_BUSREQ;
1444 omap_writel(l, OTG_CTRL);
1448 static void ep0_irq(struct omap_udc *udc, u16 irq_src)
1450 struct omap_ep *ep0 = &udc->ep[0];
1451 struct omap_req *req = NULL;
1455 /* Clear any pending requests and then scrub any rx/tx state
1456 * before starting to handle the SETUP request.
1458 if (irq_src & UDC_SETUP) {
1459 u16 ack = irq_src & (UDC_EP0_TX|UDC_EP0_RX);
1463 omap_writew(ack, UDC_IRQ_SRC);
1464 irq_src = UDC_SETUP;
1468 /* IN/OUT packets mean we're in the DATA or STATUS stage.
1469 * This driver uses only uses protocol stalls (ep0 never halts),
1470 * and if we got this far the gadget driver already had a
1471 * chance to stall. Tries to be forgiving of host oddities.
1473 * NOTE: the last chance gadget drivers have to stall control
1474 * requests is during their request completion callback.
1476 if (!list_empty(&ep0->queue))
1477 req = container_of(ep0->queue.next, struct omap_req, queue);
1479 /* IN == TX to host */
1480 if (irq_src & UDC_EP0_TX) {
1483 omap_writew(UDC_EP0_TX, UDC_IRQ_SRC);
1484 omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1485 stat = omap_readw(UDC_STAT_FLG);
1486 if (stat & UDC_ACK) {
1488 /* write next IN packet from response,
1489 * or set up the status stage.
1492 stat = write_fifo(ep0, req);
1493 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1494 if (!req && udc->ep0_pending) {
1495 omap_writew(UDC_EP_SEL, UDC_EP_NUM);
1496 omap_writew(UDC_CLR_EP, UDC_CTRL);
1497 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1498 omap_writew(0, UDC_EP_NUM);
1499 udc->ep0_pending = 0;
1500 } /* else: 6 wait states before it'll tx */
1502 /* ack status stage of OUT transfer */
1503 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1508 } else if (stat & UDC_STALL) {
1509 omap_writew(UDC_CLR_HALT, UDC_CTRL);
1510 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1512 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1516 /* OUT == RX from host */
1517 if (irq_src & UDC_EP0_RX) {
1520 omap_writew(UDC_EP0_RX, UDC_IRQ_SRC);
1521 omap_writew(UDC_EP_SEL, UDC_EP_NUM);
1522 stat = omap_readw(UDC_STAT_FLG);
1523 if (stat & UDC_ACK) {
1526 /* read next OUT packet of request, maybe
1527 * reactiviting the fifo; stall on errors.
1529 if (!req || (stat = read_fifo(ep0, req)) < 0) {
1530 omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1531 udc->ep0_pending = 0;
1533 } else if (stat == 0)
1534 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1535 omap_writew(0, UDC_EP_NUM);
1537 /* activate status stage */
1540 /* that may have STALLed ep0... */
1541 omap_writew(UDC_EP_SEL | UDC_EP_DIR,
1543 omap_writew(UDC_CLR_EP, UDC_CTRL);
1544 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1545 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1546 udc->ep0_pending = 0;
1549 /* ack status stage of IN transfer */
1550 omap_writew(0, UDC_EP_NUM);
1554 } else if (stat & UDC_STALL) {
1555 omap_writew(UDC_CLR_HALT, UDC_CTRL);
1556 omap_writew(0, UDC_EP_NUM);
1558 omap_writew(0, UDC_EP_NUM);
1562 /* SETUP starts all control transfers */
1563 if (irq_src & UDC_SETUP) {
1566 struct usb_ctrlrequest r;
1568 int status = -EINVAL;
1571 /* read the (latest) SETUP message */
1573 omap_writew(UDC_SETUP_SEL, UDC_EP_NUM);
1574 /* two bytes at a time */
1575 u.word[0] = omap_readw(UDC_DATA);
1576 u.word[1] = omap_readw(UDC_DATA);
1577 u.word[2] = omap_readw(UDC_DATA);
1578 u.word[3] = omap_readw(UDC_DATA);
1579 omap_writew(0, UDC_EP_NUM);
1580 } while (omap_readw(UDC_IRQ_SRC) & UDC_SETUP);
1582 #define w_value le16_to_cpu(u.r.wValue)
1583 #define w_index le16_to_cpu(u.r.wIndex)
1584 #define w_length le16_to_cpu(u.r.wLength)
1586 /* Delegate almost all control requests to the gadget driver,
1587 * except for a handful of ch9 status/feature requests that
1588 * hardware doesn't autodecode _and_ the gadget API hides.
1590 udc->ep0_in = (u.r.bRequestType & USB_DIR_IN) != 0;
1591 udc->ep0_set_config = 0;
1592 udc->ep0_pending = 1;
1595 switch (u.r.bRequest) {
1596 case USB_REQ_SET_CONFIGURATION:
1597 /* udc needs to know when ep != 0 is valid */
1598 if (u.r.bRequestType != USB_RECIP_DEVICE)
1602 udc->ep0_set_config = 1;
1603 udc->ep0_reset_config = (w_value == 0);
1604 VDBG("set config %d\n", w_value);
1606 /* update udc NOW since gadget driver may start
1607 * queueing requests immediately; clear config
1608 * later if it fails the request.
1610 if (udc->ep0_reset_config)
1611 omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1613 omap_writew(UDC_DEV_CFG, UDC_SYSCON2);
1616 case USB_REQ_CLEAR_FEATURE:
1617 /* clear endpoint halt */
1618 if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1620 if (w_value != USB_ENDPOINT_HALT
1623 ep = &udc->ep[w_index & 0xf];
1625 if (w_index & USB_DIR_IN)
1627 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1631 omap_writew(udc->clr_halt, UDC_CTRL);
1633 if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1634 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1635 ep->ackwait = 1 + ep->double_buf;
1637 /* NOTE: assumes the host behaves sanely,
1638 * only clearing real halts. Else we may
1639 * need to kill pending transfers and then
1640 * restart the queue... very messy for DMA!
1643 VDBG("%s halt cleared by host\n", ep->name);
1644 goto ep0out_status_stage;
1645 case USB_REQ_SET_FEATURE:
1646 /* set endpoint halt */
1647 if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1649 if (w_value != USB_ENDPOINT_HALT
1652 ep = &udc->ep[w_index & 0xf];
1653 if (w_index & USB_DIR_IN)
1655 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1656 || ep == ep0 || !ep->desc)
1658 if (use_dma && ep->has_dma) {
1659 /* this has rude side-effects (aborts) and
1660 * can't really work if DMA-IN is active
1662 DBG("%s host set_halt, NYET \n", ep->name);
1666 /* can't halt if fifo isn't empty... */
1667 omap_writew(UDC_CLR_EP, UDC_CTRL);
1668 omap_writew(UDC_SET_HALT, UDC_CTRL);
1669 VDBG("%s halted by host\n", ep->name);
1670 ep0out_status_stage:
1672 omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1673 omap_writew(UDC_CLR_EP, UDC_CTRL);
1674 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1675 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1676 udc->ep0_pending = 0;
1678 case USB_REQ_GET_STATUS:
1679 /* USB_ENDPOINT_HALT status? */
1680 if (u.r.bRequestType != (USB_DIR_IN|USB_RECIP_ENDPOINT))
1683 /* ep0 never stalls */
1684 if (!(w_index & 0xf))
1687 /* only active endpoints count */
1688 ep = &udc->ep[w_index & 0xf];
1689 if (w_index & USB_DIR_IN)
1694 /* iso never stalls */
1695 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
1698 /* FIXME don't assume non-halted endpoints!! */
1699 ERR("%s status, can't report\n", ep->ep.name);
1703 /* return interface status. if we were pedantic,
1704 * we'd detect non-existent interfaces, and stall.
1706 if (u.r.bRequestType
1707 != (USB_DIR_IN|USB_RECIP_INTERFACE))
1711 /* return two zero bytes */
1712 omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1713 omap_writew(0, UDC_DATA);
1714 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1715 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1717 VDBG("GET_STATUS, interface %d\n", w_index);
1718 /* next, status stage */
1722 /* activate the ep0out fifo right away */
1723 if (!udc->ep0_in && w_length) {
1724 omap_writew(0, UDC_EP_NUM);
1725 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1728 /* gadget drivers see class/vendor specific requests,
1729 * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION},
1732 VDBG("SETUP %02x.%02x v%04x i%04x l%04x\n",
1733 u.r.bRequestType, u.r.bRequest,
1734 w_value, w_index, w_length);
1740 /* The gadget driver may return an error here,
1741 * causing an immediate protocol stall.
1743 * Else it must issue a response, either queueing a
1744 * response buffer for the DATA stage, or halting ep0
1745 * (causing a protocol stall, not a real halt). A
1746 * zero length buffer means no DATA stage.
1748 * It's fine to issue that response after the setup()
1749 * call returns, and this IRQ was handled.
1752 spin_unlock(&udc->lock);
1753 status = udc->driver->setup (&udc->gadget, &u.r);
1754 spin_lock(&udc->lock);
1760 VDBG("req %02x.%02x protocol STALL; stat %d\n",
1761 u.r.bRequestType, u.r.bRequest, status);
1762 if (udc->ep0_set_config) {
1763 if (udc->ep0_reset_config)
1764 WARNING("error resetting config?\n");
1766 omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1768 omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1769 udc->ep0_pending = 0;
1774 /*-------------------------------------------------------------------------*/
1776 #define OTG_FLAGS (UDC_B_HNP_ENABLE|UDC_A_HNP_SUPPORT|UDC_A_ALT_HNP_SUPPORT)
1778 static void devstate_irq(struct omap_udc *udc, u16 irq_src)
1780 u16 devstat, change;
1782 devstat = omap_readw(UDC_DEVSTAT);
1783 change = devstat ^ udc->devstat;
1784 udc->devstat = devstat;
1786 if (change & (UDC_USB_RESET|UDC_ATT)) {
1789 if (change & UDC_ATT) {
1790 /* driver for any external transceiver will
1791 * have called omap_vbus_session() already
1793 if (devstat & UDC_ATT) {
1794 udc->gadget.speed = USB_SPEED_FULL;
1796 if (!udc->transceiver)
1798 // if (driver->connect) call it
1799 } else if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1800 udc->gadget.speed = USB_SPEED_UNKNOWN;
1801 if (!udc->transceiver)
1802 pullup_disable(udc);
1803 DBG("disconnect, gadget %s\n",
1804 udc->driver->driver.name);
1805 if (udc->driver->disconnect) {
1806 spin_unlock(&udc->lock);
1807 udc->driver->disconnect(&udc->gadget);
1808 spin_lock(&udc->lock);
1814 if (change & UDC_USB_RESET) {
1815 if (devstat & UDC_USB_RESET) {
1818 udc->gadget.speed = USB_SPEED_FULL;
1819 INFO("USB reset done, gadget %s\n",
1820 udc->driver->driver.name);
1821 /* ep0 traffic is legal from now on */
1822 omap_writew(UDC_DS_CHG_IE | UDC_EP0_IE,
1825 change &= ~UDC_USB_RESET;
1828 if (change & UDC_SUS) {
1829 if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1830 // FIXME tell isp1301 to suspend/resume (?)
1831 if (devstat & UDC_SUS) {
1834 /* HNP could be under way already */
1835 if (udc->gadget.speed == USB_SPEED_FULL
1836 && udc->driver->suspend) {
1837 spin_unlock(&udc->lock);
1838 udc->driver->suspend(&udc->gadget);
1839 spin_lock(&udc->lock);
1841 if (udc->transceiver)
1842 usb_phy_set_suspend(
1843 udc->transceiver, 1);
1846 if (udc->transceiver)
1847 usb_phy_set_suspend(
1848 udc->transceiver, 0);
1849 if (udc->gadget.speed == USB_SPEED_FULL
1850 && udc->driver->resume) {
1851 spin_unlock(&udc->lock);
1852 udc->driver->resume(&udc->gadget);
1853 spin_lock(&udc->lock);
1859 if (!cpu_is_omap15xx() && (change & OTG_FLAGS)) {
1861 change &= ~OTG_FLAGS;
1864 change &= ~(UDC_CFG|UDC_DEF|UDC_ADD);
1866 VDBG("devstat %03x, ignore change %03x\n",
1869 omap_writew(UDC_DS_CHG, UDC_IRQ_SRC);
1872 static irqreturn_t omap_udc_irq(int irq, void *_udc)
1874 struct omap_udc *udc = _udc;
1876 irqreturn_t status = IRQ_NONE;
1877 unsigned long flags;
1879 spin_lock_irqsave(&udc->lock, flags);
1880 irq_src = omap_readw(UDC_IRQ_SRC);
1882 /* Device state change (usb ch9 stuff) */
1883 if (irq_src & UDC_DS_CHG) {
1884 devstate_irq(_udc, irq_src);
1885 status = IRQ_HANDLED;
1886 irq_src &= ~UDC_DS_CHG;
1889 /* EP0 control transfers */
1890 if (irq_src & (UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX)) {
1891 ep0_irq(_udc, irq_src);
1892 status = IRQ_HANDLED;
1893 irq_src &= ~(UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX);
1896 /* DMA transfer completion */
1897 if (use_dma && (irq_src & (UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT))) {
1898 dma_irq(_udc, irq_src);
1899 status = IRQ_HANDLED;
1900 irq_src &= ~(UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT);
1903 irq_src &= ~(UDC_IRQ_SOF | UDC_EPN_TX|UDC_EPN_RX);
1905 DBG("udc_irq, unhandled %03x\n", irq_src);
1906 spin_unlock_irqrestore(&udc->lock, flags);
1911 /* workaround for seemingly-lost IRQs for RX ACKs... */
1912 #define PIO_OUT_TIMEOUT (jiffies + HZ/3)
1913 #define HALF_FULL(f) (!((f)&(UDC_NON_ISO_FIFO_FULL|UDC_NON_ISO_FIFO_EMPTY)))
1915 static void pio_out_timer(unsigned long _ep)
1917 struct omap_ep *ep = (void *) _ep;
1918 unsigned long flags;
1921 spin_lock_irqsave(&ep->udc->lock, flags);
1922 if (!list_empty(&ep->queue) && ep->ackwait) {
1923 use_ep(ep, UDC_EP_SEL);
1924 stat_flg = omap_readw(UDC_STAT_FLG);
1926 if ((stat_flg & UDC_ACK) && (!(stat_flg & UDC_FIFO_EN)
1927 || (ep->double_buf && HALF_FULL(stat_flg)))) {
1928 struct omap_req *req;
1930 VDBG("%s: lose, %04x\n", ep->ep.name, stat_flg);
1931 req = container_of(ep->queue.next,
1932 struct omap_req, queue);
1933 (void) read_fifo(ep, req);
1934 omap_writew(ep->bEndpointAddress, UDC_EP_NUM);
1935 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1936 ep->ackwait = 1 + ep->double_buf;
1940 mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1941 spin_unlock_irqrestore(&ep->udc->lock, flags);
1944 static irqreturn_t omap_udc_pio_irq(int irq, void *_dev)
1946 u16 epn_stat, irq_src;
1947 irqreturn_t status = IRQ_NONE;
1950 struct omap_udc *udc = _dev;
1951 struct omap_req *req;
1952 unsigned long flags;
1954 spin_lock_irqsave(&udc->lock, flags);
1955 epn_stat = omap_readw(UDC_EPN_STAT);
1956 irq_src = omap_readw(UDC_IRQ_SRC);
1958 /* handle OUT first, to avoid some wasteful NAKs */
1959 if (irq_src & UDC_EPN_RX) {
1960 epnum = (epn_stat >> 8) & 0x0f;
1961 omap_writew(UDC_EPN_RX, UDC_IRQ_SRC);
1962 status = IRQ_HANDLED;
1963 ep = &udc->ep[epnum];
1966 omap_writew(epnum | UDC_EP_SEL, UDC_EP_NUM);
1968 if (omap_readw(UDC_STAT_FLG) & UDC_ACK) {
1970 if (!list_empty(&ep->queue)) {
1972 req = container_of(ep->queue.next,
1973 struct omap_req, queue);
1974 stat = read_fifo(ep, req);
1975 if (!ep->double_buf)
1979 /* min 6 clock delay before clearing EP_SEL ... */
1980 epn_stat = omap_readw(UDC_EPN_STAT);
1981 epn_stat = omap_readw(UDC_EPN_STAT);
1982 omap_writew(epnum, UDC_EP_NUM);
1984 /* enabling fifo _after_ clearing ACK, contrary to docs,
1985 * reduces lossage; timer still needed though (sigh).
1988 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1989 ep->ackwait = 1 + ep->double_buf;
1991 mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1994 /* then IN transfers */
1995 else if (irq_src & UDC_EPN_TX) {
1996 epnum = epn_stat & 0x0f;
1997 omap_writew(UDC_EPN_TX, UDC_IRQ_SRC);
1998 status = IRQ_HANDLED;
1999 ep = &udc->ep[16 + epnum];
2002 omap_writew(epnum | UDC_EP_DIR | UDC_EP_SEL, UDC_EP_NUM);
2003 if (omap_readw(UDC_STAT_FLG) & UDC_ACK) {
2005 if (!list_empty(&ep->queue)) {
2006 req = container_of(ep->queue.next,
2007 struct omap_req, queue);
2008 (void) write_fifo(ep, req);
2011 /* min 6 clock delay before clearing EP_SEL ... */
2012 epn_stat = omap_readw(UDC_EPN_STAT);
2013 epn_stat = omap_readw(UDC_EPN_STAT);
2014 omap_writew(epnum | UDC_EP_DIR, UDC_EP_NUM);
2015 /* then 6 clocks before it'd tx */
2018 spin_unlock_irqrestore(&udc->lock, flags);
2023 static irqreturn_t omap_udc_iso_irq(int irq, void *_dev)
2025 struct omap_udc *udc = _dev;
2028 unsigned long flags;
2030 spin_lock_irqsave(&udc->lock, flags);
2032 /* handle all non-DMA ISO transfers */
2033 list_for_each_entry (ep, &udc->iso, iso) {
2035 struct omap_req *req;
2037 if (ep->has_dma || list_empty(&ep->queue))
2039 req = list_entry(ep->queue.next, struct omap_req, queue);
2041 use_ep(ep, UDC_EP_SEL);
2042 stat = omap_readw(UDC_STAT_FLG);
2044 /* NOTE: like the other controller drivers, this isn't
2045 * currently reporting lost or damaged frames.
2047 if (ep->bEndpointAddress & USB_DIR_IN) {
2048 if (stat & UDC_MISS_IN)
2049 /* done(ep, req, -EPROTO) */;
2051 write_fifo(ep, req);
2055 if (stat & UDC_NO_RXPACKET)
2056 status = -EREMOTEIO;
2057 else if (stat & UDC_ISO_ERR)
2059 else if (stat & UDC_DATA_FLUSH)
2063 /* done(ep, req, status) */;
2068 /* 6 wait states before next EP */
2071 if (!list_empty(&ep->queue))
2077 w = omap_readw(UDC_IRQ_EN);
2079 omap_writew(w, UDC_IRQ_EN);
2081 omap_writew(UDC_IRQ_SOF, UDC_IRQ_SRC);
2083 spin_unlock_irqrestore(&udc->lock, flags);
2088 /*-------------------------------------------------------------------------*/
2090 static inline int machine_without_vbus_sense(void)
2092 return (machine_is_omap_innovator()
2093 || machine_is_omap_osk()
2094 || machine_is_omap_apollon()
2095 #ifndef CONFIG_MACH_OMAP_H4_OTG
2096 || machine_is_omap_h4()
2099 || cpu_is_omap7xx() /* No known omap7xx boards with vbus sense */
2103 static int omap_udc_start(struct usb_gadget_driver *driver,
2104 int (*bind)(struct usb_gadget *))
2106 int status = -ENODEV;
2108 unsigned long flags;
2110 /* basic sanity tests */
2114 // FIXME if otg, check: driver->is_otg
2115 || driver->max_speed < USB_SPEED_FULL
2116 || !bind || !driver->setup)
2119 spin_lock_irqsave(&udc->lock, flags);
2121 spin_unlock_irqrestore(&udc->lock, flags);
2126 list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list) {
2128 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
2131 omap_writew(UDC_SET_HALT, UDC_CTRL);
2133 udc->ep0_pending = 0;
2134 udc->ep[0].irqs = 0;
2135 udc->softconnect = 1;
2137 /* hook up the driver */
2138 driver->driver.bus = NULL;
2139 udc->driver = driver;
2140 udc->gadget.dev.driver = &driver->driver;
2141 spin_unlock_irqrestore(&udc->lock, flags);
2143 if (udc->dc_clk != NULL)
2144 omap_udc_enable_clock(1);
2146 status = bind(&udc->gadget);
2148 DBG("bind to %s --> %d\n", driver->driver.name, status);
2149 udc->gadget.dev.driver = NULL;
2153 DBG("bound to driver %s\n", driver->driver.name);
2155 omap_writew(UDC_IRQ_SRC_MASK, UDC_IRQ_SRC);
2157 /* connect to bus through transceiver */
2158 if (udc->transceiver) {
2159 status = otg_set_peripheral(udc->transceiver->otg,
2162 ERR("can't bind to transceiver\n");
2163 if (driver->unbind) {
2164 driver->unbind (&udc->gadget);
2165 udc->gadget.dev.driver = NULL;
2171 if (can_pullup(udc))
2172 pullup_enable (udc);
2174 pullup_disable (udc);
2177 /* boards that don't have VBUS sensing can't autogate 48MHz;
2178 * can't enter deep sleep while a gadget driver is active.
2180 if (machine_without_vbus_sense())
2181 omap_vbus_session(&udc->gadget, 1);
2184 if (udc->dc_clk != NULL)
2185 omap_udc_enable_clock(0);
2189 static int omap_udc_stop(struct usb_gadget_driver *driver)
2191 unsigned long flags;
2192 int status = -ENODEV;
2196 if (!driver || driver != udc->driver || !driver->unbind)
2199 if (udc->dc_clk != NULL)
2200 omap_udc_enable_clock(1);
2202 if (machine_without_vbus_sense())
2203 omap_vbus_session(&udc->gadget, 0);
2205 if (udc->transceiver)
2206 (void) otg_set_peripheral(udc->transceiver->otg, NULL);
2208 pullup_disable(udc);
2210 spin_lock_irqsave(&udc->lock, flags);
2212 spin_unlock_irqrestore(&udc->lock, flags);
2214 driver->unbind(&udc->gadget);
2215 udc->gadget.dev.driver = NULL;
2218 if (udc->dc_clk != NULL)
2219 omap_udc_enable_clock(0);
2220 DBG("unregistered driver '%s'\n", driver->driver.name);
2224 /*-------------------------------------------------------------------------*/
2226 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2228 #include <linux/seq_file.h>
2230 static const char proc_filename[] = "driver/udc";
2232 #define FOURBITS "%s%s%s%s"
2233 #define EIGHTBITS FOURBITS FOURBITS
2235 static void proc_ep_show(struct seq_file *s, struct omap_ep *ep)
2238 struct omap_req *req;
2243 if (use_dma && ep->has_dma)
2244 snprintf(buf, sizeof buf, "(%cxdma%d lch%d) ",
2245 (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
2246 ep->dma_channel - 1, ep->lch);
2250 stat_flg = omap_readw(UDC_STAT_FLG);
2252 "\n%s %s%s%sirqs %ld stat %04x " EIGHTBITS FOURBITS "%s\n",
2254 ep->double_buf ? "dbuf " : "",
2255 ({char *s; switch(ep->ackwait){
2256 case 0: s = ""; break;
2257 case 1: s = "(ackw) "; break;
2258 case 2: s = "(ackw2) "; break;
2259 default: s = "(?) "; break;
2262 (stat_flg & UDC_NO_RXPACKET) ? "no_rxpacket " : "",
2263 (stat_flg & UDC_MISS_IN) ? "miss_in " : "",
2264 (stat_flg & UDC_DATA_FLUSH) ? "data_flush " : "",
2265 (stat_flg & UDC_ISO_ERR) ? "iso_err " : "",
2266 (stat_flg & UDC_ISO_FIFO_EMPTY) ? "iso_fifo_empty " : "",
2267 (stat_flg & UDC_ISO_FIFO_FULL) ? "iso_fifo_full " : "",
2268 (stat_flg & UDC_EP_HALTED) ? "HALT " : "",
2269 (stat_flg & UDC_STALL) ? "STALL " : "",
2270 (stat_flg & UDC_NAK) ? "NAK " : "",
2271 (stat_flg & UDC_ACK) ? "ACK " : "",
2272 (stat_flg & UDC_FIFO_EN) ? "fifo_en " : "",
2273 (stat_flg & UDC_NON_ISO_FIFO_EMPTY) ? "fifo_empty " : "",
2274 (stat_flg & UDC_NON_ISO_FIFO_FULL) ? "fifo_full " : "");
2276 if (list_empty (&ep->queue))
2277 seq_printf(s, "\t(queue empty)\n");
2279 list_for_each_entry (req, &ep->queue, queue) {
2280 unsigned length = req->req.actual;
2282 if (use_dma && buf[0]) {
2283 length += ((ep->bEndpointAddress & USB_DIR_IN)
2284 ? dma_src_len : dma_dest_len)
2285 (ep, req->req.dma + length);
2288 seq_printf(s, "\treq %p len %d/%d buf %p\n",
2290 req->req.length, req->req.buf);
2294 static char *trx_mode(unsigned m, int enabled)
2297 case 0: return enabled ? "*6wire" : "unused";
2298 case 1: return "4wire";
2299 case 2: return "3wire";
2300 case 3: return "6wire";
2301 default: return "unknown";
2305 static int proc_otg_show(struct seq_file *s)
2309 char *ctrl_name = "(UNKNOWN)";
2311 /* XXX This needs major revision for OMAP2+ */
2312 tmp = omap_readl(OTG_REV);
2313 if (cpu_class_is_omap1()) {
2314 ctrl_name = "tranceiver_ctrl";
2315 trans = omap_readw(USB_TRANSCEIVER_CTRL);
2317 seq_printf(s, "\nOTG rev %d.%d, %s %05x\n",
2318 tmp >> 4, tmp & 0xf, ctrl_name, trans);
2319 tmp = omap_readw(OTG_SYSCON_1);
2320 seq_printf(s, "otg_syscon1 %08x usb2 %s, usb1 %s, usb0 %s,"
2322 trx_mode(USB2_TRX_MODE(tmp), trans & CONF_USB2_UNI_R),
2323 trx_mode(USB1_TRX_MODE(tmp), trans & CONF_USB1_UNI_R),
2324 (USB0_TRX_MODE(tmp) == 0 && !cpu_is_omap1710())
2326 : trx_mode(USB0_TRX_MODE(tmp), 1),
2327 (tmp & OTG_IDLE_EN) ? " !otg" : "",
2328 (tmp & HST_IDLE_EN) ? " !host" : "",
2329 (tmp & DEV_IDLE_EN) ? " !dev" : "",
2330 (tmp & OTG_RESET_DONE) ? " reset_done" : " reset_active");
2331 tmp = omap_readl(OTG_SYSCON_2);
2332 seq_printf(s, "otg_syscon2 %08x%s" EIGHTBITS
2333 " b_ase_brst=%d hmc=%d\n", tmp,
2334 (tmp & OTG_EN) ? " otg_en" : "",
2335 (tmp & USBX_SYNCHRO) ? " synchro" : "",
2336 // much more SRP stuff
2337 (tmp & SRP_DATA) ? " srp_data" : "",
2338 (tmp & SRP_VBUS) ? " srp_vbus" : "",
2339 (tmp & OTG_PADEN) ? " otg_paden" : "",
2340 (tmp & HMC_PADEN) ? " hmc_paden" : "",
2341 (tmp & UHOST_EN) ? " uhost_en" : "",
2342 (tmp & HMC_TLLSPEED) ? " tllspeed" : "",
2343 (tmp & HMC_TLLATTACH) ? " tllattach" : "",
2346 tmp = omap_readl(OTG_CTRL);
2347 seq_printf(s, "otg_ctrl %06x" EIGHTBITS EIGHTBITS "%s\n", tmp,
2348 (tmp & OTG_ASESSVLD) ? " asess" : "",
2349 (tmp & OTG_BSESSEND) ? " bsess_end" : "",
2350 (tmp & OTG_BSESSVLD) ? " bsess" : "",
2351 (tmp & OTG_VBUSVLD) ? " vbus" : "",
2352 (tmp & OTG_ID) ? " id" : "",
2353 (tmp & OTG_DRIVER_SEL) ? " DEVICE" : " HOST",
2354 (tmp & OTG_A_SETB_HNPEN) ? " a_setb_hnpen" : "",
2355 (tmp & OTG_A_BUSREQ) ? " a_bus" : "",
2356 (tmp & OTG_B_HNPEN) ? " b_hnpen" : "",
2357 (tmp & OTG_B_BUSREQ) ? " b_bus" : "",
2358 (tmp & OTG_BUSDROP) ? " busdrop" : "",
2359 (tmp & OTG_PULLDOWN) ? " down" : "",
2360 (tmp & OTG_PULLUP) ? " up" : "",
2361 (tmp & OTG_DRV_VBUS) ? " drv" : "",
2362 (tmp & OTG_PD_VBUS) ? " pd_vb" : "",
2363 (tmp & OTG_PU_VBUS) ? " pu_vb" : "",
2364 (tmp & OTG_PU_ID) ? " pu_id" : ""
2366 tmp = omap_readw(OTG_IRQ_EN);
2367 seq_printf(s, "otg_irq_en %04x" "\n", tmp);
2368 tmp = omap_readw(OTG_IRQ_SRC);
2369 seq_printf(s, "otg_irq_src %04x" "\n", tmp);
2370 tmp = omap_readw(OTG_OUTCTRL);
2371 seq_printf(s, "otg_outctrl %04x" "\n", tmp);
2372 tmp = omap_readw(OTG_TEST);
2373 seq_printf(s, "otg_test %04x" "\n", tmp);
2377 static int proc_udc_show(struct seq_file *s, void *_)
2381 unsigned long flags;
2383 spin_lock_irqsave(&udc->lock, flags);
2385 seq_printf(s, "%s, version: " DRIVER_VERSION
2391 use_dma ? " (dma)" : "");
2393 tmp = omap_readw(UDC_REV) & 0xff;
2395 "UDC rev %d.%d, fifo mode %d, gadget %s\n"
2396 "hmc %d, transceiver %s\n",
2397 tmp >> 4, tmp & 0xf,
2399 udc->driver ? udc->driver->driver.name : "(none)",
2402 ? udc->transceiver->label
2403 : ((cpu_is_omap1710() || cpu_is_omap24xx())
2404 ? "external" : "(none)"));
2405 if (cpu_class_is_omap1()) {
2406 seq_printf(s, "ULPD control %04x req %04x status %04x\n",
2407 omap_readw(ULPD_CLOCK_CTRL),
2408 omap_readw(ULPD_SOFT_REQ),
2409 omap_readw(ULPD_STATUS_REQ));
2412 /* OTG controller registers */
2413 if (!cpu_is_omap15xx())
2416 tmp = omap_readw(UDC_SYSCON1);
2417 seq_printf(s, "\nsyscon1 %04x" EIGHTBITS "\n", tmp,
2418 (tmp & UDC_CFG_LOCK) ? " cfg_lock" : "",
2419 (tmp & UDC_DATA_ENDIAN) ? " data_endian" : "",
2420 (tmp & UDC_DMA_ENDIAN) ? " dma_endian" : "",
2421 (tmp & UDC_NAK_EN) ? " nak" : "",
2422 (tmp & UDC_AUTODECODE_DIS) ? " autodecode_dis" : "",
2423 (tmp & UDC_SELF_PWR) ? " self_pwr" : "",
2424 (tmp & UDC_SOFF_DIS) ? " soff_dis" : "",
2425 (tmp & UDC_PULLUP_EN) ? " PULLUP" : "");
2426 // syscon2 is write-only
2428 /* UDC controller registers */
2429 if (!(tmp & UDC_PULLUP_EN)) {
2430 seq_printf(s, "(suspended)\n");
2431 spin_unlock_irqrestore(&udc->lock, flags);
2435 tmp = omap_readw(UDC_DEVSTAT);
2436 seq_printf(s, "devstat %04x" EIGHTBITS "%s%s\n", tmp,
2437 (tmp & UDC_B_HNP_ENABLE) ? " b_hnp" : "",
2438 (tmp & UDC_A_HNP_SUPPORT) ? " a_hnp" : "",
2439 (tmp & UDC_A_ALT_HNP_SUPPORT) ? " a_alt_hnp" : "",
2440 (tmp & UDC_R_WK_OK) ? " r_wk_ok" : "",
2441 (tmp & UDC_USB_RESET) ? " usb_reset" : "",
2442 (tmp & UDC_SUS) ? " SUS" : "",
2443 (tmp & UDC_CFG) ? " CFG" : "",
2444 (tmp & UDC_ADD) ? " ADD" : "",
2445 (tmp & UDC_DEF) ? " DEF" : "",
2446 (tmp & UDC_ATT) ? " ATT" : "");
2447 seq_printf(s, "sof %04x\n", omap_readw(UDC_SOF));
2448 tmp = omap_readw(UDC_IRQ_EN);
2449 seq_printf(s, "irq_en %04x" FOURBITS "%s\n", tmp,
2450 (tmp & UDC_SOF_IE) ? " sof" : "",
2451 (tmp & UDC_EPN_RX_IE) ? " epn_rx" : "",
2452 (tmp & UDC_EPN_TX_IE) ? " epn_tx" : "",
2453 (tmp & UDC_DS_CHG_IE) ? " ds_chg" : "",
2454 (tmp & UDC_EP0_IE) ? " ep0" : "");
2455 tmp = omap_readw(UDC_IRQ_SRC);
2456 seq_printf(s, "irq_src %04x" EIGHTBITS "%s%s\n", tmp,
2457 (tmp & UDC_TXN_DONE) ? " txn_done" : "",
2458 (tmp & UDC_RXN_CNT) ? " rxn_cnt" : "",
2459 (tmp & UDC_RXN_EOT) ? " rxn_eot" : "",
2460 (tmp & UDC_IRQ_SOF) ? " sof" : "",
2461 (tmp & UDC_EPN_RX) ? " epn_rx" : "",
2462 (tmp & UDC_EPN_TX) ? " epn_tx" : "",
2463 (tmp & UDC_DS_CHG) ? " ds_chg" : "",
2464 (tmp & UDC_SETUP) ? " setup" : "",
2465 (tmp & UDC_EP0_RX) ? " ep0out" : "",
2466 (tmp & UDC_EP0_TX) ? " ep0in" : "");
2470 tmp = omap_readw(UDC_DMA_IRQ_EN);
2471 seq_printf(s, "dma_irq_en %04x%s" EIGHTBITS "\n", tmp,
2472 (tmp & UDC_TX_DONE_IE(3)) ? " tx2_done" : "",
2473 (tmp & UDC_RX_CNT_IE(3)) ? " rx2_cnt" : "",
2474 (tmp & UDC_RX_EOT_IE(3)) ? " rx2_eot" : "",
2476 (tmp & UDC_TX_DONE_IE(2)) ? " tx1_done" : "",
2477 (tmp & UDC_RX_CNT_IE(2)) ? " rx1_cnt" : "",
2478 (tmp & UDC_RX_EOT_IE(2)) ? " rx1_eot" : "",
2480 (tmp & UDC_TX_DONE_IE(1)) ? " tx0_done" : "",
2481 (tmp & UDC_RX_CNT_IE(1)) ? " rx0_cnt" : "",
2482 (tmp & UDC_RX_EOT_IE(1)) ? " rx0_eot" : "");
2484 tmp = omap_readw(UDC_RXDMA_CFG);
2485 seq_printf(s, "rxdma_cfg %04x\n", tmp);
2487 for (i = 0; i < 3; i++) {
2488 if ((tmp & (0x0f << (i * 4))) == 0)
2490 seq_printf(s, "rxdma[%d] %04x\n", i,
2491 omap_readw(UDC_RXDMA(i + 1)));
2494 tmp = omap_readw(UDC_TXDMA_CFG);
2495 seq_printf(s, "txdma_cfg %04x\n", tmp);
2497 for (i = 0; i < 3; i++) {
2498 if (!(tmp & (0x0f << (i * 4))))
2500 seq_printf(s, "txdma[%d] %04x\n", i,
2501 omap_readw(UDC_TXDMA(i + 1)));
2506 tmp = omap_readw(UDC_DEVSTAT);
2507 if (tmp & UDC_ATT) {
2508 proc_ep_show(s, &udc->ep[0]);
2509 if (tmp & UDC_ADD) {
2510 list_for_each_entry (ep, &udc->gadget.ep_list,
2513 proc_ep_show(s, ep);
2517 spin_unlock_irqrestore(&udc->lock, flags);
2521 static int proc_udc_open(struct inode *inode, struct file *file)
2523 return single_open(file, proc_udc_show, NULL);
2526 static const struct file_operations proc_ops = {
2527 .owner = THIS_MODULE,
2528 .open = proc_udc_open,
2530 .llseek = seq_lseek,
2531 .release = single_release,
2534 static void create_proc_file(void)
2536 proc_create(proc_filename, 0, NULL, &proc_ops);
2539 static void remove_proc_file(void)
2541 remove_proc_entry(proc_filename, NULL);
2546 static inline void create_proc_file(void) {}
2547 static inline void remove_proc_file(void) {}
2551 /*-------------------------------------------------------------------------*/
2553 /* Before this controller can enumerate, we need to pick an endpoint
2554 * configuration, or "fifo_mode" That involves allocating 2KB of packet
2555 * buffer space among the endpoints we'll be operating.
2557 * NOTE: as of OMAP 1710 ES2.0, writing a new endpoint config when
2558 * UDC_SYSCON_1.CFG_LOCK is set can now work. We won't use that
2559 * capability yet though.
2561 static unsigned __init
2562 omap_ep_setup(char *name, u8 addr, u8 type,
2563 unsigned buf, unsigned maxp, int dbuf)
2568 /* OUT endpoints first, then IN */
2569 ep = &udc->ep[addr & 0xf];
2570 if (addr & USB_DIR_IN)
2573 /* in case of ep init table bugs */
2574 BUG_ON(ep->name[0]);
2576 /* chip setup ... bit values are same for IN, OUT */
2577 if (type == USB_ENDPOINT_XFER_ISOC) {
2579 case 8: epn_rxtx = 0 << 12; break;
2580 case 16: epn_rxtx = 1 << 12; break;
2581 case 32: epn_rxtx = 2 << 12; break;
2582 case 64: epn_rxtx = 3 << 12; break;
2583 case 128: epn_rxtx = 4 << 12; break;
2584 case 256: epn_rxtx = 5 << 12; break;
2585 case 512: epn_rxtx = 6 << 12; break;
2588 epn_rxtx |= UDC_EPN_RX_ISO;
2591 /* double-buffering "not supported" on 15xx,
2592 * and ignored for PIO-IN on newer chips
2593 * (for more reliable behavior)
2595 if (!use_dma || cpu_is_omap15xx() || cpu_is_omap24xx())
2599 case 8: epn_rxtx = 0 << 12; break;
2600 case 16: epn_rxtx = 1 << 12; break;
2601 case 32: epn_rxtx = 2 << 12; break;
2602 case 64: epn_rxtx = 3 << 12; break;
2606 epn_rxtx |= UDC_EPN_RX_DB;
2607 init_timer(&ep->timer);
2608 ep->timer.function = pio_out_timer;
2609 ep->timer.data = (unsigned long) ep;
2612 epn_rxtx |= UDC_EPN_RX_VALID;
2614 epn_rxtx |= buf >> 3;
2616 DBG("%s addr %02x rxtx %04x maxp %d%s buf %d\n",
2617 name, addr, epn_rxtx, maxp, dbuf ? "x2" : "", buf);
2619 if (addr & USB_DIR_IN)
2620 omap_writew(epn_rxtx, UDC_EP_TX(addr & 0xf));
2622 omap_writew(epn_rxtx, UDC_EP_RX(addr));
2624 /* next endpoint's buffer starts after this one's */
2630 /* set up driver data structures */
2631 BUG_ON(strlen(name) >= sizeof ep->name);
2632 strlcpy(ep->name, name, sizeof ep->name);
2633 INIT_LIST_HEAD(&ep->queue);
2634 INIT_LIST_HEAD(&ep->iso);
2635 ep->bEndpointAddress = addr;
2636 ep->bmAttributes = type;
2637 ep->double_buf = dbuf;
2640 ep->ep.name = ep->name;
2641 ep->ep.ops = &omap_ep_ops;
2642 ep->ep.maxpacket = ep->maxpacket = maxp;
2643 list_add_tail (&ep->ep.ep_list, &udc->gadget.ep_list);
2648 static void omap_udc_release(struct device *dev)
2650 complete(udc->done);
2656 omap_udc_setup(struct platform_device *odev, struct usb_phy *xceiv)
2660 /* abolish any previous hardware state */
2661 omap_writew(0, UDC_SYSCON1);
2662 omap_writew(0, UDC_IRQ_EN);
2663 omap_writew(UDC_IRQ_SRC_MASK, UDC_IRQ_SRC);
2664 omap_writew(0, UDC_DMA_IRQ_EN);
2665 omap_writew(0, UDC_RXDMA_CFG);
2666 omap_writew(0, UDC_TXDMA_CFG);
2668 /* UDC_PULLUP_EN gates the chip clock */
2669 // OTG_SYSCON_1 |= DEV_IDLE_EN;
2671 udc = kzalloc(sizeof(*udc), GFP_KERNEL);
2675 spin_lock_init (&udc->lock);
2677 udc->gadget.ops = &omap_gadget_ops;
2678 udc->gadget.ep0 = &udc->ep[0].ep;
2679 INIT_LIST_HEAD(&udc->gadget.ep_list);
2680 INIT_LIST_HEAD(&udc->iso);
2681 udc->gadget.speed = USB_SPEED_UNKNOWN;
2682 udc->gadget.max_speed = USB_SPEED_FULL;
2683 udc->gadget.name = driver_name;
2685 device_initialize(&udc->gadget.dev);
2686 dev_set_name(&udc->gadget.dev, "gadget");
2687 udc->gadget.dev.release = omap_udc_release;
2688 udc->gadget.dev.parent = &odev->dev;
2690 udc->gadget.dev.dma_mask = odev->dev.dma_mask;
2692 udc->transceiver = xceiv;
2694 /* ep0 is special; put it right after the SETUP buffer */
2695 buf = omap_ep_setup("ep0", 0, USB_ENDPOINT_XFER_CONTROL,
2696 8 /* after SETUP */, 64 /* maxpacket */, 0);
2697 list_del_init(&udc->ep[0].ep.ep_list);
2699 /* initially disable all non-ep0 endpoints */
2700 for (tmp = 1; tmp < 15; tmp++) {
2701 omap_writew(0, UDC_EP_RX(tmp));
2702 omap_writew(0, UDC_EP_TX(tmp));
2705 #define OMAP_BULK_EP(name,addr) \
2706 buf = omap_ep_setup(name "-bulk", addr, \
2707 USB_ENDPOINT_XFER_BULK, buf, 64, 1);
2708 #define OMAP_INT_EP(name,addr, maxp) \
2709 buf = omap_ep_setup(name "-int", addr, \
2710 USB_ENDPOINT_XFER_INT, buf, maxp, 0);
2711 #define OMAP_ISO_EP(name,addr, maxp) \
2712 buf = omap_ep_setup(name "-iso", addr, \
2713 USB_ENDPOINT_XFER_ISOC, buf, maxp, 1);
2715 switch (fifo_mode) {
2717 OMAP_BULK_EP("ep1in", USB_DIR_IN | 1);
2718 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2719 OMAP_INT_EP("ep3in", USB_DIR_IN | 3, 16);
2722 OMAP_BULK_EP("ep1in", USB_DIR_IN | 1);
2723 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2724 OMAP_INT_EP("ep9in", USB_DIR_IN | 9, 16);
2726 OMAP_BULK_EP("ep3in", USB_DIR_IN | 3);
2727 OMAP_BULK_EP("ep4out", USB_DIR_OUT | 4);
2728 OMAP_INT_EP("ep10in", USB_DIR_IN | 10, 16);
2730 OMAP_BULK_EP("ep5in", USB_DIR_IN | 5);
2731 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2732 OMAP_INT_EP("ep11in", USB_DIR_IN | 11, 16);
2734 OMAP_BULK_EP("ep6in", USB_DIR_IN | 6);
2735 OMAP_BULK_EP("ep6out", USB_DIR_OUT | 6);
2736 OMAP_INT_EP("ep12in", USB_DIR_IN | 12, 16);
2738 OMAP_BULK_EP("ep7in", USB_DIR_IN | 7);
2739 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2740 OMAP_INT_EP("ep13in", USB_DIR_IN | 13, 16);
2741 OMAP_INT_EP("ep13out", USB_DIR_OUT | 13, 16);
2743 OMAP_BULK_EP("ep8in", USB_DIR_IN | 8);
2744 OMAP_BULK_EP("ep8out", USB_DIR_OUT | 8);
2745 OMAP_INT_EP("ep14in", USB_DIR_IN | 14, 16);
2746 OMAP_INT_EP("ep14out", USB_DIR_OUT | 14, 16);
2748 OMAP_BULK_EP("ep15in", USB_DIR_IN | 15);
2749 OMAP_BULK_EP("ep15out", USB_DIR_OUT | 15);
2754 case 2: /* mixed iso/bulk */
2755 OMAP_ISO_EP("ep1in", USB_DIR_IN | 1, 256);
2756 OMAP_ISO_EP("ep2out", USB_DIR_OUT | 2, 256);
2757 OMAP_ISO_EP("ep3in", USB_DIR_IN | 3, 128);
2758 OMAP_ISO_EP("ep4out", USB_DIR_OUT | 4, 128);
2760 OMAP_INT_EP("ep5in", USB_DIR_IN | 5, 16);
2762 OMAP_BULK_EP("ep6in", USB_DIR_IN | 6);
2763 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2764 OMAP_INT_EP("ep8in", USB_DIR_IN | 8, 16);
2766 case 3: /* mixed bulk/iso */
2767 OMAP_BULK_EP("ep1in", USB_DIR_IN | 1);
2768 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2769 OMAP_INT_EP("ep3in", USB_DIR_IN | 3, 16);
2771 OMAP_BULK_EP("ep4in", USB_DIR_IN | 4);
2772 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2773 OMAP_INT_EP("ep6in", USB_DIR_IN | 6, 16);
2775 OMAP_ISO_EP("ep7in", USB_DIR_IN | 7, 256);
2776 OMAP_ISO_EP("ep8out", USB_DIR_OUT | 8, 256);
2777 OMAP_INT_EP("ep9in", USB_DIR_IN | 9, 16);
2781 /* add more modes as needed */
2784 ERR("unsupported fifo_mode #%d\n", fifo_mode);
2787 omap_writew(UDC_CFG_LOCK|UDC_SELF_PWR, UDC_SYSCON1);
2788 INFO("fifo mode %d, %d bytes not used\n", fifo_mode, 2048 - buf);
2792 static int __init omap_udc_probe(struct platform_device *pdev)
2794 int status = -ENODEV;
2796 struct usb_phy *xceiv = NULL;
2797 const char *type = NULL;
2798 struct omap_usb_config *config = pdev->dev.platform_data;
2800 struct clk *hhc_clk;
2802 /* NOTE: "knows" the order of the resources! */
2803 if (!request_mem_region(pdev->resource[0].start,
2804 pdev->resource[0].end - pdev->resource[0].start + 1,
2806 DBG("request_mem_region failed\n");
2810 if (cpu_is_omap16xx()) {
2811 dc_clk = clk_get(&pdev->dev, "usb_dc_ck");
2812 hhc_clk = clk_get(&pdev->dev, "usb_hhc_ck");
2813 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2814 /* can't use omap_udc_enable_clock yet */
2816 clk_enable(hhc_clk);
2820 if (cpu_is_omap24xx()) {
2821 dc_clk = clk_get(&pdev->dev, "usb_fck");
2822 hhc_clk = clk_get(&pdev->dev, "usb_l4_ick");
2823 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2824 /* can't use omap_udc_enable_clock yet */
2826 clk_enable(hhc_clk);
2830 if (cpu_is_omap7xx()) {
2831 dc_clk = clk_get(&pdev->dev, "usb_dc_ck");
2832 hhc_clk = clk_get(&pdev->dev, "l3_ocpi_ck");
2833 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2834 /* can't use omap_udc_enable_clock yet */
2836 clk_enable(hhc_clk);
2840 INFO("OMAP UDC rev %d.%d%s\n",
2841 omap_readw(UDC_REV) >> 4, omap_readw(UDC_REV) & 0xf,
2842 config->otg ? ", Mini-AB" : "");
2844 /* use the mode given to us by board init code */
2845 if (cpu_is_omap15xx()) {
2849 if (machine_without_vbus_sense()) {
2850 /* just set up software VBUS detect, and then
2851 * later rig it so we always report VBUS.
2852 * FIXME without really sensing VBUS, we can't
2853 * know when to turn PULLUP_EN on/off; and that
2854 * means we always "need" the 48MHz clock.
2856 u32 tmp = omap_readl(FUNC_MUX_CTRL_0);
2857 tmp &= ~VBUS_CTRL_1510;
2858 omap_writel(tmp, FUNC_MUX_CTRL_0);
2859 tmp |= VBUS_MODE_1510;
2860 tmp &= ~VBUS_CTRL_1510;
2861 omap_writel(tmp, FUNC_MUX_CTRL_0);
2864 /* The transceiver may package some GPIO logic or handle
2865 * loopback and/or transceiverless setup; if we find one,
2866 * use it. Except for OTG, we don't _need_ to talk to one;
2867 * but not having one probably means no VBUS detection.
2869 xceiv = usb_get_transceiver();
2871 type = xceiv->label;
2872 else if (config->otg) {
2873 DBG("OTG requires external transceiver!\n");
2879 if (cpu_is_omap24xx()) {
2880 /* this could be transceiverless in one of the
2881 * "we don't need to know" modes.
2888 case 0: /* POWERUP DEFAULT == 0 */
2892 if (!cpu_is_omap1710()) {
2893 type = "integrated";
2903 DBG("external transceiver not registered!\n");
2907 case 21: /* internal loopback */
2910 case 14: /* transceiverless */
2911 if (cpu_is_omap1710())
2921 ERR("unrecognized UDC HMC mode %d\n", hmc);
2926 INFO("hmc mode %d, %s transceiver\n", hmc, type);
2928 /* a "gadget" abstracts/virtualizes the controller */
2929 status = omap_udc_setup(pdev, xceiv);
2934 // "udc" is now valid
2935 pullup_disable(udc);
2936 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
2937 udc->gadget.is_otg = (config->otg != 0);
2940 /* starting with omap1710 es2.0, clear toggle is a separate bit */
2941 if (omap_readw(UDC_REV) >= 0x61)
2942 udc->clr_halt = UDC_RESET_EP | UDC_CLRDATA_TOGGLE;
2944 udc->clr_halt = UDC_RESET_EP;
2946 /* USB general purpose IRQ: ep0, state changes, dma, etc */
2947 status = request_irq(pdev->resource[1].start, omap_udc_irq,
2948 IRQF_SAMPLE_RANDOM, driver_name, udc);
2950 ERR("can't get irq %d, err %d\n",
2951 (int) pdev->resource[1].start, status);
2955 /* USB "non-iso" IRQ (PIO for all but ep0) */
2956 status = request_irq(pdev->resource[2].start, omap_udc_pio_irq,
2957 IRQF_SAMPLE_RANDOM, "omap_udc pio", udc);
2959 ERR("can't get irq %d, err %d\n",
2960 (int) pdev->resource[2].start, status);
2964 status = request_irq(pdev->resource[3].start, omap_udc_iso_irq,
2965 0, "omap_udc iso", udc);
2967 ERR("can't get irq %d, err %d\n",
2968 (int) pdev->resource[3].start, status);
2972 if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
2973 udc->dc_clk = dc_clk;
2974 udc->hhc_clk = hhc_clk;
2975 clk_disable(hhc_clk);
2976 clk_disable(dc_clk);
2979 if (cpu_is_omap24xx()) {
2980 udc->dc_clk = dc_clk;
2981 udc->hhc_clk = hhc_clk;
2982 /* FIXME OMAP2 don't release hhc & dc clock */
2984 clk_disable(hhc_clk);
2985 clk_disable(dc_clk);
2990 status = device_add(&udc->gadget.dev);
2994 status = usb_add_gadget_udc(&pdev->dev, &udc->gadget);
2997 /* If fail, fall through */
3003 free_irq(pdev->resource[2].start, udc);
3007 free_irq(pdev->resource[1].start, udc);
3015 usb_put_transceiver(xceiv);
3017 if (cpu_is_omap16xx() || cpu_is_omap24xx() || cpu_is_omap7xx()) {
3018 clk_disable(hhc_clk);
3019 clk_disable(dc_clk);
3024 release_mem_region(pdev->resource[0].start,
3025 pdev->resource[0].end - pdev->resource[0].start + 1);
3030 static int __exit omap_udc_remove(struct platform_device *pdev)
3032 DECLARE_COMPLETION_ONSTACK(done);
3037 usb_del_gadget_udc(&udc->gadget);
3043 pullup_disable(udc);
3044 if (udc->transceiver) {
3045 usb_put_transceiver(udc->transceiver);
3046 udc->transceiver = NULL;
3048 omap_writew(0, UDC_SYSCON1);
3053 free_irq(pdev->resource[3].start, udc);
3055 free_irq(pdev->resource[2].start, udc);
3056 free_irq(pdev->resource[1].start, udc);
3059 if (udc->clk_requested)
3060 omap_udc_enable_clock(0);
3061 clk_put(udc->hhc_clk);
3062 clk_put(udc->dc_clk);
3065 release_mem_region(pdev->resource[0].start,
3066 pdev->resource[0].end - pdev->resource[0].start + 1);
3068 device_unregister(&udc->gadget.dev);
3069 wait_for_completion(&done);
3074 /* suspend/resume/wakeup from sysfs (echo > power/state) or when the
3075 * system is forced into deep sleep
3077 * REVISIT we should probably reject suspend requests when there's a host
3078 * session active, rather than disconnecting, at least on boards that can
3079 * report VBUS irqs (UDC_DEVSTAT.UDC_ATT). And in any case, we need to
3080 * make host resumes and VBUS detection trigger OMAP wakeup events; that
3081 * may involve talking to an external transceiver (e.g. isp1301).
3084 static int omap_udc_suspend(struct platform_device *dev, pm_message_t message)
3088 devstat = omap_readw(UDC_DEVSTAT);
3090 /* we're requesting 48 MHz clock if the pullup is enabled
3091 * (== we're attached to the host) and we're not suspended,
3092 * which would prevent entry to deep sleep...
3094 if ((devstat & UDC_ATT) != 0 && (devstat & UDC_SUS) == 0) {
3095 WARNING("session active; suspend requires disconnect\n");
3096 omap_pullup(&udc->gadget, 0);
3102 static int omap_udc_resume(struct platform_device *dev)
3104 DBG("resume + wakeup/SRP\n");
3105 omap_pullup(&udc->gadget, 1);
3107 /* maybe the host would enumerate us if we nudged it */
3109 return omap_wakeup(&udc->gadget);
3112 /*-------------------------------------------------------------------------*/
3114 static struct platform_driver udc_driver = {
3115 .remove = __exit_p(omap_udc_remove),
3116 .suspend = omap_udc_suspend,
3117 .resume = omap_udc_resume,
3119 .owner = THIS_MODULE,
3120 .name = (char *) driver_name,
3124 static int __init udc_init(void)
3126 /* Disable DMA for omap7xx -- it doesn't work right. */
3127 if (cpu_is_omap7xx())
3130 INFO("%s, version: " DRIVER_VERSION
3134 "%s\n", driver_desc,
3135 use_dma ? " (dma)" : "");
3136 return platform_driver_probe(&udc_driver, omap_udc_probe);
3138 module_init(udc_init);
3140 static void __exit udc_exit(void)
3142 platform_driver_unregister(&udc_driver);
3144 module_exit(udc_exit);
3146 MODULE_DESCRIPTION(DRIVER_DESC);
3147 MODULE_LICENSE("GPL");
3148 MODULE_ALIAS("platform:omap_udc");