2 * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/pci.h>
12 #include <linux/delay.h>
13 #include <linux/errno.h>
14 #include <linux/list.h>
15 #include <linux/interrupt.h>
16 #include <linux/usb/ch9.h>
17 #include <linux/usb/gadget.h>
18 #include <linux/gpio.h>
19 #include <linux/irq.h>
21 /* GPIO port for VBUS detecting */
22 static int vbus_gpio_port = -1; /* GPIO port number (-1:Not used) */
24 #define PCH_VBUS_PERIOD 3000 /* VBUS polling period (msec) */
25 #define PCH_VBUS_INTERVAL 10 /* VBUS polling interval (msec) */
27 /* Address offset of Registers */
28 #define UDC_EP_REG_SHIFT 0x20 /* Offset to next EP */
30 #define UDC_EPCTL_ADDR 0x00 /* Endpoint control */
31 #define UDC_EPSTS_ADDR 0x04 /* Endpoint status */
32 #define UDC_BUFIN_FRAMENUM_ADDR 0x08 /* buffer size in / frame number out */
33 #define UDC_BUFOUT_MAXPKT_ADDR 0x0C /* buffer size out / maxpkt in */
34 #define UDC_SUBPTR_ADDR 0x10 /* setup buffer pointer */
35 #define UDC_DESPTR_ADDR 0x14 /* Data descriptor pointer */
36 #define UDC_CONFIRM_ADDR 0x18 /* Write/Read confirmation */
38 #define UDC_DEVCFG_ADDR 0x400 /* Device configuration */
39 #define UDC_DEVCTL_ADDR 0x404 /* Device control */
40 #define UDC_DEVSTS_ADDR 0x408 /* Device status */
41 #define UDC_DEVIRQSTS_ADDR 0x40C /* Device irq status */
42 #define UDC_DEVIRQMSK_ADDR 0x410 /* Device irq mask */
43 #define UDC_EPIRQSTS_ADDR 0x414 /* Endpoint irq status */
44 #define UDC_EPIRQMSK_ADDR 0x418 /* Endpoint irq mask */
45 #define UDC_DEVLPM_ADDR 0x41C /* LPM control / status */
46 #define UDC_CSR_BUSY_ADDR 0x4f0 /* UDC_CSR_BUSY Status register */
47 #define UDC_SRST_ADDR 0x4fc /* SOFT RESET register */
48 #define UDC_CSR_ADDR 0x500 /* USB_DEVICE endpoint register */
50 /* Endpoint control register */
52 #define UDC_EPCTL_MRXFLUSH (1 << 12)
53 #define UDC_EPCTL_RRDY (1 << 9)
54 #define UDC_EPCTL_CNAK (1 << 8)
55 #define UDC_EPCTL_SNAK (1 << 7)
56 #define UDC_EPCTL_NAK (1 << 6)
57 #define UDC_EPCTL_P (1 << 3)
58 #define UDC_EPCTL_F (1 << 1)
59 #define UDC_EPCTL_S (1 << 0)
60 #define UDC_EPCTL_ET_SHIFT 4
62 #define UDC_EPCTL_ET_MASK 0x00000030
63 /* Value for ET field */
64 #define UDC_EPCTL_ET_CONTROL 0
65 #define UDC_EPCTL_ET_ISO 1
66 #define UDC_EPCTL_ET_BULK 2
67 #define UDC_EPCTL_ET_INTERRUPT 3
69 /* Endpoint status register */
71 #define UDC_EPSTS_XFERDONE (1 << 27)
72 #define UDC_EPSTS_RSS (1 << 26)
73 #define UDC_EPSTS_RCS (1 << 25)
74 #define UDC_EPSTS_TXEMPTY (1 << 24)
75 #define UDC_EPSTS_TDC (1 << 10)
76 #define UDC_EPSTS_HE (1 << 9)
77 #define UDC_EPSTS_MRXFIFO_EMP (1 << 8)
78 #define UDC_EPSTS_BNA (1 << 7)
79 #define UDC_EPSTS_IN (1 << 6)
80 #define UDC_EPSTS_OUT_SHIFT 4
82 #define UDC_EPSTS_OUT_MASK 0x00000030
83 #define UDC_EPSTS_ALL_CLR_MASK 0x1F0006F0
84 /* Value for OUT field */
85 #define UDC_EPSTS_OUT_SETUP 2
86 #define UDC_EPSTS_OUT_DATA 1
88 /* Device configuration register */
90 #define UDC_DEVCFG_CSR_PRG (1 << 17)
91 #define UDC_DEVCFG_SP (1 << 3)
93 #define UDC_DEVCFG_SPD_HS 0x0
94 #define UDC_DEVCFG_SPD_FS 0x1
95 #define UDC_DEVCFG_SPD_LS 0x2
97 /* Device control register */
99 #define UDC_DEVCTL_THLEN_SHIFT 24
100 #define UDC_DEVCTL_BRLEN_SHIFT 16
101 #define UDC_DEVCTL_CSR_DONE (1 << 13)
102 #define UDC_DEVCTL_SD (1 << 10)
103 #define UDC_DEVCTL_MODE (1 << 9)
104 #define UDC_DEVCTL_BREN (1 << 8)
105 #define UDC_DEVCTL_THE (1 << 7)
106 #define UDC_DEVCTL_DU (1 << 4)
107 #define UDC_DEVCTL_TDE (1 << 3)
108 #define UDC_DEVCTL_RDE (1 << 2)
109 #define UDC_DEVCTL_RES (1 << 0)
111 /* Device status register */
113 #define UDC_DEVSTS_TS_SHIFT 18
114 #define UDC_DEVSTS_ENUM_SPEED_SHIFT 13
115 #define UDC_DEVSTS_ALT_SHIFT 8
116 #define UDC_DEVSTS_INTF_SHIFT 4
117 #define UDC_DEVSTS_CFG_SHIFT 0
119 #define UDC_DEVSTS_TS_MASK 0xfffc0000
120 #define UDC_DEVSTS_ENUM_SPEED_MASK 0x00006000
121 #define UDC_DEVSTS_ALT_MASK 0x00000f00
122 #define UDC_DEVSTS_INTF_MASK 0x000000f0
123 #define UDC_DEVSTS_CFG_MASK 0x0000000f
124 /* value for maximum speed for SPEED field */
125 #define UDC_DEVSTS_ENUM_SPEED_FULL 1
126 #define UDC_DEVSTS_ENUM_SPEED_HIGH 0
127 #define UDC_DEVSTS_ENUM_SPEED_LOW 2
128 #define UDC_DEVSTS_ENUM_SPEED_FULLX 3
130 /* Device irq register */
132 #define UDC_DEVINT_RWKP (1 << 7)
133 #define UDC_DEVINT_ENUM (1 << 6)
134 #define UDC_DEVINT_SOF (1 << 5)
135 #define UDC_DEVINT_US (1 << 4)
136 #define UDC_DEVINT_UR (1 << 3)
137 #define UDC_DEVINT_ES (1 << 2)
138 #define UDC_DEVINT_SI (1 << 1)
139 #define UDC_DEVINT_SC (1 << 0)
141 #define UDC_DEVINT_MSK 0x7f
143 /* Endpoint irq register */
145 #define UDC_EPINT_IN_SHIFT 0
146 #define UDC_EPINT_OUT_SHIFT 16
147 #define UDC_EPINT_IN_EP0 (1 << 0)
148 #define UDC_EPINT_OUT_EP0 (1 << 16)
150 #define UDC_EPINT_MSK_DISABLE_ALL 0xffffffff
152 /* UDC_CSR_BUSY Status register */
154 #define UDC_CSR_BUSY (1 << 0)
156 /* SOFT RESET register */
158 #define UDC_PSRST (1 << 1)
159 #define UDC_SRST (1 << 0)
161 /* USB_DEVICE endpoint register */
163 #define UDC_CSR_NE_NUM_SHIFT 0
164 #define UDC_CSR_NE_DIR_SHIFT 4
165 #define UDC_CSR_NE_TYPE_SHIFT 5
166 #define UDC_CSR_NE_CFG_SHIFT 7
167 #define UDC_CSR_NE_INTF_SHIFT 11
168 #define UDC_CSR_NE_ALT_SHIFT 15
169 #define UDC_CSR_NE_MAX_PKT_SHIFT 19
171 #define UDC_CSR_NE_NUM_MASK 0x0000000f
172 #define UDC_CSR_NE_DIR_MASK 0x00000010
173 #define UDC_CSR_NE_TYPE_MASK 0x00000060
174 #define UDC_CSR_NE_CFG_MASK 0x00000780
175 #define UDC_CSR_NE_INTF_MASK 0x00007800
176 #define UDC_CSR_NE_ALT_MASK 0x00078000
177 #define UDC_CSR_NE_MAX_PKT_MASK 0x3ff80000
179 #define PCH_UDC_CSR(ep) (UDC_CSR_ADDR + ep*4)
180 #define PCH_UDC_EPINT(in, num)\
181 (1 << (num + (in ? UDC_EPINT_IN_SHIFT : UDC_EPINT_OUT_SHIFT)))
183 /* Index of endpoint */
184 #define UDC_EP0IN_IDX 0
185 #define UDC_EP0OUT_IDX 1
186 #define UDC_EPIN_IDX(ep) (ep * 2)
187 #define UDC_EPOUT_IDX(ep) (ep * 2 + 1)
188 #define PCH_UDC_EP0 0
189 #define PCH_UDC_EP1 1
190 #define PCH_UDC_EP2 2
191 #define PCH_UDC_EP3 3
193 /* Number of endpoint */
194 #define PCH_UDC_EP_NUM 32 /* Total number of EPs (16 IN,16 OUT) */
195 #define PCH_UDC_USED_EP_NUM 4 /* EP number of EP's really used */
197 #define PCH_UDC_BRLEN 0x0F /* Burst length */
198 #define PCH_UDC_THLEN 0x1F /* Threshold length */
199 /* Value of EP Buffer Size */
200 #define UDC_EP0IN_BUFF_SIZE 16
201 #define UDC_EPIN_BUFF_SIZE 256
202 #define UDC_EP0OUT_BUFF_SIZE 16
203 #define UDC_EPOUT_BUFF_SIZE 256
204 /* Value of EP maximum packet size */
205 #define UDC_EP0IN_MAX_PKT_SIZE 64
206 #define UDC_EP0OUT_MAX_PKT_SIZE 64
207 #define UDC_BULK_MAX_PKT_SIZE 512
210 #define DMA_DIR_RX 1 /* DMA for data receive */
211 #define DMA_DIR_TX 2 /* DMA for data transmit */
212 #define DMA_ADDR_INVALID (~(dma_addr_t)0)
213 #define UDC_DMA_MAXPACKET 65536 /* maximum packet size for DMA */
216 * struct pch_udc_data_dma_desc - Structure to hold DMA descriptor information
218 * @status: Status quadlet
219 * @reserved: Reserved
220 * @dataptr: Buffer descriptor
221 * @next: Next descriptor
223 struct pch_udc_data_dma_desc {
231 * struct pch_udc_stp_dma_desc - Structure to hold DMA descriptor information
234 * @reserved: Reserved
235 * @data12: First setup word
236 * @data34: Second setup word
238 struct pch_udc_stp_dma_desc {
241 struct usb_ctrlrequest request;
242 } __attribute((packed));
244 /* DMA status definitions */
246 #define PCH_UDC_BUFF_STS 0xC0000000
247 #define PCH_UDC_BS_HST_RDY 0x00000000
248 #define PCH_UDC_BS_DMA_BSY 0x40000000
249 #define PCH_UDC_BS_DMA_DONE 0x80000000
250 #define PCH_UDC_BS_HST_BSY 0xC0000000
252 #define PCH_UDC_RXTX_STS 0x30000000
253 #define PCH_UDC_RTS_SUCC 0x00000000
254 #define PCH_UDC_RTS_DESERR 0x10000000
255 #define PCH_UDC_RTS_BUFERR 0x30000000
256 /* Last Descriptor Indication */
257 #define PCH_UDC_DMA_LAST 0x08000000
258 /* Number of Rx/Tx Bytes Mask */
259 #define PCH_UDC_RXTX_BYTES 0x0000ffff
262 * struct pch_udc_cfg_data - Structure to hold current configuration
263 * and interface information
264 * @cur_cfg: current configuration in use
265 * @cur_intf: current interface in use
266 * @cur_alt: current alt interface in use
268 struct pch_udc_cfg_data {
275 * struct pch_udc_ep - Structure holding a PCH USB device Endpoint information
276 * @ep: embedded ep request
277 * @td_stp_phys: for setup request
278 * @td_data_phys: for data request
279 * @td_stp: for setup request
280 * @td_data: for data request
281 * @dev: reference to device struct
282 * @offset_addr: offset address of ep register
284 * @queue: queue for requests
285 * @num: endpoint number
286 * @in: endpoint is IN
287 * @halted: endpoint halted?
288 * @epsts: Endpoint status
292 dma_addr_t td_stp_phys;
293 dma_addr_t td_data_phys;
294 struct pch_udc_stp_dma_desc *td_stp;
295 struct pch_udc_data_dma_desc *td_data;
296 struct pch_udc_dev *dev;
297 unsigned long offset_addr;
298 const struct usb_endpoint_descriptor *desc;
299 struct list_head queue;
307 * struct pch_vbus_gpio_data - Structure holding GPIO informaton
309 * @port: gpio port number
310 * @intr: gpio interrupt number
311 * @irq_work_fall Structure for WorkQueue
312 * @irq_work_rise Structure for WorkQueue
314 struct pch_vbus_gpio_data {
317 struct work_struct irq_work_fall;
318 struct work_struct irq_work_rise;
322 * struct pch_udc_dev - Structure holding complete information
323 * of the PCH USB device
324 * @gadget: gadget driver data
325 * @driver: reference to gadget driver bound
326 * @pdev: reference to the PCI device
327 * @ep: array of endpoints
328 * @lock: protects all state
329 * @active: enabled the PCI device
330 * @stall: stall requested
331 * @prot_stall: protcol stall requested
332 * @irq_registered: irq registered with system
333 * @mem_region: device memory mapped
334 * @registered: driver regsitered with system
335 * @suspended: driver in suspended state
336 * @connected: gadget driver associated
337 * @vbus_session: required vbus_session state
338 * @set_cfg_not_acked: pending acknowledgement 4 setup
339 * @waiting_zlp_ack: pending acknowledgement 4 ZLP
340 * @data_requests: DMA pool for data requests
341 * @stp_requests: DMA pool for setup requests
342 * @dma_addr: DMA pool for received
343 * @ep0out_buf: Buffer for DMA
344 * @setup_data: Received setup data
345 * @phys_addr: of device memory
346 * @base_addr: for mapped device memory
347 * @irq: IRQ line for the device
348 * @cfg_data: current cfg, intf, and alt in use
349 * @vbus_gpio: GPIO informaton for detecting VBUS
352 struct usb_gadget gadget;
353 struct usb_gadget_driver *driver;
354 struct pci_dev *pdev;
355 struct pch_udc_ep ep[PCH_UDC_EP_NUM];
356 spinlock_t lock; /* protects all state */
368 struct pci_pool *data_requests;
369 struct pci_pool *stp_requests;
372 struct usb_ctrlrequest setup_data;
373 unsigned long phys_addr;
374 void __iomem *base_addr;
376 struct pch_udc_cfg_data cfg_data;
377 struct pch_vbus_gpio_data vbus_gpio;
380 #define PCH_UDC_PCI_BAR 1
381 #define PCI_DEVICE_ID_INTEL_EG20T_UDC 0x8808
382 #define PCI_VENDOR_ID_ROHM 0x10DB
383 #define PCI_DEVICE_ID_ML7213_IOH_UDC 0x801D
384 #define PCI_DEVICE_ID_ML7831_IOH_UDC 0x8808
386 static const char ep0_string[] = "ep0in";
387 static DEFINE_SPINLOCK(udc_stall_spinlock); /* stall spin lock */
388 struct pch_udc_dev *pch_udc; /* pointer to device object */
389 static bool speed_fs;
390 module_param_named(speed_fs, speed_fs, bool, S_IRUGO);
391 MODULE_PARM_DESC(speed_fs, "true for Full speed operation");
394 * struct pch_udc_request - Structure holding a PCH USB device request packet
395 * @req: embedded ep request
396 * @td_data_phys: phys. address
397 * @td_data: first dma desc. of chain
398 * @td_data_last: last dma desc. of chain
399 * @queue: associated queue
400 * @dma_going: DMA in progress for request
401 * @dma_mapped: DMA memory mapped for request
402 * @dma_done: DMA completed for request
403 * @chain_len: chain length
404 * @buf: Buffer memory for align adjustment
405 * @dma: DMA memory for align adjustment
407 struct pch_udc_request {
408 struct usb_request req;
409 dma_addr_t td_data_phys;
410 struct pch_udc_data_dma_desc *td_data;
411 struct pch_udc_data_dma_desc *td_data_last;
412 struct list_head queue;
413 unsigned dma_going:1,
421 static inline u32 pch_udc_readl(struct pch_udc_dev *dev, unsigned long reg)
423 return ioread32(dev->base_addr + reg);
426 static inline void pch_udc_writel(struct pch_udc_dev *dev,
427 unsigned long val, unsigned long reg)
429 iowrite32(val, dev->base_addr + reg);
432 static inline void pch_udc_bit_set(struct pch_udc_dev *dev,
434 unsigned long bitmask)
436 pch_udc_writel(dev, pch_udc_readl(dev, reg) | bitmask, reg);
439 static inline void pch_udc_bit_clr(struct pch_udc_dev *dev,
441 unsigned long bitmask)
443 pch_udc_writel(dev, pch_udc_readl(dev, reg) & ~(bitmask), reg);
446 static inline u32 pch_udc_ep_readl(struct pch_udc_ep *ep, unsigned long reg)
448 return ioread32(ep->dev->base_addr + ep->offset_addr + reg);
451 static inline void pch_udc_ep_writel(struct pch_udc_ep *ep,
452 unsigned long val, unsigned long reg)
454 iowrite32(val, ep->dev->base_addr + ep->offset_addr + reg);
457 static inline void pch_udc_ep_bit_set(struct pch_udc_ep *ep,
459 unsigned long bitmask)
461 pch_udc_ep_writel(ep, pch_udc_ep_readl(ep, reg) | bitmask, reg);
464 static inline void pch_udc_ep_bit_clr(struct pch_udc_ep *ep,
466 unsigned long bitmask)
468 pch_udc_ep_writel(ep, pch_udc_ep_readl(ep, reg) & ~(bitmask), reg);
472 * pch_udc_csr_busy() - Wait till idle.
473 * @dev: Reference to pch_udc_dev structure
475 static void pch_udc_csr_busy(struct pch_udc_dev *dev)
477 unsigned int count = 200;
480 while ((pch_udc_readl(dev, UDC_CSR_BUSY_ADDR) & UDC_CSR_BUSY)
484 dev_err(&dev->pdev->dev, "%s: wait error\n", __func__);
488 * pch_udc_write_csr() - Write the command and status registers.
489 * @dev: Reference to pch_udc_dev structure
490 * @val: value to be written to CSR register
491 * @addr: address of CSR register
493 static void pch_udc_write_csr(struct pch_udc_dev *dev, unsigned long val,
496 unsigned long reg = PCH_UDC_CSR(ep);
498 pch_udc_csr_busy(dev); /* Wait till idle */
499 pch_udc_writel(dev, val, reg);
500 pch_udc_csr_busy(dev); /* Wait till idle */
504 * pch_udc_read_csr() - Read the command and status registers.
505 * @dev: Reference to pch_udc_dev structure
506 * @addr: address of CSR register
508 * Return codes: content of CSR register
510 static u32 pch_udc_read_csr(struct pch_udc_dev *dev, unsigned int ep)
512 unsigned long reg = PCH_UDC_CSR(ep);
514 pch_udc_csr_busy(dev); /* Wait till idle */
515 pch_udc_readl(dev, reg); /* Dummy read */
516 pch_udc_csr_busy(dev); /* Wait till idle */
517 return pch_udc_readl(dev, reg);
521 * pch_udc_rmt_wakeup() - Initiate for remote wakeup
522 * @dev: Reference to pch_udc_dev structure
524 static inline void pch_udc_rmt_wakeup(struct pch_udc_dev *dev)
526 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
528 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
532 * pch_udc_get_frame() - Get the current frame from device status register
533 * @dev: Reference to pch_udc_dev structure
534 * Retern current frame
536 static inline int pch_udc_get_frame(struct pch_udc_dev *dev)
538 u32 frame = pch_udc_readl(dev, UDC_DEVSTS_ADDR);
539 return (frame & UDC_DEVSTS_TS_MASK) >> UDC_DEVSTS_TS_SHIFT;
543 * pch_udc_clear_selfpowered() - Clear the self power control
544 * @dev: Reference to pch_udc_regs structure
546 static inline void pch_udc_clear_selfpowered(struct pch_udc_dev *dev)
548 pch_udc_bit_clr(dev, UDC_DEVCFG_ADDR, UDC_DEVCFG_SP);
552 * pch_udc_set_selfpowered() - Set the self power control
553 * @dev: Reference to pch_udc_regs structure
555 static inline void pch_udc_set_selfpowered(struct pch_udc_dev *dev)
557 pch_udc_bit_set(dev, UDC_DEVCFG_ADDR, UDC_DEVCFG_SP);
561 * pch_udc_set_disconnect() - Set the disconnect status.
562 * @dev: Reference to pch_udc_regs structure
564 static inline void pch_udc_set_disconnect(struct pch_udc_dev *dev)
566 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_SD);
570 * pch_udc_clear_disconnect() - Clear the disconnect status.
571 * @dev: Reference to pch_udc_regs structure
573 static void pch_udc_clear_disconnect(struct pch_udc_dev *dev)
575 /* Clear the disconnect */
576 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
577 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_SD);
579 /* Resume USB signalling */
580 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
584 * pch_udc_reconnect() - This API initializes usb device controller,
585 * and clear the disconnect status.
586 * @dev: Reference to pch_udc_regs structure
588 static void pch_udc_init(struct pch_udc_dev *dev);
589 static void pch_udc_reconnect(struct pch_udc_dev *dev)
593 /* enable device interrupts */
594 /* pch_udc_enable_interrupts() */
595 pch_udc_bit_clr(dev, UDC_DEVIRQMSK_ADDR,
596 UDC_DEVINT_UR | UDC_DEVINT_ENUM);
598 /* Clear the disconnect */
599 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
600 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_SD);
602 /* Resume USB signalling */
603 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
607 * pch_udc_vbus_session() - set or clearr the disconnect status.
608 * @dev: Reference to pch_udc_regs structure
609 * @is_active: Parameter specifying the action
610 * 0: indicating VBUS power is ending
611 * !0: indicating VBUS power is starting
613 static inline void pch_udc_vbus_session(struct pch_udc_dev *dev,
617 pch_udc_reconnect(dev);
618 dev->vbus_session = 1;
620 if (dev->driver && dev->driver->disconnect) {
621 spin_unlock(&dev->lock);
622 dev->driver->disconnect(&dev->gadget);
623 spin_lock(&dev->lock);
625 pch_udc_set_disconnect(dev);
626 dev->vbus_session = 0;
631 * pch_udc_ep_set_stall() - Set the stall of endpoint
632 * @ep: Reference to structure of type pch_udc_ep_regs
634 static void pch_udc_ep_set_stall(struct pch_udc_ep *ep)
637 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_F);
638 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_S);
640 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_S);
645 * pch_udc_ep_clear_stall() - Clear the stall of endpoint
646 * @ep: Reference to structure of type pch_udc_ep_regs
648 static inline void pch_udc_ep_clear_stall(struct pch_udc_ep *ep)
650 /* Clear the stall */
651 pch_udc_ep_bit_clr(ep, UDC_EPCTL_ADDR, UDC_EPCTL_S);
652 /* Clear NAK by writing CNAK */
653 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_CNAK);
657 * pch_udc_ep_set_trfr_type() - Set the transfer type of endpoint
658 * @ep: Reference to structure of type pch_udc_ep_regs
659 * @type: Type of endpoint
661 static inline void pch_udc_ep_set_trfr_type(struct pch_udc_ep *ep,
664 pch_udc_ep_writel(ep, ((type << UDC_EPCTL_ET_SHIFT) &
665 UDC_EPCTL_ET_MASK), UDC_EPCTL_ADDR);
669 * pch_udc_ep_set_bufsz() - Set the maximum packet size for the endpoint
670 * @ep: Reference to structure of type pch_udc_ep_regs
671 * @buf_size: The buffer word size
673 static void pch_udc_ep_set_bufsz(struct pch_udc_ep *ep,
674 u32 buf_size, u32 ep_in)
678 data = pch_udc_ep_readl(ep, UDC_BUFIN_FRAMENUM_ADDR);
679 data = (data & 0xffff0000) | (buf_size & 0xffff);
680 pch_udc_ep_writel(ep, data, UDC_BUFIN_FRAMENUM_ADDR);
682 data = pch_udc_ep_readl(ep, UDC_BUFOUT_MAXPKT_ADDR);
683 data = (buf_size << 16) | (data & 0xffff);
684 pch_udc_ep_writel(ep, data, UDC_BUFOUT_MAXPKT_ADDR);
689 * pch_udc_ep_set_maxpkt() - Set the Max packet size for the endpoint
690 * @ep: Reference to structure of type pch_udc_ep_regs
691 * @pkt_size: The packet byte size
693 static void pch_udc_ep_set_maxpkt(struct pch_udc_ep *ep, u32 pkt_size)
695 u32 data = pch_udc_ep_readl(ep, UDC_BUFOUT_MAXPKT_ADDR);
696 data = (data & 0xffff0000) | (pkt_size & 0xffff);
697 pch_udc_ep_writel(ep, data, UDC_BUFOUT_MAXPKT_ADDR);
701 * pch_udc_ep_set_subptr() - Set the Setup buffer pointer for the endpoint
702 * @ep: Reference to structure of type pch_udc_ep_regs
703 * @addr: Address of the register
705 static inline void pch_udc_ep_set_subptr(struct pch_udc_ep *ep, u32 addr)
707 pch_udc_ep_writel(ep, addr, UDC_SUBPTR_ADDR);
711 * pch_udc_ep_set_ddptr() - Set the Data descriptor pointer for the endpoint
712 * @ep: Reference to structure of type pch_udc_ep_regs
713 * @addr: Address of the register
715 static inline void pch_udc_ep_set_ddptr(struct pch_udc_ep *ep, u32 addr)
717 pch_udc_ep_writel(ep, addr, UDC_DESPTR_ADDR);
721 * pch_udc_ep_set_pd() - Set the poll demand bit for the endpoint
722 * @ep: Reference to structure of type pch_udc_ep_regs
724 static inline void pch_udc_ep_set_pd(struct pch_udc_ep *ep)
726 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_P);
730 * pch_udc_ep_set_rrdy() - Set the receive ready bit for the endpoint
731 * @ep: Reference to structure of type pch_udc_ep_regs
733 static inline void pch_udc_ep_set_rrdy(struct pch_udc_ep *ep)
735 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_RRDY);
739 * pch_udc_ep_clear_rrdy() - Clear the receive ready bit for the endpoint
740 * @ep: Reference to structure of type pch_udc_ep_regs
742 static inline void pch_udc_ep_clear_rrdy(struct pch_udc_ep *ep)
744 pch_udc_ep_bit_clr(ep, UDC_EPCTL_ADDR, UDC_EPCTL_RRDY);
748 * pch_udc_set_dma() - Set the 'TDE' or RDE bit of device control
749 * register depending on the direction specified
750 * @dev: Reference to structure of type pch_udc_regs
751 * @dir: whether Tx or Rx
752 * DMA_DIR_RX: Receive
753 * DMA_DIR_TX: Transmit
755 static inline void pch_udc_set_dma(struct pch_udc_dev *dev, int dir)
757 if (dir == DMA_DIR_RX)
758 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RDE);
759 else if (dir == DMA_DIR_TX)
760 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_TDE);
764 * pch_udc_clear_dma() - Clear the 'TDE' or RDE bit of device control
765 * register depending on the direction specified
766 * @dev: Reference to structure of type pch_udc_regs
767 * @dir: Whether Tx or Rx
768 * DMA_DIR_RX: Receive
769 * DMA_DIR_TX: Transmit
771 static inline void pch_udc_clear_dma(struct pch_udc_dev *dev, int dir)
773 if (dir == DMA_DIR_RX)
774 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RDE);
775 else if (dir == DMA_DIR_TX)
776 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_TDE);
780 * pch_udc_set_csr_done() - Set the device control register
781 * CSR done field (bit 13)
782 * @dev: reference to structure of type pch_udc_regs
784 static inline void pch_udc_set_csr_done(struct pch_udc_dev *dev)
786 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_CSR_DONE);
790 * pch_udc_disable_interrupts() - Disables the specified interrupts
791 * @dev: Reference to structure of type pch_udc_regs
792 * @mask: Mask to disable interrupts
794 static inline void pch_udc_disable_interrupts(struct pch_udc_dev *dev,
797 pch_udc_bit_set(dev, UDC_DEVIRQMSK_ADDR, mask);
801 * pch_udc_enable_interrupts() - Enable the specified interrupts
802 * @dev: Reference to structure of type pch_udc_regs
803 * @mask: Mask to enable interrupts
805 static inline void pch_udc_enable_interrupts(struct pch_udc_dev *dev,
808 pch_udc_bit_clr(dev, UDC_DEVIRQMSK_ADDR, mask);
812 * pch_udc_disable_ep_interrupts() - Disable endpoint interrupts
813 * @dev: Reference to structure of type pch_udc_regs
814 * @mask: Mask to disable interrupts
816 static inline void pch_udc_disable_ep_interrupts(struct pch_udc_dev *dev,
819 pch_udc_bit_set(dev, UDC_EPIRQMSK_ADDR, mask);
823 * pch_udc_enable_ep_interrupts() - Enable endpoint interrupts
824 * @dev: Reference to structure of type pch_udc_regs
825 * @mask: Mask to enable interrupts
827 static inline void pch_udc_enable_ep_interrupts(struct pch_udc_dev *dev,
830 pch_udc_bit_clr(dev, UDC_EPIRQMSK_ADDR, mask);
834 * pch_udc_read_device_interrupts() - Read the device interrupts
835 * @dev: Reference to structure of type pch_udc_regs
836 * Retern The device interrupts
838 static inline u32 pch_udc_read_device_interrupts(struct pch_udc_dev *dev)
840 return pch_udc_readl(dev, UDC_DEVIRQSTS_ADDR);
844 * pch_udc_write_device_interrupts() - Write device interrupts
845 * @dev: Reference to structure of type pch_udc_regs
846 * @val: The value to be written to interrupt register
848 static inline void pch_udc_write_device_interrupts(struct pch_udc_dev *dev,
851 pch_udc_writel(dev, val, UDC_DEVIRQSTS_ADDR);
855 * pch_udc_read_ep_interrupts() - Read the endpoint interrupts
856 * @dev: Reference to structure of type pch_udc_regs
857 * Retern The endpoint interrupt
859 static inline u32 pch_udc_read_ep_interrupts(struct pch_udc_dev *dev)
861 return pch_udc_readl(dev, UDC_EPIRQSTS_ADDR);
865 * pch_udc_write_ep_interrupts() - Clear endpoint interupts
866 * @dev: Reference to structure of type pch_udc_regs
867 * @val: The value to be written to interrupt register
869 static inline void pch_udc_write_ep_interrupts(struct pch_udc_dev *dev,
872 pch_udc_writel(dev, val, UDC_EPIRQSTS_ADDR);
876 * pch_udc_read_device_status() - Read the device status
877 * @dev: Reference to structure of type pch_udc_regs
878 * Retern The device status
880 static inline u32 pch_udc_read_device_status(struct pch_udc_dev *dev)
882 return pch_udc_readl(dev, UDC_DEVSTS_ADDR);
886 * pch_udc_read_ep_control() - Read the endpoint control
887 * @ep: Reference to structure of type pch_udc_ep_regs
888 * Retern The endpoint control register value
890 static inline u32 pch_udc_read_ep_control(struct pch_udc_ep *ep)
892 return pch_udc_ep_readl(ep, UDC_EPCTL_ADDR);
896 * pch_udc_clear_ep_control() - Clear the endpoint control register
897 * @ep: Reference to structure of type pch_udc_ep_regs
898 * Retern The endpoint control register value
900 static inline void pch_udc_clear_ep_control(struct pch_udc_ep *ep)
902 return pch_udc_ep_writel(ep, 0, UDC_EPCTL_ADDR);
906 * pch_udc_read_ep_status() - Read the endpoint status
907 * @ep: Reference to structure of type pch_udc_ep_regs
908 * Retern The endpoint status
910 static inline u32 pch_udc_read_ep_status(struct pch_udc_ep *ep)
912 return pch_udc_ep_readl(ep, UDC_EPSTS_ADDR);
916 * pch_udc_clear_ep_status() - Clear the endpoint status
917 * @ep: Reference to structure of type pch_udc_ep_regs
918 * @stat: Endpoint status
920 static inline void pch_udc_clear_ep_status(struct pch_udc_ep *ep,
923 return pch_udc_ep_writel(ep, stat, UDC_EPSTS_ADDR);
927 * pch_udc_ep_set_nak() - Set the bit 7 (SNAK field)
928 * of the endpoint control register
929 * @ep: Reference to structure of type pch_udc_ep_regs
931 static inline void pch_udc_ep_set_nak(struct pch_udc_ep *ep)
933 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_SNAK);
937 * pch_udc_ep_clear_nak() - Set the bit 8 (CNAK field)
938 * of the endpoint control register
939 * @ep: reference to structure of type pch_udc_ep_regs
941 static void pch_udc_ep_clear_nak(struct pch_udc_ep *ep)
943 unsigned int loopcnt = 0;
944 struct pch_udc_dev *dev = ep->dev;
946 if (!(pch_udc_ep_readl(ep, UDC_EPCTL_ADDR) & UDC_EPCTL_NAK))
950 while (!(pch_udc_read_ep_status(ep) & UDC_EPSTS_MRXFIFO_EMP) &&
954 dev_err(&dev->pdev->dev, "%s: RxFIFO not Empty\n",
958 while ((pch_udc_read_ep_control(ep) & UDC_EPCTL_NAK) && --loopcnt) {
959 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_CNAK);
963 dev_err(&dev->pdev->dev, "%s: Clear NAK not set for ep%d%s\n",
964 __func__, ep->num, (ep->in ? "in" : "out"));
968 * pch_udc_ep_fifo_flush() - Flush the endpoint fifo
969 * @ep: reference to structure of type pch_udc_ep_regs
970 * @dir: direction of endpoint
974 static void pch_udc_ep_fifo_flush(struct pch_udc_ep *ep, int dir)
976 if (dir) { /* IN ep */
977 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_F);
983 * pch_udc_ep_enable() - This api enables endpoint
984 * @regs: Reference to structure pch_udc_ep_regs
985 * @desc: endpoint descriptor
987 static void pch_udc_ep_enable(struct pch_udc_ep *ep,
988 struct pch_udc_cfg_data *cfg,
989 const struct usb_endpoint_descriptor *desc)
994 pch_udc_ep_set_trfr_type(ep, desc->bmAttributes);
996 buff_size = UDC_EPIN_BUFF_SIZE;
998 buff_size = UDC_EPOUT_BUFF_SIZE;
999 pch_udc_ep_set_bufsz(ep, buff_size, ep->in);
1000 pch_udc_ep_set_maxpkt(ep, usb_endpoint_maxp(desc));
1001 pch_udc_ep_set_nak(ep);
1002 pch_udc_ep_fifo_flush(ep, ep->in);
1003 /* Configure the endpoint */
1004 val = ep->num << UDC_CSR_NE_NUM_SHIFT | ep->in << UDC_CSR_NE_DIR_SHIFT |
1005 ((desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) <<
1006 UDC_CSR_NE_TYPE_SHIFT) |
1007 (cfg->cur_cfg << UDC_CSR_NE_CFG_SHIFT) |
1008 (cfg->cur_intf << UDC_CSR_NE_INTF_SHIFT) |
1009 (cfg->cur_alt << UDC_CSR_NE_ALT_SHIFT) |
1010 usb_endpoint_maxp(desc) << UDC_CSR_NE_MAX_PKT_SHIFT;
1013 pch_udc_write_csr(ep->dev, val, UDC_EPIN_IDX(ep->num));
1015 pch_udc_write_csr(ep->dev, val, UDC_EPOUT_IDX(ep->num));
1019 * pch_udc_ep_disable() - This api disables endpoint
1020 * @regs: Reference to structure pch_udc_ep_regs
1022 static void pch_udc_ep_disable(struct pch_udc_ep *ep)
1025 /* flush the fifo */
1026 pch_udc_ep_writel(ep, UDC_EPCTL_F, UDC_EPCTL_ADDR);
1028 pch_udc_ep_writel(ep, UDC_EPCTL_SNAK, UDC_EPCTL_ADDR);
1029 pch_udc_ep_bit_set(ep, UDC_EPSTS_ADDR, UDC_EPSTS_IN);
1032 pch_udc_ep_writel(ep, UDC_EPCTL_SNAK, UDC_EPCTL_ADDR);
1034 /* reset desc pointer */
1035 pch_udc_ep_writel(ep, 0, UDC_DESPTR_ADDR);
1039 * pch_udc_wait_ep_stall() - Wait EP stall.
1040 * @dev: Reference to pch_udc_dev structure
1042 static void pch_udc_wait_ep_stall(struct pch_udc_ep *ep)
1044 unsigned int count = 10000;
1046 /* Wait till idle */
1047 while ((pch_udc_read_ep_control(ep) & UDC_EPCTL_S) && --count)
1050 dev_err(&ep->dev->pdev->dev, "%s: wait error\n", __func__);
1054 * pch_udc_init() - This API initializes usb device controller
1055 * @dev: Rreference to pch_udc_regs structure
1057 static void pch_udc_init(struct pch_udc_dev *dev)
1060 pr_err("%s: Invalid address\n", __func__);
1063 /* Soft Reset and Reset PHY */
1064 pch_udc_writel(dev, UDC_SRST, UDC_SRST_ADDR);
1065 pch_udc_writel(dev, UDC_SRST | UDC_PSRST, UDC_SRST_ADDR);
1067 pch_udc_writel(dev, UDC_SRST, UDC_SRST_ADDR);
1068 pch_udc_writel(dev, 0x00, UDC_SRST_ADDR);
1070 /* mask and clear all device interrupts */
1071 pch_udc_bit_set(dev, UDC_DEVIRQMSK_ADDR, UDC_DEVINT_MSK);
1072 pch_udc_bit_set(dev, UDC_DEVIRQSTS_ADDR, UDC_DEVINT_MSK);
1074 /* mask and clear all ep interrupts */
1075 pch_udc_bit_set(dev, UDC_EPIRQMSK_ADDR, UDC_EPINT_MSK_DISABLE_ALL);
1076 pch_udc_bit_set(dev, UDC_EPIRQSTS_ADDR, UDC_EPINT_MSK_DISABLE_ALL);
1078 /* enable dynamic CSR programmingi, self powered and device speed */
1080 pch_udc_bit_set(dev, UDC_DEVCFG_ADDR, UDC_DEVCFG_CSR_PRG |
1081 UDC_DEVCFG_SP | UDC_DEVCFG_SPD_FS);
1082 else /* defaul high speed */
1083 pch_udc_bit_set(dev, UDC_DEVCFG_ADDR, UDC_DEVCFG_CSR_PRG |
1084 UDC_DEVCFG_SP | UDC_DEVCFG_SPD_HS);
1085 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR,
1086 (PCH_UDC_THLEN << UDC_DEVCTL_THLEN_SHIFT) |
1087 (PCH_UDC_BRLEN << UDC_DEVCTL_BRLEN_SHIFT) |
1088 UDC_DEVCTL_MODE | UDC_DEVCTL_BREN |
1093 * pch_udc_exit() - This API exit usb device controller
1094 * @dev: Reference to pch_udc_regs structure
1096 static void pch_udc_exit(struct pch_udc_dev *dev)
1098 /* mask all device interrupts */
1099 pch_udc_bit_set(dev, UDC_DEVIRQMSK_ADDR, UDC_DEVINT_MSK);
1100 /* mask all ep interrupts */
1101 pch_udc_bit_set(dev, UDC_EPIRQMSK_ADDR, UDC_EPINT_MSK_DISABLE_ALL);
1102 /* put device in disconnected state */
1103 pch_udc_set_disconnect(dev);
1107 * pch_udc_pcd_get_frame() - This API is invoked to get the current frame number
1108 * @gadget: Reference to the gadget driver
1112 * -EINVAL: If the gadget passed is NULL
1114 static int pch_udc_pcd_get_frame(struct usb_gadget *gadget)
1116 struct pch_udc_dev *dev;
1120 dev = container_of(gadget, struct pch_udc_dev, gadget);
1121 return pch_udc_get_frame(dev);
1125 * pch_udc_pcd_wakeup() - This API is invoked to initiate a remote wakeup
1126 * @gadget: Reference to the gadget driver
1130 * -EINVAL: If the gadget passed is NULL
1132 static int pch_udc_pcd_wakeup(struct usb_gadget *gadget)
1134 struct pch_udc_dev *dev;
1135 unsigned long flags;
1139 dev = container_of(gadget, struct pch_udc_dev, gadget);
1140 spin_lock_irqsave(&dev->lock, flags);
1141 pch_udc_rmt_wakeup(dev);
1142 spin_unlock_irqrestore(&dev->lock, flags);
1147 * pch_udc_pcd_selfpowered() - This API is invoked to specify whether the device
1148 * is self powered or not
1149 * @gadget: Reference to the gadget driver
1150 * @value: Specifies self powered or not
1154 * -EINVAL: If the gadget passed is NULL
1156 static int pch_udc_pcd_selfpowered(struct usb_gadget *gadget, int value)
1158 struct pch_udc_dev *dev;
1162 dev = container_of(gadget, struct pch_udc_dev, gadget);
1164 pch_udc_set_selfpowered(dev);
1166 pch_udc_clear_selfpowered(dev);
1171 * pch_udc_pcd_pullup() - This API is invoked to make the device
1172 * visible/invisible to the host
1173 * @gadget: Reference to the gadget driver
1174 * @is_on: Specifies whether the pull up is made active or inactive
1178 * -EINVAL: If the gadget passed is NULL
1180 static int pch_udc_pcd_pullup(struct usb_gadget *gadget, int is_on)
1182 struct pch_udc_dev *dev;
1186 dev = container_of(gadget, struct pch_udc_dev, gadget);
1188 pch_udc_reconnect(dev);
1190 if (dev->driver && dev->driver->disconnect) {
1191 spin_unlock(&dev->lock);
1192 dev->driver->disconnect(&dev->gadget);
1193 spin_lock(&dev->lock);
1195 pch_udc_set_disconnect(dev);
1202 * pch_udc_pcd_vbus_session() - This API is used by a driver for an external
1203 * transceiver (or GPIO) that
1204 * detects a VBUS power session starting/ending
1205 * @gadget: Reference to the gadget driver
1206 * @is_active: specifies whether the session is starting or ending
1210 * -EINVAL: If the gadget passed is NULL
1212 static int pch_udc_pcd_vbus_session(struct usb_gadget *gadget, int is_active)
1214 struct pch_udc_dev *dev;
1218 dev = container_of(gadget, struct pch_udc_dev, gadget);
1219 pch_udc_vbus_session(dev, is_active);
1224 * pch_udc_pcd_vbus_draw() - This API is used by gadget drivers during
1225 * SET_CONFIGURATION calls to
1226 * specify how much power the device can consume
1227 * @gadget: Reference to the gadget driver
1228 * @mA: specifies the current limit in 2mA unit
1231 * -EINVAL: If the gadget passed is NULL
1234 static int pch_udc_pcd_vbus_draw(struct usb_gadget *gadget, unsigned int mA)
1239 static int pch_udc_start(struct usb_gadget_driver *driver,
1240 int (*bind)(struct usb_gadget *));
1241 static int pch_udc_stop(struct usb_gadget_driver *driver);
1242 static const struct usb_gadget_ops pch_udc_ops = {
1243 .get_frame = pch_udc_pcd_get_frame,
1244 .wakeup = pch_udc_pcd_wakeup,
1245 .set_selfpowered = pch_udc_pcd_selfpowered,
1246 .pullup = pch_udc_pcd_pullup,
1247 .vbus_session = pch_udc_pcd_vbus_session,
1248 .vbus_draw = pch_udc_pcd_vbus_draw,
1249 .start = pch_udc_start,
1250 .stop = pch_udc_stop,
1254 * pch_vbus_gpio_get_value() - This API gets value of GPIO port as VBUS status.
1255 * @dev: Reference to the driver structure
1260 * -1: It is not enable to detect VBUS using GPIO
1262 static int pch_vbus_gpio_get_value(struct pch_udc_dev *dev)
1266 if (dev->vbus_gpio.port)
1267 vbus = gpio_get_value(dev->vbus_gpio.port) ? 1 : 0;
1275 * pch_vbus_gpio_work_fall() - This API keeps watch on VBUS becoming Low.
1276 * If VBUS is Low, disconnect is processed
1277 * @irq_work: Structure for WorkQueue
1280 static void pch_vbus_gpio_work_fall(struct work_struct *irq_work)
1282 struct pch_vbus_gpio_data *vbus_gpio = container_of(irq_work,
1283 struct pch_vbus_gpio_data, irq_work_fall);
1284 struct pch_udc_dev *dev =
1285 container_of(vbus_gpio, struct pch_udc_dev, vbus_gpio);
1286 int vbus_saved = -1;
1290 if (!dev->vbus_gpio.port)
1293 for (count = 0; count < (PCH_VBUS_PERIOD / PCH_VBUS_INTERVAL);
1295 vbus = pch_vbus_gpio_get_value(dev);
1297 if ((vbus_saved == vbus) && (vbus == 0)) {
1298 dev_dbg(&dev->pdev->dev, "VBUS fell");
1300 && dev->driver->disconnect) {
1301 dev->driver->disconnect(
1304 if (dev->vbus_gpio.intr)
1307 pch_udc_reconnect(dev);
1311 mdelay(PCH_VBUS_INTERVAL);
1316 * pch_vbus_gpio_work_rise() - This API checks VBUS is High.
1317 * If VBUS is High, connect is processed
1318 * @irq_work: Structure for WorkQueue
1321 static void pch_vbus_gpio_work_rise(struct work_struct *irq_work)
1323 struct pch_vbus_gpio_data *vbus_gpio = container_of(irq_work,
1324 struct pch_vbus_gpio_data, irq_work_rise);
1325 struct pch_udc_dev *dev =
1326 container_of(vbus_gpio, struct pch_udc_dev, vbus_gpio);
1329 if (!dev->vbus_gpio.port)
1332 mdelay(PCH_VBUS_INTERVAL);
1333 vbus = pch_vbus_gpio_get_value(dev);
1336 dev_dbg(&dev->pdev->dev, "VBUS rose");
1337 pch_udc_reconnect(dev);
1343 * pch_vbus_gpio_irq() - IRQ handler for GPIO intrerrupt for changing VBUS
1344 * @irq: Interrupt request number
1345 * @dev: Reference to the device structure
1349 * -EINVAL: GPIO port is invalid or can't be initialized.
1351 static irqreturn_t pch_vbus_gpio_irq(int irq, void *data)
1353 struct pch_udc_dev *dev = (struct pch_udc_dev *)data;
1355 if (!dev->vbus_gpio.port || !dev->vbus_gpio.intr)
1358 if (pch_vbus_gpio_get_value(dev))
1359 schedule_work(&dev->vbus_gpio.irq_work_rise);
1361 schedule_work(&dev->vbus_gpio.irq_work_fall);
1367 * pch_vbus_gpio_init() - This API initializes GPIO port detecting VBUS.
1368 * @dev: Reference to the driver structure
1369 * @vbus_gpio Number of GPIO port to detect gpio
1373 * -EINVAL: GPIO port is invalid or can't be initialized.
1375 static int pch_vbus_gpio_init(struct pch_udc_dev *dev, int vbus_gpio_port)
1380 dev->vbus_gpio.port = 0;
1381 dev->vbus_gpio.intr = 0;
1383 if (vbus_gpio_port <= -1)
1386 err = gpio_is_valid(vbus_gpio_port);
1388 pr_err("%s: gpio port %d is invalid\n",
1389 __func__, vbus_gpio_port);
1393 err = gpio_request(vbus_gpio_port, "pch_vbus");
1395 pr_err("%s: can't request gpio port %d, err: %d\n",
1396 __func__, vbus_gpio_port, err);
1400 dev->vbus_gpio.port = vbus_gpio_port;
1401 gpio_direction_input(vbus_gpio_port);
1402 INIT_WORK(&dev->vbus_gpio.irq_work_fall, pch_vbus_gpio_work_fall);
1404 irq_num = gpio_to_irq(vbus_gpio_port);
1406 irq_set_irq_type(irq_num, IRQ_TYPE_EDGE_BOTH);
1407 err = request_irq(irq_num, pch_vbus_gpio_irq, 0,
1408 "vbus_detect", dev);
1410 dev->vbus_gpio.intr = irq_num;
1411 INIT_WORK(&dev->vbus_gpio.irq_work_rise,
1412 pch_vbus_gpio_work_rise);
1414 pr_err("%s: can't request irq %d, err: %d\n",
1415 __func__, irq_num, err);
1423 * pch_vbus_gpio_free() - This API frees resources of GPIO port
1424 * @dev: Reference to the driver structure
1426 static void pch_vbus_gpio_free(struct pch_udc_dev *dev)
1428 if (dev->vbus_gpio.intr)
1429 free_irq(dev->vbus_gpio.intr, dev);
1431 if (dev->vbus_gpio.port)
1432 gpio_free(dev->vbus_gpio.port);
1436 * complete_req() - This API is invoked from the driver when processing
1437 * of a request is complete
1438 * @ep: Reference to the endpoint structure
1439 * @req: Reference to the request structure
1440 * @status: Indicates the success/failure of completion
1442 static void complete_req(struct pch_udc_ep *ep, struct pch_udc_request *req,
1445 struct pch_udc_dev *dev;
1446 unsigned halted = ep->halted;
1448 list_del_init(&req->queue);
1450 /* set new status if pending */
1451 if (req->req.status == -EINPROGRESS)
1452 req->req.status = status;
1454 status = req->req.status;
1457 if (req->dma_mapped) {
1458 if (req->dma == DMA_ADDR_INVALID) {
1460 dma_unmap_single(&dev->pdev->dev, req->req.dma,
1464 dma_unmap_single(&dev->pdev->dev, req->req.dma,
1467 req->req.dma = DMA_ADDR_INVALID;
1470 dma_unmap_single(&dev->pdev->dev, req->dma,
1474 dma_unmap_single(&dev->pdev->dev, req->dma,
1477 memcpy(req->req.buf, req->buf, req->req.length);
1480 req->dma = DMA_ADDR_INVALID;
1482 req->dma_mapped = 0;
1485 spin_unlock(&dev->lock);
1487 pch_udc_ep_clear_rrdy(ep);
1488 req->req.complete(&ep->ep, &req->req);
1489 spin_lock(&dev->lock);
1490 ep->halted = halted;
1494 * empty_req_queue() - This API empties the request queue of an endpoint
1495 * @ep: Reference to the endpoint structure
1497 static void empty_req_queue(struct pch_udc_ep *ep)
1499 struct pch_udc_request *req;
1502 while (!list_empty(&ep->queue)) {
1503 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
1504 complete_req(ep, req, -ESHUTDOWN); /* Remove from list */
1509 * pch_udc_free_dma_chain() - This function frees the DMA chain created
1511 * @dev Reference to the driver structure
1512 * @req Reference to the request to be freed
1517 static void pch_udc_free_dma_chain(struct pch_udc_dev *dev,
1518 struct pch_udc_request *req)
1520 struct pch_udc_data_dma_desc *td = req->td_data;
1521 unsigned i = req->chain_len;
1524 dma_addr_t addr = (dma_addr_t)td->next;
1526 for (; i > 1; --i) {
1527 /* do not free first desc., will be done by free for request */
1528 td = phys_to_virt(addr);
1529 addr2 = (dma_addr_t)td->next;
1530 pci_pool_free(dev->data_requests, td, addr);
1538 * pch_udc_create_dma_chain() - This function creates or reinitializes
1540 * @ep: Reference to the endpoint structure
1541 * @req: Reference to the request
1542 * @buf_len: The buffer length
1543 * @gfp_flags: Flags to be used while mapping the data buffer
1547 * -ENOMEM: pci_pool_alloc invocation fails
1549 static int pch_udc_create_dma_chain(struct pch_udc_ep *ep,
1550 struct pch_udc_request *req,
1551 unsigned long buf_len,
1554 struct pch_udc_data_dma_desc *td = req->td_data, *last;
1555 unsigned long bytes = req->req.length, i = 0;
1556 dma_addr_t dma_addr;
1559 if (req->chain_len > 1)
1560 pch_udc_free_dma_chain(ep->dev, req);
1562 if (req->dma == DMA_ADDR_INVALID)
1563 td->dataptr = req->req.dma;
1565 td->dataptr = req->dma;
1567 td->status = PCH_UDC_BS_HST_BSY;
1568 for (; ; bytes -= buf_len, ++len) {
1569 td->status = PCH_UDC_BS_HST_BSY | min(buf_len, bytes);
1570 if (bytes <= buf_len)
1573 td = pci_pool_alloc(ep->dev->data_requests, gfp_flags,
1578 td->dataptr = req->td_data->dataptr + i;
1579 last->next = dma_addr;
1582 req->td_data_last = td;
1583 td->status |= PCH_UDC_DMA_LAST;
1584 td->next = req->td_data_phys;
1585 req->chain_len = len;
1590 req->chain_len = len;
1591 pch_udc_free_dma_chain(ep->dev, req);
1598 * prepare_dma() - This function creates and initializes the DMA chain
1600 * @ep: Reference to the endpoint structure
1601 * @req: Reference to the request
1602 * @gfp: Flag to be used while mapping the data buffer
1606 * Other 0: linux error number on failure
1608 static int prepare_dma(struct pch_udc_ep *ep, struct pch_udc_request *req,
1613 /* Allocate and create a DMA chain */
1614 retval = pch_udc_create_dma_chain(ep, req, ep->ep.maxpacket, gfp);
1616 pr_err("%s: could not create DMA chain:%d\n", __func__, retval);
1620 req->td_data->status = (req->td_data->status &
1621 ~PCH_UDC_BUFF_STS) | PCH_UDC_BS_HST_RDY;
1626 * process_zlp() - This function process zero length packets
1627 * from the gadget driver
1628 * @ep: Reference to the endpoint structure
1629 * @req: Reference to the request
1631 static void process_zlp(struct pch_udc_ep *ep, struct pch_udc_request *req)
1633 struct pch_udc_dev *dev = ep->dev;
1635 /* IN zlp's are handled by hardware */
1636 complete_req(ep, req, 0);
1638 /* if set_config or set_intf is waiting for ack by zlp
1641 if (dev->set_cfg_not_acked) {
1642 pch_udc_set_csr_done(dev);
1643 dev->set_cfg_not_acked = 0;
1645 /* setup command is ACK'ed now by zlp */
1646 if (!dev->stall && dev->waiting_zlp_ack) {
1647 pch_udc_ep_clear_nak(&(dev->ep[UDC_EP0IN_IDX]));
1648 dev->waiting_zlp_ack = 0;
1653 * pch_udc_start_rxrequest() - This function starts the receive requirement.
1654 * @ep: Reference to the endpoint structure
1655 * @req: Reference to the request structure
1657 static void pch_udc_start_rxrequest(struct pch_udc_ep *ep,
1658 struct pch_udc_request *req)
1660 struct pch_udc_data_dma_desc *td_data;
1662 pch_udc_clear_dma(ep->dev, DMA_DIR_RX);
1663 td_data = req->td_data;
1664 /* Set the status bits for all descriptors */
1666 td_data->status = (td_data->status & ~PCH_UDC_BUFF_STS) |
1668 if ((td_data->status & PCH_UDC_DMA_LAST) == PCH_UDC_DMA_LAST)
1670 td_data = phys_to_virt(td_data->next);
1672 /* Write the descriptor pointer */
1673 pch_udc_ep_set_ddptr(ep, req->td_data_phys);
1675 pch_udc_enable_ep_interrupts(ep->dev, UDC_EPINT_OUT_EP0 << ep->num);
1676 pch_udc_set_dma(ep->dev, DMA_DIR_RX);
1677 pch_udc_ep_clear_nak(ep);
1678 pch_udc_ep_set_rrdy(ep);
1682 * pch_udc_pcd_ep_enable() - This API enables the endpoint. It is called
1683 * from gadget driver
1684 * @usbep: Reference to the USB endpoint structure
1685 * @desc: Reference to the USB endpoint descriptor structure
1692 static int pch_udc_pcd_ep_enable(struct usb_ep *usbep,
1693 const struct usb_endpoint_descriptor *desc)
1695 struct pch_udc_ep *ep;
1696 struct pch_udc_dev *dev;
1697 unsigned long iflags;
1699 if (!usbep || (usbep->name == ep0_string) || !desc ||
1700 (desc->bDescriptorType != USB_DT_ENDPOINT) || !desc->wMaxPacketSize)
1703 ep = container_of(usbep, struct pch_udc_ep, ep);
1705 if (!dev->driver || (dev->gadget.speed == USB_SPEED_UNKNOWN))
1707 spin_lock_irqsave(&dev->lock, iflags);
1710 pch_udc_ep_enable(ep, &ep->dev->cfg_data, desc);
1711 ep->ep.maxpacket = usb_endpoint_maxp(desc);
1712 pch_udc_enable_ep_interrupts(ep->dev, PCH_UDC_EPINT(ep->in, ep->num));
1713 spin_unlock_irqrestore(&dev->lock, iflags);
1718 * pch_udc_pcd_ep_disable() - This API disables endpoint and is called
1719 * from gadget driver
1720 * @usbep Reference to the USB endpoint structure
1726 static int pch_udc_pcd_ep_disable(struct usb_ep *usbep)
1728 struct pch_udc_ep *ep;
1729 struct pch_udc_dev *dev;
1730 unsigned long iflags;
1735 ep = container_of(usbep, struct pch_udc_ep, ep);
1737 if ((usbep->name == ep0_string) || !ep->desc)
1740 spin_lock_irqsave(&ep->dev->lock, iflags);
1741 empty_req_queue(ep);
1743 pch_udc_ep_disable(ep);
1744 pch_udc_disable_ep_interrupts(ep->dev, PCH_UDC_EPINT(ep->in, ep->num));
1747 INIT_LIST_HEAD(&ep->queue);
1748 spin_unlock_irqrestore(&ep->dev->lock, iflags);
1753 * pch_udc_alloc_request() - This function allocates request structure.
1754 * It is called by gadget driver
1755 * @usbep: Reference to the USB endpoint structure
1756 * @gfp: Flag to be used while allocating memory
1760 * Allocated address: Success
1762 static struct usb_request *pch_udc_alloc_request(struct usb_ep *usbep,
1765 struct pch_udc_request *req;
1766 struct pch_udc_ep *ep;
1767 struct pch_udc_data_dma_desc *dma_desc;
1768 struct pch_udc_dev *dev;
1772 ep = container_of(usbep, struct pch_udc_ep, ep);
1774 req = kzalloc(sizeof *req, gfp);
1777 req->req.dma = DMA_ADDR_INVALID;
1778 req->dma = DMA_ADDR_INVALID;
1779 INIT_LIST_HEAD(&req->queue);
1780 if (!ep->dev->dma_addr)
1782 /* ep0 in requests are allocated from data pool here */
1783 dma_desc = pci_pool_alloc(ep->dev->data_requests, gfp,
1784 &req->td_data_phys);
1785 if (NULL == dma_desc) {
1789 /* prevent from using desc. - set HOST BUSY */
1790 dma_desc->status |= PCH_UDC_BS_HST_BSY;
1791 dma_desc->dataptr = __constant_cpu_to_le32(DMA_ADDR_INVALID);
1792 req->td_data = dma_desc;
1793 req->td_data_last = dma_desc;
1799 * pch_udc_free_request() - This function frees request structure.
1800 * It is called by gadget driver
1801 * @usbep: Reference to the USB endpoint structure
1802 * @usbreq: Reference to the USB request
1804 static void pch_udc_free_request(struct usb_ep *usbep,
1805 struct usb_request *usbreq)
1807 struct pch_udc_ep *ep;
1808 struct pch_udc_request *req;
1809 struct pch_udc_dev *dev;
1811 if (!usbep || !usbreq)
1813 ep = container_of(usbep, struct pch_udc_ep, ep);
1814 req = container_of(usbreq, struct pch_udc_request, req);
1816 if (!list_empty(&req->queue))
1817 dev_err(&dev->pdev->dev, "%s: %s req=0x%p queue not empty\n",
1818 __func__, usbep->name, req);
1819 if (req->td_data != NULL) {
1820 if (req->chain_len > 1)
1821 pch_udc_free_dma_chain(ep->dev, req);
1822 pci_pool_free(ep->dev->data_requests, req->td_data,
1829 * pch_udc_pcd_queue() - This function queues a request packet. It is called
1831 * @usbep: Reference to the USB endpoint structure
1832 * @usbreq: Reference to the USB request
1833 * @gfp: Flag to be used while mapping the data buffer
1837 * linux error number: Failure
1839 static int pch_udc_pcd_queue(struct usb_ep *usbep, struct usb_request *usbreq,
1843 struct pch_udc_ep *ep;
1844 struct pch_udc_dev *dev;
1845 struct pch_udc_request *req;
1846 unsigned long iflags;
1848 if (!usbep || !usbreq || !usbreq->complete || !usbreq->buf)
1850 ep = container_of(usbep, struct pch_udc_ep, ep);
1852 if (!ep->desc && ep->num)
1854 req = container_of(usbreq, struct pch_udc_request, req);
1855 if (!list_empty(&req->queue))
1857 if (!dev->driver || (dev->gadget.speed == USB_SPEED_UNKNOWN))
1859 spin_lock_irqsave(&dev->lock, iflags);
1860 /* map the buffer for dma */
1861 if (usbreq->length &&
1862 ((usbreq->dma == DMA_ADDR_INVALID) || !usbreq->dma)) {
1863 if (!((unsigned long)(usbreq->buf) & 0x03)) {
1865 usbreq->dma = dma_map_single(&dev->pdev->dev,
1870 usbreq->dma = dma_map_single(&dev->pdev->dev,
1875 req->buf = kzalloc(usbreq->length, GFP_ATOMIC);
1881 memcpy(req->buf, usbreq->buf, usbreq->length);
1882 req->dma = dma_map_single(&dev->pdev->dev,
1887 req->dma = dma_map_single(&dev->pdev->dev,
1892 req->dma_mapped = 1;
1894 if (usbreq->length > 0) {
1895 retval = prepare_dma(ep, req, GFP_ATOMIC);
1900 usbreq->status = -EINPROGRESS;
1902 if (list_empty(&ep->queue) && !ep->halted) {
1903 /* no pending transfer, so start this req */
1904 if (!usbreq->length) {
1905 process_zlp(ep, req);
1910 pch_udc_start_rxrequest(ep, req);
1913 * For IN trfr the descriptors will be programmed and
1914 * P bit will be set when
1915 * we get an IN token
1917 pch_udc_wait_ep_stall(ep);
1918 pch_udc_ep_clear_nak(ep);
1919 pch_udc_enable_ep_interrupts(ep->dev, (1 << ep->num));
1922 /* Now add this request to the ep's pending requests */
1924 list_add_tail(&req->queue, &ep->queue);
1927 spin_unlock_irqrestore(&dev->lock, iflags);
1932 * pch_udc_pcd_dequeue() - This function de-queues a request packet.
1933 * It is called by gadget driver
1934 * @usbep: Reference to the USB endpoint structure
1935 * @usbreq: Reference to the USB request
1939 * linux error number: Failure
1941 static int pch_udc_pcd_dequeue(struct usb_ep *usbep,
1942 struct usb_request *usbreq)
1944 struct pch_udc_ep *ep;
1945 struct pch_udc_request *req;
1946 struct pch_udc_dev *dev;
1947 unsigned long flags;
1950 ep = container_of(usbep, struct pch_udc_ep, ep);
1952 if (!usbep || !usbreq || (!ep->desc && ep->num))
1954 req = container_of(usbreq, struct pch_udc_request, req);
1955 spin_lock_irqsave(&ep->dev->lock, flags);
1956 /* make sure it's still queued on this endpoint */
1957 list_for_each_entry(req, &ep->queue, queue) {
1958 if (&req->req == usbreq) {
1959 pch_udc_ep_set_nak(ep);
1960 if (!list_empty(&req->queue))
1961 complete_req(ep, req, -ECONNRESET);
1966 spin_unlock_irqrestore(&ep->dev->lock, flags);
1971 * pch_udc_pcd_set_halt() - This function Sets or clear the endpoint halt
1973 * @usbep: Reference to the USB endpoint structure
1974 * @halt: Specifies whether to set or clear the feature
1978 * linux error number: Failure
1980 static int pch_udc_pcd_set_halt(struct usb_ep *usbep, int halt)
1982 struct pch_udc_ep *ep;
1983 struct pch_udc_dev *dev;
1984 unsigned long iflags;
1989 ep = container_of(usbep, struct pch_udc_ep, ep);
1991 if (!ep->desc && !ep->num)
1993 if (!ep->dev->driver || (ep->dev->gadget.speed == USB_SPEED_UNKNOWN))
1995 spin_lock_irqsave(&udc_stall_spinlock, iflags);
1996 if (list_empty(&ep->queue)) {
1998 if (ep->num == PCH_UDC_EP0)
2000 pch_udc_ep_set_stall(ep);
2001 pch_udc_enable_ep_interrupts(ep->dev,
2002 PCH_UDC_EPINT(ep->in,
2005 pch_udc_ep_clear_stall(ep);
2011 spin_unlock_irqrestore(&udc_stall_spinlock, iflags);
2016 * pch_udc_pcd_set_wedge() - This function Sets or clear the endpoint
2018 * @usbep: Reference to the USB endpoint structure
2019 * @halt: Specifies whether to set or clear the feature
2023 * linux error number: Failure
2025 static int pch_udc_pcd_set_wedge(struct usb_ep *usbep)
2027 struct pch_udc_ep *ep;
2028 struct pch_udc_dev *dev;
2029 unsigned long iflags;
2034 ep = container_of(usbep, struct pch_udc_ep, ep);
2036 if (!ep->desc && !ep->num)
2038 if (!ep->dev->driver || (ep->dev->gadget.speed == USB_SPEED_UNKNOWN))
2040 spin_lock_irqsave(&udc_stall_spinlock, iflags);
2041 if (!list_empty(&ep->queue)) {
2044 if (ep->num == PCH_UDC_EP0)
2046 pch_udc_ep_set_stall(ep);
2047 pch_udc_enable_ep_interrupts(ep->dev,
2048 PCH_UDC_EPINT(ep->in, ep->num));
2049 ep->dev->prot_stall = 1;
2052 spin_unlock_irqrestore(&udc_stall_spinlock, iflags);
2057 * pch_udc_pcd_fifo_flush() - This function Flush the FIFO of specified endpoint
2058 * @usbep: Reference to the USB endpoint structure
2060 static void pch_udc_pcd_fifo_flush(struct usb_ep *usbep)
2062 struct pch_udc_ep *ep;
2067 ep = container_of(usbep, struct pch_udc_ep, ep);
2068 if (ep->desc || !ep->num)
2069 pch_udc_ep_fifo_flush(ep, ep->in);
2072 static const struct usb_ep_ops pch_udc_ep_ops = {
2073 .enable = pch_udc_pcd_ep_enable,
2074 .disable = pch_udc_pcd_ep_disable,
2075 .alloc_request = pch_udc_alloc_request,
2076 .free_request = pch_udc_free_request,
2077 .queue = pch_udc_pcd_queue,
2078 .dequeue = pch_udc_pcd_dequeue,
2079 .set_halt = pch_udc_pcd_set_halt,
2080 .set_wedge = pch_udc_pcd_set_wedge,
2081 .fifo_status = NULL,
2082 .fifo_flush = pch_udc_pcd_fifo_flush,
2086 * pch_udc_init_setup_buff() - This function initializes the SETUP buffer
2087 * @td_stp: Reference to the SETP buffer structure
2089 static void pch_udc_init_setup_buff(struct pch_udc_stp_dma_desc *td_stp)
2091 static u32 pky_marker;
2095 td_stp->reserved = ++pky_marker;
2096 memset(&td_stp->request, 0xFF, sizeof td_stp->request);
2097 td_stp->status = PCH_UDC_BS_HST_RDY;
2101 * pch_udc_start_next_txrequest() - This function starts
2102 * the next transmission requirement
2103 * @ep: Reference to the endpoint structure
2105 static void pch_udc_start_next_txrequest(struct pch_udc_ep *ep)
2107 struct pch_udc_request *req;
2108 struct pch_udc_data_dma_desc *td_data;
2110 if (pch_udc_read_ep_control(ep) & UDC_EPCTL_P)
2113 if (list_empty(&ep->queue))
2117 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
2122 pch_udc_wait_ep_stall(ep);
2124 pch_udc_ep_set_ddptr(ep, 0);
2125 td_data = req->td_data;
2127 td_data->status = (td_data->status & ~PCH_UDC_BUFF_STS) |
2129 if ((td_data->status & PCH_UDC_DMA_LAST) == PCH_UDC_DMA_LAST)
2131 td_data = phys_to_virt(td_data->next);
2133 pch_udc_ep_set_ddptr(ep, req->td_data_phys);
2134 pch_udc_set_dma(ep->dev, DMA_DIR_TX);
2135 pch_udc_ep_set_pd(ep);
2136 pch_udc_enable_ep_interrupts(ep->dev, PCH_UDC_EPINT(ep->in, ep->num));
2137 pch_udc_ep_clear_nak(ep);
2141 * pch_udc_complete_transfer() - This function completes a transfer
2142 * @ep: Reference to the endpoint structure
2144 static void pch_udc_complete_transfer(struct pch_udc_ep *ep)
2146 struct pch_udc_request *req;
2147 struct pch_udc_dev *dev = ep->dev;
2149 if (list_empty(&ep->queue))
2151 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
2152 if ((req->td_data_last->status & PCH_UDC_BUFF_STS) !=
2153 PCH_UDC_BS_DMA_DONE)
2155 if ((req->td_data_last->status & PCH_UDC_RXTX_STS) !=
2157 dev_err(&dev->pdev->dev, "Invalid RXTX status (0x%08x) "
2158 "epstatus=0x%08x\n",
2159 (req->td_data_last->status & PCH_UDC_RXTX_STS),
2164 req->req.actual = req->req.length;
2165 req->td_data_last->status = PCH_UDC_BS_HST_BSY | PCH_UDC_DMA_LAST;
2166 req->td_data->status = PCH_UDC_BS_HST_BSY | PCH_UDC_DMA_LAST;
2167 complete_req(ep, req, 0);
2169 if (!list_empty(&ep->queue)) {
2170 pch_udc_wait_ep_stall(ep);
2171 pch_udc_ep_clear_nak(ep);
2172 pch_udc_enable_ep_interrupts(ep->dev,
2173 PCH_UDC_EPINT(ep->in, ep->num));
2175 pch_udc_disable_ep_interrupts(ep->dev,
2176 PCH_UDC_EPINT(ep->in, ep->num));
2181 * pch_udc_complete_receiver() - This function completes a receiver
2182 * @ep: Reference to the endpoint structure
2184 static void pch_udc_complete_receiver(struct pch_udc_ep *ep)
2186 struct pch_udc_request *req;
2187 struct pch_udc_dev *dev = ep->dev;
2189 struct pch_udc_data_dma_desc *td;
2192 if (list_empty(&ep->queue))
2195 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
2196 pch_udc_clear_dma(ep->dev, DMA_DIR_RX);
2197 pch_udc_ep_set_ddptr(ep, 0);
2198 if ((req->td_data_last->status & PCH_UDC_BUFF_STS) ==
2199 PCH_UDC_BS_DMA_DONE)
2200 td = req->td_data_last;
2205 if ((td->status & PCH_UDC_RXTX_STS) != PCH_UDC_RTS_SUCC) {
2206 dev_err(&dev->pdev->dev, "Invalid RXTX status=0x%08x "
2207 "epstatus=0x%08x\n",
2208 (req->td_data->status & PCH_UDC_RXTX_STS),
2212 if ((td->status & PCH_UDC_BUFF_STS) == PCH_UDC_BS_DMA_DONE)
2213 if (td->status | PCH_UDC_DMA_LAST) {
2214 count = td->status & PCH_UDC_RXTX_BYTES;
2217 if (td == req->td_data_last) {
2218 dev_err(&dev->pdev->dev, "Not complete RX descriptor");
2221 addr = (dma_addr_t)td->next;
2222 td = phys_to_virt(addr);
2224 /* on 64k packets the RXBYTES field is zero */
2225 if (!count && (req->req.length == UDC_DMA_MAXPACKET))
2226 count = UDC_DMA_MAXPACKET;
2227 req->td_data->status |= PCH_UDC_DMA_LAST;
2228 td->status |= PCH_UDC_BS_HST_BSY;
2231 req->req.actual = count;
2232 complete_req(ep, req, 0);
2233 /* If there is a new/failed requests try that now */
2234 if (!list_empty(&ep->queue)) {
2235 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
2236 pch_udc_start_rxrequest(ep, req);
2241 * pch_udc_svc_data_in() - This function process endpoint interrupts
2243 * @dev: Reference to the device structure
2244 * @ep_num: Endpoint that generated the interrupt
2246 static void pch_udc_svc_data_in(struct pch_udc_dev *dev, int ep_num)
2249 struct pch_udc_ep *ep;
2251 ep = &dev->ep[UDC_EPIN_IDX(ep_num)];
2255 if (!(epsts & (UDC_EPSTS_IN | UDC_EPSTS_BNA | UDC_EPSTS_HE |
2256 UDC_EPSTS_TDC | UDC_EPSTS_RCS | UDC_EPSTS_TXEMPTY |
2257 UDC_EPSTS_RSS | UDC_EPSTS_XFERDONE)))
2259 if ((epsts & UDC_EPSTS_BNA))
2261 if (epsts & UDC_EPSTS_HE)
2263 if (epsts & UDC_EPSTS_RSS) {
2264 pch_udc_ep_set_stall(ep);
2265 pch_udc_enable_ep_interrupts(ep->dev,
2266 PCH_UDC_EPINT(ep->in, ep->num));
2268 if (epsts & UDC_EPSTS_RCS) {
2269 if (!dev->prot_stall) {
2270 pch_udc_ep_clear_stall(ep);
2272 pch_udc_ep_set_stall(ep);
2273 pch_udc_enable_ep_interrupts(ep->dev,
2274 PCH_UDC_EPINT(ep->in, ep->num));
2277 if (epsts & UDC_EPSTS_TDC)
2278 pch_udc_complete_transfer(ep);
2279 /* On IN interrupt, provide data if we have any */
2280 if ((epsts & UDC_EPSTS_IN) && !(epsts & UDC_EPSTS_RSS) &&
2281 !(epsts & UDC_EPSTS_TDC) && !(epsts & UDC_EPSTS_TXEMPTY))
2282 pch_udc_start_next_txrequest(ep);
2286 * pch_udc_svc_data_out() - Handles interrupts from OUT endpoint
2287 * @dev: Reference to the device structure
2288 * @ep_num: Endpoint that generated the interrupt
2290 static void pch_udc_svc_data_out(struct pch_udc_dev *dev, int ep_num)
2293 struct pch_udc_ep *ep;
2294 struct pch_udc_request *req = NULL;
2296 ep = &dev->ep[UDC_EPOUT_IDX(ep_num)];
2300 if ((epsts & UDC_EPSTS_BNA) && (!list_empty(&ep->queue))) {
2302 req = list_entry(ep->queue.next, struct pch_udc_request,
2304 if ((req->td_data_last->status & PCH_UDC_BUFF_STS) !=
2305 PCH_UDC_BS_DMA_DONE) {
2306 if (!req->dma_going)
2307 pch_udc_start_rxrequest(ep, req);
2311 if (epsts & UDC_EPSTS_HE)
2313 if (epsts & UDC_EPSTS_RSS) {
2314 pch_udc_ep_set_stall(ep);
2315 pch_udc_enable_ep_interrupts(ep->dev,
2316 PCH_UDC_EPINT(ep->in, ep->num));
2318 if (epsts & UDC_EPSTS_RCS) {
2319 if (!dev->prot_stall) {
2320 pch_udc_ep_clear_stall(ep);
2322 pch_udc_ep_set_stall(ep);
2323 pch_udc_enable_ep_interrupts(ep->dev,
2324 PCH_UDC_EPINT(ep->in, ep->num));
2327 if (((epsts & UDC_EPSTS_OUT_MASK) >> UDC_EPSTS_OUT_SHIFT) ==
2328 UDC_EPSTS_OUT_DATA) {
2329 if (ep->dev->prot_stall == 1) {
2330 pch_udc_ep_set_stall(ep);
2331 pch_udc_enable_ep_interrupts(ep->dev,
2332 PCH_UDC_EPINT(ep->in, ep->num));
2334 pch_udc_complete_receiver(ep);
2337 if (list_empty(&ep->queue))
2338 pch_udc_set_dma(dev, DMA_DIR_RX);
2342 * pch_udc_svc_control_in() - Handle Control IN endpoint interrupts
2343 * @dev: Reference to the device structure
2345 static void pch_udc_svc_control_in(struct pch_udc_dev *dev)
2348 struct pch_udc_ep *ep;
2349 struct pch_udc_ep *ep_out;
2351 ep = &dev->ep[UDC_EP0IN_IDX];
2352 ep_out = &dev->ep[UDC_EP0OUT_IDX];
2356 if (!(epsts & (UDC_EPSTS_IN | UDC_EPSTS_BNA | UDC_EPSTS_HE |
2357 UDC_EPSTS_TDC | UDC_EPSTS_RCS | UDC_EPSTS_TXEMPTY |
2358 UDC_EPSTS_XFERDONE)))
2360 if ((epsts & UDC_EPSTS_BNA))
2362 if (epsts & UDC_EPSTS_HE)
2364 if ((epsts & UDC_EPSTS_TDC) && (!dev->stall)) {
2365 pch_udc_complete_transfer(ep);
2366 pch_udc_clear_dma(dev, DMA_DIR_RX);
2367 ep_out->td_data->status = (ep_out->td_data->status &
2368 ~PCH_UDC_BUFF_STS) |
2370 pch_udc_ep_clear_nak(ep_out);
2371 pch_udc_set_dma(dev, DMA_DIR_RX);
2372 pch_udc_ep_set_rrdy(ep_out);
2374 /* On IN interrupt, provide data if we have any */
2375 if ((epsts & UDC_EPSTS_IN) && !(epsts & UDC_EPSTS_TDC) &&
2376 !(epsts & UDC_EPSTS_TXEMPTY))
2377 pch_udc_start_next_txrequest(ep);
2381 * pch_udc_svc_control_out() - Routine that handle Control
2382 * OUT endpoint interrupts
2383 * @dev: Reference to the device structure
2385 static void pch_udc_svc_control_out(struct pch_udc_dev *dev)
2388 int setup_supported;
2389 struct pch_udc_ep *ep;
2391 ep = &dev->ep[UDC_EP0OUT_IDX];
2396 if (((stat & UDC_EPSTS_OUT_MASK) >> UDC_EPSTS_OUT_SHIFT) ==
2397 UDC_EPSTS_OUT_SETUP) {
2399 dev->ep[UDC_EP0IN_IDX].halted = 0;
2400 dev->ep[UDC_EP0OUT_IDX].halted = 0;
2401 dev->setup_data = ep->td_stp->request;
2402 pch_udc_init_setup_buff(ep->td_stp);
2403 pch_udc_clear_dma(dev, DMA_DIR_RX);
2404 pch_udc_ep_fifo_flush(&(dev->ep[UDC_EP0IN_IDX]),
2405 dev->ep[UDC_EP0IN_IDX].in);
2406 if ((dev->setup_data.bRequestType & USB_DIR_IN))
2407 dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IDX].ep;
2409 dev->gadget.ep0 = &ep->ep;
2410 spin_unlock(&dev->lock);
2411 /* If Mass storage Reset */
2412 if ((dev->setup_data.bRequestType == 0x21) &&
2413 (dev->setup_data.bRequest == 0xFF))
2414 dev->prot_stall = 0;
2415 /* call gadget with setup data received */
2416 setup_supported = dev->driver->setup(&dev->gadget,
2418 spin_lock(&dev->lock);
2420 if (dev->setup_data.bRequestType & USB_DIR_IN) {
2421 ep->td_data->status = (ep->td_data->status &
2422 ~PCH_UDC_BUFF_STS) |
2424 pch_udc_ep_set_ddptr(ep, ep->td_data_phys);
2426 /* ep0 in returns data on IN phase */
2427 if (setup_supported >= 0 && setup_supported <
2428 UDC_EP0IN_MAX_PKT_SIZE) {
2429 pch_udc_ep_clear_nak(&(dev->ep[UDC_EP0IN_IDX]));
2430 /* Gadget would have queued a request when
2431 * we called the setup */
2432 if (!(dev->setup_data.bRequestType & USB_DIR_IN)) {
2433 pch_udc_set_dma(dev, DMA_DIR_RX);
2434 pch_udc_ep_clear_nak(ep);
2436 } else if (setup_supported < 0) {
2437 /* if unsupported request, then stall */
2438 pch_udc_ep_set_stall(&(dev->ep[UDC_EP0IN_IDX]));
2439 pch_udc_enable_ep_interrupts(ep->dev,
2440 PCH_UDC_EPINT(ep->in, ep->num));
2442 pch_udc_set_dma(dev, DMA_DIR_RX);
2444 dev->waiting_zlp_ack = 1;
2446 } else if ((((stat & UDC_EPSTS_OUT_MASK) >> UDC_EPSTS_OUT_SHIFT) ==
2447 UDC_EPSTS_OUT_DATA) && !dev->stall) {
2448 pch_udc_clear_dma(dev, DMA_DIR_RX);
2449 pch_udc_ep_set_ddptr(ep, 0);
2450 if (!list_empty(&ep->queue)) {
2452 pch_udc_svc_data_out(dev, PCH_UDC_EP0);
2454 pch_udc_set_dma(dev, DMA_DIR_RX);
2456 pch_udc_ep_set_rrdy(ep);
2461 * pch_udc_postsvc_epinters() - This function enables end point interrupts
2462 * and clears NAK status
2463 * @dev: Reference to the device structure
2464 * @ep_num: End point number
2466 static void pch_udc_postsvc_epinters(struct pch_udc_dev *dev, int ep_num)
2468 struct pch_udc_ep *ep;
2469 struct pch_udc_request *req;
2471 ep = &dev->ep[UDC_EPIN_IDX(ep_num)];
2472 if (!list_empty(&ep->queue)) {
2473 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
2474 pch_udc_enable_ep_interrupts(ep->dev,
2475 PCH_UDC_EPINT(ep->in, ep->num));
2476 pch_udc_ep_clear_nak(ep);
2481 * pch_udc_read_all_epstatus() - This function read all endpoint status
2482 * @dev: Reference to the device structure
2483 * @ep_intr: Status of endpoint interrupt
2485 static void pch_udc_read_all_epstatus(struct pch_udc_dev *dev, u32 ep_intr)
2488 struct pch_udc_ep *ep;
2490 for (i = 0; i < PCH_UDC_USED_EP_NUM; i++) {
2492 if (ep_intr & (0x1 << i)) {
2493 ep = &dev->ep[UDC_EPIN_IDX(i)];
2494 ep->epsts = pch_udc_read_ep_status(ep);
2495 pch_udc_clear_ep_status(ep, ep->epsts);
2498 if (ep_intr & (0x10000 << i)) {
2499 ep = &dev->ep[UDC_EPOUT_IDX(i)];
2500 ep->epsts = pch_udc_read_ep_status(ep);
2501 pch_udc_clear_ep_status(ep, ep->epsts);
2507 * pch_udc_activate_control_ep() - This function enables the control endpoints
2508 * for traffic after a reset
2509 * @dev: Reference to the device structure
2511 static void pch_udc_activate_control_ep(struct pch_udc_dev *dev)
2513 struct pch_udc_ep *ep;
2516 /* Setup the IN endpoint */
2517 ep = &dev->ep[UDC_EP0IN_IDX];
2518 pch_udc_clear_ep_control(ep);
2519 pch_udc_ep_fifo_flush(ep, ep->in);
2520 pch_udc_ep_set_bufsz(ep, UDC_EP0IN_BUFF_SIZE, ep->in);
2521 pch_udc_ep_set_maxpkt(ep, UDC_EP0IN_MAX_PKT_SIZE);
2522 /* Initialize the IN EP Descriptor */
2525 ep->td_data_phys = 0;
2526 ep->td_stp_phys = 0;
2528 /* Setup the OUT endpoint */
2529 ep = &dev->ep[UDC_EP0OUT_IDX];
2530 pch_udc_clear_ep_control(ep);
2531 pch_udc_ep_fifo_flush(ep, ep->in);
2532 pch_udc_ep_set_bufsz(ep, UDC_EP0OUT_BUFF_SIZE, ep->in);
2533 pch_udc_ep_set_maxpkt(ep, UDC_EP0OUT_MAX_PKT_SIZE);
2534 val = UDC_EP0OUT_MAX_PKT_SIZE << UDC_CSR_NE_MAX_PKT_SHIFT;
2535 pch_udc_write_csr(ep->dev, val, UDC_EP0OUT_IDX);
2537 /* Initialize the SETUP buffer */
2538 pch_udc_init_setup_buff(ep->td_stp);
2539 /* Write the pointer address of dma descriptor */
2540 pch_udc_ep_set_subptr(ep, ep->td_stp_phys);
2541 /* Write the pointer address of Setup descriptor */
2542 pch_udc_ep_set_ddptr(ep, ep->td_data_phys);
2544 /* Initialize the dma descriptor */
2545 ep->td_data->status = PCH_UDC_DMA_LAST;
2546 ep->td_data->dataptr = dev->dma_addr;
2547 ep->td_data->next = ep->td_data_phys;
2549 pch_udc_ep_clear_nak(ep);
2554 * pch_udc_svc_ur_interrupt() - This function handles a USB reset interrupt
2555 * @dev: Reference to driver structure
2557 static void pch_udc_svc_ur_interrupt(struct pch_udc_dev *dev)
2559 struct pch_udc_ep *ep;
2562 pch_udc_clear_dma(dev, DMA_DIR_TX);
2563 pch_udc_clear_dma(dev, DMA_DIR_RX);
2564 /* Mask all endpoint interrupts */
2565 pch_udc_disable_ep_interrupts(dev, UDC_EPINT_MSK_DISABLE_ALL);
2566 /* clear all endpoint interrupts */
2567 pch_udc_write_ep_interrupts(dev, UDC_EPINT_MSK_DISABLE_ALL);
2569 for (i = 0; i < PCH_UDC_EP_NUM; i++) {
2571 pch_udc_clear_ep_status(ep, UDC_EPSTS_ALL_CLR_MASK);
2572 pch_udc_clear_ep_control(ep);
2573 pch_udc_ep_set_ddptr(ep, 0);
2574 pch_udc_write_csr(ep->dev, 0x00, i);
2577 dev->prot_stall = 0;
2578 dev->waiting_zlp_ack = 0;
2579 dev->set_cfg_not_acked = 0;
2581 /* disable ep to empty req queue. Skip the control EP's */
2582 for (i = 0; i < (PCH_UDC_USED_EP_NUM*2); i++) {
2584 pch_udc_ep_set_nak(ep);
2585 pch_udc_ep_fifo_flush(ep, ep->in);
2586 /* Complete request queue */
2587 empty_req_queue(ep);
2589 if (dev->driver && dev->driver->disconnect) {
2590 spin_unlock(&dev->lock);
2591 dev->driver->disconnect(&dev->gadget);
2592 spin_lock(&dev->lock);
2597 * pch_udc_svc_enum_interrupt() - This function handles a USB speed enumeration
2599 * @dev: Reference to driver structure
2601 static void pch_udc_svc_enum_interrupt(struct pch_udc_dev *dev)
2603 u32 dev_stat, dev_speed;
2604 u32 speed = USB_SPEED_FULL;
2606 dev_stat = pch_udc_read_device_status(dev);
2607 dev_speed = (dev_stat & UDC_DEVSTS_ENUM_SPEED_MASK) >>
2608 UDC_DEVSTS_ENUM_SPEED_SHIFT;
2609 switch (dev_speed) {
2610 case UDC_DEVSTS_ENUM_SPEED_HIGH:
2611 speed = USB_SPEED_HIGH;
2613 case UDC_DEVSTS_ENUM_SPEED_FULL:
2614 speed = USB_SPEED_FULL;
2616 case UDC_DEVSTS_ENUM_SPEED_LOW:
2617 speed = USB_SPEED_LOW;
2622 dev->gadget.speed = speed;
2623 pch_udc_activate_control_ep(dev);
2624 pch_udc_enable_ep_interrupts(dev, UDC_EPINT_IN_EP0 | UDC_EPINT_OUT_EP0);
2625 pch_udc_set_dma(dev, DMA_DIR_TX);
2626 pch_udc_set_dma(dev, DMA_DIR_RX);
2627 pch_udc_ep_set_rrdy(&(dev->ep[UDC_EP0OUT_IDX]));
2629 /* enable device interrupts */
2630 pch_udc_enable_interrupts(dev, UDC_DEVINT_UR | UDC_DEVINT_US |
2631 UDC_DEVINT_ES | UDC_DEVINT_ENUM |
2632 UDC_DEVINT_SI | UDC_DEVINT_SC);
2636 * pch_udc_svc_intf_interrupt() - This function handles a set interface
2638 * @dev: Reference to driver structure
2640 static void pch_udc_svc_intf_interrupt(struct pch_udc_dev *dev)
2642 u32 reg, dev_stat = 0;
2645 dev_stat = pch_udc_read_device_status(dev);
2646 dev->cfg_data.cur_intf = (dev_stat & UDC_DEVSTS_INTF_MASK) >>
2647 UDC_DEVSTS_INTF_SHIFT;
2648 dev->cfg_data.cur_alt = (dev_stat & UDC_DEVSTS_ALT_MASK) >>
2649 UDC_DEVSTS_ALT_SHIFT;
2650 dev->set_cfg_not_acked = 1;
2651 /* Construct the usb request for gadget driver and inform it */
2652 memset(&dev->setup_data, 0 , sizeof dev->setup_data);
2653 dev->setup_data.bRequest = USB_REQ_SET_INTERFACE;
2654 dev->setup_data.bRequestType = USB_RECIP_INTERFACE;
2655 dev->setup_data.wValue = cpu_to_le16(dev->cfg_data.cur_alt);
2656 dev->setup_data.wIndex = cpu_to_le16(dev->cfg_data.cur_intf);
2657 /* programm the Endpoint Cfg registers */
2658 /* Only one end point cfg register */
2659 reg = pch_udc_read_csr(dev, UDC_EP0OUT_IDX);
2660 reg = (reg & ~UDC_CSR_NE_INTF_MASK) |
2661 (dev->cfg_data.cur_intf << UDC_CSR_NE_INTF_SHIFT);
2662 reg = (reg & ~UDC_CSR_NE_ALT_MASK) |
2663 (dev->cfg_data.cur_alt << UDC_CSR_NE_ALT_SHIFT);
2664 pch_udc_write_csr(dev, reg, UDC_EP0OUT_IDX);
2665 for (i = 0; i < PCH_UDC_USED_EP_NUM * 2; i++) {
2666 /* clear stall bits */
2667 pch_udc_ep_clear_stall(&(dev->ep[i]));
2668 dev->ep[i].halted = 0;
2671 spin_unlock(&dev->lock);
2672 ret = dev->driver->setup(&dev->gadget, &dev->setup_data);
2673 spin_lock(&dev->lock);
2677 * pch_udc_svc_cfg_interrupt() - This function handles a set configuration
2679 * @dev: Reference to driver structure
2681 static void pch_udc_svc_cfg_interrupt(struct pch_udc_dev *dev)
2684 u32 reg, dev_stat = 0;
2686 dev_stat = pch_udc_read_device_status(dev);
2687 dev->set_cfg_not_acked = 1;
2688 dev->cfg_data.cur_cfg = (dev_stat & UDC_DEVSTS_CFG_MASK) >>
2689 UDC_DEVSTS_CFG_SHIFT;
2690 /* make usb request for gadget driver */
2691 memset(&dev->setup_data, 0 , sizeof dev->setup_data);
2692 dev->setup_data.bRequest = USB_REQ_SET_CONFIGURATION;
2693 dev->setup_data.wValue = cpu_to_le16(dev->cfg_data.cur_cfg);
2694 /* program the NE registers */
2695 /* Only one end point cfg register */
2696 reg = pch_udc_read_csr(dev, UDC_EP0OUT_IDX);
2697 reg = (reg & ~UDC_CSR_NE_CFG_MASK) |
2698 (dev->cfg_data.cur_cfg << UDC_CSR_NE_CFG_SHIFT);
2699 pch_udc_write_csr(dev, reg, UDC_EP0OUT_IDX);
2700 for (i = 0; i < PCH_UDC_USED_EP_NUM * 2; i++) {
2701 /* clear stall bits */
2702 pch_udc_ep_clear_stall(&(dev->ep[i]));
2703 dev->ep[i].halted = 0;
2707 /* call gadget zero with setup data received */
2708 spin_unlock(&dev->lock);
2709 ret = dev->driver->setup(&dev->gadget, &dev->setup_data);
2710 spin_lock(&dev->lock);
2714 * pch_udc_dev_isr() - This function services device interrupts
2715 * by invoking appropriate routines.
2716 * @dev: Reference to the device structure
2717 * @dev_intr: The Device interrupt status.
2719 static void pch_udc_dev_isr(struct pch_udc_dev *dev, u32 dev_intr)
2723 /* USB Reset Interrupt */
2724 if (dev_intr & UDC_DEVINT_UR) {
2725 pch_udc_svc_ur_interrupt(dev);
2726 dev_dbg(&dev->pdev->dev, "USB_RESET\n");
2728 /* Enumeration Done Interrupt */
2729 if (dev_intr & UDC_DEVINT_ENUM) {
2730 pch_udc_svc_enum_interrupt(dev);
2731 dev_dbg(&dev->pdev->dev, "USB_ENUM\n");
2733 /* Set Interface Interrupt */
2734 if (dev_intr & UDC_DEVINT_SI)
2735 pch_udc_svc_intf_interrupt(dev);
2736 /* Set Config Interrupt */
2737 if (dev_intr & UDC_DEVINT_SC)
2738 pch_udc_svc_cfg_interrupt(dev);
2739 /* USB Suspend interrupt */
2740 if (dev_intr & UDC_DEVINT_US) {
2742 && dev->driver->suspend) {
2743 spin_unlock(&dev->lock);
2744 dev->driver->suspend(&dev->gadget);
2745 spin_lock(&dev->lock);
2748 vbus = pch_vbus_gpio_get_value(dev);
2749 if ((dev->vbus_session == 0)
2751 if (dev->driver && dev->driver->disconnect) {
2752 spin_unlock(&dev->lock);
2753 dev->driver->disconnect(&dev->gadget);
2754 spin_lock(&dev->lock);
2756 pch_udc_reconnect(dev);
2757 } else if ((dev->vbus_session == 0)
2759 && !dev->vbus_gpio.intr)
2760 schedule_work(&dev->vbus_gpio.irq_work_fall);
2762 dev_dbg(&dev->pdev->dev, "USB_SUSPEND\n");
2764 /* Clear the SOF interrupt, if enabled */
2765 if (dev_intr & UDC_DEVINT_SOF)
2766 dev_dbg(&dev->pdev->dev, "SOF\n");
2767 /* ES interrupt, IDLE > 3ms on the USB */
2768 if (dev_intr & UDC_DEVINT_ES)
2769 dev_dbg(&dev->pdev->dev, "ES\n");
2770 /* RWKP interrupt */
2771 if (dev_intr & UDC_DEVINT_RWKP)
2772 dev_dbg(&dev->pdev->dev, "RWKP\n");
2776 * pch_udc_isr() - This function handles interrupts from the PCH USB Device
2777 * @irq: Interrupt request number
2778 * @dev: Reference to the device structure
2780 static irqreturn_t pch_udc_isr(int irq, void *pdev)
2782 struct pch_udc_dev *dev = (struct pch_udc_dev *) pdev;
2783 u32 dev_intr, ep_intr;
2786 dev_intr = pch_udc_read_device_interrupts(dev);
2787 ep_intr = pch_udc_read_ep_interrupts(dev);
2789 /* For a hot plug, this find that the controller is hung up. */
2790 if (dev_intr == ep_intr)
2791 if (dev_intr == pch_udc_readl(dev, UDC_DEVCFG_ADDR)) {
2792 dev_dbg(&dev->pdev->dev, "UDC: Hung up\n");
2793 /* The controller is reset */
2794 pch_udc_writel(dev, UDC_SRST, UDC_SRST_ADDR);
2798 /* Clear device interrupts */
2799 pch_udc_write_device_interrupts(dev, dev_intr);
2801 /* Clear ep interrupts */
2802 pch_udc_write_ep_interrupts(dev, ep_intr);
2803 if (!dev_intr && !ep_intr)
2805 spin_lock(&dev->lock);
2807 pch_udc_dev_isr(dev, dev_intr);
2809 pch_udc_read_all_epstatus(dev, ep_intr);
2810 /* Process Control In interrupts, if present */
2811 if (ep_intr & UDC_EPINT_IN_EP0) {
2812 pch_udc_svc_control_in(dev);
2813 pch_udc_postsvc_epinters(dev, 0);
2815 /* Process Control Out interrupts, if present */
2816 if (ep_intr & UDC_EPINT_OUT_EP0)
2817 pch_udc_svc_control_out(dev);
2818 /* Process data in end point interrupts */
2819 for (i = 1; i < PCH_UDC_USED_EP_NUM; i++) {
2820 if (ep_intr & (1 << i)) {
2821 pch_udc_svc_data_in(dev, i);
2822 pch_udc_postsvc_epinters(dev, i);
2825 /* Process data out end point interrupts */
2826 for (i = UDC_EPINT_OUT_SHIFT + 1; i < (UDC_EPINT_OUT_SHIFT +
2827 PCH_UDC_USED_EP_NUM); i++)
2828 if (ep_intr & (1 << i))
2829 pch_udc_svc_data_out(dev, i -
2830 UDC_EPINT_OUT_SHIFT);
2832 spin_unlock(&dev->lock);
2837 * pch_udc_setup_ep0() - This function enables control endpoint for traffic
2838 * @dev: Reference to the device structure
2840 static void pch_udc_setup_ep0(struct pch_udc_dev *dev)
2842 /* enable ep0 interrupts */
2843 pch_udc_enable_ep_interrupts(dev, UDC_EPINT_IN_EP0 |
2845 /* enable device interrupts */
2846 pch_udc_enable_interrupts(dev, UDC_DEVINT_UR | UDC_DEVINT_US |
2847 UDC_DEVINT_ES | UDC_DEVINT_ENUM |
2848 UDC_DEVINT_SI | UDC_DEVINT_SC);
2852 * gadget_release() - Free the gadget driver private data
2853 * @pdev reference to struct pci_dev
2855 static void gadget_release(struct device *pdev)
2857 struct pch_udc_dev *dev = dev_get_drvdata(pdev);
2863 * pch_udc_pcd_reinit() - This API initializes the endpoint structures
2864 * @dev: Reference to the driver structure
2866 static void pch_udc_pcd_reinit(struct pch_udc_dev *dev)
2868 const char *const ep_string[] = {
2869 ep0_string, "ep0out", "ep1in", "ep1out", "ep2in", "ep2out",
2870 "ep3in", "ep3out", "ep4in", "ep4out", "ep5in", "ep5out",
2871 "ep6in", "ep6out", "ep7in", "ep7out", "ep8in", "ep8out",
2872 "ep9in", "ep9out", "ep10in", "ep10out", "ep11in", "ep11out",
2873 "ep12in", "ep12out", "ep13in", "ep13out", "ep14in", "ep14out",
2874 "ep15in", "ep15out",
2878 dev->gadget.speed = USB_SPEED_UNKNOWN;
2879 INIT_LIST_HEAD(&dev->gadget.ep_list);
2881 /* Initialize the endpoints structures */
2882 memset(dev->ep, 0, sizeof dev->ep);
2883 for (i = 0; i < PCH_UDC_EP_NUM; i++) {
2884 struct pch_udc_ep *ep = &dev->ep[i];
2889 ep->ep.name = ep_string[i];
2890 ep->ep.ops = &pch_udc_ep_ops;
2892 ep->offset_addr = ep->num * UDC_EP_REG_SHIFT;
2894 ep->offset_addr = (UDC_EPINT_OUT_SHIFT + ep->num) *
2896 /* need to set ep->ep.maxpacket and set Default Configuration?*/
2897 ep->ep.maxpacket = UDC_BULK_MAX_PKT_SIZE;
2898 list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
2899 INIT_LIST_HEAD(&ep->queue);
2901 dev->ep[UDC_EP0IN_IDX].ep.maxpacket = UDC_EP0IN_MAX_PKT_SIZE;
2902 dev->ep[UDC_EP0OUT_IDX].ep.maxpacket = UDC_EP0OUT_MAX_PKT_SIZE;
2904 /* remove ep0 in and out from the list. They have own pointer */
2905 list_del_init(&dev->ep[UDC_EP0IN_IDX].ep.ep_list);
2906 list_del_init(&dev->ep[UDC_EP0OUT_IDX].ep.ep_list);
2908 dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IDX].ep;
2909 INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
2913 * pch_udc_pcd_init() - This API initializes the driver structure
2914 * @dev: Reference to the driver structure
2919 static int pch_udc_pcd_init(struct pch_udc_dev *dev)
2922 pch_udc_pcd_reinit(dev);
2923 pch_vbus_gpio_init(dev, vbus_gpio_port);
2928 * init_dma_pools() - create dma pools during initialization
2929 * @pdev: reference to struct pci_dev
2931 static int init_dma_pools(struct pch_udc_dev *dev)
2933 struct pch_udc_stp_dma_desc *td_stp;
2934 struct pch_udc_data_dma_desc *td_data;
2937 dev->data_requests = pci_pool_create("data_requests", dev->pdev,
2938 sizeof(struct pch_udc_data_dma_desc), 0, 0);
2939 if (!dev->data_requests) {
2940 dev_err(&dev->pdev->dev, "%s: can't get request data pool\n",
2945 /* dma desc for setup data */
2946 dev->stp_requests = pci_pool_create("setup requests", dev->pdev,
2947 sizeof(struct pch_udc_stp_dma_desc), 0, 0);
2948 if (!dev->stp_requests) {
2949 dev_err(&dev->pdev->dev, "%s: can't get setup request pool\n",
2954 td_stp = pci_pool_alloc(dev->stp_requests, GFP_KERNEL,
2955 &dev->ep[UDC_EP0OUT_IDX].td_stp_phys);
2957 dev_err(&dev->pdev->dev,
2958 "%s: can't allocate setup dma descriptor\n", __func__);
2961 dev->ep[UDC_EP0OUT_IDX].td_stp = td_stp;
2963 /* data: 0 packets !? */
2964 td_data = pci_pool_alloc(dev->data_requests, GFP_KERNEL,
2965 &dev->ep[UDC_EP0OUT_IDX].td_data_phys);
2967 dev_err(&dev->pdev->dev,
2968 "%s: can't allocate data dma descriptor\n", __func__);
2971 dev->ep[UDC_EP0OUT_IDX].td_data = td_data;
2972 dev->ep[UDC_EP0IN_IDX].td_stp = NULL;
2973 dev->ep[UDC_EP0IN_IDX].td_stp_phys = 0;
2974 dev->ep[UDC_EP0IN_IDX].td_data = NULL;
2975 dev->ep[UDC_EP0IN_IDX].td_data_phys = 0;
2977 dev->ep0out_buf = kzalloc(UDC_EP0OUT_BUFF_SIZE * 4, GFP_KERNEL);
2978 if (!dev->ep0out_buf)
2980 dev->dma_addr = dma_map_single(&dev->pdev->dev, dev->ep0out_buf,
2981 UDC_EP0OUT_BUFF_SIZE * 4,
2986 static int pch_udc_start(struct usb_gadget_driver *driver,
2987 int (*bind)(struct usb_gadget *))
2989 struct pch_udc_dev *dev = pch_udc;
2992 if (!driver || (driver->max_speed == USB_SPEED_UNKNOWN) || !bind ||
2993 !driver->setup || !driver->unbind || !driver->disconnect) {
2994 dev_err(&dev->pdev->dev,
2995 "%s: invalid driver parameter\n", __func__);
3003 dev_err(&dev->pdev->dev, "%s: already bound\n", __func__);
3006 driver->driver.bus = NULL;
3007 dev->driver = driver;
3008 dev->gadget.dev.driver = &driver->driver;
3010 /* Invoke the bind routine of the gadget driver */
3011 retval = bind(&dev->gadget);
3014 dev_err(&dev->pdev->dev, "%s: binding to %s returning %d\n",
3015 __func__, driver->driver.name, retval);
3017 dev->gadget.dev.driver = NULL;
3020 /* get ready for ep0 traffic */
3021 pch_udc_setup_ep0(dev);
3024 if ((pch_vbus_gpio_get_value(dev) != 0) || !dev->vbus_gpio.intr)
3025 pch_udc_clear_disconnect(dev);
3031 static int pch_udc_stop(struct usb_gadget_driver *driver)
3033 struct pch_udc_dev *dev = pch_udc;
3038 if (!driver || (driver != dev->driver)) {
3039 dev_err(&dev->pdev->dev,
3040 "%s: invalid driver parameter\n", __func__);
3044 pch_udc_disable_interrupts(dev, UDC_DEVINT_MSK);
3046 /* Assures that there are no pending requests with this driver */
3047 driver->disconnect(&dev->gadget);
3048 driver->unbind(&dev->gadget);
3049 dev->gadget.dev.driver = NULL;
3054 pch_udc_set_disconnect(dev);
3058 static void pch_udc_shutdown(struct pci_dev *pdev)
3060 struct pch_udc_dev *dev = pci_get_drvdata(pdev);
3062 pch_udc_disable_interrupts(dev, UDC_DEVINT_MSK);
3063 pch_udc_disable_ep_interrupts(dev, UDC_EPINT_MSK_DISABLE_ALL);
3065 /* disable the pullup so the host will think we're gone */
3066 pch_udc_set_disconnect(dev);
3069 static void pch_udc_remove(struct pci_dev *pdev)
3071 struct pch_udc_dev *dev = pci_get_drvdata(pdev);
3073 usb_del_gadget_udc(&dev->gadget);
3075 /* gadget driver must not be registered */
3078 "%s: gadget driver still bound!!!\n", __func__);
3079 /* dma pool cleanup */
3080 if (dev->data_requests)
3081 pci_pool_destroy(dev->data_requests);
3083 if (dev->stp_requests) {
3084 /* cleanup DMA desc's for ep0in */
3085 if (dev->ep[UDC_EP0OUT_IDX].td_stp) {
3086 pci_pool_free(dev->stp_requests,
3087 dev->ep[UDC_EP0OUT_IDX].td_stp,
3088 dev->ep[UDC_EP0OUT_IDX].td_stp_phys);
3090 if (dev->ep[UDC_EP0OUT_IDX].td_data) {
3091 pci_pool_free(dev->stp_requests,
3092 dev->ep[UDC_EP0OUT_IDX].td_data,
3093 dev->ep[UDC_EP0OUT_IDX].td_data_phys);
3095 pci_pool_destroy(dev->stp_requests);
3099 dma_unmap_single(&dev->pdev->dev, dev->dma_addr,
3100 UDC_EP0OUT_BUFF_SIZE * 4, DMA_FROM_DEVICE);
3101 kfree(dev->ep0out_buf);
3103 pch_vbus_gpio_free(dev);
3107 if (dev->irq_registered)
3108 free_irq(pdev->irq, dev);
3110 iounmap(dev->base_addr);
3111 if (dev->mem_region)
3112 release_mem_region(dev->phys_addr,
3113 pci_resource_len(pdev, PCH_UDC_PCI_BAR));
3115 pci_disable_device(pdev);
3116 if (dev->registered)
3117 device_unregister(&dev->gadget.dev);
3119 pci_set_drvdata(pdev, NULL);
3123 static int pch_udc_suspend(struct pci_dev *pdev, pm_message_t state)
3125 struct pch_udc_dev *dev = pci_get_drvdata(pdev);
3127 pch_udc_disable_interrupts(dev, UDC_DEVINT_MSK);
3128 pch_udc_disable_ep_interrupts(dev, UDC_EPINT_MSK_DISABLE_ALL);
3130 pci_disable_device(pdev);
3131 pci_enable_wake(pdev, PCI_D3hot, 0);
3133 if (pci_save_state(pdev)) {
3135 "%s: could not save PCI config state\n", __func__);
3138 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3142 static int pch_udc_resume(struct pci_dev *pdev)
3146 pci_set_power_state(pdev, PCI_D0);
3147 pci_restore_state(pdev);
3148 ret = pci_enable_device(pdev);
3150 dev_err(&pdev->dev, "%s: pci_enable_device failed\n", __func__);
3153 pci_enable_wake(pdev, PCI_D3hot, 0);
3157 #define pch_udc_suspend NULL
3158 #define pch_udc_resume NULL
3159 #endif /* CONFIG_PM */
3161 static int pch_udc_probe(struct pci_dev *pdev,
3162 const struct pci_device_id *id)
3164 unsigned long resource;
3167 struct pch_udc_dev *dev;
3171 pr_err("%s: already probed\n", __func__);
3175 dev = kzalloc(sizeof *dev, GFP_KERNEL);
3177 pr_err("%s: no memory for device structure\n", __func__);
3181 if (pci_enable_device(pdev) < 0) {
3183 pr_err("%s: pci_enable_device failed\n", __func__);
3187 pci_set_drvdata(pdev, dev);
3189 /* PCI resource allocation */
3190 resource = pci_resource_start(pdev, 1);
3191 len = pci_resource_len(pdev, 1);
3193 if (!request_mem_region(resource, len, KBUILD_MODNAME)) {
3194 dev_err(&pdev->dev, "%s: pci device used already\n", __func__);
3198 dev->phys_addr = resource;
3199 dev->mem_region = 1;
3201 dev->base_addr = ioremap_nocache(resource, len);
3202 if (!dev->base_addr) {
3203 pr_err("%s: device memory cannot be mapped\n", __func__);
3208 dev_err(&pdev->dev, "%s: irq not set\n", __func__);
3213 /* initialize the hardware */
3214 if (pch_udc_pcd_init(dev)) {
3218 if (request_irq(pdev->irq, pch_udc_isr, IRQF_SHARED, KBUILD_MODNAME,
3220 dev_err(&pdev->dev, "%s: request_irq(%d) fail\n", __func__,
3225 dev->irq = pdev->irq;
3226 dev->irq_registered = 1;
3228 pci_set_master(pdev);
3229 pci_try_set_mwi(pdev);
3231 /* device struct setup */
3232 spin_lock_init(&dev->lock);
3234 dev->gadget.ops = &pch_udc_ops;
3236 retval = init_dma_pools(dev);
3240 dev_set_name(&dev->gadget.dev, "gadget");
3241 dev->gadget.dev.parent = &pdev->dev;
3242 dev->gadget.dev.dma_mask = pdev->dev.dma_mask;
3243 dev->gadget.dev.release = gadget_release;
3244 dev->gadget.name = KBUILD_MODNAME;
3245 dev->gadget.max_speed = USB_SPEED_HIGH;
3247 retval = device_register(&dev->gadget.dev);
3250 dev->registered = 1;
3252 /* Put the device in disconnected state till a driver is bound */
3253 pch_udc_set_disconnect(dev);
3254 retval = usb_add_gadget_udc(&pdev->dev, &dev->gadget);
3260 pch_udc_remove(pdev);
3264 static DEFINE_PCI_DEVICE_TABLE(pch_udc_pcidev_id) = {
3266 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EG20T_UDC),
3267 .class = (PCI_CLASS_SERIAL_USB << 8) | 0xfe,
3268 .class_mask = 0xffffffff,
3271 PCI_DEVICE(PCI_VENDOR_ID_ROHM, PCI_DEVICE_ID_ML7213_IOH_UDC),
3272 .class = (PCI_CLASS_SERIAL_USB << 8) | 0xfe,
3273 .class_mask = 0xffffffff,
3276 PCI_DEVICE(PCI_VENDOR_ID_ROHM, PCI_DEVICE_ID_ML7831_IOH_UDC),
3277 .class = (PCI_CLASS_SERIAL_USB << 8) | 0xfe,
3278 .class_mask = 0xffffffff,
3283 MODULE_DEVICE_TABLE(pci, pch_udc_pcidev_id);
3286 static struct pci_driver pch_udc_driver = {
3287 .name = KBUILD_MODNAME,
3288 .id_table = pch_udc_pcidev_id,
3289 .probe = pch_udc_probe,
3290 .remove = pch_udc_remove,
3291 .suspend = pch_udc_suspend,
3292 .resume = pch_udc_resume,
3293 .shutdown = pch_udc_shutdown,
3296 static int __init pch_udc_pci_init(void)
3298 return pci_register_driver(&pch_udc_driver);
3300 module_init(pch_udc_pci_init);
3302 static void __exit pch_udc_pci_exit(void)
3304 pci_unregister_driver(&pch_udc_driver);
3306 module_exit(pch_udc_pci_exit);
3308 MODULE_DESCRIPTION("Intel EG20T USB Device Controller");
3309 MODULE_AUTHOR("LAPIS Semiconductor, <tomoya-linux@dsn.lapis-semi.com>");
3310 MODULE_LICENSE("GPL");