1 /* linux/drivers/usb/gadget/s3c-hsotg.c
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
8 * S3C USB2.0 High-speed / OtG driver
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/spinlock.h>
18 #include <linux/interrupt.h>
19 #include <linux/platform_device.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/debugfs.h>
22 #include <linux/seq_file.h>
23 #include <linux/delay.h>
25 #include <linux/slab.h>
27 #include <linux/usb/ch9.h>
28 #include <linux/usb/gadget.h>
32 #include <plat/regs-usb-hsotg-phy.h>
33 #include <plat/regs-usb-hsotg.h>
34 #include <mach/regs-sys.h>
35 #include <plat/udc-hs.h>
37 #define DMA_ADDR_INVALID (~((dma_addr_t)0))
41 * Unfortunately there seems to be a limit of the amount of data that can
42 * be transfered by IN transactions on EP0. This is either 127 bytes or 3
43 * packets (which practially means 1 packet and 63 bytes of data) when the
46 * This means if we are wanting to move >127 bytes of data, we need to
47 * split the transactions up, but just doing one packet at a time does
48 * not work (this may be an implicit DATA0 PID on first packet of the
49 * transaction) and doing 2 packets is outside the controller's limits.
51 * If we try to lower the MPS size for EP0, then no transfers work properly
52 * for EP0, and the system will fail basic enumeration. As no cause for this
53 * has currently been found, we cannot support any large IN transfers for
56 #define EP0_MPS_LIMIT 64
62 * struct s3c_hsotg_ep - driver endpoint definition.
63 * @ep: The gadget layer representation of the endpoint.
64 * @name: The driver generated name for the endpoint.
65 * @queue: Queue of requests for this endpoint.
66 * @parent: Reference back to the parent device structure.
67 * @req: The current request that the endpoint is processing. This is
68 * used to indicate an request has been loaded onto the endpoint
69 * and has yet to be completed (maybe due to data move, or simply
70 * awaiting an ack from the core all the data has been completed).
71 * @debugfs: File entry for debugfs file for this endpoint.
72 * @lock: State lock to protect contents of endpoint.
73 * @dir_in: Set to true if this endpoint is of the IN direction, which
74 * means that it is sending data to the Host.
75 * @index: The index for the endpoint registers.
76 * @name: The name array passed to the USB core.
77 * @halted: Set if the endpoint has been halted.
78 * @periodic: Set if this is a periodic ep, such as Interrupt
79 * @sent_zlp: Set if we've sent a zero-length packet.
80 * @total_data: The total number of data bytes done.
81 * @fifo_size: The size of the FIFO (for periodic IN endpoints)
82 * @fifo_load: The amount of data loaded into the FIFO (periodic IN)
83 * @last_load: The offset of data for the last start of request.
84 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN
86 * This is the driver's state for each registered enpoint, allowing it
87 * to keep track of transactions that need doing. Each endpoint has a
88 * lock to protect the state, to try and avoid using an overall lock
89 * for the host controller as much as possible.
91 * For periodic IN endpoints, we have fifo_size and fifo_load to try
92 * and keep track of the amount of data in the periodic FIFO for each
93 * of these as we don't have a status register that tells us how much
98 struct list_head queue;
99 struct s3c_hsotg *parent;
100 struct s3c_hsotg_req *req;
101 struct dentry *debugfs;
105 unsigned long total_data;
106 unsigned int size_loaded;
107 unsigned int last_load;
108 unsigned int fifo_load;
109 unsigned short fifo_size;
111 unsigned char dir_in;
114 unsigned int halted:1;
115 unsigned int periodic:1;
116 unsigned int sent_zlp:1;
121 #define S3C_HSOTG_EPS (8+1) /* limit to 9 for the moment */
124 * struct s3c_hsotg - driver state.
125 * @dev: The parent device supplied to the probe function
126 * @driver: USB gadget driver
127 * @plat: The platform specific configuration data.
128 * @regs: The memory area mapped for accessing registers.
129 * @regs_res: The resource that was allocated when claiming register space.
130 * @irq: The IRQ number we are using
131 * @debug_root: root directrory for debugfs.
132 * @debug_file: main status file for debugfs.
133 * @debug_fifo: FIFO status file for debugfs.
134 * @ep0_reply: Request used for ep0 reply.
135 * @ep0_buff: Buffer for EP0 reply data, if needed.
136 * @ctrl_buff: Buffer for EP0 control requests.
137 * @ctrl_req: Request for EP0 control packets.
138 * @eps: The endpoints being supplied to the gadget framework
142 struct usb_gadget_driver *driver;
143 struct s3c_hsotg_plat *plat;
146 struct resource *regs_res;
149 struct dentry *debug_root;
150 struct dentry *debug_file;
151 struct dentry *debug_fifo;
153 struct usb_request *ep0_reply;
154 struct usb_request *ctrl_req;
158 struct usb_gadget gadget;
159 struct s3c_hsotg_ep eps[];
163 * struct s3c_hsotg_req - data transfer request
164 * @req: The USB gadget request
165 * @queue: The list of requests for the endpoint this is queued for.
166 * @in_progress: Has already had size/packets written to core
167 * @mapped: DMA buffer for this request has been mapped via dma_map_single().
169 struct s3c_hsotg_req {
170 struct usb_request req;
171 struct list_head queue;
172 unsigned char in_progress;
173 unsigned char mapped;
176 /* conversion functions */
177 static inline struct s3c_hsotg_req *our_req(struct usb_request *req)
179 return container_of(req, struct s3c_hsotg_req, req);
182 static inline struct s3c_hsotg_ep *our_ep(struct usb_ep *ep)
184 return container_of(ep, struct s3c_hsotg_ep, ep);
187 static inline struct s3c_hsotg *to_hsotg(struct usb_gadget *gadget)
189 return container_of(gadget, struct s3c_hsotg, gadget);
192 static inline void __orr32(void __iomem *ptr, u32 val)
194 writel(readl(ptr) | val, ptr);
197 static inline void __bic32(void __iomem *ptr, u32 val)
199 writel(readl(ptr) & ~val, ptr);
202 /* forward decleration of functions */
203 static void s3c_hsotg_dump(struct s3c_hsotg *hsotg);
206 * using_dma - return the DMA status of the driver.
207 * @hsotg: The driver state.
209 * Return true if we're using DMA.
211 * Currently, we have the DMA support code worked into everywhere
212 * that needs it, but the AMBA DMA implementation in the hardware can
213 * only DMA from 32bit aligned addresses. This means that gadgets such
214 * as the CDC Ethernet cannot work as they often pass packets which are
217 * Unfortunately the choice to use DMA or not is global to the controller
218 * and seems to be only settable when the controller is being put through
219 * a core reset. This means we either need to fix the gadgets to take
220 * account of DMA alignment, or add bounce buffers (yuerk).
222 * Until this issue is sorted out, we always return 'false'.
224 static inline bool using_dma(struct s3c_hsotg *hsotg)
226 return false; /* support is not complete */
230 * s3c_hsotg_en_gsint - enable one or more of the general interrupt
231 * @hsotg: The device state
232 * @ints: A bitmask of the interrupts to enable
234 static void s3c_hsotg_en_gsint(struct s3c_hsotg *hsotg, u32 ints)
236 u32 gsintmsk = readl(hsotg->regs + S3C_GINTMSK);
239 new_gsintmsk = gsintmsk | ints;
241 if (new_gsintmsk != gsintmsk) {
242 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
243 writel(new_gsintmsk, hsotg->regs + S3C_GINTMSK);
248 * s3c_hsotg_disable_gsint - disable one or more of the general interrupt
249 * @hsotg: The device state
250 * @ints: A bitmask of the interrupts to enable
252 static void s3c_hsotg_disable_gsint(struct s3c_hsotg *hsotg, u32 ints)
254 u32 gsintmsk = readl(hsotg->regs + S3C_GINTMSK);
257 new_gsintmsk = gsintmsk & ~ints;
259 if (new_gsintmsk != gsintmsk)
260 writel(new_gsintmsk, hsotg->regs + S3C_GINTMSK);
264 * s3c_hsotg_ctrl_epint - enable/disable an endpoint irq
265 * @hsotg: The device state
266 * @ep: The endpoint index
267 * @dir_in: True if direction is in.
268 * @en: The enable value, true to enable
270 * Set or clear the mask for an individual endpoint's interrupt
273 static void s3c_hsotg_ctrl_epint(struct s3c_hsotg *hsotg,
274 unsigned int ep, unsigned int dir_in,
284 local_irq_save(flags);
285 daint = readl(hsotg->regs + S3C_DAINTMSK);
290 writel(daint, hsotg->regs + S3C_DAINTMSK);
291 local_irq_restore(flags);
295 * s3c_hsotg_init_fifo - initialise non-periodic FIFOs
296 * @hsotg: The device instance.
298 static void s3c_hsotg_init_fifo(struct s3c_hsotg *hsotg)
300 /* the ryu 2.6.24 release ahs
301 writel(0x1C0, hsotg->regs + S3C_GRXFSIZ);
302 writel(S3C_GNPTXFSIZ_NPTxFStAddr(0x200) |
303 S3C_GNPTXFSIZ_NPTxFDep(0x1C0),
304 hsotg->regs + S3C_GNPTXFSIZ);
307 /* set FIFO sizes to 2048/0x1C0 */
309 writel(2048, hsotg->regs + S3C_GRXFSIZ);
310 writel(S3C_GNPTXFSIZ_NPTxFStAddr(2048) |
311 S3C_GNPTXFSIZ_NPTxFDep(0x1C0),
312 hsotg->regs + S3C_GNPTXFSIZ);
316 * @ep: USB endpoint to allocate request for.
317 * @flags: Allocation flags
319 * Allocate a new USB request structure appropriate for the specified endpoint
321 static struct usb_request *s3c_hsotg_ep_alloc_request(struct usb_ep *ep,
324 struct s3c_hsotg_req *req;
326 req = kzalloc(sizeof(struct s3c_hsotg_req), flags);
330 INIT_LIST_HEAD(&req->queue);
332 req->req.dma = DMA_ADDR_INVALID;
337 * is_ep_periodic - return true if the endpoint is in periodic mode.
338 * @hs_ep: The endpoint to query.
340 * Returns true if the endpoint is in periodic mode, meaning it is being
341 * used for an Interrupt or ISO transfer.
343 static inline int is_ep_periodic(struct s3c_hsotg_ep *hs_ep)
345 return hs_ep->periodic;
349 * s3c_hsotg_unmap_dma - unmap the DMA memory being used for the request
350 * @hsotg: The device state.
351 * @hs_ep: The endpoint for the request
352 * @hs_req: The request being processed.
354 * This is the reverse of s3c_hsotg_map_dma(), called for the completion
355 * of a request to ensure the buffer is ready for access by the caller.
357 static void s3c_hsotg_unmap_dma(struct s3c_hsotg *hsotg,
358 struct s3c_hsotg_ep *hs_ep,
359 struct s3c_hsotg_req *hs_req)
361 struct usb_request *req = &hs_req->req;
362 enum dma_data_direction dir;
364 dir = hs_ep->dir_in ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
366 /* ignore this if we're not moving any data */
367 if (hs_req->req.length == 0)
370 if (hs_req->mapped) {
371 /* we mapped this, so unmap and remove the dma */
373 dma_unmap_single(hsotg->dev, req->dma, req->length, dir);
375 req->dma = DMA_ADDR_INVALID;
378 dma_sync_single_for_cpu(hsotg->dev, req->dma, req->length, dir);
383 * s3c_hsotg_write_fifo - write packet Data to the TxFIFO
384 * @hsotg: The controller state.
385 * @hs_ep: The endpoint we're going to write for.
386 * @hs_req: The request to write data for.
388 * This is called when the TxFIFO has some space in it to hold a new
389 * transmission and we have something to give it. The actual setup of
390 * the data size is done elsewhere, so all we have to do is to actually
393 * The return value is zero if there is more space (or nothing was done)
394 * otherwise -ENOSPC is returned if the FIFO space was used up.
396 * This routine is only needed for PIO
398 static int s3c_hsotg_write_fifo(struct s3c_hsotg *hsotg,
399 struct s3c_hsotg_ep *hs_ep,
400 struct s3c_hsotg_req *hs_req)
402 bool periodic = is_ep_periodic(hs_ep);
403 u32 gnptxsts = readl(hsotg->regs + S3C_GNPTXSTS);
404 int buf_pos = hs_req->req.actual;
405 int to_write = hs_ep->size_loaded;
410 to_write -= (buf_pos - hs_ep->last_load);
412 /* if there's nothing to write, get out early */
417 u32 epsize = readl(hsotg->regs + S3C_DIEPTSIZ(hs_ep->index));
421 /* work out how much data was loaded so we can calculate
422 * how much data is left in the fifo. */
424 size_left = S3C_DxEPTSIZ_XferSize_GET(epsize);
426 dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n",
428 hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size);
430 /* how much of the data has moved */
431 size_done = hs_ep->size_loaded - size_left;
433 /* how much data is left in the fifo */
434 can_write = hs_ep->fifo_load - size_done;
435 dev_dbg(hsotg->dev, "%s: => can_write1=%d\n",
436 __func__, can_write);
438 can_write = hs_ep->fifo_size - can_write;
439 dev_dbg(hsotg->dev, "%s: => can_write2=%d\n",
440 __func__, can_write);
442 if (can_write <= 0) {
443 s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_PTxFEmp);
447 if (S3C_GNPTXSTS_NPTxQSpcAvail_GET(gnptxsts) == 0) {
449 "%s: no queue slots available (0x%08x)\n",
452 s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_NPTxFEmp);
456 can_write = S3C_GNPTXSTS_NPTxFSpcAvail_GET(gnptxsts);
459 dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, mps %d\n",
460 __func__, gnptxsts, can_write, to_write, hs_ep->ep.maxpacket);
462 /* limit to 512 bytes of data, it seems at least on the non-periodic
463 * FIFO, requests of >512 cause the endpoint to get stuck with a
464 * fragment of the end of the transfer in it.
469 /* see if we can write data */
471 if (to_write > can_write) {
472 to_write = can_write;
473 pkt_round = to_write % hs_ep->ep.maxpacket;
475 /* Not sure, but we probably shouldn't be writing partial
476 * packets into the FIFO, so round the write down to an
477 * exact number of packets.
479 * Note, we do not currently check to see if we can ever
480 * write a full packet or not to the FIFO.
484 to_write -= pkt_round;
486 /* enable correct FIFO interrupt to alert us when there
487 * is more room left. */
489 s3c_hsotg_en_gsint(hsotg,
490 periodic ? S3C_GINTSTS_PTxFEmp :
491 S3C_GINTSTS_NPTxFEmp);
494 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
495 to_write, hs_req->req.length, can_write, buf_pos);
500 hs_req->req.actual = buf_pos + to_write;
501 hs_ep->total_data += to_write;
504 hs_ep->fifo_load += to_write;
506 to_write = DIV_ROUND_UP(to_write, 4);
507 data = hs_req->req.buf + buf_pos;
509 writesl(hsotg->regs + S3C_EPFIFO(hs_ep->index), data, to_write);
511 return (to_write >= can_write) ? -ENOSPC : 0;
515 * get_ep_limit - get the maximum data legnth for this endpoint
516 * @hs_ep: The endpoint
518 * Return the maximum data that can be queued in one go on a given endpoint
519 * so that transfers that are too long can be split.
521 static unsigned get_ep_limit(struct s3c_hsotg_ep *hs_ep)
523 int index = hs_ep->index;
528 maxsize = S3C_DxEPTSIZ_XferSize_LIMIT + 1;
529 maxpkt = S3C_DxEPTSIZ_PktCnt_LIMIT + 1;
532 /* maxsize = S3C_DIEPTSIZ0_XferSize_LIMIT + 1; */
534 maxpkt = S3C_DIEPTSIZ0_PktCnt_LIMIT + 1;
541 /* we made the constant loading easier above by using +1 */
545 /* constrain by packet count if maxpkts*pktsize is greater
546 * than the length register size. */
548 if ((maxpkt * hs_ep->ep.maxpacket) < maxsize)
549 maxsize = maxpkt * hs_ep->ep.maxpacket;
555 * s3c_hsotg_start_req - start a USB request from an endpoint's queue
556 * @hsotg: The controller state.
557 * @hs_ep: The endpoint to process a request for
558 * @hs_req: The request to start.
559 * @continuing: True if we are doing more for the current request.
561 * Start the given request running by setting the endpoint registers
562 * appropriately, and writing any data to the FIFOs.
564 static void s3c_hsotg_start_req(struct s3c_hsotg *hsotg,
565 struct s3c_hsotg_ep *hs_ep,
566 struct s3c_hsotg_req *hs_req,
569 struct usb_request *ureq = &hs_req->req;
570 int index = hs_ep->index;
571 int dir_in = hs_ep->dir_in;
581 if (hs_ep->req && !continuing) {
582 dev_err(hsotg->dev, "%s: active request\n", __func__);
585 } else if (hs_ep->req != hs_req && continuing) {
587 "%s: continue different req\n", __func__);
593 epctrl_reg = dir_in ? S3C_DIEPCTL(index) : S3C_DOEPCTL(index);
594 epsize_reg = dir_in ? S3C_DIEPTSIZ(index) : S3C_DOEPTSIZ(index);
596 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
597 __func__, readl(hsotg->regs + epctrl_reg), index,
598 hs_ep->dir_in ? "in" : "out");
600 length = ureq->length - ureq->actual;
604 "REQ buf %p len %d dma 0x%08x noi=%d zp=%d snok=%d\n",
605 ureq->buf, length, ureq->dma,
606 ureq->no_interrupt, ureq->zero, ureq->short_not_ok);
608 maxreq = get_ep_limit(hs_ep);
609 if (length > maxreq) {
610 int round = maxreq % hs_ep->ep.maxpacket;
612 dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n",
613 __func__, length, maxreq, round);
615 /* round down to multiple of packets */
623 packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket);
625 packets = 1; /* send one packet if length is zero. */
627 if (dir_in && index != 0)
628 epsize = S3C_DxEPTSIZ_MC(1);
632 if (index != 0 && ureq->zero) {
633 /* test for the packets being exactly right for the
636 if (length == (packets * hs_ep->ep.maxpacket))
640 epsize |= S3C_DxEPTSIZ_PktCnt(packets);
641 epsize |= S3C_DxEPTSIZ_XferSize(length);
643 dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
644 __func__, packets, length, ureq->length, epsize, epsize_reg);
646 /* store the request as the current one we're doing */
649 /* write size / packets */
650 writel(epsize, hsotg->regs + epsize_reg);
652 ctrl = readl(hsotg->regs + epctrl_reg);
654 if (ctrl & S3C_DxEPCTL_Stall) {
655 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
657 /* not sure what we can do here, if it is EP0 then we should
658 * get this cleared once the endpoint has transmitted the
659 * STALL packet, otherwise it needs to be cleared by the
664 if (using_dma(hsotg)) {
665 unsigned int dma_reg;
667 /* write DMA address to control register, buffer already
668 * synced by s3c_hsotg_ep_queue(). */
670 dma_reg = dir_in ? S3C_DIEPDMA(index) : S3C_DOEPDMA(index);
671 writel(ureq->dma, hsotg->regs + dma_reg);
673 dev_dbg(hsotg->dev, "%s: 0x%08x => 0x%08x\n",
674 __func__, ureq->dma, dma_reg);
677 ctrl |= S3C_DxEPCTL_EPEna; /* ensure ep enabled */
678 ctrl |= S3C_DxEPCTL_USBActEp;
679 ctrl |= S3C_DxEPCTL_CNAK; /* clear NAK set by core */
681 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
682 writel(ctrl, hsotg->regs + epctrl_reg);
684 /* set these, it seems that DMA support increments past the end
685 * of the packet buffer so we need to calculate the length from
686 * this information. */
687 hs_ep->size_loaded = length;
688 hs_ep->last_load = ureq->actual;
690 if (dir_in && !using_dma(hsotg)) {
691 /* set these anyway, we may need them for non-periodic in */
692 hs_ep->fifo_load = 0;
694 s3c_hsotg_write_fifo(hsotg, hs_ep, hs_req);
697 /* clear the INTknTXFEmpMsk when we start request, more as a aide
698 * to debugging to see what is going on. */
700 writel(S3C_DIEPMSK_INTknTXFEmpMsk,
701 hsotg->regs + S3C_DIEPINT(index));
703 /* Note, trying to clear the NAK here causes problems with transmit
704 * on the S3C6400 ending up with the TXFIFO becomming full. */
706 /* check ep is enabled */
707 if (!(readl(hsotg->regs + epctrl_reg) & S3C_DxEPCTL_EPEna))
709 "ep%d: failed to become enabled (DxEPCTL=0x%08x)?\n",
710 index, readl(hsotg->regs + epctrl_reg));
712 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n",
713 __func__, readl(hsotg->regs + epctrl_reg));
717 * s3c_hsotg_map_dma - map the DMA memory being used for the request
718 * @hsotg: The device state.
719 * @hs_ep: The endpoint the request is on.
720 * @req: The request being processed.
722 * We've been asked to queue a request, so ensure that the memory buffer
723 * is correctly setup for DMA. If we've been passed an extant DMA address
724 * then ensure the buffer has been synced to memory. If our buffer has no
725 * DMA memory, then we map the memory and mark our request to allow us to
726 * cleanup on completion.
728 static int s3c_hsotg_map_dma(struct s3c_hsotg *hsotg,
729 struct s3c_hsotg_ep *hs_ep,
730 struct usb_request *req)
732 enum dma_data_direction dir;
733 struct s3c_hsotg_req *hs_req = our_req(req);
735 dir = hs_ep->dir_in ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
737 /* if the length is zero, ignore the DMA data */
738 if (hs_req->req.length == 0)
741 if (req->dma == DMA_ADDR_INVALID) {
744 dma = dma_map_single(hsotg->dev, req->buf, req->length, dir);
746 if (unlikely(dma_mapping_error(hsotg->dev, dma)))
750 dev_err(hsotg->dev, "%s: unaligned dma buffer\n",
753 dma_unmap_single(hsotg->dev, dma, req->length, dir);
760 dma_sync_single_for_cpu(hsotg->dev, req->dma, req->length, dir);
767 dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n",
768 __func__, req->buf, req->length);
773 static int s3c_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
776 struct s3c_hsotg_req *hs_req = our_req(req);
777 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
778 struct s3c_hsotg *hs = hs_ep->parent;
779 unsigned long irqflags;
782 dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
783 ep->name, req, req->length, req->buf, req->no_interrupt,
784 req->zero, req->short_not_ok);
786 /* initialise status of the request */
787 INIT_LIST_HEAD(&hs_req->queue);
789 req->status = -EINPROGRESS;
791 /* if we're using DMA, sync the buffers as necessary */
793 int ret = s3c_hsotg_map_dma(hs, hs_ep, req);
798 spin_lock_irqsave(&hs_ep->lock, irqflags);
800 first = list_empty(&hs_ep->queue);
801 list_add_tail(&hs_req->queue, &hs_ep->queue);
804 s3c_hsotg_start_req(hs, hs_ep, hs_req, false);
806 spin_unlock_irqrestore(&hs_ep->lock, irqflags);
811 static void s3c_hsotg_ep_free_request(struct usb_ep *ep,
812 struct usb_request *req)
814 struct s3c_hsotg_req *hs_req = our_req(req);
820 * s3c_hsotg_complete_oursetup - setup completion callback
821 * @ep: The endpoint the request was on.
822 * @req: The request completed.
824 * Called on completion of any requests the driver itself
825 * submitted that need cleaning up.
827 static void s3c_hsotg_complete_oursetup(struct usb_ep *ep,
828 struct usb_request *req)
830 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
831 struct s3c_hsotg *hsotg = hs_ep->parent;
833 dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req);
835 s3c_hsotg_ep_free_request(ep, req);
839 * ep_from_windex - convert control wIndex value to endpoint
840 * @hsotg: The driver state.
841 * @windex: The control request wIndex field (in host order).
843 * Convert the given wIndex into a pointer to an driver endpoint
844 * structure, or return NULL if it is not a valid endpoint.
846 static struct s3c_hsotg_ep *ep_from_windex(struct s3c_hsotg *hsotg,
849 struct s3c_hsotg_ep *ep = &hsotg->eps[windex & 0x7F];
850 int dir = (windex & USB_DIR_IN) ? 1 : 0;
851 int idx = windex & 0x7F;
856 if (idx > S3C_HSOTG_EPS)
859 if (idx && ep->dir_in != dir)
866 * s3c_hsotg_send_reply - send reply to control request
867 * @hsotg: The device state
869 * @buff: Buffer for request
870 * @length: Length of reply.
872 * Create a request and queue it on the given endpoint. This is useful as
873 * an internal method of sending replies to certain control requests, etc.
875 static int s3c_hsotg_send_reply(struct s3c_hsotg *hsotg,
876 struct s3c_hsotg_ep *ep,
880 struct usb_request *req;
883 dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length);
885 req = s3c_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC);
886 hsotg->ep0_reply = req;
888 dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__);
892 req->buf = hsotg->ep0_buff;
893 req->length = length;
894 req->zero = 1; /* always do zero-length final transfer */
895 req->complete = s3c_hsotg_complete_oursetup;
898 memcpy(req->buf, buff, length);
902 ret = s3c_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC);
904 dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__);
912 * s3c_hsotg_process_req_status - process request GET_STATUS
913 * @hsotg: The device state
914 * @ctrl: USB control request
916 static int s3c_hsotg_process_req_status(struct s3c_hsotg *hsotg,
917 struct usb_ctrlrequest *ctrl)
919 struct s3c_hsotg_ep *ep0 = &hsotg->eps[0];
920 struct s3c_hsotg_ep *ep;
924 dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__);
927 dev_warn(hsotg->dev, "%s: direction out?\n", __func__);
931 switch (ctrl->bRequestType & USB_RECIP_MASK) {
932 case USB_RECIP_DEVICE:
933 reply = cpu_to_le16(0); /* bit 0 => self powered,
934 * bit 1 => remote wakeup */
937 case USB_RECIP_INTERFACE:
938 /* currently, the data result should be zero */
939 reply = cpu_to_le16(0);
942 case USB_RECIP_ENDPOINT:
943 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
947 reply = cpu_to_le16(ep->halted ? 1 : 0);
954 if (le16_to_cpu(ctrl->wLength) != 2)
957 ret = s3c_hsotg_send_reply(hsotg, ep0, &reply, 2);
959 dev_err(hsotg->dev, "%s: failed to send reply\n", __func__);
966 static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value);
969 * s3c_hsotg_process_req_featire - process request {SET,CLEAR}_FEATURE
970 * @hsotg: The device state
971 * @ctrl: USB control request
973 static int s3c_hsotg_process_req_feature(struct s3c_hsotg *hsotg,
974 struct usb_ctrlrequest *ctrl)
976 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
977 struct s3c_hsotg_ep *ep;
979 dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",
980 __func__, set ? "SET" : "CLEAR");
982 if (ctrl->bRequestType == USB_RECIP_ENDPOINT) {
983 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
985 dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n",
986 __func__, le16_to_cpu(ctrl->wIndex));
990 switch (le16_to_cpu(ctrl->wValue)) {
991 case USB_ENDPOINT_HALT:
992 s3c_hsotg_ep_sethalt(&ep->ep, set);
999 return -ENOENT; /* currently only deal with endpoint */
1005 * s3c_hsotg_process_control - process a control request
1006 * @hsotg: The device state
1007 * @ctrl: The control request received
1009 * The controller has received the SETUP phase of a control request, and
1010 * needs to work out what to do next (and whether to pass it on to the
1013 static void s3c_hsotg_process_control(struct s3c_hsotg *hsotg,
1014 struct usb_ctrlrequest *ctrl)
1016 struct s3c_hsotg_ep *ep0 = &hsotg->eps[0];
1022 dev_dbg(hsotg->dev, "ctrl Req=%02x, Type=%02x, V=%04x, L=%04x\n",
1023 ctrl->bRequest, ctrl->bRequestType,
1024 ctrl->wValue, ctrl->wLength);
1026 /* record the direction of the request, for later use when enquing
1027 * packets onto EP0. */
1029 ep0->dir_in = (ctrl->bRequestType & USB_DIR_IN) ? 1 : 0;
1030 dev_dbg(hsotg->dev, "ctrl: dir_in=%d\n", ep0->dir_in);
1032 /* if we've no data with this request, then the last part of the
1033 * transaction is going to implicitly be IN. */
1034 if (ctrl->wLength == 0)
1037 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1038 switch (ctrl->bRequest) {
1039 case USB_REQ_SET_ADDRESS:
1040 dcfg = readl(hsotg->regs + S3C_DCFG);
1041 dcfg &= ~S3C_DCFG_DevAddr_MASK;
1042 dcfg |= ctrl->wValue << S3C_DCFG_DevAddr_SHIFT;
1043 writel(dcfg, hsotg->regs + S3C_DCFG);
1045 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1047 ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0);
1050 case USB_REQ_GET_STATUS:
1051 ret = s3c_hsotg_process_req_status(hsotg, ctrl);
1054 case USB_REQ_CLEAR_FEATURE:
1055 case USB_REQ_SET_FEATURE:
1056 ret = s3c_hsotg_process_req_feature(hsotg, ctrl);
1061 /* as a fallback, try delivering it to the driver to deal with */
1063 if (ret == 0 && hsotg->driver) {
1064 ret = hsotg->driver->setup(&hsotg->gadget, ctrl);
1066 dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
1071 /* need to generate zlp in reply or take data */
1072 /* todo - deal with any data we might be sent? */
1073 ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0);
1077 /* the request is either unhandlable, or is not formatted correctly
1078 * so respond with a STALL for the status stage to indicate failure.
1085 dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
1086 reg = (ep0->dir_in) ? S3C_DIEPCTL0 : S3C_DOEPCTL0;
1088 /* S3C_DxEPCTL_Stall will be cleared by EP once it has
1089 * taken effect, so no need to clear later. */
1091 ctrl = readl(hsotg->regs + reg);
1092 ctrl |= S3C_DxEPCTL_Stall;
1093 ctrl |= S3C_DxEPCTL_CNAK;
1094 writel(ctrl, hsotg->regs + reg);
1097 "writen DxEPCTL=0x%08x to %08x (DxEPCTL=0x%08x)\n",
1098 ctrl, reg, readl(hsotg->regs + reg));
1100 /* don't belive we need to anything more to get the EP
1101 * to reply with a STALL packet */
1105 static void s3c_hsotg_enqueue_setup(struct s3c_hsotg *hsotg);
1108 * s3c_hsotg_complete_setup - completion of a setup transfer
1109 * @ep: The endpoint the request was on.
1110 * @req: The request completed.
1112 * Called on completion of any requests the driver itself submitted for
1115 static void s3c_hsotg_complete_setup(struct usb_ep *ep,
1116 struct usb_request *req)
1118 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
1119 struct s3c_hsotg *hsotg = hs_ep->parent;
1121 if (req->status < 0) {
1122 dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status);
1126 if (req->actual == 0)
1127 s3c_hsotg_enqueue_setup(hsotg);
1129 s3c_hsotg_process_control(hsotg, req->buf);
1133 * s3c_hsotg_enqueue_setup - start a request for EP0 packets
1134 * @hsotg: The device state.
1136 * Enqueue a request on EP0 if necessary to received any SETUP packets
1137 * received from the host.
1139 static void s3c_hsotg_enqueue_setup(struct s3c_hsotg *hsotg)
1141 struct usb_request *req = hsotg->ctrl_req;
1142 struct s3c_hsotg_req *hs_req = our_req(req);
1145 dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__);
1149 req->buf = hsotg->ctrl_buff;
1150 req->complete = s3c_hsotg_complete_setup;
1152 if (!list_empty(&hs_req->queue)) {
1153 dev_dbg(hsotg->dev, "%s already queued???\n", __func__);
1157 hsotg->eps[0].dir_in = 0;
1159 ret = s3c_hsotg_ep_queue(&hsotg->eps[0].ep, req, GFP_ATOMIC);
1161 dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret);
1162 /* Don't think there's much we can do other than watch the
1168 * get_ep_head - return the first request on the endpoint
1169 * @hs_ep: The controller endpoint to get
1171 * Get the first request on the endpoint.
1173 static struct s3c_hsotg_req *get_ep_head(struct s3c_hsotg_ep *hs_ep)
1175 if (list_empty(&hs_ep->queue))
1178 return list_first_entry(&hs_ep->queue, struct s3c_hsotg_req, queue);
1182 * s3c_hsotg_complete_request - complete a request given to us
1183 * @hsotg: The device state.
1184 * @hs_ep: The endpoint the request was on.
1185 * @hs_req: The request to complete.
1186 * @result: The result code (0 => Ok, otherwise errno)
1188 * The given request has finished, so call the necessary completion
1189 * if it has one and then look to see if we can start a new request
1192 * Note, expects the ep to already be locked as appropriate.
1194 static void s3c_hsotg_complete_request(struct s3c_hsotg *hsotg,
1195 struct s3c_hsotg_ep *hs_ep,
1196 struct s3c_hsotg_req *hs_req,
1202 dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__);
1206 dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n",
1207 hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete);
1209 /* only replace the status if we've not already set an error
1210 * from a previous transaction */
1212 if (hs_req->req.status == -EINPROGRESS)
1213 hs_req->req.status = result;
1216 list_del_init(&hs_req->queue);
1218 if (using_dma(hsotg))
1219 s3c_hsotg_unmap_dma(hsotg, hs_ep, hs_req);
1221 /* call the complete request with the locks off, just in case the
1222 * request tries to queue more work for this endpoint. */
1224 if (hs_req->req.complete) {
1225 spin_unlock(&hs_ep->lock);
1226 hs_req->req.complete(&hs_ep->ep, &hs_req->req);
1227 spin_lock(&hs_ep->lock);
1230 /* Look to see if there is anything else to do. Note, the completion
1231 * of the previous request may have caused a new request to be started
1232 * so be careful when doing this. */
1234 if (!hs_ep->req && result >= 0) {
1235 restart = !list_empty(&hs_ep->queue);
1237 hs_req = get_ep_head(hs_ep);
1238 s3c_hsotg_start_req(hsotg, hs_ep, hs_req, false);
1244 * s3c_hsotg_complete_request_lock - complete a request given to us (locked)
1245 * @hsotg: The device state.
1246 * @hs_ep: The endpoint the request was on.
1247 * @hs_req: The request to complete.
1248 * @result: The result code (0 => Ok, otherwise errno)
1250 * See s3c_hsotg_complete_request(), but called with the endpoint's
1253 static void s3c_hsotg_complete_request_lock(struct s3c_hsotg *hsotg,
1254 struct s3c_hsotg_ep *hs_ep,
1255 struct s3c_hsotg_req *hs_req,
1258 unsigned long flags;
1260 spin_lock_irqsave(&hs_ep->lock, flags);
1261 s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
1262 spin_unlock_irqrestore(&hs_ep->lock, flags);
1266 * s3c_hsotg_rx_data - receive data from the FIFO for an endpoint
1267 * @hsotg: The device state.
1268 * @ep_idx: The endpoint index for the data
1269 * @size: The size of data in the fifo, in bytes
1271 * The FIFO status shows there is data to read from the FIFO for a given
1272 * endpoint, so sort out whether we need to read the data into a request
1273 * that has been made for that endpoint.
1275 static void s3c_hsotg_rx_data(struct s3c_hsotg *hsotg, int ep_idx, int size)
1277 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[ep_idx];
1278 struct s3c_hsotg_req *hs_req = hs_ep->req;
1279 void __iomem *fifo = hsotg->regs + S3C_EPFIFO(ep_idx);
1285 u32 epctl = readl(hsotg->regs + S3C_DOEPCTL(ep_idx));
1288 dev_warn(hsotg->dev,
1289 "%s: FIFO %d bytes on ep%d but no req (DxEPCTl=0x%08x)\n",
1290 __func__, size, ep_idx, epctl);
1292 /* dump the data from the FIFO, we've nothing we can do */
1293 for (ptr = 0; ptr < size; ptr += 4)
1299 spin_lock(&hs_ep->lock);
1302 read_ptr = hs_req->req.actual;
1303 max_req = hs_req->req.length - read_ptr;
1305 if (to_read > max_req) {
1306 /* more data appeared than we where willing
1307 * to deal with in this request.
1310 /* currently we don't deal this */
1314 dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n",
1315 __func__, to_read, max_req, read_ptr, hs_req->req.length);
1317 hs_ep->total_data += to_read;
1318 hs_req->req.actual += to_read;
1319 to_read = DIV_ROUND_UP(to_read, 4);
1321 /* note, we might over-write the buffer end by 3 bytes depending on
1322 * alignment of the data. */
1323 readsl(fifo, hs_req->req.buf + read_ptr, to_read);
1325 spin_unlock(&hs_ep->lock);
1329 * s3c_hsotg_send_zlp - send zero-length packet on control endpoint
1330 * @hsotg: The device instance
1331 * @req: The request currently on this endpoint
1333 * Generate a zero-length IN packet request for terminating a SETUP
1336 * Note, since we don't write any data to the TxFIFO, then it is
1337 * currently belived that we do not need to wait for any space in
1340 static void s3c_hsotg_send_zlp(struct s3c_hsotg *hsotg,
1341 struct s3c_hsotg_req *req)
1346 dev_warn(hsotg->dev, "%s: no request?\n", __func__);
1350 if (req->req.length == 0) {
1351 hsotg->eps[0].sent_zlp = 1;
1352 s3c_hsotg_enqueue_setup(hsotg);
1356 hsotg->eps[0].dir_in = 1;
1357 hsotg->eps[0].sent_zlp = 1;
1359 dev_dbg(hsotg->dev, "sending zero-length packet\n");
1361 /* issue a zero-sized packet to terminate this */
1362 writel(S3C_DxEPTSIZ_MC(1) | S3C_DxEPTSIZ_PktCnt(1) |
1363 S3C_DxEPTSIZ_XferSize(0), hsotg->regs + S3C_DIEPTSIZ(0));
1365 ctrl = readl(hsotg->regs + S3C_DIEPCTL0);
1366 ctrl |= S3C_DxEPCTL_CNAK; /* clear NAK set by core */
1367 ctrl |= S3C_DxEPCTL_EPEna; /* ensure ep enabled */
1368 ctrl |= S3C_DxEPCTL_USBActEp;
1369 writel(ctrl, hsotg->regs + S3C_DIEPCTL0);
1373 * s3c_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
1374 * @hsotg: The device instance
1375 * @epnum: The endpoint received from
1376 * @was_setup: Set if processing a SetupDone event.
1378 * The RXFIFO has delivered an OutDone event, which means that the data
1379 * transfer for an OUT endpoint has been completed, either by a short
1380 * packet or by the finish of a transfer.
1382 static void s3c_hsotg_handle_outdone(struct s3c_hsotg *hsotg,
1383 int epnum, bool was_setup)
1385 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[epnum];
1386 struct s3c_hsotg_req *hs_req = hs_ep->req;
1387 struct usb_request *req = &hs_req->req;
1391 dev_dbg(hsotg->dev, "%s: no request active\n", __func__);
1395 if (using_dma(hsotg)) {
1396 u32 epsize = readl(hsotg->regs + S3C_DOEPTSIZ(epnum));
1400 /* Calculate the size of the transfer by checking how much
1401 * is left in the endpoint size register and then working it
1402 * out from the amount we loaded for the transfer.
1404 * We need to do this as DMA pointers are always 32bit aligned
1405 * so may overshoot/undershoot the transfer.
1408 size_left = S3C_DxEPTSIZ_XferSize_GET(epsize);
1410 size_done = hs_ep->size_loaded - size_left;
1411 size_done += hs_ep->last_load;
1413 req->actual = size_done;
1416 if (req->actual < req->length && req->short_not_ok) {
1417 dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",
1418 __func__, req->actual, req->length);
1420 /* todo - what should we return here? there's no one else
1421 * even bothering to check the status. */
1425 if (!was_setup && req->complete != s3c_hsotg_complete_setup)
1426 s3c_hsotg_send_zlp(hsotg, hs_req);
1429 s3c_hsotg_complete_request_lock(hsotg, hs_ep, hs_req, result);
1433 * s3c_hsotg_read_frameno - read current frame number
1434 * @hsotg: The device instance
1436 * Return the current frame number
1438 static u32 s3c_hsotg_read_frameno(struct s3c_hsotg *hsotg)
1442 dsts = readl(hsotg->regs + S3C_DSTS);
1443 dsts &= S3C_DSTS_SOFFN_MASK;
1444 dsts >>= S3C_DSTS_SOFFN_SHIFT;
1450 * s3c_hsotg_handle_rx - RX FIFO has data
1451 * @hsotg: The device instance
1453 * The IRQ handler has detected that the RX FIFO has some data in it
1454 * that requires processing, so find out what is in there and do the
1457 * The RXFIFO is a true FIFO, the packets comming out are still in packet
1458 * chunks, so if you have x packets received on an endpoint you'll get x
1459 * FIFO events delivered, each with a packet's worth of data in it.
1461 * When using DMA, we should not be processing events from the RXFIFO
1462 * as the actual data should be sent to the memory directly and we turn
1463 * on the completion interrupts to get notifications of transfer completion.
1465 static void s3c_hsotg_handle_rx(struct s3c_hsotg *hsotg)
1467 u32 grxstsr = readl(hsotg->regs + S3C_GRXSTSP);
1468 u32 epnum, status, size;
1470 WARN_ON(using_dma(hsotg));
1472 epnum = grxstsr & S3C_GRXSTS_EPNum_MASK;
1473 status = grxstsr & S3C_GRXSTS_PktSts_MASK;
1475 size = grxstsr & S3C_GRXSTS_ByteCnt_MASK;
1476 size >>= S3C_GRXSTS_ByteCnt_SHIFT;
1479 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
1480 __func__, grxstsr, size, epnum);
1482 #define __status(x) ((x) >> S3C_GRXSTS_PktSts_SHIFT)
1484 switch (status >> S3C_GRXSTS_PktSts_SHIFT) {
1485 case __status(S3C_GRXSTS_PktSts_GlobalOutNAK):
1486 dev_dbg(hsotg->dev, "GlobalOutNAK\n");
1489 case __status(S3C_GRXSTS_PktSts_OutDone):
1490 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
1491 s3c_hsotg_read_frameno(hsotg));
1493 if (!using_dma(hsotg))
1494 s3c_hsotg_handle_outdone(hsotg, epnum, false);
1497 case __status(S3C_GRXSTS_PktSts_SetupDone):
1499 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1500 s3c_hsotg_read_frameno(hsotg),
1501 readl(hsotg->regs + S3C_DOEPCTL(0)));
1503 s3c_hsotg_handle_outdone(hsotg, epnum, true);
1506 case __status(S3C_GRXSTS_PktSts_OutRX):
1507 s3c_hsotg_rx_data(hsotg, epnum, size);
1510 case __status(S3C_GRXSTS_PktSts_SetupRX):
1512 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1513 s3c_hsotg_read_frameno(hsotg),
1514 readl(hsotg->regs + S3C_DOEPCTL(0)));
1516 s3c_hsotg_rx_data(hsotg, epnum, size);
1520 dev_warn(hsotg->dev, "%s: unknown status %08x\n",
1523 s3c_hsotg_dump(hsotg);
1529 * s3c_hsotg_ep0_mps - turn max packet size into register setting
1530 * @mps: The maximum packet size in bytes.
1532 static u32 s3c_hsotg_ep0_mps(unsigned int mps)
1536 return S3C_D0EPCTL_MPS_64;
1538 return S3C_D0EPCTL_MPS_32;
1540 return S3C_D0EPCTL_MPS_16;
1542 return S3C_D0EPCTL_MPS_8;
1545 /* bad max packet size, warn and return invalid result */
1551 * s3c_hsotg_set_ep_maxpacket - set endpoint's max-packet field
1552 * @hsotg: The driver state.
1553 * @ep: The index number of the endpoint
1554 * @mps: The maximum packet size in bytes
1556 * Configure the maximum packet size for the given endpoint, updating
1557 * the hardware control registers to reflect this.
1559 static void s3c_hsotg_set_ep_maxpacket(struct s3c_hsotg *hsotg,
1560 unsigned int ep, unsigned int mps)
1562 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[ep];
1563 void __iomem *regs = hsotg->regs;
1568 /* EP0 is a special case */
1569 mpsval = s3c_hsotg_ep0_mps(mps);
1573 if (mps >= S3C_DxEPCTL_MPS_LIMIT+1)
1579 hs_ep->ep.maxpacket = mps;
1581 /* update both the in and out endpoint controldir_ registers, even
1582 * if one of the directions may not be in use. */
1584 reg = readl(regs + S3C_DIEPCTL(ep));
1585 reg &= ~S3C_DxEPCTL_MPS_MASK;
1587 writel(reg, regs + S3C_DIEPCTL(ep));
1589 reg = readl(regs + S3C_DOEPCTL(ep));
1590 reg &= ~S3C_DxEPCTL_MPS_MASK;
1592 writel(reg, regs + S3C_DOEPCTL(ep));
1597 dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps);
1602 * s3c_hsotg_trytx - check to see if anything needs transmitting
1603 * @hsotg: The driver state
1604 * @hs_ep: The driver endpoint to check.
1606 * Check to see if there is a request that has data to send, and if so
1607 * make an attempt to write data into the FIFO.
1609 static int s3c_hsotg_trytx(struct s3c_hsotg *hsotg,
1610 struct s3c_hsotg_ep *hs_ep)
1612 struct s3c_hsotg_req *hs_req = hs_ep->req;
1614 if (!hs_ep->dir_in || !hs_req)
1617 if (hs_req->req.actual < hs_req->req.length) {
1618 dev_dbg(hsotg->dev, "trying to write more for ep%d\n",
1620 return s3c_hsotg_write_fifo(hsotg, hs_ep, hs_req);
1627 * s3c_hsotg_complete_in - complete IN transfer
1628 * @hsotg: The device state.
1629 * @hs_ep: The endpoint that has just completed.
1631 * An IN transfer has been completed, update the transfer's state and then
1632 * call the relevant completion routines.
1634 static void s3c_hsotg_complete_in(struct s3c_hsotg *hsotg,
1635 struct s3c_hsotg_ep *hs_ep)
1637 struct s3c_hsotg_req *hs_req = hs_ep->req;
1638 u32 epsize = readl(hsotg->regs + S3C_DIEPTSIZ(hs_ep->index));
1639 int size_left, size_done;
1642 dev_dbg(hsotg->dev, "XferCompl but no req\n");
1646 /* Calculate the size of the transfer by checking how much is left
1647 * in the endpoint size register and then working it out from
1648 * the amount we loaded for the transfer.
1650 * We do this even for DMA, as the transfer may have incremented
1651 * past the end of the buffer (DMA transfers are always 32bit
1655 size_left = S3C_DxEPTSIZ_XferSize_GET(epsize);
1657 size_done = hs_ep->size_loaded - size_left;
1658 size_done += hs_ep->last_load;
1660 if (hs_req->req.actual != size_done)
1661 dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n",
1662 __func__, hs_req->req.actual, size_done);
1664 hs_req->req.actual = size_done;
1666 /* if we did all of the transfer, and there is more data left
1667 * around, then try restarting the rest of the request */
1669 if (!size_left && hs_req->req.actual < hs_req->req.length) {
1670 dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__);
1671 s3c_hsotg_start_req(hsotg, hs_ep, hs_req, true);
1673 s3c_hsotg_complete_request_lock(hsotg, hs_ep, hs_req, 0);
1677 * s3c_hsotg_epint - handle an in/out endpoint interrupt
1678 * @hsotg: The driver state
1679 * @idx: The index for the endpoint (0..15)
1680 * @dir_in: Set if this is an IN endpoint
1682 * Process and clear any interrupt pending for an individual endpoint
1684 static void s3c_hsotg_epint(struct s3c_hsotg *hsotg, unsigned int idx,
1687 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[idx];
1688 u32 epint_reg = dir_in ? S3C_DIEPINT(idx) : S3C_DOEPINT(idx);
1689 u32 epctl_reg = dir_in ? S3C_DIEPCTL(idx) : S3C_DOEPCTL(idx);
1690 u32 epsiz_reg = dir_in ? S3C_DIEPTSIZ(idx) : S3C_DOEPTSIZ(idx);
1694 ints = readl(hsotg->regs + epint_reg);
1696 dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
1697 __func__, idx, dir_in ? "in" : "out", ints);
1699 if (ints & S3C_DxEPINT_XferCompl) {
1701 "%s: XferCompl: DxEPCTL=0x%08x, DxEPTSIZ=%08x\n",
1702 __func__, readl(hsotg->regs + epctl_reg),
1703 readl(hsotg->regs + epsiz_reg));
1705 /* we get OutDone from the FIFO, so we only need to look
1706 * at completing IN requests here */
1708 s3c_hsotg_complete_in(hsotg, hs_ep);
1711 s3c_hsotg_enqueue_setup(hsotg);
1712 } else if (using_dma(hsotg)) {
1713 /* We're using DMA, we need to fire an OutDone here
1714 * as we ignore the RXFIFO. */
1716 s3c_hsotg_handle_outdone(hsotg, idx, false);
1719 clear |= S3C_DxEPINT_XferCompl;
1722 if (ints & S3C_DxEPINT_EPDisbld) {
1723 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
1724 clear |= S3C_DxEPINT_EPDisbld;
1727 if (ints & S3C_DxEPINT_AHBErr) {
1728 dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
1729 clear |= S3C_DxEPINT_AHBErr;
1732 if (ints & S3C_DxEPINT_Setup) { /* Setup or Timeout */
1733 dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__);
1735 if (using_dma(hsotg) && idx == 0) {
1736 /* this is the notification we've received a
1737 * setup packet. In non-DMA mode we'd get this
1738 * from the RXFIFO, instead we need to process
1739 * the setup here. */
1744 s3c_hsotg_handle_outdone(hsotg, 0, true);
1747 clear |= S3C_DxEPINT_Setup;
1750 if (ints & S3C_DxEPINT_Back2BackSetup) {
1751 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
1752 clear |= S3C_DxEPINT_Back2BackSetup;
1756 /* not sure if this is important, but we'll clear it anyway
1758 if (ints & S3C_DIEPMSK_INTknTXFEmpMsk) {
1759 dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
1761 clear |= S3C_DIEPMSK_INTknTXFEmpMsk;
1764 /* this probably means something bad is happening */
1765 if (ints & S3C_DIEPMSK_INTknEPMisMsk) {
1766 dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
1768 clear |= S3C_DIEPMSK_INTknEPMisMsk;
1772 writel(clear, hsotg->regs + epint_reg);
1776 * s3c_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
1777 * @hsotg: The device state.
1779 * Handle updating the device settings after the enumeration phase has
1782 static void s3c_hsotg_irq_enumdone(struct s3c_hsotg *hsotg)
1784 u32 dsts = readl(hsotg->regs + S3C_DSTS);
1785 int ep0_mps = 0, ep_mps;
1787 /* This should signal the finish of the enumeration phase
1788 * of the USB handshaking, so we should now know what rate
1789 * we connected at. */
1791 dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts);
1793 /* note, since we're limited by the size of transfer on EP0, and
1794 * it seems IN transfers must be a even number of packets we do
1795 * not advertise a 64byte MPS on EP0. */
1797 /* catch both EnumSpd_FS and EnumSpd_FS48 */
1798 switch (dsts & S3C_DSTS_EnumSpd_MASK) {
1799 case S3C_DSTS_EnumSpd_FS:
1800 case S3C_DSTS_EnumSpd_FS48:
1801 hsotg->gadget.speed = USB_SPEED_FULL;
1802 dev_info(hsotg->dev, "new device is full-speed\n");
1804 ep0_mps = EP0_MPS_LIMIT;
1808 case S3C_DSTS_EnumSpd_HS:
1809 dev_info(hsotg->dev, "new device is high-speed\n");
1810 hsotg->gadget.speed = USB_SPEED_HIGH;
1812 ep0_mps = EP0_MPS_LIMIT;
1816 case S3C_DSTS_EnumSpd_LS:
1817 hsotg->gadget.speed = USB_SPEED_LOW;
1818 dev_info(hsotg->dev, "new device is low-speed\n");
1820 /* note, we don't actually support LS in this driver at the
1821 * moment, and the documentation seems to imply that it isn't
1822 * supported by the PHYs on some of the devices.
1827 /* we should now know the maximum packet size for an
1828 * endpoint, so set the endpoints to a default value. */
1832 s3c_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps);
1833 for (i = 1; i < S3C_HSOTG_EPS; i++)
1834 s3c_hsotg_set_ep_maxpacket(hsotg, i, ep_mps);
1837 /* ensure after enumeration our EP0 is active */
1839 s3c_hsotg_enqueue_setup(hsotg);
1841 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
1842 readl(hsotg->regs + S3C_DIEPCTL0),
1843 readl(hsotg->regs + S3C_DOEPCTL0));
1847 * kill_all_requests - remove all requests from the endpoint's queue
1848 * @hsotg: The device state.
1849 * @ep: The endpoint the requests may be on.
1850 * @result: The result code to use.
1851 * @force: Force removal of any current requests
1853 * Go through the requests on the given endpoint and mark them
1854 * completed with the given result code.
1856 static void kill_all_requests(struct s3c_hsotg *hsotg,
1857 struct s3c_hsotg_ep *ep,
1858 int result, bool force)
1860 struct s3c_hsotg_req *req, *treq;
1861 unsigned long flags;
1863 spin_lock_irqsave(&ep->lock, flags);
1865 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
1866 /* currently, we can't do much about an already
1867 * running request on an in endpoint */
1869 if (ep->req == req && ep->dir_in && !force)
1872 s3c_hsotg_complete_request(hsotg, ep, req,
1876 spin_unlock_irqrestore(&ep->lock, flags);
1879 #define call_gadget(_hs, _entry) \
1880 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \
1881 (_hs)->driver && (_hs)->driver->_entry) \
1882 (_hs)->driver->_entry(&(_hs)->gadget);
1885 * s3c_hsotg_disconnect_irq - disconnect irq service
1886 * @hsotg: The device state.
1888 * A disconnect IRQ has been received, meaning that the host has
1889 * lost contact with the bus. Remove all current transactions
1890 * and signal the gadget driver that this has happened.
1892 static void s3c_hsotg_disconnect_irq(struct s3c_hsotg *hsotg)
1896 for (ep = 0; ep < S3C_HSOTG_EPS; ep++)
1897 kill_all_requests(hsotg, &hsotg->eps[ep], -ESHUTDOWN, true);
1899 call_gadget(hsotg, disconnect);
1903 * s3c_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
1904 * @hsotg: The device state:
1905 * @periodic: True if this is a periodic FIFO interrupt
1907 static void s3c_hsotg_irq_fifoempty(struct s3c_hsotg *hsotg, bool periodic)
1909 struct s3c_hsotg_ep *ep;
1912 /* look through for any more data to transmit */
1914 for (epno = 0; epno < S3C_HSOTG_EPS; epno++) {
1915 ep = &hsotg->eps[epno];
1920 if ((periodic && !ep->periodic) ||
1921 (!periodic && ep->periodic))
1924 ret = s3c_hsotg_trytx(hsotg, ep);
1930 static struct s3c_hsotg *our_hsotg;
1932 /* IRQ flags which will trigger a retry around the IRQ loop */
1933 #define IRQ_RETRY_MASK (S3C_GINTSTS_NPTxFEmp | \
1934 S3C_GINTSTS_PTxFEmp | \
1938 * s3c_hsotg_irq - handle device interrupt
1939 * @irq: The IRQ number triggered
1940 * @pw: The pw value when registered the handler.
1942 static irqreturn_t s3c_hsotg_irq(int irq, void *pw)
1944 struct s3c_hsotg *hsotg = pw;
1945 int retry_count = 8;
1950 gintsts = readl(hsotg->regs + S3C_GINTSTS);
1951 gintmsk = readl(hsotg->regs + S3C_GINTMSK);
1953 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
1954 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
1958 if (gintsts & S3C_GINTSTS_OTGInt) {
1959 u32 otgint = readl(hsotg->regs + S3C_GOTGINT);
1961 dev_info(hsotg->dev, "OTGInt: %08x\n", otgint);
1963 writel(otgint, hsotg->regs + S3C_GOTGINT);
1964 writel(S3C_GINTSTS_OTGInt, hsotg->regs + S3C_GINTSTS);
1967 if (gintsts & S3C_GINTSTS_DisconnInt) {
1968 dev_dbg(hsotg->dev, "%s: DisconnInt\n", __func__);
1969 writel(S3C_GINTSTS_DisconnInt, hsotg->regs + S3C_GINTSTS);
1971 s3c_hsotg_disconnect_irq(hsotg);
1974 if (gintsts & S3C_GINTSTS_SessReqInt) {
1975 dev_dbg(hsotg->dev, "%s: SessReqInt\n", __func__);
1976 writel(S3C_GINTSTS_SessReqInt, hsotg->regs + S3C_GINTSTS);
1979 if (gintsts & S3C_GINTSTS_EnumDone) {
1980 s3c_hsotg_irq_enumdone(hsotg);
1981 writel(S3C_GINTSTS_EnumDone, hsotg->regs + S3C_GINTSTS);
1984 if (gintsts & S3C_GINTSTS_ConIDStsChng) {
1985 dev_dbg(hsotg->dev, "ConIDStsChg (DSTS=0x%08x, GOTCTL=%08x)\n",
1986 readl(hsotg->regs + S3C_DSTS),
1987 readl(hsotg->regs + S3C_GOTGCTL));
1989 writel(S3C_GINTSTS_ConIDStsChng, hsotg->regs + S3C_GINTSTS);
1992 if (gintsts & (S3C_GINTSTS_OEPInt | S3C_GINTSTS_IEPInt)) {
1993 u32 daint = readl(hsotg->regs + S3C_DAINT);
1994 u32 daint_out = daint >> S3C_DAINT_OutEP_SHIFT;
1995 u32 daint_in = daint & ~(daint_out << S3C_DAINT_OutEP_SHIFT);
1998 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
2000 for (ep = 0; ep < 15 && daint_out; ep++, daint_out >>= 1) {
2002 s3c_hsotg_epint(hsotg, ep, 0);
2005 for (ep = 0; ep < 15 && daint_in; ep++, daint_in >>= 1) {
2007 s3c_hsotg_epint(hsotg, ep, 1);
2010 writel(daint, hsotg->regs + S3C_DAINT);
2011 writel(gintsts & (S3C_GINTSTS_OEPInt | S3C_GINTSTS_IEPInt),
2012 hsotg->regs + S3C_GINTSTS);
2015 if (gintsts & S3C_GINTSTS_USBRst) {
2016 dev_info(hsotg->dev, "%s: USBRst\n", __func__);
2017 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
2018 readl(hsotg->regs + S3C_GNPTXSTS));
2020 kill_all_requests(hsotg, &hsotg->eps[0], -ECONNRESET, true);
2022 /* it seems after a reset we can end up with a situation
2023 * where the TXFIFO still has data in it... try flushing
2024 * it to remove anything that may still be in it.
2028 writel(S3C_GRSTCTL_TxFNum(0) | S3C_GRSTCTL_TxFFlsh,
2029 hsotg->regs + S3C_GRSTCTL);
2031 dev_info(hsotg->dev, "GNPTXSTS=%08x\n",
2032 readl(hsotg->regs + S3C_GNPTXSTS));
2035 s3c_hsotg_enqueue_setup(hsotg);
2037 writel(S3C_GINTSTS_USBRst, hsotg->regs + S3C_GINTSTS);
2040 /* check both FIFOs */
2042 if (gintsts & S3C_GINTSTS_NPTxFEmp) {
2043 dev_dbg(hsotg->dev, "NPTxFEmp\n");
2045 /* Disable the interrupt to stop it happening again
2046 * unless one of these endpoint routines decides that
2047 * it needs re-enabling */
2049 s3c_hsotg_disable_gsint(hsotg, S3C_GINTSTS_NPTxFEmp);
2050 s3c_hsotg_irq_fifoempty(hsotg, false);
2052 writel(S3C_GINTSTS_NPTxFEmp, hsotg->regs + S3C_GINTSTS);
2055 if (gintsts & S3C_GINTSTS_PTxFEmp) {
2056 dev_dbg(hsotg->dev, "PTxFEmp\n");
2058 /* See note in S3C_GINTSTS_NPTxFEmp */
2060 s3c_hsotg_disable_gsint(hsotg, S3C_GINTSTS_PTxFEmp);
2061 s3c_hsotg_irq_fifoempty(hsotg, true);
2063 writel(S3C_GINTSTS_PTxFEmp, hsotg->regs + S3C_GINTSTS);
2066 if (gintsts & S3C_GINTSTS_RxFLvl) {
2067 /* note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
2068 * we need to retry s3c_hsotg_handle_rx if this is still
2071 s3c_hsotg_handle_rx(hsotg);
2072 writel(S3C_GINTSTS_RxFLvl, hsotg->regs + S3C_GINTSTS);
2075 if (gintsts & S3C_GINTSTS_ModeMis) {
2076 dev_warn(hsotg->dev, "warning, mode mismatch triggered\n");
2077 writel(S3C_GINTSTS_ModeMis, hsotg->regs + S3C_GINTSTS);
2080 if (gintsts & S3C_GINTSTS_USBSusp) {
2081 dev_info(hsotg->dev, "S3C_GINTSTS_USBSusp\n");
2082 writel(S3C_GINTSTS_USBSusp, hsotg->regs + S3C_GINTSTS);
2084 call_gadget(hsotg, suspend);
2087 if (gintsts & S3C_GINTSTS_WkUpInt) {
2088 dev_info(hsotg->dev, "S3C_GINTSTS_WkUpIn\n");
2089 writel(S3C_GINTSTS_WkUpInt, hsotg->regs + S3C_GINTSTS);
2091 call_gadget(hsotg, resume);
2094 if (gintsts & S3C_GINTSTS_ErlySusp) {
2095 dev_dbg(hsotg->dev, "S3C_GINTSTS_ErlySusp\n");
2096 writel(S3C_GINTSTS_ErlySusp, hsotg->regs + S3C_GINTSTS);
2099 /* these next two seem to crop-up occasionally causing the core
2100 * to shutdown the USB transfer, so try clearing them and logging
2103 if (gintsts & S3C_GINTSTS_GOUTNakEff) {
2104 dev_info(hsotg->dev, "GOUTNakEff triggered\n");
2106 s3c_hsotg_dump(hsotg);
2108 writel(S3C_DCTL_CGOUTNak, hsotg->regs + S3C_DCTL);
2109 writel(S3C_GINTSTS_GOUTNakEff, hsotg->regs + S3C_GINTSTS);
2112 if (gintsts & S3C_GINTSTS_GINNakEff) {
2113 dev_info(hsotg->dev, "GINNakEff triggered\n");
2115 s3c_hsotg_dump(hsotg);
2117 writel(S3C_DCTL_CGNPInNAK, hsotg->regs + S3C_DCTL);
2118 writel(S3C_GINTSTS_GINNakEff, hsotg->regs + S3C_GINTSTS);
2121 /* if we've had fifo events, we should try and go around the
2122 * loop again to see if there's any point in returning yet. */
2124 if (gintsts & IRQ_RETRY_MASK && --retry_count > 0)
2131 * s3c_hsotg_ep_enable - enable the given endpoint
2132 * @ep: The USB endpint to configure
2133 * @desc: The USB endpoint descriptor to configure with.
2135 * This is called from the USB gadget code's usb_ep_enable().
2137 static int s3c_hsotg_ep_enable(struct usb_ep *ep,
2138 const struct usb_endpoint_descriptor *desc)
2140 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2141 struct s3c_hsotg *hsotg = hs_ep->parent;
2142 unsigned long flags;
2143 int index = hs_ep->index;
2151 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
2152 __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes,
2153 desc->wMaxPacketSize, desc->bInterval);
2155 /* not to be called for EP0 */
2156 WARN_ON(index == 0);
2158 dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
2159 if (dir_in != hs_ep->dir_in) {
2160 dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__);
2164 mps = le16_to_cpu(desc->wMaxPacketSize);
2166 /* note, we handle this here instead of s3c_hsotg_set_ep_maxpacket */
2168 epctrl_reg = dir_in ? S3C_DIEPCTL(index) : S3C_DOEPCTL(index);
2169 epctrl = readl(hsotg->regs + epctrl_reg);
2171 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
2172 __func__, epctrl, epctrl_reg);
2174 spin_lock_irqsave(&hs_ep->lock, flags);
2176 epctrl &= ~(S3C_DxEPCTL_EPType_MASK | S3C_DxEPCTL_MPS_MASK);
2177 epctrl |= S3C_DxEPCTL_MPS(mps);
2179 /* mark the endpoint as active, otherwise the core may ignore
2180 * transactions entirely for this endpoint */
2181 epctrl |= S3C_DxEPCTL_USBActEp;
2183 /* set the NAK status on the endpoint, otherwise we might try and
2184 * do something with data that we've yet got a request to process
2185 * since the RXFIFO will take data for an endpoint even if the
2186 * size register hasn't been set.
2189 epctrl |= S3C_DxEPCTL_SNAK;
2191 /* update the endpoint state */
2192 hs_ep->ep.maxpacket = mps;
2194 /* default, set to non-periodic */
2195 hs_ep->periodic = 0;
2197 switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
2198 case USB_ENDPOINT_XFER_ISOC:
2199 dev_err(hsotg->dev, "no current ISOC support\n");
2203 case USB_ENDPOINT_XFER_BULK:
2204 epctrl |= S3C_DxEPCTL_EPType_Bulk;
2207 case USB_ENDPOINT_XFER_INT:
2209 /* Allocate our TxFNum by simply using the index
2210 * of the endpoint for the moment. We could do
2211 * something better if the host indicates how
2212 * many FIFOs we are expecting to use. */
2214 hs_ep->periodic = 1;
2215 epctrl |= S3C_DxEPCTL_TxFNum(index);
2218 epctrl |= S3C_DxEPCTL_EPType_Intterupt;
2221 case USB_ENDPOINT_XFER_CONTROL:
2222 epctrl |= S3C_DxEPCTL_EPType_Control;
2226 /* for non control endpoints, set PID to D0 */
2228 epctrl |= S3C_DxEPCTL_SetD0PID;
2230 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
2233 writel(epctrl, hsotg->regs + epctrl_reg);
2234 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
2235 __func__, readl(hsotg->regs + epctrl_reg));
2237 /* enable the endpoint interrupt */
2238 s3c_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
2241 spin_unlock_irqrestore(&hs_ep->lock, flags);
2245 static int s3c_hsotg_ep_disable(struct usb_ep *ep)
2247 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2248 struct s3c_hsotg *hsotg = hs_ep->parent;
2249 int dir_in = hs_ep->dir_in;
2250 int index = hs_ep->index;
2251 unsigned long flags;
2255 dev_info(hsotg->dev, "%s(ep %p)\n", __func__, ep);
2257 if (ep == &hsotg->eps[0].ep) {
2258 dev_err(hsotg->dev, "%s: called for ep0\n", __func__);
2262 epctrl_reg = dir_in ? S3C_DIEPCTL(index) : S3C_DOEPCTL(index);
2264 /* terminate all requests with shutdown */
2265 kill_all_requests(hsotg, hs_ep, -ESHUTDOWN, false);
2267 spin_lock_irqsave(&hs_ep->lock, flags);
2269 ctrl = readl(hsotg->regs + epctrl_reg);
2270 ctrl &= ~S3C_DxEPCTL_EPEna;
2271 ctrl &= ~S3C_DxEPCTL_USBActEp;
2272 ctrl |= S3C_DxEPCTL_SNAK;
2274 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
2275 writel(ctrl, hsotg->regs + epctrl_reg);
2277 /* disable endpoint interrupts */
2278 s3c_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
2280 spin_unlock_irqrestore(&hs_ep->lock, flags);
2285 * on_list - check request is on the given endpoint
2286 * @ep: The endpoint to check.
2287 * @test: The request to test if it is on the endpoint.
2289 static bool on_list(struct s3c_hsotg_ep *ep, struct s3c_hsotg_req *test)
2291 struct s3c_hsotg_req *req, *treq;
2293 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
2301 static int s3c_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
2303 struct s3c_hsotg_req *hs_req = our_req(req);
2304 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2305 struct s3c_hsotg *hs = hs_ep->parent;
2306 unsigned long flags;
2308 dev_info(hs->dev, "ep_dequeue(%p,%p)\n", ep, req);
2310 if (hs_req == hs_ep->req) {
2311 dev_dbg(hs->dev, "%s: already in progress\n", __func__);
2312 return -EINPROGRESS;
2315 spin_lock_irqsave(&hs_ep->lock, flags);
2317 if (!on_list(hs_ep, hs_req)) {
2318 spin_unlock_irqrestore(&hs_ep->lock, flags);
2322 s3c_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET);
2323 spin_unlock_irqrestore(&hs_ep->lock, flags);
2328 static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value)
2330 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2331 struct s3c_hsotg *hs = hs_ep->parent;
2332 int index = hs_ep->index;
2333 unsigned long irqflags;
2337 dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value);
2339 spin_lock_irqsave(&hs_ep->lock, irqflags);
2341 /* write both IN and OUT control registers */
2343 epreg = S3C_DIEPCTL(index);
2344 epctl = readl(hs->regs + epreg);
2347 epctl |= S3C_DxEPCTL_Stall;
2349 epctl &= ~S3C_DxEPCTL_Stall;
2351 writel(epctl, hs->regs + epreg);
2353 epreg = S3C_DOEPCTL(index);
2354 epctl = readl(hs->regs + epreg);
2357 epctl |= S3C_DxEPCTL_Stall;
2359 epctl &= ~S3C_DxEPCTL_Stall;
2361 writel(epctl, hs->regs + epreg);
2363 spin_unlock_irqrestore(&hs_ep->lock, irqflags);
2368 static struct usb_ep_ops s3c_hsotg_ep_ops = {
2369 .enable = s3c_hsotg_ep_enable,
2370 .disable = s3c_hsotg_ep_disable,
2371 .alloc_request = s3c_hsotg_ep_alloc_request,
2372 .free_request = s3c_hsotg_ep_free_request,
2373 .queue = s3c_hsotg_ep_queue,
2374 .dequeue = s3c_hsotg_ep_dequeue,
2375 .set_halt = s3c_hsotg_ep_sethalt,
2376 /* note, don't belive we have any call for the fifo routines */
2380 * s3c_hsotg_corereset - issue softreset to the core
2381 * @hsotg: The device state
2383 * Issue a soft reset to the core, and await the core finishing it.
2385 static int s3c_hsotg_corereset(struct s3c_hsotg *hsotg)
2390 dev_dbg(hsotg->dev, "resetting core\n");
2392 /* issue soft reset */
2393 writel(S3C_GRSTCTL_CSftRst, hsotg->regs + S3C_GRSTCTL);
2397 grstctl = readl(hsotg->regs + S3C_GRSTCTL);
2398 } while (!(grstctl & S3C_GRSTCTL_CSftRst) && timeout-- > 0);
2400 if (!(grstctl & S3C_GRSTCTL_CSftRst)) {
2401 dev_err(hsotg->dev, "Failed to get CSftRst asserted\n");
2408 u32 grstctl = readl(hsotg->regs + S3C_GRSTCTL);
2410 if (timeout-- < 0) {
2411 dev_info(hsotg->dev,
2412 "%s: reset failed, GRSTCTL=%08x\n",
2417 if (grstctl & S3C_GRSTCTL_CSftRst)
2420 if (!(grstctl & S3C_GRSTCTL_AHBIdle))
2423 break; /* reset done */
2426 dev_dbg(hsotg->dev, "reset successful\n");
2430 int usb_gadget_register_driver(struct usb_gadget_driver *driver)
2432 struct s3c_hsotg *hsotg = our_hsotg;
2436 printk(KERN_ERR "%s: called with no device\n", __func__);
2441 dev_err(hsotg->dev, "%s: no driver\n", __func__);
2445 if (driver->speed != USB_SPEED_HIGH &&
2446 driver->speed != USB_SPEED_FULL) {
2447 dev_err(hsotg->dev, "%s: bad speed\n", __func__);
2450 if (!driver->bind || !driver->setup) {
2451 dev_err(hsotg->dev, "%s: missing entry points\n", __func__);
2455 WARN_ON(hsotg->driver);
2457 driver->driver.bus = NULL;
2458 hsotg->driver = driver;
2459 hsotg->gadget.dev.driver = &driver->driver;
2460 hsotg->gadget.dev.dma_mask = hsotg->dev->dma_mask;
2461 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
2463 ret = device_add(&hsotg->gadget.dev);
2465 dev_err(hsotg->dev, "failed to register gadget device\n");
2469 ret = driver->bind(&hsotg->gadget);
2471 dev_err(hsotg->dev, "failed bind %s\n", driver->driver.name);
2473 hsotg->gadget.dev.driver = NULL;
2474 hsotg->driver = NULL;
2478 /* we must now enable ep0 ready for host detection and then
2479 * set configuration. */
2481 s3c_hsotg_corereset(hsotg);
2483 /* set the PLL on, remove the HNP/SRP and set the PHY */
2484 writel(S3C_GUSBCFG_PHYIf16 | S3C_GUSBCFG_TOutCal(7) |
2485 (0x5 << 10), hsotg->regs + S3C_GUSBCFG);
2487 /* looks like soft-reset changes state of FIFOs */
2488 s3c_hsotg_init_fifo(hsotg);
2490 __orr32(hsotg->regs + S3C_DCTL, S3C_DCTL_SftDiscon);
2492 writel(1 << 18 | S3C_DCFG_DevSpd_HS, hsotg->regs + S3C_DCFG);
2494 writel(S3C_GINTSTS_DisconnInt | S3C_GINTSTS_SessReqInt |
2495 S3C_GINTSTS_ConIDStsChng | S3C_GINTSTS_USBRst |
2496 S3C_GINTSTS_EnumDone | S3C_GINTSTS_OTGInt |
2497 S3C_GINTSTS_USBSusp | S3C_GINTSTS_WkUpInt |
2498 S3C_GINTSTS_GOUTNakEff | S3C_GINTSTS_GINNakEff |
2499 S3C_GINTSTS_ErlySusp,
2500 hsotg->regs + S3C_GINTMSK);
2502 if (using_dma(hsotg))
2503 writel(S3C_GAHBCFG_GlblIntrEn | S3C_GAHBCFG_DMAEn |
2504 S3C_GAHBCFG_HBstLen_Incr4,
2505 hsotg->regs + S3C_GAHBCFG);
2507 writel(S3C_GAHBCFG_GlblIntrEn, hsotg->regs + S3C_GAHBCFG);
2509 /* Enabling INTknTXFEmpMsk here seems to be a big mistake, we end
2510 * up being flooded with interrupts if the host is polling the
2511 * endpoint to try and read data. */
2513 writel(S3C_DIEPMSK_TimeOUTMsk | S3C_DIEPMSK_AHBErrMsk |
2514 S3C_DIEPMSK_INTknEPMisMsk |
2515 S3C_DIEPMSK_EPDisbldMsk | S3C_DIEPMSK_XferComplMsk,
2516 hsotg->regs + S3C_DIEPMSK);
2518 /* don't need XferCompl, we get that from RXFIFO in slave mode. In
2519 * DMA mode we may need this. */
2520 writel(S3C_DOEPMSK_SetupMsk | S3C_DOEPMSK_AHBErrMsk |
2521 S3C_DOEPMSK_EPDisbldMsk |
2522 (using_dma(hsotg) ? (S3C_DIEPMSK_XferComplMsk |
2523 S3C_DIEPMSK_TimeOUTMsk) : 0),
2524 hsotg->regs + S3C_DOEPMSK);
2526 writel(0, hsotg->regs + S3C_DAINTMSK);
2528 dev_info(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2529 readl(hsotg->regs + S3C_DIEPCTL0),
2530 readl(hsotg->regs + S3C_DOEPCTL0));
2532 /* enable in and out endpoint interrupts */
2533 s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_OEPInt | S3C_GINTSTS_IEPInt);
2535 /* Enable the RXFIFO when in slave mode, as this is how we collect
2536 * the data. In DMA mode, we get events from the FIFO but also
2537 * things we cannot process, so do not use it. */
2538 if (!using_dma(hsotg))
2539 s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_RxFLvl);
2541 /* Enable interrupts for EP0 in and out */
2542 s3c_hsotg_ctrl_epint(hsotg, 0, 0, 1);
2543 s3c_hsotg_ctrl_epint(hsotg, 0, 1, 1);
2545 __orr32(hsotg->regs + S3C_DCTL, S3C_DCTL_PWROnPrgDone);
2546 udelay(10); /* see openiboot */
2547 __bic32(hsotg->regs + S3C_DCTL, S3C_DCTL_PWROnPrgDone);
2549 dev_info(hsotg->dev, "DCTL=0x%08x\n", readl(hsotg->regs + S3C_DCTL));
2551 /* S3C_DxEPCTL_USBActEp says RO in manual, but seems to be set by
2552 writing to the EPCTL register.. */
2554 /* set to read 1 8byte packet */
2555 writel(S3C_DxEPTSIZ_MC(1) | S3C_DxEPTSIZ_PktCnt(1) |
2556 S3C_DxEPTSIZ_XferSize(8), hsotg->regs + DOEPTSIZ0);
2558 writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) |
2559 S3C_DxEPCTL_CNAK | S3C_DxEPCTL_EPEna |
2560 S3C_DxEPCTL_USBActEp,
2561 hsotg->regs + S3C_DOEPCTL0);
2563 /* enable, but don't activate EP0in */
2564 writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) |
2565 S3C_DxEPCTL_USBActEp, hsotg->regs + S3C_DIEPCTL0);
2567 s3c_hsotg_enqueue_setup(hsotg);
2569 dev_info(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2570 readl(hsotg->regs + S3C_DIEPCTL0),
2571 readl(hsotg->regs + S3C_DOEPCTL0));
2573 /* clear global NAKs */
2574 writel(S3C_DCTL_CGOUTNak | S3C_DCTL_CGNPInNAK,
2575 hsotg->regs + S3C_DCTL);
2577 /* remove the soft-disconnect and let's go */
2578 __bic32(hsotg->regs + S3C_DCTL, S3C_DCTL_SftDiscon);
2580 /* report to the user, and return */
2582 dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
2586 hsotg->driver = NULL;
2587 hsotg->gadget.dev.driver = NULL;
2590 EXPORT_SYMBOL(usb_gadget_register_driver);
2592 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
2594 struct s3c_hsotg *hsotg = our_hsotg;
2600 if (!driver || driver != hsotg->driver || !driver->unbind)
2603 /* all endpoints should be shutdown */
2604 for (ep = 0; ep < S3C_HSOTG_EPS; ep++)
2605 s3c_hsotg_ep_disable(&hsotg->eps[ep].ep);
2607 call_gadget(hsotg, disconnect);
2609 driver->unbind(&hsotg->gadget);
2610 hsotg->driver = NULL;
2611 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
2613 device_del(&hsotg->gadget.dev);
2615 dev_info(hsotg->dev, "unregistered gadget driver '%s'\n",
2616 driver->driver.name);
2620 EXPORT_SYMBOL(usb_gadget_unregister_driver);
2622 static int s3c_hsotg_gadget_getframe(struct usb_gadget *gadget)
2624 return s3c_hsotg_read_frameno(to_hsotg(gadget));
2627 static struct usb_gadget_ops s3c_hsotg_gadget_ops = {
2628 .get_frame = s3c_hsotg_gadget_getframe,
2632 * s3c_hsotg_initep - initialise a single endpoint
2633 * @hsotg: The device state.
2634 * @hs_ep: The endpoint to be initialised.
2635 * @epnum: The endpoint number
2637 * Initialise the given endpoint (as part of the probe and device state
2638 * creation) to give to the gadget driver. Setup the endpoint name, any
2639 * direction information and other state that may be required.
2641 static void __devinit s3c_hsotg_initep(struct s3c_hsotg *hsotg,
2642 struct s3c_hsotg_ep *hs_ep,
2650 else if ((epnum % 2) == 0) {
2657 hs_ep->index = epnum;
2659 snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir);
2661 INIT_LIST_HEAD(&hs_ep->queue);
2662 INIT_LIST_HEAD(&hs_ep->ep.ep_list);
2664 spin_lock_init(&hs_ep->lock);
2666 /* add to the list of endpoints known by the gadget driver */
2668 list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list);
2670 hs_ep->parent = hsotg;
2671 hs_ep->ep.name = hs_ep->name;
2672 hs_ep->ep.maxpacket = epnum ? 512 : EP0_MPS_LIMIT;
2673 hs_ep->ep.ops = &s3c_hsotg_ep_ops;
2675 /* Read the FIFO size for the Periodic TX FIFO, even if we're
2676 * an OUT endpoint, we may as well do this if in future the
2677 * code is changed to make each endpoint's direction changeable.
2680 ptxfifo = readl(hsotg->regs + S3C_DPTXFSIZn(epnum));
2681 hs_ep->fifo_size = S3C_DPTXFSIZn_DPTxFSize_GET(ptxfifo);
2683 /* if we're using dma, we need to set the next-endpoint pointer
2684 * to be something valid.
2687 if (using_dma(hsotg)) {
2688 u32 next = S3C_DxEPCTL_NextEp((epnum + 1) % 15);
2689 writel(next, hsotg->regs + S3C_DIEPCTL(epnum));
2690 writel(next, hsotg->regs + S3C_DOEPCTL(epnum));
2695 * s3c_hsotg_otgreset - reset the OtG phy block
2696 * @hsotg: The host state.
2698 * Power up the phy, set the basic configuration and start the PHY.
2700 static void s3c_hsotg_otgreset(struct s3c_hsotg *hsotg)
2704 writel(0, S3C_PHYPWR);
2707 osc = hsotg->plat->is_osc ? S3C_PHYCLK_EXT_OSC : 0;
2709 writel(osc | 0x10, S3C_PHYCLK);
2711 /* issue a full set of resets to the otg and core */
2713 writel(S3C_RSTCON_PHY, S3C_RSTCON);
2714 udelay(20); /* at-least 10uS */
2715 writel(0, S3C_RSTCON);
2719 static void s3c_hsotg_init(struct s3c_hsotg *hsotg)
2721 /* unmask subset of endpoint interrupts */
2723 writel(S3C_DIEPMSK_TimeOUTMsk | S3C_DIEPMSK_AHBErrMsk |
2724 S3C_DIEPMSK_EPDisbldMsk | S3C_DIEPMSK_XferComplMsk,
2725 hsotg->regs + S3C_DIEPMSK);
2727 writel(S3C_DOEPMSK_SetupMsk | S3C_DOEPMSK_AHBErrMsk |
2728 S3C_DOEPMSK_EPDisbldMsk | S3C_DOEPMSK_XferComplMsk,
2729 hsotg->regs + S3C_DOEPMSK);
2731 writel(0, hsotg->regs + S3C_DAINTMSK);
2734 /* post global nak until we're ready */
2735 writel(S3C_DCTL_SGNPInNAK | S3C_DCTL_SGOUTNak,
2736 hsotg->regs + S3C_DCTL);
2741 dev_info(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
2742 readl(hsotg->regs + S3C_GRXFSIZ),
2743 readl(hsotg->regs + S3C_GNPTXFSIZ));
2745 s3c_hsotg_init_fifo(hsotg);
2747 /* set the PLL on, remove the HNP/SRP and set the PHY */
2748 writel(S3C_GUSBCFG_PHYIf16 | S3C_GUSBCFG_TOutCal(7) | (0x5 << 10),
2749 hsotg->regs + S3C_GUSBCFG);
2751 writel(using_dma(hsotg) ? S3C_GAHBCFG_DMAEn : 0x0,
2752 hsotg->regs + S3C_GAHBCFG);
2755 static void s3c_hsotg_dump(struct s3c_hsotg *hsotg)
2757 struct device *dev = hsotg->dev;
2758 void __iomem *regs = hsotg->regs;
2762 dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
2763 readl(regs + S3C_DCFG), readl(regs + S3C_DCTL),
2764 readl(regs + S3C_DIEPMSK));
2766 dev_info(dev, "GAHBCFG=0x%08x, 0x44=0x%08x\n",
2767 readl(regs + S3C_GAHBCFG), readl(regs + 0x44));
2769 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
2770 readl(regs + S3C_GRXFSIZ), readl(regs + S3C_GNPTXFSIZ));
2772 /* show periodic fifo settings */
2774 for (idx = 1; idx <= 15; idx++) {
2775 val = readl(regs + S3C_DPTXFSIZn(idx));
2776 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
2777 val >> S3C_DPTXFSIZn_DPTxFSize_SHIFT,
2778 val & S3C_DPTXFSIZn_DPTxFStAddr_MASK);
2781 for (idx = 0; idx < 15; idx++) {
2783 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
2784 readl(regs + S3C_DIEPCTL(idx)),
2785 readl(regs + S3C_DIEPTSIZ(idx)),
2786 readl(regs + S3C_DIEPDMA(idx)));
2788 val = readl(regs + S3C_DOEPCTL(idx));
2790 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
2791 idx, readl(regs + S3C_DOEPCTL(idx)),
2792 readl(regs + S3C_DOEPTSIZ(idx)),
2793 readl(regs + S3C_DOEPDMA(idx)));
2797 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
2798 readl(regs + S3C_DVBUSDIS), readl(regs + S3C_DVBUSPULSE));
2803 * state_show - debugfs: show overall driver and device state.
2804 * @seq: The seq file to write to.
2805 * @v: Unused parameter.
2807 * This debugfs entry shows the overall state of the hardware and
2808 * some general information about each of the endpoints available
2811 static int state_show(struct seq_file *seq, void *v)
2813 struct s3c_hsotg *hsotg = seq->private;
2814 void __iomem *regs = hsotg->regs;
2817 seq_printf(seq, "DCFG=0x%08x, DCTL=0x%08x, DSTS=0x%08x\n",
2818 readl(regs + S3C_DCFG),
2819 readl(regs + S3C_DCTL),
2820 readl(regs + S3C_DSTS));
2822 seq_printf(seq, "DIEPMSK=0x%08x, DOEPMASK=0x%08x\n",
2823 readl(regs + S3C_DIEPMSK), readl(regs + S3C_DOEPMSK));
2825 seq_printf(seq, "GINTMSK=0x%08x, GINTSTS=0x%08x\n",
2826 readl(regs + S3C_GINTMSK),
2827 readl(regs + S3C_GINTSTS));
2829 seq_printf(seq, "DAINTMSK=0x%08x, DAINT=0x%08x\n",
2830 readl(regs + S3C_DAINTMSK),
2831 readl(regs + S3C_DAINT));
2833 seq_printf(seq, "GNPTXSTS=0x%08x, GRXSTSR=%08x\n",
2834 readl(regs + S3C_GNPTXSTS),
2835 readl(regs + S3C_GRXSTSR));
2837 seq_printf(seq, "\nEndpoint status:\n");
2839 for (idx = 0; idx < 15; idx++) {
2842 in = readl(regs + S3C_DIEPCTL(idx));
2843 out = readl(regs + S3C_DOEPCTL(idx));
2845 seq_printf(seq, "ep%d: DIEPCTL=0x%08x, DOEPCTL=0x%08x",
2848 in = readl(regs + S3C_DIEPTSIZ(idx));
2849 out = readl(regs + S3C_DOEPTSIZ(idx));
2851 seq_printf(seq, ", DIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x",
2854 seq_printf(seq, "\n");
2860 static int state_open(struct inode *inode, struct file *file)
2862 return single_open(file, state_show, inode->i_private);
2865 static const struct file_operations state_fops = {
2866 .owner = THIS_MODULE,
2869 .llseek = seq_lseek,
2870 .release = single_release,
2874 * fifo_show - debugfs: show the fifo information
2875 * @seq: The seq_file to write data to.
2876 * @v: Unused parameter.
2878 * Show the FIFO information for the overall fifo and all the
2879 * periodic transmission FIFOs.
2881 static int fifo_show(struct seq_file *seq, void *v)
2883 struct s3c_hsotg *hsotg = seq->private;
2884 void __iomem *regs = hsotg->regs;
2888 seq_printf(seq, "Non-periodic FIFOs:\n");
2889 seq_printf(seq, "RXFIFO: Size %d\n", readl(regs + S3C_GRXFSIZ));
2891 val = readl(regs + S3C_GNPTXFSIZ);
2892 seq_printf(seq, "NPTXFIFO: Size %d, Start 0x%08x\n",
2893 val >> S3C_GNPTXFSIZ_NPTxFDep_SHIFT,
2894 val & S3C_GNPTXFSIZ_NPTxFStAddr_MASK);
2896 seq_printf(seq, "\nPeriodic TXFIFOs:\n");
2898 for (idx = 1; idx <= 15; idx++) {
2899 val = readl(regs + S3C_DPTXFSIZn(idx));
2901 seq_printf(seq, "\tDPTXFIFO%2d: Size %d, Start 0x%08x\n", idx,
2902 val >> S3C_DPTXFSIZn_DPTxFSize_SHIFT,
2903 val & S3C_DPTXFSIZn_DPTxFStAddr_MASK);
2909 static int fifo_open(struct inode *inode, struct file *file)
2911 return single_open(file, fifo_show, inode->i_private);
2914 static const struct file_operations fifo_fops = {
2915 .owner = THIS_MODULE,
2918 .llseek = seq_lseek,
2919 .release = single_release,
2923 static const char *decode_direction(int is_in)
2925 return is_in ? "in" : "out";
2929 * ep_show - debugfs: show the state of an endpoint.
2930 * @seq: The seq_file to write data to.
2931 * @v: Unused parameter.
2933 * This debugfs entry shows the state of the given endpoint (one is
2934 * registered for each available).
2936 static int ep_show(struct seq_file *seq, void *v)
2938 struct s3c_hsotg_ep *ep = seq->private;
2939 struct s3c_hsotg *hsotg = ep->parent;
2940 struct s3c_hsotg_req *req;
2941 void __iomem *regs = hsotg->regs;
2942 int index = ep->index;
2943 int show_limit = 15;
2944 unsigned long flags;
2946 seq_printf(seq, "Endpoint index %d, named %s, dir %s:\n",
2947 ep->index, ep->ep.name, decode_direction(ep->dir_in));
2949 /* first show the register state */
2951 seq_printf(seq, "\tDIEPCTL=0x%08x, DOEPCTL=0x%08x\n",
2952 readl(regs + S3C_DIEPCTL(index)),
2953 readl(regs + S3C_DOEPCTL(index)));
2955 seq_printf(seq, "\tDIEPDMA=0x%08x, DOEPDMA=0x%08x\n",
2956 readl(regs + S3C_DIEPDMA(index)),
2957 readl(regs + S3C_DOEPDMA(index)));
2959 seq_printf(seq, "\tDIEPINT=0x%08x, DOEPINT=0x%08x\n",
2960 readl(regs + S3C_DIEPINT(index)),
2961 readl(regs + S3C_DOEPINT(index)));
2963 seq_printf(seq, "\tDIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x\n",
2964 readl(regs + S3C_DIEPTSIZ(index)),
2965 readl(regs + S3C_DOEPTSIZ(index)));
2967 seq_printf(seq, "\n");
2968 seq_printf(seq, "mps %d\n", ep->ep.maxpacket);
2969 seq_printf(seq, "total_data=%ld\n", ep->total_data);
2971 seq_printf(seq, "request list (%p,%p):\n",
2972 ep->queue.next, ep->queue.prev);
2974 spin_lock_irqsave(&ep->lock, flags);
2976 list_for_each_entry(req, &ep->queue, queue) {
2977 if (--show_limit < 0) {
2978 seq_printf(seq, "not showing more requests...\n");
2982 seq_printf(seq, "%c req %p: %d bytes @%p, ",
2983 req == ep->req ? '*' : ' ',
2984 req, req->req.length, req->req.buf);
2985 seq_printf(seq, "%d done, res %d\n",
2986 req->req.actual, req->req.status);
2989 spin_unlock_irqrestore(&ep->lock, flags);
2994 static int ep_open(struct inode *inode, struct file *file)
2996 return single_open(file, ep_show, inode->i_private);
2999 static const struct file_operations ep_fops = {
3000 .owner = THIS_MODULE,
3003 .llseek = seq_lseek,
3004 .release = single_release,
3008 * s3c_hsotg_create_debug - create debugfs directory and files
3009 * @hsotg: The driver state
3011 * Create the debugfs files to allow the user to get information
3012 * about the state of the system. The directory name is created
3013 * with the same name as the device itself, in case we end up
3014 * with multiple blocks in future systems.
3016 static void __devinit s3c_hsotg_create_debug(struct s3c_hsotg *hsotg)
3018 struct dentry *root;
3021 root = debugfs_create_dir(dev_name(hsotg->dev), NULL);
3022 hsotg->debug_root = root;
3024 dev_err(hsotg->dev, "cannot create debug root\n");
3028 /* create general state file */
3030 hsotg->debug_file = debugfs_create_file("state", 0444, root,
3031 hsotg, &state_fops);
3033 if (IS_ERR(hsotg->debug_file))
3034 dev_err(hsotg->dev, "%s: failed to create state\n", __func__);
3036 hsotg->debug_fifo = debugfs_create_file("fifo", 0444, root,
3039 if (IS_ERR(hsotg->debug_fifo))
3040 dev_err(hsotg->dev, "%s: failed to create fifo\n", __func__);
3042 /* create one file for each endpoint */
3044 for (epidx = 0; epidx < S3C_HSOTG_EPS; epidx++) {
3045 struct s3c_hsotg_ep *ep = &hsotg->eps[epidx];
3047 ep->debugfs = debugfs_create_file(ep->name, 0444,
3048 root, ep, &ep_fops);
3050 if (IS_ERR(ep->debugfs))
3051 dev_err(hsotg->dev, "failed to create %s debug file\n",
3057 * s3c_hsotg_delete_debug - cleanup debugfs entries
3058 * @hsotg: The driver state
3060 * Cleanup (remove) the debugfs files for use on module exit.
3062 static void __devexit s3c_hsotg_delete_debug(struct s3c_hsotg *hsotg)
3066 for (epidx = 0; epidx < S3C_HSOTG_EPS; epidx++) {
3067 struct s3c_hsotg_ep *ep = &hsotg->eps[epidx];
3068 debugfs_remove(ep->debugfs);
3071 debugfs_remove(hsotg->debug_file);
3072 debugfs_remove(hsotg->debug_fifo);
3073 debugfs_remove(hsotg->debug_root);
3077 * s3c_hsotg_gate - set the hardware gate for the block
3078 * @pdev: The device we bound to
3081 * Set the hardware gate setting into the block. If we end up on
3082 * something other than an S3C64XX, then we might need to change this
3083 * to using a platform data callback, or some other mechanism.
3085 static void s3c_hsotg_gate(struct platform_device *pdev, bool on)
3087 unsigned long flags;
3090 local_irq_save(flags);
3092 others = __raw_readl(S3C64XX_OTHERS);
3094 others |= S3C64XX_OTHERS_USBMASK;
3096 others &= ~S3C64XX_OTHERS_USBMASK;
3097 __raw_writel(others, S3C64XX_OTHERS);
3099 local_irq_restore(flags);
3102 static struct s3c_hsotg_plat s3c_hsotg_default_pdata;
3104 static int __devinit s3c_hsotg_probe(struct platform_device *pdev)
3106 struct s3c_hsotg_plat *plat = pdev->dev.platform_data;
3107 struct device *dev = &pdev->dev;
3108 struct s3c_hsotg *hsotg;
3109 struct resource *res;
3114 plat = &s3c_hsotg_default_pdata;
3116 hsotg = kzalloc(sizeof(struct s3c_hsotg) +
3117 sizeof(struct s3c_hsotg_ep) * S3C_HSOTG_EPS,
3120 dev_err(dev, "cannot get memory\n");
3127 platform_set_drvdata(pdev, hsotg);
3129 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3131 dev_err(dev, "cannot find register resource 0\n");
3136 hsotg->regs_res = request_mem_region(res->start, resource_size(res),
3138 if (!hsotg->regs_res) {
3139 dev_err(dev, "cannot reserve registers\n");
3144 hsotg->regs = ioremap(res->start, resource_size(res));
3146 dev_err(dev, "cannot map registers\n");
3151 ret = platform_get_irq(pdev, 0);
3153 dev_err(dev, "cannot find IRQ\n");
3159 ret = request_irq(ret, s3c_hsotg_irq, 0, dev_name(dev), hsotg);
3161 dev_err(dev, "cannot claim IRQ\n");
3165 dev_info(dev, "regs %p, irq %d\n", hsotg->regs, hsotg->irq);
3167 device_initialize(&hsotg->gadget.dev);
3169 dev_set_name(&hsotg->gadget.dev, "gadget");
3171 hsotg->gadget.is_dualspeed = 1;
3172 hsotg->gadget.ops = &s3c_hsotg_gadget_ops;
3173 hsotg->gadget.name = dev_name(dev);
3175 hsotg->gadget.dev.parent = dev;
3176 hsotg->gadget.dev.dma_mask = dev->dma_mask;
3178 /* setup endpoint information */
3180 INIT_LIST_HEAD(&hsotg->gadget.ep_list);
3181 hsotg->gadget.ep0 = &hsotg->eps[0].ep;
3183 /* allocate EP0 request */
3185 hsotg->ctrl_req = s3c_hsotg_ep_alloc_request(&hsotg->eps[0].ep,
3187 if (!hsotg->ctrl_req) {
3188 dev_err(dev, "failed to allocate ctrl req\n");
3192 /* reset the system */
3194 s3c_hsotg_gate(pdev, true);
3196 s3c_hsotg_otgreset(hsotg);
3197 s3c_hsotg_corereset(hsotg);
3198 s3c_hsotg_init(hsotg);
3200 /* initialise the endpoints now the core has been initialised */
3201 for (epnum = 0; epnum < S3C_HSOTG_EPS; epnum++)
3202 s3c_hsotg_initep(hsotg, &hsotg->eps[epnum], epnum);
3204 s3c_hsotg_create_debug(hsotg);
3206 s3c_hsotg_dump(hsotg);
3212 iounmap(hsotg->regs);
3215 release_resource(hsotg->regs_res);
3216 kfree(hsotg->regs_res);
3223 static int __devexit s3c_hsotg_remove(struct platform_device *pdev)
3225 struct s3c_hsotg *hsotg = platform_get_drvdata(pdev);
3227 s3c_hsotg_delete_debug(hsotg);
3229 usb_gadget_unregister_driver(hsotg->driver);
3231 free_irq(hsotg->irq, hsotg);
3232 iounmap(hsotg->regs);
3234 release_resource(hsotg->regs_res);
3235 kfree(hsotg->regs_res);
3237 s3c_hsotg_gate(pdev, false);
3244 #define s3c_hsotg_suspend NULL
3245 #define s3c_hsotg_resume NULL
3248 static struct platform_driver s3c_hsotg_driver = {
3250 .name = "s3c-hsotg",
3251 .owner = THIS_MODULE,
3253 .probe = s3c_hsotg_probe,
3254 .remove = __devexit_p(s3c_hsotg_remove),
3255 .suspend = s3c_hsotg_suspend,
3256 .resume = s3c_hsotg_resume,
3259 static int __init s3c_hsotg_modinit(void)
3261 return platform_driver_register(&s3c_hsotg_driver);
3264 static void __exit s3c_hsotg_modexit(void)
3266 platform_driver_unregister(&s3c_hsotg_driver);
3269 module_init(s3c_hsotg_modinit);
3270 module_exit(s3c_hsotg_modexit);
3272 MODULE_DESCRIPTION("Samsung S3C USB High-speed/OtG device");
3273 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
3274 MODULE_LICENSE("GPL");
3275 MODULE_ALIAS("platform:s3c-hsotg");