1 /* linux/drivers/usb/gadget/s3c-hsotg.c
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * Copyright 2008 Openmoko, Inc.
7 * Copyright 2008 Simtec Electronics
8 * Ben Dooks <ben@simtec.co.uk>
9 * http://armlinux.simtec.co.uk/
11 * S3C USB2.0 High-speed / OtG driver
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/spinlock.h>
21 #include <linux/interrupt.h>
22 #include <linux/platform_device.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/debugfs.h>
25 #include <linux/seq_file.h>
26 #include <linux/delay.h>
28 #include <linux/slab.h>
29 #include <linux/clk.h>
31 #include <linux/usb/ch9.h>
32 #include <linux/usb/gadget.h>
36 #include "s3c-hsotg.h"
37 #include <linux/platform_data/s3c-hsotg.h>
39 #define DMA_ADDR_INVALID (~((dma_addr_t)0))
43 * Unfortunately there seems to be a limit of the amount of data that can
44 * be transferred by IN transactions on EP0. This is either 127 bytes or 3
45 * packets (which practically means 1 packet and 63 bytes of data) when the
48 * This means if we are wanting to move >127 bytes of data, we need to
49 * split the transactions up, but just doing one packet at a time does
50 * not work (this may be an implicit DATA0 PID on first packet of the
51 * transaction) and doing 2 packets is outside the controller's limits.
53 * If we try to lower the MPS size for EP0, then no transfers work properly
54 * for EP0, and the system will fail basic enumeration. As no cause for this
55 * has currently been found, we cannot support any large IN transfers for
58 #define EP0_MPS_LIMIT 64
64 * struct s3c_hsotg_ep - driver endpoint definition.
65 * @ep: The gadget layer representation of the endpoint.
66 * @name: The driver generated name for the endpoint.
67 * @queue: Queue of requests for this endpoint.
68 * @parent: Reference back to the parent device structure.
69 * @req: The current request that the endpoint is processing. This is
70 * used to indicate an request has been loaded onto the endpoint
71 * and has yet to be completed (maybe due to data move, or simply
72 * awaiting an ack from the core all the data has been completed).
73 * @debugfs: File entry for debugfs file for this endpoint.
74 * @lock: State lock to protect contents of endpoint.
75 * @dir_in: Set to true if this endpoint is of the IN direction, which
76 * means that it is sending data to the Host.
77 * @index: The index for the endpoint registers.
78 * @name: The name array passed to the USB core.
79 * @halted: Set if the endpoint has been halted.
80 * @periodic: Set if this is a periodic ep, such as Interrupt
81 * @sent_zlp: Set if we've sent a zero-length packet.
82 * @total_data: The total number of data bytes done.
83 * @fifo_size: The size of the FIFO (for periodic IN endpoints)
84 * @fifo_load: The amount of data loaded into the FIFO (periodic IN)
85 * @last_load: The offset of data for the last start of request.
86 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN
88 * This is the driver's state for each registered enpoint, allowing it
89 * to keep track of transactions that need doing. Each endpoint has a
90 * lock to protect the state, to try and avoid using an overall lock
91 * for the host controller as much as possible.
93 * For periodic IN endpoints, we have fifo_size and fifo_load to try
94 * and keep track of the amount of data in the periodic FIFO for each
95 * of these as we don't have a status register that tells us how much
96 * is in each of them. (note, this may actually be useless information
97 * as in shared-fifo mode periodic in acts like a single-frame packet
100 struct s3c_hsotg_ep {
102 struct list_head queue;
103 struct s3c_hsotg *parent;
104 struct s3c_hsotg_req *req;
105 struct dentry *debugfs;
109 unsigned long total_data;
110 unsigned int size_loaded;
111 unsigned int last_load;
112 unsigned int fifo_load;
113 unsigned short fifo_size;
115 unsigned char dir_in;
118 unsigned int halted:1;
119 unsigned int periodic:1;
120 unsigned int sent_zlp:1;
125 #define S3C_HSOTG_EPS (8+1) /* limit to 9 for the moment */
128 * struct s3c_hsotg - driver state.
129 * @dev: The parent device supplied to the probe function
130 * @driver: USB gadget driver
131 * @plat: The platform specific configuration data.
132 * @regs: The memory area mapped for accessing registers.
133 * @regs_res: The resource that was allocated when claiming register space.
134 * @irq: The IRQ number we are using
135 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos.
136 * @debug_root: root directrory for debugfs.
137 * @debug_file: main status file for debugfs.
138 * @debug_fifo: FIFO status file for debugfs.
139 * @ep0_reply: Request used for ep0 reply.
140 * @ep0_buff: Buffer for EP0 reply data, if needed.
141 * @ctrl_buff: Buffer for EP0 control requests.
142 * @ctrl_req: Request for EP0 control packets.
143 * @eps: The endpoints being supplied to the gadget framework
147 struct usb_gadget_driver *driver;
148 struct s3c_hsotg_plat *plat;
151 struct resource *regs_res;
155 unsigned int dedicated_fifos:1;
157 struct dentry *debug_root;
158 struct dentry *debug_file;
159 struct dentry *debug_fifo;
161 struct usb_request *ep0_reply;
162 struct usb_request *ctrl_req;
166 struct usb_gadget gadget;
167 struct s3c_hsotg_ep eps[];
171 * struct s3c_hsotg_req - data transfer request
172 * @req: The USB gadget request
173 * @queue: The list of requests for the endpoint this is queued for.
174 * @in_progress: Has already had size/packets written to core
175 * @mapped: DMA buffer for this request has been mapped via dma_map_single().
177 struct s3c_hsotg_req {
178 struct usb_request req;
179 struct list_head queue;
180 unsigned char in_progress;
181 unsigned char mapped;
184 /* conversion functions */
185 static inline struct s3c_hsotg_req *our_req(struct usb_request *req)
187 return container_of(req, struct s3c_hsotg_req, req);
190 static inline struct s3c_hsotg_ep *our_ep(struct usb_ep *ep)
192 return container_of(ep, struct s3c_hsotg_ep, ep);
195 static inline struct s3c_hsotg *to_hsotg(struct usb_gadget *gadget)
197 return container_of(gadget, struct s3c_hsotg, gadget);
200 static inline void __orr32(void __iomem *ptr, u32 val)
202 writel(readl(ptr) | val, ptr);
205 static inline void __bic32(void __iomem *ptr, u32 val)
207 writel(readl(ptr) & ~val, ptr);
210 /* forward decleration of functions */
211 static void s3c_hsotg_dump(struct s3c_hsotg *hsotg);
214 * using_dma - return the DMA status of the driver.
215 * @hsotg: The driver state.
217 * Return true if we're using DMA.
219 * Currently, we have the DMA support code worked into everywhere
220 * that needs it, but the AMBA DMA implementation in the hardware can
221 * only DMA from 32bit aligned addresses. This means that gadgets such
222 * as the CDC Ethernet cannot work as they often pass packets which are
225 * Unfortunately the choice to use DMA or not is global to the controller
226 * and seems to be only settable when the controller is being put through
227 * a core reset. This means we either need to fix the gadgets to take
228 * account of DMA alignment, or add bounce buffers (yuerk).
230 * Until this issue is sorted out, we always return 'false'.
232 static inline bool using_dma(struct s3c_hsotg *hsotg)
234 return false; /* support is not complete */
238 * s3c_hsotg_en_gsint - enable one or more of the general interrupt
239 * @hsotg: The device state
240 * @ints: A bitmask of the interrupts to enable
242 static void s3c_hsotg_en_gsint(struct s3c_hsotg *hsotg, u32 ints)
244 u32 gsintmsk = readl(hsotg->regs + S3C_GINTMSK);
247 new_gsintmsk = gsintmsk | ints;
249 if (new_gsintmsk != gsintmsk) {
250 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
251 writel(new_gsintmsk, hsotg->regs + S3C_GINTMSK);
256 * s3c_hsotg_disable_gsint - disable one or more of the general interrupt
257 * @hsotg: The device state
258 * @ints: A bitmask of the interrupts to enable
260 static void s3c_hsotg_disable_gsint(struct s3c_hsotg *hsotg, u32 ints)
262 u32 gsintmsk = readl(hsotg->regs + S3C_GINTMSK);
265 new_gsintmsk = gsintmsk & ~ints;
267 if (new_gsintmsk != gsintmsk)
268 writel(new_gsintmsk, hsotg->regs + S3C_GINTMSK);
272 * s3c_hsotg_ctrl_epint - enable/disable an endpoint irq
273 * @hsotg: The device state
274 * @ep: The endpoint index
275 * @dir_in: True if direction is in.
276 * @en: The enable value, true to enable
278 * Set or clear the mask for an individual endpoint's interrupt
281 static void s3c_hsotg_ctrl_epint(struct s3c_hsotg *hsotg,
282 unsigned int ep, unsigned int dir_in,
292 local_irq_save(flags);
293 daint = readl(hsotg->regs + S3C_DAINTMSK);
298 writel(daint, hsotg->regs + S3C_DAINTMSK);
299 local_irq_restore(flags);
303 * s3c_hsotg_init_fifo - initialise non-periodic FIFOs
304 * @hsotg: The device instance.
306 static void s3c_hsotg_init_fifo(struct s3c_hsotg *hsotg)
314 /* the ryu 2.6.24 release ahs
315 writel(0x1C0, hsotg->regs + S3C_GRXFSIZ);
316 writel(S3C_GNPTXFSIZ_NPTxFStAddr(0x200) |
317 S3C_GNPTXFSIZ_NPTxFDep(0x1C0),
318 hsotg->regs + S3C_GNPTXFSIZ);
321 /* set FIFO sizes to 2048/1024 */
323 writel(2048, hsotg->regs + S3C_GRXFSIZ);
324 writel(S3C_GNPTXFSIZ_NPTxFStAddr(2048) |
325 S3C_GNPTXFSIZ_NPTxFDep(1024),
326 hsotg->regs + S3C_GNPTXFSIZ);
328 /* arange all the rest of the TX FIFOs, as some versions of this
329 * block have overlapping default addresses. This also ensures
330 * that if the settings have been changed, then they are set to
333 /* start at the end of the GNPTXFSIZ, rounded up */
337 /* currently we allocate TX FIFOs for all possible endpoints,
338 * and assume that they are all the same size. */
340 for (ep = 1; ep <= 15; ep++) {
342 val |= size << S3C_DPTXFSIZn_DPTxFSize_SHIFT;
345 writel(val, hsotg->regs + S3C_DPTXFSIZn(ep));
348 /* according to p428 of the design guide, we need to ensure that
349 * all fifos are flushed before continuing */
351 writel(S3C_GRSTCTL_TxFNum(0x10) | S3C_GRSTCTL_TxFFlsh |
352 S3C_GRSTCTL_RxFFlsh, hsotg->regs + S3C_GRSTCTL);
354 /* wait until the fifos are both flushed */
357 val = readl(hsotg->regs + S3C_GRSTCTL);
359 if ((val & (S3C_GRSTCTL_TxFFlsh | S3C_GRSTCTL_RxFFlsh)) == 0)
362 if (--timeout == 0) {
364 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
371 dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout);
375 * @ep: USB endpoint to allocate request for.
376 * @flags: Allocation flags
378 * Allocate a new USB request structure appropriate for the specified endpoint
380 static struct usb_request *s3c_hsotg_ep_alloc_request(struct usb_ep *ep,
383 struct s3c_hsotg_req *req;
385 req = kzalloc(sizeof(struct s3c_hsotg_req), flags);
389 INIT_LIST_HEAD(&req->queue);
391 req->req.dma = DMA_ADDR_INVALID;
396 * is_ep_periodic - return true if the endpoint is in periodic mode.
397 * @hs_ep: The endpoint to query.
399 * Returns true if the endpoint is in periodic mode, meaning it is being
400 * used for an Interrupt or ISO transfer.
402 static inline int is_ep_periodic(struct s3c_hsotg_ep *hs_ep)
404 return hs_ep->periodic;
408 * s3c_hsotg_unmap_dma - unmap the DMA memory being used for the request
409 * @hsotg: The device state.
410 * @hs_ep: The endpoint for the request
411 * @hs_req: The request being processed.
413 * This is the reverse of s3c_hsotg_map_dma(), called for the completion
414 * of a request to ensure the buffer is ready for access by the caller.
416 static void s3c_hsotg_unmap_dma(struct s3c_hsotg *hsotg,
417 struct s3c_hsotg_ep *hs_ep,
418 struct s3c_hsotg_req *hs_req)
420 struct usb_request *req = &hs_req->req;
421 enum dma_data_direction dir;
423 dir = hs_ep->dir_in ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
425 /* ignore this if we're not moving any data */
426 if (hs_req->req.length == 0)
429 if (hs_req->mapped) {
430 /* we mapped this, so unmap and remove the dma */
432 dma_unmap_single(hsotg->dev, req->dma, req->length, dir);
434 req->dma = DMA_ADDR_INVALID;
437 dma_sync_single_for_cpu(hsotg->dev, req->dma, req->length, dir);
442 * s3c_hsotg_write_fifo - write packet Data to the TxFIFO
443 * @hsotg: The controller state.
444 * @hs_ep: The endpoint we're going to write for.
445 * @hs_req: The request to write data for.
447 * This is called when the TxFIFO has some space in it to hold a new
448 * transmission and we have something to give it. The actual setup of
449 * the data size is done elsewhere, so all we have to do is to actually
452 * The return value is zero if there is more space (or nothing was done)
453 * otherwise -ENOSPC is returned if the FIFO space was used up.
455 * This routine is only needed for PIO
457 static int s3c_hsotg_write_fifo(struct s3c_hsotg *hsotg,
458 struct s3c_hsotg_ep *hs_ep,
459 struct s3c_hsotg_req *hs_req)
461 bool periodic = is_ep_periodic(hs_ep);
462 u32 gnptxsts = readl(hsotg->regs + S3C_GNPTXSTS);
463 int buf_pos = hs_req->req.actual;
464 int to_write = hs_ep->size_loaded;
469 to_write -= (buf_pos - hs_ep->last_load);
471 /* if there's nothing to write, get out early */
475 if (periodic && !hsotg->dedicated_fifos) {
476 u32 epsize = readl(hsotg->regs + S3C_DIEPTSIZ(hs_ep->index));
480 /* work out how much data was loaded so we can calculate
481 * how much data is left in the fifo. */
483 size_left = S3C_DxEPTSIZ_XferSize_GET(epsize);
485 /* if shared fifo, we cannot write anything until the
486 * previous data has been completely sent.
488 if (hs_ep->fifo_load != 0) {
489 s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_PTxFEmp);
493 dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n",
495 hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size);
497 /* how much of the data has moved */
498 size_done = hs_ep->size_loaded - size_left;
500 /* how much data is left in the fifo */
501 can_write = hs_ep->fifo_load - size_done;
502 dev_dbg(hsotg->dev, "%s: => can_write1=%d\n",
503 __func__, can_write);
505 can_write = hs_ep->fifo_size - can_write;
506 dev_dbg(hsotg->dev, "%s: => can_write2=%d\n",
507 __func__, can_write);
509 if (can_write <= 0) {
510 s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_PTxFEmp);
513 } else if (hsotg->dedicated_fifos && hs_ep->index != 0) {
514 can_write = readl(hsotg->regs + S3C_DTXFSTS(hs_ep->index));
519 if (S3C_GNPTXSTS_NPTxQSpcAvail_GET(gnptxsts) == 0) {
521 "%s: no queue slots available (0x%08x)\n",
524 s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_NPTxFEmp);
528 can_write = S3C_GNPTXSTS_NPTxFSpcAvail_GET(gnptxsts);
529 can_write *= 4; /* fifo size is in 32bit quantities. */
532 dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, mps %d\n",
533 __func__, gnptxsts, can_write, to_write, hs_ep->ep.maxpacket);
535 /* limit to 512 bytes of data, it seems at least on the non-periodic
536 * FIFO, requests of >512 cause the endpoint to get stuck with a
537 * fragment of the end of the transfer in it.
542 /* limit the write to one max-packet size worth of data, but allow
543 * the transfer to return that it did not run out of fifo space
545 if (to_write > hs_ep->ep.maxpacket) {
546 to_write = hs_ep->ep.maxpacket;
548 s3c_hsotg_en_gsint(hsotg,
549 periodic ? S3C_GINTSTS_PTxFEmp :
550 S3C_GINTSTS_NPTxFEmp);
553 /* see if we can write data */
555 if (to_write > can_write) {
556 to_write = can_write;
557 pkt_round = to_write % hs_ep->ep.maxpacket;
559 /* Not sure, but we probably shouldn't be writing partial
560 * packets into the FIFO, so round the write down to an
561 * exact number of packets.
563 * Note, we do not currently check to see if we can ever
564 * write a full packet or not to the FIFO.
568 to_write -= pkt_round;
570 /* enable correct FIFO interrupt to alert us when there
571 * is more room left. */
573 s3c_hsotg_en_gsint(hsotg,
574 periodic ? S3C_GINTSTS_PTxFEmp :
575 S3C_GINTSTS_NPTxFEmp);
578 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
579 to_write, hs_req->req.length, can_write, buf_pos);
584 hs_req->req.actual = buf_pos + to_write;
585 hs_ep->total_data += to_write;
588 hs_ep->fifo_load += to_write;
590 to_write = DIV_ROUND_UP(to_write, 4);
591 data = hs_req->req.buf + buf_pos;
593 writesl(hsotg->regs + S3C_EPFIFO(hs_ep->index), data, to_write);
595 return (to_write >= can_write) ? -ENOSPC : 0;
599 * get_ep_limit - get the maximum data legnth for this endpoint
600 * @hs_ep: The endpoint
602 * Return the maximum data that can be queued in one go on a given endpoint
603 * so that transfers that are too long can be split.
605 static unsigned get_ep_limit(struct s3c_hsotg_ep *hs_ep)
607 int index = hs_ep->index;
612 maxsize = S3C_DxEPTSIZ_XferSize_LIMIT + 1;
613 maxpkt = S3C_DxEPTSIZ_PktCnt_LIMIT + 1;
617 maxpkt = S3C_DIEPTSIZ0_PktCnt_LIMIT + 1;
622 /* we made the constant loading easier above by using +1 */
626 /* constrain by packet count if maxpkts*pktsize is greater
627 * than the length register size. */
629 if ((maxpkt * hs_ep->ep.maxpacket) < maxsize)
630 maxsize = maxpkt * hs_ep->ep.maxpacket;
636 * s3c_hsotg_start_req - start a USB request from an endpoint's queue
637 * @hsotg: The controller state.
638 * @hs_ep: The endpoint to process a request for
639 * @hs_req: The request to start.
640 * @continuing: True if we are doing more for the current request.
642 * Start the given request running by setting the endpoint registers
643 * appropriately, and writing any data to the FIFOs.
645 static void s3c_hsotg_start_req(struct s3c_hsotg *hsotg,
646 struct s3c_hsotg_ep *hs_ep,
647 struct s3c_hsotg_req *hs_req,
650 struct usb_request *ureq = &hs_req->req;
651 int index = hs_ep->index;
652 int dir_in = hs_ep->dir_in;
662 if (hs_ep->req && !continuing) {
663 dev_err(hsotg->dev, "%s: active request\n", __func__);
666 } else if (hs_ep->req != hs_req && continuing) {
668 "%s: continue different req\n", __func__);
674 epctrl_reg = dir_in ? S3C_DIEPCTL(index) : S3C_DOEPCTL(index);
675 epsize_reg = dir_in ? S3C_DIEPTSIZ(index) : S3C_DOEPTSIZ(index);
677 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
678 __func__, readl(hsotg->regs + epctrl_reg), index,
679 hs_ep->dir_in ? "in" : "out");
681 /* If endpoint is stalled, we will restart request later */
682 ctrl = readl(hsotg->regs + epctrl_reg);
684 if (ctrl & S3C_DxEPCTL_Stall) {
685 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
689 length = ureq->length - ureq->actual;
693 "REQ buf %p len %d dma 0x%08x noi=%d zp=%d snok=%d\n",
694 ureq->buf, length, ureq->dma,
695 ureq->no_interrupt, ureq->zero, ureq->short_not_ok);
697 maxreq = get_ep_limit(hs_ep);
698 if (length > maxreq) {
699 int round = maxreq % hs_ep->ep.maxpacket;
701 dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n",
702 __func__, length, maxreq, round);
704 /* round down to multiple of packets */
712 packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket);
714 packets = 1; /* send one packet if length is zero. */
716 if (dir_in && index != 0)
717 epsize = S3C_DxEPTSIZ_MC(1);
721 if (index != 0 && ureq->zero) {
722 /* test for the packets being exactly right for the
725 if (length == (packets * hs_ep->ep.maxpacket))
729 epsize |= S3C_DxEPTSIZ_PktCnt(packets);
730 epsize |= S3C_DxEPTSIZ_XferSize(length);
732 dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
733 __func__, packets, length, ureq->length, epsize, epsize_reg);
735 /* store the request as the current one we're doing */
738 /* write size / packets */
739 writel(epsize, hsotg->regs + epsize_reg);
741 if (using_dma(hsotg) && !continuing) {
742 unsigned int dma_reg;
744 /* write DMA address to control register, buffer already
745 * synced by s3c_hsotg_ep_queue(). */
747 dma_reg = dir_in ? S3C_DIEPDMA(index) : S3C_DOEPDMA(index);
748 writel(ureq->dma, hsotg->regs + dma_reg);
750 dev_dbg(hsotg->dev, "%s: 0x%08x => 0x%08x\n",
751 __func__, ureq->dma, dma_reg);
754 ctrl |= S3C_DxEPCTL_EPEna; /* ensure ep enabled */
755 ctrl |= S3C_DxEPCTL_USBActEp;
756 ctrl |= S3C_DxEPCTL_CNAK; /* clear NAK set by core */
758 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
759 writel(ctrl, hsotg->regs + epctrl_reg);
761 /* set these, it seems that DMA support increments past the end
762 * of the packet buffer so we need to calculate the length from
763 * this information. */
764 hs_ep->size_loaded = length;
765 hs_ep->last_load = ureq->actual;
767 if (dir_in && !using_dma(hsotg)) {
768 /* set these anyway, we may need them for non-periodic in */
769 hs_ep->fifo_load = 0;
771 s3c_hsotg_write_fifo(hsotg, hs_ep, hs_req);
774 /* clear the INTknTXFEmpMsk when we start request, more as a aide
775 * to debugging to see what is going on. */
777 writel(S3C_DIEPMSK_INTknTXFEmpMsk,
778 hsotg->regs + S3C_DIEPINT(index));
780 /* Note, trying to clear the NAK here causes problems with transmit
781 * on the S3C6400 ending up with the TXFIFO becoming full. */
783 /* check ep is enabled */
784 if (!(readl(hsotg->regs + epctrl_reg) & S3C_DxEPCTL_EPEna))
786 "ep%d: failed to become enabled (DxEPCTL=0x%08x)?\n",
787 index, readl(hsotg->regs + epctrl_reg));
789 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n",
790 __func__, readl(hsotg->regs + epctrl_reg));
794 * s3c_hsotg_map_dma - map the DMA memory being used for the request
795 * @hsotg: The device state.
796 * @hs_ep: The endpoint the request is on.
797 * @req: The request being processed.
799 * We've been asked to queue a request, so ensure that the memory buffer
800 * is correctly setup for DMA. If we've been passed an extant DMA address
801 * then ensure the buffer has been synced to memory. If our buffer has no
802 * DMA memory, then we map the memory and mark our request to allow us to
803 * cleanup on completion.
805 static int s3c_hsotg_map_dma(struct s3c_hsotg *hsotg,
806 struct s3c_hsotg_ep *hs_ep,
807 struct usb_request *req)
809 enum dma_data_direction dir;
810 struct s3c_hsotg_req *hs_req = our_req(req);
812 dir = hs_ep->dir_in ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
814 /* if the length is zero, ignore the DMA data */
815 if (hs_req->req.length == 0)
818 if (req->dma == DMA_ADDR_INVALID) {
821 dma = dma_map_single(hsotg->dev, req->buf, req->length, dir);
823 if (unlikely(dma_mapping_error(hsotg->dev, dma)))
827 dev_err(hsotg->dev, "%s: unaligned dma buffer\n",
830 dma_unmap_single(hsotg->dev, dma, req->length, dir);
837 dma_sync_single_for_cpu(hsotg->dev, req->dma, req->length, dir);
844 dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n",
845 __func__, req->buf, req->length);
850 static int s3c_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
853 struct s3c_hsotg_req *hs_req = our_req(req);
854 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
855 struct s3c_hsotg *hs = hs_ep->parent;
856 unsigned long irqflags;
859 dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
860 ep->name, req, req->length, req->buf, req->no_interrupt,
861 req->zero, req->short_not_ok);
863 /* initialise status of the request */
864 INIT_LIST_HEAD(&hs_req->queue);
866 req->status = -EINPROGRESS;
868 /* if we're using DMA, sync the buffers as necessary */
870 int ret = s3c_hsotg_map_dma(hs, hs_ep, req);
875 spin_lock_irqsave(&hs_ep->lock, irqflags);
877 first = list_empty(&hs_ep->queue);
878 list_add_tail(&hs_req->queue, &hs_ep->queue);
881 s3c_hsotg_start_req(hs, hs_ep, hs_req, false);
883 spin_unlock_irqrestore(&hs_ep->lock, irqflags);
888 static void s3c_hsotg_ep_free_request(struct usb_ep *ep,
889 struct usb_request *req)
891 struct s3c_hsotg_req *hs_req = our_req(req);
897 * s3c_hsotg_complete_oursetup - setup completion callback
898 * @ep: The endpoint the request was on.
899 * @req: The request completed.
901 * Called on completion of any requests the driver itself
902 * submitted that need cleaning up.
904 static void s3c_hsotg_complete_oursetup(struct usb_ep *ep,
905 struct usb_request *req)
907 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
908 struct s3c_hsotg *hsotg = hs_ep->parent;
910 dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req);
912 s3c_hsotg_ep_free_request(ep, req);
916 * ep_from_windex - convert control wIndex value to endpoint
917 * @hsotg: The driver state.
918 * @windex: The control request wIndex field (in host order).
920 * Convert the given wIndex into a pointer to an driver endpoint
921 * structure, or return NULL if it is not a valid endpoint.
923 static struct s3c_hsotg_ep *ep_from_windex(struct s3c_hsotg *hsotg,
926 struct s3c_hsotg_ep *ep = &hsotg->eps[windex & 0x7F];
927 int dir = (windex & USB_DIR_IN) ? 1 : 0;
928 int idx = windex & 0x7F;
933 if (idx > S3C_HSOTG_EPS)
936 if (idx && ep->dir_in != dir)
943 * s3c_hsotg_send_reply - send reply to control request
944 * @hsotg: The device state
946 * @buff: Buffer for request
947 * @length: Length of reply.
949 * Create a request and queue it on the given endpoint. This is useful as
950 * an internal method of sending replies to certain control requests, etc.
952 static int s3c_hsotg_send_reply(struct s3c_hsotg *hsotg,
953 struct s3c_hsotg_ep *ep,
957 struct usb_request *req;
960 dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length);
962 req = s3c_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC);
963 hsotg->ep0_reply = req;
965 dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__);
969 req->buf = hsotg->ep0_buff;
970 req->length = length;
971 req->zero = 1; /* always do zero-length final transfer */
972 req->complete = s3c_hsotg_complete_oursetup;
975 memcpy(req->buf, buff, length);
979 ret = s3c_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC);
981 dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__);
989 * s3c_hsotg_process_req_status - process request GET_STATUS
990 * @hsotg: The device state
991 * @ctrl: USB control request
993 static int s3c_hsotg_process_req_status(struct s3c_hsotg *hsotg,
994 struct usb_ctrlrequest *ctrl)
996 struct s3c_hsotg_ep *ep0 = &hsotg->eps[0];
997 struct s3c_hsotg_ep *ep;
1001 dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__);
1004 dev_warn(hsotg->dev, "%s: direction out?\n", __func__);
1008 switch (ctrl->bRequestType & USB_RECIP_MASK) {
1009 case USB_RECIP_DEVICE:
1010 reply = cpu_to_le16(0); /* bit 0 => self powered,
1011 * bit 1 => remote wakeup */
1014 case USB_RECIP_INTERFACE:
1015 /* currently, the data result should be zero */
1016 reply = cpu_to_le16(0);
1019 case USB_RECIP_ENDPOINT:
1020 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
1024 reply = cpu_to_le16(ep->halted ? 1 : 0);
1031 if (le16_to_cpu(ctrl->wLength) != 2)
1034 ret = s3c_hsotg_send_reply(hsotg, ep0, &reply, 2);
1036 dev_err(hsotg->dev, "%s: failed to send reply\n", __func__);
1043 static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value);
1046 * get_ep_head - return the first request on the endpoint
1047 * @hs_ep: The controller endpoint to get
1049 * Get the first request on the endpoint.
1051 static struct s3c_hsotg_req *get_ep_head(struct s3c_hsotg_ep *hs_ep)
1053 if (list_empty(&hs_ep->queue))
1056 return list_first_entry(&hs_ep->queue, struct s3c_hsotg_req, queue);
1060 * s3c_hsotg_process_req_featire - process request {SET,CLEAR}_FEATURE
1061 * @hsotg: The device state
1062 * @ctrl: USB control request
1064 static int s3c_hsotg_process_req_feature(struct s3c_hsotg *hsotg,
1065 struct usb_ctrlrequest *ctrl)
1067 struct s3c_hsotg_ep *ep0 = &hsotg->eps[0];
1068 struct s3c_hsotg_req *hs_req;
1070 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
1071 struct s3c_hsotg_ep *ep;
1074 dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",
1075 __func__, set ? "SET" : "CLEAR");
1077 if (ctrl->bRequestType == USB_RECIP_ENDPOINT) {
1078 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
1080 dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n",
1081 __func__, le16_to_cpu(ctrl->wIndex));
1085 switch (le16_to_cpu(ctrl->wValue)) {
1086 case USB_ENDPOINT_HALT:
1087 s3c_hsotg_ep_sethalt(&ep->ep, set);
1089 ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0);
1092 "%s: failed to send reply\n", __func__);
1098 * If we have request in progress,
1104 list_del_init(&hs_req->queue);
1105 hs_req->req.complete(&ep->ep,
1109 /* If we have pending request, then start it */
1110 restart = !list_empty(&ep->queue);
1112 hs_req = get_ep_head(ep);
1113 s3c_hsotg_start_req(hsotg, ep,
1124 return -ENOENT; /* currently only deal with endpoint */
1130 * s3c_hsotg_process_control - process a control request
1131 * @hsotg: The device state
1132 * @ctrl: The control request received
1134 * The controller has received the SETUP phase of a control request, and
1135 * needs to work out what to do next (and whether to pass it on to the
1138 static void s3c_hsotg_process_control(struct s3c_hsotg *hsotg,
1139 struct usb_ctrlrequest *ctrl)
1141 struct s3c_hsotg_ep *ep0 = &hsotg->eps[0];
1147 dev_dbg(hsotg->dev, "ctrl Req=%02x, Type=%02x, V=%04x, L=%04x\n",
1148 ctrl->bRequest, ctrl->bRequestType,
1149 ctrl->wValue, ctrl->wLength);
1151 /* record the direction of the request, for later use when enquing
1152 * packets onto EP0. */
1154 ep0->dir_in = (ctrl->bRequestType & USB_DIR_IN) ? 1 : 0;
1155 dev_dbg(hsotg->dev, "ctrl: dir_in=%d\n", ep0->dir_in);
1157 /* if we've no data with this request, then the last part of the
1158 * transaction is going to implicitly be IN. */
1159 if (ctrl->wLength == 0)
1162 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1163 switch (ctrl->bRequest) {
1164 case USB_REQ_SET_ADDRESS:
1165 dcfg = readl(hsotg->regs + S3C_DCFG);
1166 dcfg &= ~S3C_DCFG_DevAddr_MASK;
1167 dcfg |= ctrl->wValue << S3C_DCFG_DevAddr_SHIFT;
1168 writel(dcfg, hsotg->regs + S3C_DCFG);
1170 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1172 ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0);
1175 case USB_REQ_GET_STATUS:
1176 ret = s3c_hsotg_process_req_status(hsotg, ctrl);
1179 case USB_REQ_CLEAR_FEATURE:
1180 case USB_REQ_SET_FEATURE:
1181 ret = s3c_hsotg_process_req_feature(hsotg, ctrl);
1186 /* as a fallback, try delivering it to the driver to deal with */
1188 if (ret == 0 && hsotg->driver) {
1189 ret = hsotg->driver->setup(&hsotg->gadget, ctrl);
1191 dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
1194 /* the request is either unhandlable, or is not formatted correctly
1195 * so respond with a STALL for the status stage to indicate failure.
1202 dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
1203 reg = (ep0->dir_in) ? S3C_DIEPCTL0 : S3C_DOEPCTL0;
1205 /* S3C_DxEPCTL_Stall will be cleared by EP once it has
1206 * taken effect, so no need to clear later. */
1208 ctrl = readl(hsotg->regs + reg);
1209 ctrl |= S3C_DxEPCTL_Stall;
1210 ctrl |= S3C_DxEPCTL_CNAK;
1211 writel(ctrl, hsotg->regs + reg);
1214 "written DxEPCTL=0x%08x to %08x (DxEPCTL=0x%08x)\n",
1215 ctrl, reg, readl(hsotg->regs + reg));
1217 /* don't believe we need to anything more to get the EP
1218 * to reply with a STALL packet */
1222 static void s3c_hsotg_enqueue_setup(struct s3c_hsotg *hsotg);
1225 * s3c_hsotg_complete_setup - completion of a setup transfer
1226 * @ep: The endpoint the request was on.
1227 * @req: The request completed.
1229 * Called on completion of any requests the driver itself submitted for
1232 static void s3c_hsotg_complete_setup(struct usb_ep *ep,
1233 struct usb_request *req)
1235 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
1236 struct s3c_hsotg *hsotg = hs_ep->parent;
1238 if (req->status < 0) {
1239 dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status);
1243 if (req->actual == 0)
1244 s3c_hsotg_enqueue_setup(hsotg);
1246 s3c_hsotg_process_control(hsotg, req->buf);
1250 * s3c_hsotg_enqueue_setup - start a request for EP0 packets
1251 * @hsotg: The device state.
1253 * Enqueue a request on EP0 if necessary to received any SETUP packets
1254 * received from the host.
1256 static void s3c_hsotg_enqueue_setup(struct s3c_hsotg *hsotg)
1258 struct usb_request *req = hsotg->ctrl_req;
1259 struct s3c_hsotg_req *hs_req = our_req(req);
1262 dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__);
1266 req->buf = hsotg->ctrl_buff;
1267 req->complete = s3c_hsotg_complete_setup;
1269 if (!list_empty(&hs_req->queue)) {
1270 dev_dbg(hsotg->dev, "%s already queued???\n", __func__);
1274 hsotg->eps[0].dir_in = 0;
1276 ret = s3c_hsotg_ep_queue(&hsotg->eps[0].ep, req, GFP_ATOMIC);
1278 dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret);
1279 /* Don't think there's much we can do other than watch the
1285 * s3c_hsotg_complete_request - complete a request given to us
1286 * @hsotg: The device state.
1287 * @hs_ep: The endpoint the request was on.
1288 * @hs_req: The request to complete.
1289 * @result: The result code (0 => Ok, otherwise errno)
1291 * The given request has finished, so call the necessary completion
1292 * if it has one and then look to see if we can start a new request
1295 * Note, expects the ep to already be locked as appropriate.
1297 static void s3c_hsotg_complete_request(struct s3c_hsotg *hsotg,
1298 struct s3c_hsotg_ep *hs_ep,
1299 struct s3c_hsotg_req *hs_req,
1305 dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__);
1309 dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n",
1310 hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete);
1312 /* only replace the status if we've not already set an error
1313 * from a previous transaction */
1315 if (hs_req->req.status == -EINPROGRESS)
1316 hs_req->req.status = result;
1319 list_del_init(&hs_req->queue);
1321 if (using_dma(hsotg))
1322 s3c_hsotg_unmap_dma(hsotg, hs_ep, hs_req);
1324 /* call the complete request with the locks off, just in case the
1325 * request tries to queue more work for this endpoint. */
1327 if (hs_req->req.complete) {
1328 spin_unlock(&hs_ep->lock);
1329 hs_req->req.complete(&hs_ep->ep, &hs_req->req);
1330 spin_lock(&hs_ep->lock);
1333 /* Look to see if there is anything else to do. Note, the completion
1334 * of the previous request may have caused a new request to be started
1335 * so be careful when doing this. */
1337 if (!hs_ep->req && result >= 0) {
1338 restart = !list_empty(&hs_ep->queue);
1340 hs_req = get_ep_head(hs_ep);
1341 s3c_hsotg_start_req(hsotg, hs_ep, hs_req, false);
1347 * s3c_hsotg_complete_request_lock - complete a request given to us (locked)
1348 * @hsotg: The device state.
1349 * @hs_ep: The endpoint the request was on.
1350 * @hs_req: The request to complete.
1351 * @result: The result code (0 => Ok, otherwise errno)
1353 * See s3c_hsotg_complete_request(), but called with the endpoint's
1356 static void s3c_hsotg_complete_request_lock(struct s3c_hsotg *hsotg,
1357 struct s3c_hsotg_ep *hs_ep,
1358 struct s3c_hsotg_req *hs_req,
1361 unsigned long flags;
1363 spin_lock_irqsave(&hs_ep->lock, flags);
1364 s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
1365 spin_unlock_irqrestore(&hs_ep->lock, flags);
1369 * s3c_hsotg_rx_data - receive data from the FIFO for an endpoint
1370 * @hsotg: The device state.
1371 * @ep_idx: The endpoint index for the data
1372 * @size: The size of data in the fifo, in bytes
1374 * The FIFO status shows there is data to read from the FIFO for a given
1375 * endpoint, so sort out whether we need to read the data into a request
1376 * that has been made for that endpoint.
1378 static void s3c_hsotg_rx_data(struct s3c_hsotg *hsotg, int ep_idx, int size)
1380 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[ep_idx];
1381 struct s3c_hsotg_req *hs_req = hs_ep->req;
1382 void __iomem *fifo = hsotg->regs + S3C_EPFIFO(ep_idx);
1388 u32 epctl = readl(hsotg->regs + S3C_DOEPCTL(ep_idx));
1391 dev_warn(hsotg->dev,
1392 "%s: FIFO %d bytes on ep%d but no req (DxEPCTl=0x%08x)\n",
1393 __func__, size, ep_idx, epctl);
1395 /* dump the data from the FIFO, we've nothing we can do */
1396 for (ptr = 0; ptr < size; ptr += 4)
1402 spin_lock(&hs_ep->lock);
1405 read_ptr = hs_req->req.actual;
1406 max_req = hs_req->req.length - read_ptr;
1408 dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n",
1409 __func__, to_read, max_req, read_ptr, hs_req->req.length);
1411 if (to_read > max_req) {
1412 /* more data appeared than we where willing
1413 * to deal with in this request.
1416 /* currently we don't deal this */
1420 hs_ep->total_data += to_read;
1421 hs_req->req.actual += to_read;
1422 to_read = DIV_ROUND_UP(to_read, 4);
1424 /* note, we might over-write the buffer end by 3 bytes depending on
1425 * alignment of the data. */
1426 readsl(fifo, hs_req->req.buf + read_ptr, to_read);
1428 spin_unlock(&hs_ep->lock);
1432 * s3c_hsotg_send_zlp - send zero-length packet on control endpoint
1433 * @hsotg: The device instance
1434 * @req: The request currently on this endpoint
1436 * Generate a zero-length IN packet request for terminating a SETUP
1439 * Note, since we don't write any data to the TxFIFO, then it is
1440 * currently believed that we do not need to wait for any space in
1443 static void s3c_hsotg_send_zlp(struct s3c_hsotg *hsotg,
1444 struct s3c_hsotg_req *req)
1449 dev_warn(hsotg->dev, "%s: no request?\n", __func__);
1453 if (req->req.length == 0) {
1454 hsotg->eps[0].sent_zlp = 1;
1455 s3c_hsotg_enqueue_setup(hsotg);
1459 hsotg->eps[0].dir_in = 1;
1460 hsotg->eps[0].sent_zlp = 1;
1462 dev_dbg(hsotg->dev, "sending zero-length packet\n");
1464 /* issue a zero-sized packet to terminate this */
1465 writel(S3C_DxEPTSIZ_MC(1) | S3C_DxEPTSIZ_PktCnt(1) |
1466 S3C_DxEPTSIZ_XferSize(0), hsotg->regs + S3C_DIEPTSIZ(0));
1468 ctrl = readl(hsotg->regs + S3C_DIEPCTL0);
1469 ctrl |= S3C_DxEPCTL_CNAK; /* clear NAK set by core */
1470 ctrl |= S3C_DxEPCTL_EPEna; /* ensure ep enabled */
1471 ctrl |= S3C_DxEPCTL_USBActEp;
1472 writel(ctrl, hsotg->regs + S3C_DIEPCTL0);
1476 * s3c_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
1477 * @hsotg: The device instance
1478 * @epnum: The endpoint received from
1479 * @was_setup: Set if processing a SetupDone event.
1481 * The RXFIFO has delivered an OutDone event, which means that the data
1482 * transfer for an OUT endpoint has been completed, either by a short
1483 * packet or by the finish of a transfer.
1485 static void s3c_hsotg_handle_outdone(struct s3c_hsotg *hsotg,
1486 int epnum, bool was_setup)
1488 u32 epsize = readl(hsotg->regs + S3C_DOEPTSIZ(epnum));
1489 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[epnum];
1490 struct s3c_hsotg_req *hs_req = hs_ep->req;
1491 struct usb_request *req = &hs_req->req;
1492 unsigned size_left = S3C_DxEPTSIZ_XferSize_GET(epsize);
1496 dev_dbg(hsotg->dev, "%s: no request active\n", __func__);
1500 if (using_dma(hsotg)) {
1503 /* Calculate the size of the transfer by checking how much
1504 * is left in the endpoint size register and then working it
1505 * out from the amount we loaded for the transfer.
1507 * We need to do this as DMA pointers are always 32bit aligned
1508 * so may overshoot/undershoot the transfer.
1511 size_done = hs_ep->size_loaded - size_left;
1512 size_done += hs_ep->last_load;
1514 req->actual = size_done;
1517 /* if there is more request to do, schedule new transfer */
1518 if (req->actual < req->length && size_left == 0) {
1519 s3c_hsotg_start_req(hsotg, hs_ep, hs_req, true);
1523 if (req->actual < req->length && req->short_not_ok) {
1524 dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",
1525 __func__, req->actual, req->length);
1527 /* todo - what should we return here? there's no one else
1528 * even bothering to check the status. */
1532 if (!was_setup && req->complete != s3c_hsotg_complete_setup)
1533 s3c_hsotg_send_zlp(hsotg, hs_req);
1536 s3c_hsotg_complete_request_lock(hsotg, hs_ep, hs_req, result);
1540 * s3c_hsotg_read_frameno - read current frame number
1541 * @hsotg: The device instance
1543 * Return the current frame number
1545 static u32 s3c_hsotg_read_frameno(struct s3c_hsotg *hsotg)
1549 dsts = readl(hsotg->regs + S3C_DSTS);
1550 dsts &= S3C_DSTS_SOFFN_MASK;
1551 dsts >>= S3C_DSTS_SOFFN_SHIFT;
1557 * s3c_hsotg_handle_rx - RX FIFO has data
1558 * @hsotg: The device instance
1560 * The IRQ handler has detected that the RX FIFO has some data in it
1561 * that requires processing, so find out what is in there and do the
1564 * The RXFIFO is a true FIFO, the packets coming out are still in packet
1565 * chunks, so if you have x packets received on an endpoint you'll get x
1566 * FIFO events delivered, each with a packet's worth of data in it.
1568 * When using DMA, we should not be processing events from the RXFIFO
1569 * as the actual data should be sent to the memory directly and we turn
1570 * on the completion interrupts to get notifications of transfer completion.
1572 static void s3c_hsotg_handle_rx(struct s3c_hsotg *hsotg)
1574 u32 grxstsr = readl(hsotg->regs + S3C_GRXSTSP);
1575 u32 epnum, status, size;
1577 WARN_ON(using_dma(hsotg));
1579 epnum = grxstsr & S3C_GRXSTS_EPNum_MASK;
1580 status = grxstsr & S3C_GRXSTS_PktSts_MASK;
1582 size = grxstsr & S3C_GRXSTS_ByteCnt_MASK;
1583 size >>= S3C_GRXSTS_ByteCnt_SHIFT;
1586 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
1587 __func__, grxstsr, size, epnum);
1589 #define __status(x) ((x) >> S3C_GRXSTS_PktSts_SHIFT)
1591 switch (status >> S3C_GRXSTS_PktSts_SHIFT) {
1592 case __status(S3C_GRXSTS_PktSts_GlobalOutNAK):
1593 dev_dbg(hsotg->dev, "GlobalOutNAK\n");
1596 case __status(S3C_GRXSTS_PktSts_OutDone):
1597 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
1598 s3c_hsotg_read_frameno(hsotg));
1600 if (!using_dma(hsotg))
1601 s3c_hsotg_handle_outdone(hsotg, epnum, false);
1604 case __status(S3C_GRXSTS_PktSts_SetupDone):
1606 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1607 s3c_hsotg_read_frameno(hsotg),
1608 readl(hsotg->regs + S3C_DOEPCTL(0)));
1610 s3c_hsotg_handle_outdone(hsotg, epnum, true);
1613 case __status(S3C_GRXSTS_PktSts_OutRX):
1614 s3c_hsotg_rx_data(hsotg, epnum, size);
1617 case __status(S3C_GRXSTS_PktSts_SetupRX):
1619 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1620 s3c_hsotg_read_frameno(hsotg),
1621 readl(hsotg->regs + S3C_DOEPCTL(0)));
1623 s3c_hsotg_rx_data(hsotg, epnum, size);
1627 dev_warn(hsotg->dev, "%s: unknown status %08x\n",
1630 s3c_hsotg_dump(hsotg);
1636 * s3c_hsotg_ep0_mps - turn max packet size into register setting
1637 * @mps: The maximum packet size in bytes.
1639 static u32 s3c_hsotg_ep0_mps(unsigned int mps)
1643 return S3C_D0EPCTL_MPS_64;
1645 return S3C_D0EPCTL_MPS_32;
1647 return S3C_D0EPCTL_MPS_16;
1649 return S3C_D0EPCTL_MPS_8;
1652 /* bad max packet size, warn and return invalid result */
1658 * s3c_hsotg_set_ep_maxpacket - set endpoint's max-packet field
1659 * @hsotg: The driver state.
1660 * @ep: The index number of the endpoint
1661 * @mps: The maximum packet size in bytes
1663 * Configure the maximum packet size for the given endpoint, updating
1664 * the hardware control registers to reflect this.
1666 static void s3c_hsotg_set_ep_maxpacket(struct s3c_hsotg *hsotg,
1667 unsigned int ep, unsigned int mps)
1669 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[ep];
1670 void __iomem *regs = hsotg->regs;
1675 /* EP0 is a special case */
1676 mpsval = s3c_hsotg_ep0_mps(mps);
1680 if (mps >= S3C_DxEPCTL_MPS_LIMIT+1)
1686 hs_ep->ep.maxpacket = mps;
1688 /* update both the in and out endpoint controldir_ registers, even
1689 * if one of the directions may not be in use. */
1691 reg = readl(regs + S3C_DIEPCTL(ep));
1692 reg &= ~S3C_DxEPCTL_MPS_MASK;
1694 writel(reg, regs + S3C_DIEPCTL(ep));
1697 reg = readl(regs + S3C_DOEPCTL(ep));
1698 reg &= ~S3C_DxEPCTL_MPS_MASK;
1700 writel(reg, regs + S3C_DOEPCTL(ep));
1706 dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps);
1710 * s3c_hsotg_txfifo_flush - flush Tx FIFO
1711 * @hsotg: The driver state
1712 * @idx: The index for the endpoint (0..15)
1714 static void s3c_hsotg_txfifo_flush(struct s3c_hsotg *hsotg, unsigned int idx)
1719 writel(S3C_GRSTCTL_TxFNum(idx) | S3C_GRSTCTL_TxFFlsh,
1720 hsotg->regs + S3C_GRSTCTL);
1722 /* wait until the fifo is flushed */
1726 val = readl(hsotg->regs + S3C_GRSTCTL);
1728 if ((val & (S3C_GRSTCTL_TxFFlsh)) == 0)
1731 if (--timeout == 0) {
1733 "%s: timeout flushing fifo (GRSTCTL=%08x)\n",
1742 * s3c_hsotg_trytx - check to see if anything needs transmitting
1743 * @hsotg: The driver state
1744 * @hs_ep: The driver endpoint to check.
1746 * Check to see if there is a request that has data to send, and if so
1747 * make an attempt to write data into the FIFO.
1749 static int s3c_hsotg_trytx(struct s3c_hsotg *hsotg,
1750 struct s3c_hsotg_ep *hs_ep)
1752 struct s3c_hsotg_req *hs_req = hs_ep->req;
1754 if (!hs_ep->dir_in || !hs_req)
1757 if (hs_req->req.actual < hs_req->req.length) {
1758 dev_dbg(hsotg->dev, "trying to write more for ep%d\n",
1760 return s3c_hsotg_write_fifo(hsotg, hs_ep, hs_req);
1767 * s3c_hsotg_complete_in - complete IN transfer
1768 * @hsotg: The device state.
1769 * @hs_ep: The endpoint that has just completed.
1771 * An IN transfer has been completed, update the transfer's state and then
1772 * call the relevant completion routines.
1774 static void s3c_hsotg_complete_in(struct s3c_hsotg *hsotg,
1775 struct s3c_hsotg_ep *hs_ep)
1777 struct s3c_hsotg_req *hs_req = hs_ep->req;
1778 u32 epsize = readl(hsotg->regs + S3C_DIEPTSIZ(hs_ep->index));
1779 int size_left, size_done;
1782 dev_dbg(hsotg->dev, "XferCompl but no req\n");
1786 /* Calculate the size of the transfer by checking how much is left
1787 * in the endpoint size register and then working it out from
1788 * the amount we loaded for the transfer.
1790 * We do this even for DMA, as the transfer may have incremented
1791 * past the end of the buffer (DMA transfers are always 32bit
1795 size_left = S3C_DxEPTSIZ_XferSize_GET(epsize);
1797 size_done = hs_ep->size_loaded - size_left;
1798 size_done += hs_ep->last_load;
1800 if (hs_req->req.actual != size_done)
1801 dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n",
1802 __func__, hs_req->req.actual, size_done);
1804 hs_req->req.actual = size_done;
1806 /* if we did all of the transfer, and there is more data left
1807 * around, then try restarting the rest of the request */
1809 if (!size_left && hs_req->req.actual < hs_req->req.length) {
1810 dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__);
1811 s3c_hsotg_start_req(hsotg, hs_ep, hs_req, true);
1813 s3c_hsotg_complete_request_lock(hsotg, hs_ep, hs_req, 0);
1817 * s3c_hsotg_epint - handle an in/out endpoint interrupt
1818 * @hsotg: The driver state
1819 * @idx: The index for the endpoint (0..15)
1820 * @dir_in: Set if this is an IN endpoint
1822 * Process and clear any interrupt pending for an individual endpoint
1824 static void s3c_hsotg_epint(struct s3c_hsotg *hsotg, unsigned int idx,
1827 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[idx];
1828 u32 epint_reg = dir_in ? S3C_DIEPINT(idx) : S3C_DOEPINT(idx);
1829 u32 epctl_reg = dir_in ? S3C_DIEPCTL(idx) : S3C_DOEPCTL(idx);
1830 u32 epsiz_reg = dir_in ? S3C_DIEPTSIZ(idx) : S3C_DOEPTSIZ(idx);
1833 ints = readl(hsotg->regs + epint_reg);
1835 /* Clear endpoint interrupts */
1836 writel(ints, hsotg->regs + epint_reg);
1838 dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
1839 __func__, idx, dir_in ? "in" : "out", ints);
1841 if (ints & S3C_DxEPINT_XferCompl) {
1843 "%s: XferCompl: DxEPCTL=0x%08x, DxEPTSIZ=%08x\n",
1844 __func__, readl(hsotg->regs + epctl_reg),
1845 readl(hsotg->regs + epsiz_reg));
1847 /* we get OutDone from the FIFO, so we only need to look
1848 * at completing IN requests here */
1850 s3c_hsotg_complete_in(hsotg, hs_ep);
1852 if (idx == 0 && !hs_ep->req)
1853 s3c_hsotg_enqueue_setup(hsotg);
1854 } else if (using_dma(hsotg)) {
1855 /* We're using DMA, we need to fire an OutDone here
1856 * as we ignore the RXFIFO. */
1858 s3c_hsotg_handle_outdone(hsotg, idx, false);
1862 if (ints & S3C_DxEPINT_EPDisbld) {
1863 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
1866 int epctl = readl(hsotg->regs + epctl_reg);
1868 s3c_hsotg_txfifo_flush(hsotg, idx);
1870 if ((epctl & S3C_DxEPCTL_Stall) &&
1871 (epctl & S3C_DxEPCTL_EPType_Bulk)) {
1872 int dctl = readl(hsotg->regs + S3C_DCTL);
1874 dctl |= S3C_DCTL_CGNPInNAK;
1875 writel(dctl, hsotg->regs + S3C_DCTL);
1880 if (ints & S3C_DxEPINT_AHBErr)
1881 dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
1883 if (ints & S3C_DxEPINT_Setup) { /* Setup or Timeout */
1884 dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__);
1886 if (using_dma(hsotg) && idx == 0) {
1887 /* this is the notification we've received a
1888 * setup packet. In non-DMA mode we'd get this
1889 * from the RXFIFO, instead we need to process
1890 * the setup here. */
1895 s3c_hsotg_handle_outdone(hsotg, 0, true);
1899 if (ints & S3C_DxEPINT_Back2BackSetup)
1900 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
1903 /* not sure if this is important, but we'll clear it anyway
1905 if (ints & S3C_DIEPMSK_INTknTXFEmpMsk) {
1906 dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
1910 /* this probably means something bad is happening */
1911 if (ints & S3C_DIEPMSK_INTknEPMisMsk) {
1912 dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
1916 /* FIFO has space or is empty (see GAHBCFG) */
1917 if (hsotg->dedicated_fifos &&
1918 ints & S3C_DIEPMSK_TxFIFOEmpty) {
1919 dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n",
1921 if (!using_dma(hsotg))
1922 s3c_hsotg_trytx(hsotg, hs_ep);
1928 * s3c_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
1929 * @hsotg: The device state.
1931 * Handle updating the device settings after the enumeration phase has
1934 static void s3c_hsotg_irq_enumdone(struct s3c_hsotg *hsotg)
1936 u32 dsts = readl(hsotg->regs + S3C_DSTS);
1937 int ep0_mps = 0, ep_mps;
1939 /* This should signal the finish of the enumeration phase
1940 * of the USB handshaking, so we should now know what rate
1941 * we connected at. */
1943 dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts);
1945 /* note, since we're limited by the size of transfer on EP0, and
1946 * it seems IN transfers must be a even number of packets we do
1947 * not advertise a 64byte MPS on EP0. */
1949 /* catch both EnumSpd_FS and EnumSpd_FS48 */
1950 switch (dsts & S3C_DSTS_EnumSpd_MASK) {
1951 case S3C_DSTS_EnumSpd_FS:
1952 case S3C_DSTS_EnumSpd_FS48:
1953 hsotg->gadget.speed = USB_SPEED_FULL;
1954 ep0_mps = EP0_MPS_LIMIT;
1958 case S3C_DSTS_EnumSpd_HS:
1959 hsotg->gadget.speed = USB_SPEED_HIGH;
1960 ep0_mps = EP0_MPS_LIMIT;
1964 case S3C_DSTS_EnumSpd_LS:
1965 hsotg->gadget.speed = USB_SPEED_LOW;
1966 /* note, we don't actually support LS in this driver at the
1967 * moment, and the documentation seems to imply that it isn't
1968 * supported by the PHYs on some of the devices.
1972 dev_info(hsotg->dev, "new device is %s\n",
1973 usb_speed_string(hsotg->gadget.speed));
1975 /* we should now know the maximum packet size for an
1976 * endpoint, so set the endpoints to a default value. */
1980 s3c_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps);
1981 for (i = 1; i < S3C_HSOTG_EPS; i++)
1982 s3c_hsotg_set_ep_maxpacket(hsotg, i, ep_mps);
1985 /* ensure after enumeration our EP0 is active */
1987 s3c_hsotg_enqueue_setup(hsotg);
1989 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
1990 readl(hsotg->regs + S3C_DIEPCTL0),
1991 readl(hsotg->regs + S3C_DOEPCTL0));
1995 * kill_all_requests - remove all requests from the endpoint's queue
1996 * @hsotg: The device state.
1997 * @ep: The endpoint the requests may be on.
1998 * @result: The result code to use.
1999 * @force: Force removal of any current requests
2001 * Go through the requests on the given endpoint and mark them
2002 * completed with the given result code.
2004 static void kill_all_requests(struct s3c_hsotg *hsotg,
2005 struct s3c_hsotg_ep *ep,
2006 int result, bool force)
2008 struct s3c_hsotg_req *req, *treq;
2009 unsigned long flags;
2011 spin_lock_irqsave(&ep->lock, flags);
2013 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
2014 /* currently, we can't do much about an already
2015 * running request on an in endpoint */
2017 if (ep->req == req && ep->dir_in && !force)
2020 s3c_hsotg_complete_request(hsotg, ep, req,
2024 spin_unlock_irqrestore(&ep->lock, flags);
2027 #define call_gadget(_hs, _entry) \
2028 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \
2029 (_hs)->driver && (_hs)->driver->_entry) \
2030 (_hs)->driver->_entry(&(_hs)->gadget);
2033 * s3c_hsotg_disconnect_irq - disconnect irq service
2034 * @hsotg: The device state.
2036 * A disconnect IRQ has been received, meaning that the host has
2037 * lost contact with the bus. Remove all current transactions
2038 * and signal the gadget driver that this has happened.
2040 static void s3c_hsotg_disconnect_irq(struct s3c_hsotg *hsotg)
2044 for (ep = 0; ep < S3C_HSOTG_EPS; ep++)
2045 kill_all_requests(hsotg, &hsotg->eps[ep], -ESHUTDOWN, true);
2047 call_gadget(hsotg, disconnect);
2051 * s3c_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
2052 * @hsotg: The device state:
2053 * @periodic: True if this is a periodic FIFO interrupt
2055 static void s3c_hsotg_irq_fifoempty(struct s3c_hsotg *hsotg, bool periodic)
2057 struct s3c_hsotg_ep *ep;
2060 /* look through for any more data to transmit */
2062 for (epno = 0; epno < S3C_HSOTG_EPS; epno++) {
2063 ep = &hsotg->eps[epno];
2068 if ((periodic && !ep->periodic) ||
2069 (!periodic && ep->periodic))
2072 ret = s3c_hsotg_trytx(hsotg, ep);
2078 static struct s3c_hsotg *our_hsotg;
2080 /* IRQ flags which will trigger a retry around the IRQ loop */
2081 #define IRQ_RETRY_MASK (S3C_GINTSTS_NPTxFEmp | \
2082 S3C_GINTSTS_PTxFEmp | \
2086 * s3c_hsotg_irq - handle device interrupt
2087 * @irq: The IRQ number triggered
2088 * @pw: The pw value when registered the handler.
2090 static irqreturn_t s3c_hsotg_irq(int irq, void *pw)
2092 struct s3c_hsotg *hsotg = pw;
2093 int retry_count = 8;
2098 gintsts = readl(hsotg->regs + S3C_GINTSTS);
2099 gintmsk = readl(hsotg->regs + S3C_GINTMSK);
2101 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
2102 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
2106 if (gintsts & S3C_GINTSTS_OTGInt) {
2107 u32 otgint = readl(hsotg->regs + S3C_GOTGINT);
2109 dev_info(hsotg->dev, "OTGInt: %08x\n", otgint);
2111 writel(otgint, hsotg->regs + S3C_GOTGINT);
2114 if (gintsts & S3C_GINTSTS_DisconnInt) {
2115 dev_dbg(hsotg->dev, "%s: DisconnInt\n", __func__);
2116 writel(S3C_GINTSTS_DisconnInt, hsotg->regs + S3C_GINTSTS);
2118 s3c_hsotg_disconnect_irq(hsotg);
2121 if (gintsts & S3C_GINTSTS_SessReqInt) {
2122 dev_dbg(hsotg->dev, "%s: SessReqInt\n", __func__);
2123 writel(S3C_GINTSTS_SessReqInt, hsotg->regs + S3C_GINTSTS);
2126 if (gintsts & S3C_GINTSTS_EnumDone) {
2127 writel(S3C_GINTSTS_EnumDone, hsotg->regs + S3C_GINTSTS);
2129 s3c_hsotg_irq_enumdone(hsotg);
2132 if (gintsts & S3C_GINTSTS_ConIDStsChng) {
2133 dev_dbg(hsotg->dev, "ConIDStsChg (DSTS=0x%08x, GOTCTL=%08x)\n",
2134 readl(hsotg->regs + S3C_DSTS),
2135 readl(hsotg->regs + S3C_GOTGCTL));
2137 writel(S3C_GINTSTS_ConIDStsChng, hsotg->regs + S3C_GINTSTS);
2140 if (gintsts & (S3C_GINTSTS_OEPInt | S3C_GINTSTS_IEPInt)) {
2141 u32 daint = readl(hsotg->regs + S3C_DAINT);
2142 u32 daint_out = daint >> S3C_DAINT_OutEP_SHIFT;
2143 u32 daint_in = daint & ~(daint_out << S3C_DAINT_OutEP_SHIFT);
2146 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
2148 for (ep = 0; ep < 15 && daint_out; ep++, daint_out >>= 1) {
2150 s3c_hsotg_epint(hsotg, ep, 0);
2153 for (ep = 0; ep < 15 && daint_in; ep++, daint_in >>= 1) {
2155 s3c_hsotg_epint(hsotg, ep, 1);
2159 if (gintsts & S3C_GINTSTS_USBRst) {
2160 dev_info(hsotg->dev, "%s: USBRst\n", __func__);
2161 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
2162 readl(hsotg->regs + S3C_GNPTXSTS));
2164 writel(S3C_GINTSTS_USBRst, hsotg->regs + S3C_GINTSTS);
2166 kill_all_requests(hsotg, &hsotg->eps[0], -ECONNRESET, true);
2168 /* it seems after a reset we can end up with a situation
2169 * where the TXFIFO still has data in it... the docs
2170 * suggest resetting all the fifos, so use the init_fifo
2171 * code to relayout and flush the fifos.
2174 s3c_hsotg_init_fifo(hsotg);
2176 s3c_hsotg_enqueue_setup(hsotg);
2179 /* check both FIFOs */
2181 if (gintsts & S3C_GINTSTS_NPTxFEmp) {
2182 dev_dbg(hsotg->dev, "NPTxFEmp\n");
2184 /* Disable the interrupt to stop it happening again
2185 * unless one of these endpoint routines decides that
2186 * it needs re-enabling */
2188 s3c_hsotg_disable_gsint(hsotg, S3C_GINTSTS_NPTxFEmp);
2189 s3c_hsotg_irq_fifoempty(hsotg, false);
2192 if (gintsts & S3C_GINTSTS_PTxFEmp) {
2193 dev_dbg(hsotg->dev, "PTxFEmp\n");
2195 /* See note in S3C_GINTSTS_NPTxFEmp */
2197 s3c_hsotg_disable_gsint(hsotg, S3C_GINTSTS_PTxFEmp);
2198 s3c_hsotg_irq_fifoempty(hsotg, true);
2201 if (gintsts & S3C_GINTSTS_RxFLvl) {
2202 /* note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
2203 * we need to retry s3c_hsotg_handle_rx if this is still
2206 s3c_hsotg_handle_rx(hsotg);
2209 if (gintsts & S3C_GINTSTS_ModeMis) {
2210 dev_warn(hsotg->dev, "warning, mode mismatch triggered\n");
2211 writel(S3C_GINTSTS_ModeMis, hsotg->regs + S3C_GINTSTS);
2214 if (gintsts & S3C_GINTSTS_USBSusp) {
2215 dev_info(hsotg->dev, "S3C_GINTSTS_USBSusp\n");
2216 writel(S3C_GINTSTS_USBSusp, hsotg->regs + S3C_GINTSTS);
2218 call_gadget(hsotg, suspend);
2221 if (gintsts & S3C_GINTSTS_WkUpInt) {
2222 dev_info(hsotg->dev, "S3C_GINTSTS_WkUpIn\n");
2223 writel(S3C_GINTSTS_WkUpInt, hsotg->regs + S3C_GINTSTS);
2225 call_gadget(hsotg, resume);
2228 if (gintsts & S3C_GINTSTS_ErlySusp) {
2229 dev_dbg(hsotg->dev, "S3C_GINTSTS_ErlySusp\n");
2230 writel(S3C_GINTSTS_ErlySusp, hsotg->regs + S3C_GINTSTS);
2233 /* these next two seem to crop-up occasionally causing the core
2234 * to shutdown the USB transfer, so try clearing them and logging
2235 * the occurrence. */
2237 if (gintsts & S3C_GINTSTS_GOUTNakEff) {
2238 dev_info(hsotg->dev, "GOUTNakEff triggered\n");
2240 writel(S3C_DCTL_CGOUTNak, hsotg->regs + S3C_DCTL);
2242 s3c_hsotg_dump(hsotg);
2245 if (gintsts & S3C_GINTSTS_GINNakEff) {
2246 dev_info(hsotg->dev, "GINNakEff triggered\n");
2248 writel(S3C_DCTL_CGNPInNAK, hsotg->regs + S3C_DCTL);
2250 s3c_hsotg_dump(hsotg);
2253 /* if we've had fifo events, we should try and go around the
2254 * loop again to see if there's any point in returning yet. */
2256 if (gintsts & IRQ_RETRY_MASK && --retry_count > 0)
2263 * s3c_hsotg_ep_enable - enable the given endpoint
2264 * @ep: The USB endpint to configure
2265 * @desc: The USB endpoint descriptor to configure with.
2267 * This is called from the USB gadget code's usb_ep_enable().
2269 static int s3c_hsotg_ep_enable(struct usb_ep *ep,
2270 const struct usb_endpoint_descriptor *desc)
2272 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2273 struct s3c_hsotg *hsotg = hs_ep->parent;
2274 unsigned long flags;
2275 int index = hs_ep->index;
2283 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
2284 __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes,
2285 desc->wMaxPacketSize, desc->bInterval);
2287 /* not to be called for EP0 */
2288 WARN_ON(index == 0);
2290 dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
2291 if (dir_in != hs_ep->dir_in) {
2292 dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__);
2296 mps = usb_endpoint_maxp(desc);
2298 /* note, we handle this here instead of s3c_hsotg_set_ep_maxpacket */
2300 epctrl_reg = dir_in ? S3C_DIEPCTL(index) : S3C_DOEPCTL(index);
2301 epctrl = readl(hsotg->regs + epctrl_reg);
2303 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
2304 __func__, epctrl, epctrl_reg);
2306 spin_lock_irqsave(&hs_ep->lock, flags);
2308 epctrl &= ~(S3C_DxEPCTL_EPType_MASK | S3C_DxEPCTL_MPS_MASK);
2309 epctrl |= S3C_DxEPCTL_MPS(mps);
2311 /* mark the endpoint as active, otherwise the core may ignore
2312 * transactions entirely for this endpoint */
2313 epctrl |= S3C_DxEPCTL_USBActEp;
2315 /* set the NAK status on the endpoint, otherwise we might try and
2316 * do something with data that we've yet got a request to process
2317 * since the RXFIFO will take data for an endpoint even if the
2318 * size register hasn't been set.
2321 epctrl |= S3C_DxEPCTL_SNAK;
2323 /* update the endpoint state */
2324 hs_ep->ep.maxpacket = mps;
2326 /* default, set to non-periodic */
2327 hs_ep->periodic = 0;
2329 switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
2330 case USB_ENDPOINT_XFER_ISOC:
2331 dev_err(hsotg->dev, "no current ISOC support\n");
2335 case USB_ENDPOINT_XFER_BULK:
2336 epctrl |= S3C_DxEPCTL_EPType_Bulk;
2339 case USB_ENDPOINT_XFER_INT:
2341 /* Allocate our TxFNum by simply using the index
2342 * of the endpoint for the moment. We could do
2343 * something better if the host indicates how
2344 * many FIFOs we are expecting to use. */
2346 hs_ep->periodic = 1;
2347 epctrl |= S3C_DxEPCTL_TxFNum(index);
2350 epctrl |= S3C_DxEPCTL_EPType_Intterupt;
2353 case USB_ENDPOINT_XFER_CONTROL:
2354 epctrl |= S3C_DxEPCTL_EPType_Control;
2358 /* if the hardware has dedicated fifos, we must give each IN EP
2359 * a unique tx-fifo even if it is non-periodic.
2361 if (dir_in && hsotg->dedicated_fifos)
2362 epctrl |= S3C_DxEPCTL_TxFNum(index);
2364 /* for non control endpoints, set PID to D0 */
2366 epctrl |= S3C_DxEPCTL_SetD0PID;
2368 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
2371 writel(epctrl, hsotg->regs + epctrl_reg);
2372 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
2373 __func__, readl(hsotg->regs + epctrl_reg));
2375 /* enable the endpoint interrupt */
2376 s3c_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
2379 spin_unlock_irqrestore(&hs_ep->lock, flags);
2383 static int s3c_hsotg_ep_disable(struct usb_ep *ep)
2385 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2386 struct s3c_hsotg *hsotg = hs_ep->parent;
2387 int dir_in = hs_ep->dir_in;
2388 int index = hs_ep->index;
2389 unsigned long flags;
2393 dev_info(hsotg->dev, "%s(ep %p)\n", __func__, ep);
2395 if (ep == &hsotg->eps[0].ep) {
2396 dev_err(hsotg->dev, "%s: called for ep0\n", __func__);
2400 epctrl_reg = dir_in ? S3C_DIEPCTL(index) : S3C_DOEPCTL(index);
2402 /* terminate all requests with shutdown */
2403 kill_all_requests(hsotg, hs_ep, -ESHUTDOWN, false);
2405 spin_lock_irqsave(&hs_ep->lock, flags);
2407 ctrl = readl(hsotg->regs + epctrl_reg);
2408 ctrl &= ~S3C_DxEPCTL_EPEna;
2409 ctrl &= ~S3C_DxEPCTL_USBActEp;
2410 ctrl |= S3C_DxEPCTL_SNAK;
2412 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
2413 writel(ctrl, hsotg->regs + epctrl_reg);
2415 /* disable endpoint interrupts */
2416 s3c_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
2418 spin_unlock_irqrestore(&hs_ep->lock, flags);
2423 * on_list - check request is on the given endpoint
2424 * @ep: The endpoint to check.
2425 * @test: The request to test if it is on the endpoint.
2427 static bool on_list(struct s3c_hsotg_ep *ep, struct s3c_hsotg_req *test)
2429 struct s3c_hsotg_req *req, *treq;
2431 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
2439 static int s3c_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
2441 struct s3c_hsotg_req *hs_req = our_req(req);
2442 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2443 struct s3c_hsotg *hs = hs_ep->parent;
2444 unsigned long flags;
2446 dev_info(hs->dev, "ep_dequeue(%p,%p)\n", ep, req);
2448 spin_lock_irqsave(&hs_ep->lock, flags);
2450 if (!on_list(hs_ep, hs_req)) {
2451 spin_unlock_irqrestore(&hs_ep->lock, flags);
2455 s3c_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET);
2456 spin_unlock_irqrestore(&hs_ep->lock, flags);
2461 static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value)
2463 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2464 struct s3c_hsotg *hs = hs_ep->parent;
2465 int index = hs_ep->index;
2466 unsigned long irqflags;
2471 dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value);
2473 spin_lock_irqsave(&hs_ep->lock, irqflags);
2475 /* write both IN and OUT control registers */
2477 epreg = S3C_DIEPCTL(index);
2478 epctl = readl(hs->regs + epreg);
2481 epctl |= S3C_DxEPCTL_Stall + S3C_DxEPCTL_SNAK;
2482 if (epctl & S3C_DxEPCTL_EPEna)
2483 epctl |= S3C_DxEPCTL_EPDis;
2485 epctl &= ~S3C_DxEPCTL_Stall;
2486 xfertype = epctl & S3C_DxEPCTL_EPType_MASK;
2487 if (xfertype == S3C_DxEPCTL_EPType_Bulk ||
2488 xfertype == S3C_DxEPCTL_EPType_Intterupt)
2489 epctl |= S3C_DxEPCTL_SetD0PID;
2492 writel(epctl, hs->regs + epreg);
2494 epreg = S3C_DOEPCTL(index);
2495 epctl = readl(hs->regs + epreg);
2498 epctl |= S3C_DxEPCTL_Stall;
2500 epctl &= ~S3C_DxEPCTL_Stall;
2501 xfertype = epctl & S3C_DxEPCTL_EPType_MASK;
2502 if (xfertype == S3C_DxEPCTL_EPType_Bulk ||
2503 xfertype == S3C_DxEPCTL_EPType_Intterupt)
2504 epctl |= S3C_DxEPCTL_SetD0PID;
2507 writel(epctl, hs->regs + epreg);
2509 spin_unlock_irqrestore(&hs_ep->lock, irqflags);
2514 static struct usb_ep_ops s3c_hsotg_ep_ops = {
2515 .enable = s3c_hsotg_ep_enable,
2516 .disable = s3c_hsotg_ep_disable,
2517 .alloc_request = s3c_hsotg_ep_alloc_request,
2518 .free_request = s3c_hsotg_ep_free_request,
2519 .queue = s3c_hsotg_ep_queue,
2520 .dequeue = s3c_hsotg_ep_dequeue,
2521 .set_halt = s3c_hsotg_ep_sethalt,
2522 /* note, don't believe we have any call for the fifo routines */
2526 * s3c_hsotg_corereset - issue softreset to the core
2527 * @hsotg: The device state
2529 * Issue a soft reset to the core, and await the core finishing it.
2531 static int s3c_hsotg_corereset(struct s3c_hsotg *hsotg)
2536 dev_dbg(hsotg->dev, "resetting core\n");
2538 /* issue soft reset */
2539 writel(S3C_GRSTCTL_CSftRst, hsotg->regs + S3C_GRSTCTL);
2543 grstctl = readl(hsotg->regs + S3C_GRSTCTL);
2544 } while ((grstctl & S3C_GRSTCTL_CSftRst) && timeout-- > 0);
2546 if (grstctl & S3C_GRSTCTL_CSftRst) {
2547 dev_err(hsotg->dev, "Failed to get CSftRst asserted\n");
2554 u32 grstctl = readl(hsotg->regs + S3C_GRSTCTL);
2556 if (timeout-- < 0) {
2557 dev_info(hsotg->dev,
2558 "%s: reset failed, GRSTCTL=%08x\n",
2563 if (!(grstctl & S3C_GRSTCTL_AHBIdle))
2566 break; /* reset done */
2569 dev_dbg(hsotg->dev, "reset successful\n");
2574 * s3c_hsotg_phy_enable - enable platform phy dev
2576 * @param: The driver state
2578 * A wrapper for platform code responsible for controlling
2579 * low-level USB code
2581 static void s3c_hsotg_phy_enable(struct s3c_hsotg *hsotg)
2583 struct platform_device *pdev = to_platform_device(hsotg->dev);
2585 dev_dbg(hsotg->dev, "pdev 0x%p\n", pdev);
2586 if (hsotg->plat->phy_init)
2587 hsotg->plat->phy_init(pdev, hsotg->plat->phy_type);
2591 * s3c_hsotg_phy_disable - disable platform phy dev
2593 * @param: The driver state
2595 * A wrapper for platform code responsible for controlling
2596 * low-level USB code
2598 static void s3c_hsotg_phy_disable(struct s3c_hsotg *hsotg)
2600 struct platform_device *pdev = to_platform_device(hsotg->dev);
2602 if (hsotg->plat->phy_exit)
2603 hsotg->plat->phy_exit(pdev, hsotg->plat->phy_type);
2606 static int s3c_hsotg_start(struct usb_gadget_driver *driver,
2607 int (*bind)(struct usb_gadget *))
2609 struct s3c_hsotg *hsotg = our_hsotg;
2613 printk(KERN_ERR "%s: called with no device\n", __func__);
2618 dev_err(hsotg->dev, "%s: no driver\n", __func__);
2622 if (driver->max_speed < USB_SPEED_FULL)
2623 dev_err(hsotg->dev, "%s: bad speed\n", __func__);
2625 if (!bind || !driver->setup) {
2626 dev_err(hsotg->dev, "%s: missing entry points\n", __func__);
2630 WARN_ON(hsotg->driver);
2632 driver->driver.bus = NULL;
2633 hsotg->driver = driver;
2634 hsotg->gadget.dev.driver = &driver->driver;
2635 hsotg->gadget.dev.dma_mask = hsotg->dev->dma_mask;
2636 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
2638 ret = device_add(&hsotg->gadget.dev);
2640 dev_err(hsotg->dev, "failed to register gadget device\n");
2644 ret = bind(&hsotg->gadget);
2646 dev_err(hsotg->dev, "failed bind %s\n", driver->driver.name);
2648 hsotg->gadget.dev.driver = NULL;
2649 hsotg->driver = NULL;
2653 /* we must now enable ep0 ready for host detection and then
2654 * set configuration. */
2656 s3c_hsotg_corereset(hsotg);
2658 /* set the PLL on, remove the HNP/SRP and set the PHY */
2659 writel(S3C_GUSBCFG_PHYIf16 | S3C_GUSBCFG_TOutCal(7) |
2660 (0x5 << 10), hsotg->regs + S3C_GUSBCFG);
2662 /* looks like soft-reset changes state of FIFOs */
2663 s3c_hsotg_init_fifo(hsotg);
2665 __orr32(hsotg->regs + S3C_DCTL, S3C_DCTL_SftDiscon);
2667 writel(1 << 18 | S3C_DCFG_DevSpd_HS, hsotg->regs + S3C_DCFG);
2669 /* Clear any pending OTG interrupts */
2670 writel(0xffffffff, hsotg->regs + S3C_GOTGINT);
2672 /* Clear any pending interrupts */
2673 writel(0xffffffff, hsotg->regs + S3C_GINTSTS);
2675 writel(S3C_GINTSTS_DisconnInt | S3C_GINTSTS_SessReqInt |
2676 S3C_GINTSTS_ConIDStsChng | S3C_GINTSTS_USBRst |
2677 S3C_GINTSTS_EnumDone | S3C_GINTSTS_OTGInt |
2678 S3C_GINTSTS_USBSusp | S3C_GINTSTS_WkUpInt |
2679 S3C_GINTSTS_GOUTNakEff | S3C_GINTSTS_GINNakEff |
2680 S3C_GINTSTS_ErlySusp,
2681 hsotg->regs + S3C_GINTMSK);
2683 if (using_dma(hsotg))
2684 writel(S3C_GAHBCFG_GlblIntrEn | S3C_GAHBCFG_DMAEn |
2685 S3C_GAHBCFG_HBstLen_Incr4,
2686 hsotg->regs + S3C_GAHBCFG);
2688 writel(S3C_GAHBCFG_GlblIntrEn, hsotg->regs + S3C_GAHBCFG);
2690 /* Enabling INTknTXFEmpMsk here seems to be a big mistake, we end
2691 * up being flooded with interrupts if the host is polling the
2692 * endpoint to try and read data. */
2694 writel(S3C_DIEPMSK_TimeOUTMsk | S3C_DIEPMSK_AHBErrMsk |
2695 S3C_DIEPMSK_INTknEPMisMsk |
2696 S3C_DIEPMSK_EPDisbldMsk | S3C_DIEPMSK_XferComplMsk |
2697 ((hsotg->dedicated_fifos) ? S3C_DIEPMSK_TxFIFOEmpty : 0),
2698 hsotg->regs + S3C_DIEPMSK);
2700 /* don't need XferCompl, we get that from RXFIFO in slave mode. In
2701 * DMA mode we may need this. */
2702 writel(S3C_DOEPMSK_SetupMsk | S3C_DOEPMSK_AHBErrMsk |
2703 S3C_DOEPMSK_EPDisbldMsk |
2704 (using_dma(hsotg) ? (S3C_DIEPMSK_XferComplMsk |
2705 S3C_DIEPMSK_TimeOUTMsk) : 0),
2706 hsotg->regs + S3C_DOEPMSK);
2708 writel(0, hsotg->regs + S3C_DAINTMSK);
2710 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2711 readl(hsotg->regs + S3C_DIEPCTL0),
2712 readl(hsotg->regs + S3C_DOEPCTL0));
2714 /* enable in and out endpoint interrupts */
2715 s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_OEPInt | S3C_GINTSTS_IEPInt);
2717 /* Enable the RXFIFO when in slave mode, as this is how we collect
2718 * the data. In DMA mode, we get events from the FIFO but also
2719 * things we cannot process, so do not use it. */
2720 if (!using_dma(hsotg))
2721 s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_RxFLvl);
2723 /* Enable interrupts for EP0 in and out */
2724 s3c_hsotg_ctrl_epint(hsotg, 0, 0, 1);
2725 s3c_hsotg_ctrl_epint(hsotg, 0, 1, 1);
2727 __orr32(hsotg->regs + S3C_DCTL, S3C_DCTL_PWROnPrgDone);
2728 udelay(10); /* see openiboot */
2729 __bic32(hsotg->regs + S3C_DCTL, S3C_DCTL_PWROnPrgDone);
2731 dev_dbg(hsotg->dev, "DCTL=0x%08x\n", readl(hsotg->regs + S3C_DCTL));
2733 /* S3C_DxEPCTL_USBActEp says RO in manual, but seems to be set by
2734 writing to the EPCTL register.. */
2736 /* set to read 1 8byte packet */
2737 writel(S3C_DxEPTSIZ_MC(1) | S3C_DxEPTSIZ_PktCnt(1) |
2738 S3C_DxEPTSIZ_XferSize(8), hsotg->regs + DOEPTSIZ0);
2740 writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) |
2741 S3C_DxEPCTL_CNAK | S3C_DxEPCTL_EPEna |
2742 S3C_DxEPCTL_USBActEp,
2743 hsotg->regs + S3C_DOEPCTL0);
2745 /* enable, but don't activate EP0in */
2746 writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) |
2747 S3C_DxEPCTL_USBActEp, hsotg->regs + S3C_DIEPCTL0);
2749 s3c_hsotg_enqueue_setup(hsotg);
2751 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2752 readl(hsotg->regs + S3C_DIEPCTL0),
2753 readl(hsotg->regs + S3C_DOEPCTL0));
2755 /* clear global NAKs */
2756 writel(S3C_DCTL_CGOUTNak | S3C_DCTL_CGNPInNAK,
2757 hsotg->regs + S3C_DCTL);
2759 /* must be at-least 3ms to allow bus to see disconnect */
2762 /* remove the soft-disconnect and let's go */
2763 __bic32(hsotg->regs + S3C_DCTL, S3C_DCTL_SftDiscon);
2765 /* report to the user, and return */
2767 dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
2771 hsotg->driver = NULL;
2772 hsotg->gadget.dev.driver = NULL;
2776 static int s3c_hsotg_stop(struct usb_gadget_driver *driver)
2778 struct s3c_hsotg *hsotg = our_hsotg;
2784 if (!driver || driver != hsotg->driver || !driver->unbind)
2787 /* all endpoints should be shutdown */
2788 for (ep = 0; ep < S3C_HSOTG_EPS; ep++)
2789 s3c_hsotg_ep_disable(&hsotg->eps[ep].ep);
2791 call_gadget(hsotg, disconnect);
2793 driver->unbind(&hsotg->gadget);
2794 hsotg->driver = NULL;
2795 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
2797 device_del(&hsotg->gadget.dev);
2799 dev_info(hsotg->dev, "unregistered gadget driver '%s'\n",
2800 driver->driver.name);
2805 static int s3c_hsotg_gadget_getframe(struct usb_gadget *gadget)
2807 return s3c_hsotg_read_frameno(to_hsotg(gadget));
2810 static struct usb_gadget_ops s3c_hsotg_gadget_ops = {
2811 .get_frame = s3c_hsotg_gadget_getframe,
2812 .start = s3c_hsotg_start,
2813 .stop = s3c_hsotg_stop,
2817 * s3c_hsotg_initep - initialise a single endpoint
2818 * @hsotg: The device state.
2819 * @hs_ep: The endpoint to be initialised.
2820 * @epnum: The endpoint number
2822 * Initialise the given endpoint (as part of the probe and device state
2823 * creation) to give to the gadget driver. Setup the endpoint name, any
2824 * direction information and other state that may be required.
2826 static void __devinit s3c_hsotg_initep(struct s3c_hsotg *hsotg,
2827 struct s3c_hsotg_ep *hs_ep,
2835 else if ((epnum % 2) == 0) {
2842 hs_ep->index = epnum;
2844 snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir);
2846 INIT_LIST_HEAD(&hs_ep->queue);
2847 INIT_LIST_HEAD(&hs_ep->ep.ep_list);
2849 spin_lock_init(&hs_ep->lock);
2851 /* add to the list of endpoints known by the gadget driver */
2853 list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list);
2855 hs_ep->parent = hsotg;
2856 hs_ep->ep.name = hs_ep->name;
2857 hs_ep->ep.maxpacket = epnum ? 512 : EP0_MPS_LIMIT;
2858 hs_ep->ep.ops = &s3c_hsotg_ep_ops;
2860 /* Read the FIFO size for the Periodic TX FIFO, even if we're
2861 * an OUT endpoint, we may as well do this if in future the
2862 * code is changed to make each endpoint's direction changeable.
2865 ptxfifo = readl(hsotg->regs + S3C_DPTXFSIZn(epnum));
2866 hs_ep->fifo_size = S3C_DPTXFSIZn_DPTxFSize_GET(ptxfifo) * 4;
2868 /* if we're using dma, we need to set the next-endpoint pointer
2869 * to be something valid.
2872 if (using_dma(hsotg)) {
2873 u32 next = S3C_DxEPCTL_NextEp((epnum + 1) % 15);
2874 writel(next, hsotg->regs + S3C_DIEPCTL(epnum));
2875 writel(next, hsotg->regs + S3C_DOEPCTL(epnum));
2879 static void s3c_hsotg_init(struct s3c_hsotg *hsotg)
2883 /* unmask subset of endpoint interrupts */
2885 writel(S3C_DIEPMSK_TimeOUTMsk | S3C_DIEPMSK_AHBErrMsk |
2886 S3C_DIEPMSK_EPDisbldMsk | S3C_DIEPMSK_XferComplMsk,
2887 hsotg->regs + S3C_DIEPMSK);
2889 writel(S3C_DOEPMSK_SetupMsk | S3C_DOEPMSK_AHBErrMsk |
2890 S3C_DOEPMSK_EPDisbldMsk | S3C_DOEPMSK_XferComplMsk,
2891 hsotg->regs + S3C_DOEPMSK);
2893 writel(0, hsotg->regs + S3C_DAINTMSK);
2895 /* Be in disconnected state until gadget is registered */
2896 __orr32(hsotg->regs + S3C_DCTL, S3C_DCTL_SftDiscon);
2899 /* post global nak until we're ready */
2900 writel(S3C_DCTL_SGNPInNAK | S3C_DCTL_SGOUTNak,
2901 hsotg->regs + S3C_DCTL);
2906 dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
2907 readl(hsotg->regs + S3C_GRXFSIZ),
2908 readl(hsotg->regs + S3C_GNPTXFSIZ));
2910 s3c_hsotg_init_fifo(hsotg);
2912 /* set the PLL on, remove the HNP/SRP and set the PHY */
2913 writel(S3C_GUSBCFG_PHYIf16 | S3C_GUSBCFG_TOutCal(7) | (0x5 << 10),
2914 hsotg->regs + S3C_GUSBCFG);
2916 writel(using_dma(hsotg) ? S3C_GAHBCFG_DMAEn : 0x0,
2917 hsotg->regs + S3C_GAHBCFG);
2919 /* check hardware configuration */
2921 cfg4 = readl(hsotg->regs + 0x50);
2922 hsotg->dedicated_fifos = (cfg4 >> 25) & 1;
2924 dev_info(hsotg->dev, "%s fifos\n",
2925 hsotg->dedicated_fifos ? "dedicated" : "shared");
2928 static void s3c_hsotg_dump(struct s3c_hsotg *hsotg)
2931 struct device *dev = hsotg->dev;
2932 void __iomem *regs = hsotg->regs;
2936 dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
2937 readl(regs + S3C_DCFG), readl(regs + S3C_DCTL),
2938 readl(regs + S3C_DIEPMSK));
2940 dev_info(dev, "GAHBCFG=0x%08x, 0x44=0x%08x\n",
2941 readl(regs + S3C_GAHBCFG), readl(regs + 0x44));
2943 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
2944 readl(regs + S3C_GRXFSIZ), readl(regs + S3C_GNPTXFSIZ));
2946 /* show periodic fifo settings */
2948 for (idx = 1; idx <= 15; idx++) {
2949 val = readl(regs + S3C_DPTXFSIZn(idx));
2950 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
2951 val >> S3C_DPTXFSIZn_DPTxFSize_SHIFT,
2952 val & S3C_DPTXFSIZn_DPTxFStAddr_MASK);
2955 for (idx = 0; idx < 15; idx++) {
2957 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
2958 readl(regs + S3C_DIEPCTL(idx)),
2959 readl(regs + S3C_DIEPTSIZ(idx)),
2960 readl(regs + S3C_DIEPDMA(idx)));
2962 val = readl(regs + S3C_DOEPCTL(idx));
2964 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
2965 idx, readl(regs + S3C_DOEPCTL(idx)),
2966 readl(regs + S3C_DOEPTSIZ(idx)),
2967 readl(regs + S3C_DOEPDMA(idx)));
2971 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
2972 readl(regs + S3C_DVBUSDIS), readl(regs + S3C_DVBUSPULSE));
2978 * state_show - debugfs: show overall driver and device state.
2979 * @seq: The seq file to write to.
2980 * @v: Unused parameter.
2982 * This debugfs entry shows the overall state of the hardware and
2983 * some general information about each of the endpoints available
2986 static int state_show(struct seq_file *seq, void *v)
2988 struct s3c_hsotg *hsotg = seq->private;
2989 void __iomem *regs = hsotg->regs;
2992 seq_printf(seq, "DCFG=0x%08x, DCTL=0x%08x, DSTS=0x%08x\n",
2993 readl(regs + S3C_DCFG),
2994 readl(regs + S3C_DCTL),
2995 readl(regs + S3C_DSTS));
2997 seq_printf(seq, "DIEPMSK=0x%08x, DOEPMASK=0x%08x\n",
2998 readl(regs + S3C_DIEPMSK), readl(regs + S3C_DOEPMSK));
3000 seq_printf(seq, "GINTMSK=0x%08x, GINTSTS=0x%08x\n",
3001 readl(regs + S3C_GINTMSK),
3002 readl(regs + S3C_GINTSTS));
3004 seq_printf(seq, "DAINTMSK=0x%08x, DAINT=0x%08x\n",
3005 readl(regs + S3C_DAINTMSK),
3006 readl(regs + S3C_DAINT));
3008 seq_printf(seq, "GNPTXSTS=0x%08x, GRXSTSR=%08x\n",
3009 readl(regs + S3C_GNPTXSTS),
3010 readl(regs + S3C_GRXSTSR));
3012 seq_printf(seq, "\nEndpoint status:\n");
3014 for (idx = 0; idx < 15; idx++) {
3017 in = readl(regs + S3C_DIEPCTL(idx));
3018 out = readl(regs + S3C_DOEPCTL(idx));
3020 seq_printf(seq, "ep%d: DIEPCTL=0x%08x, DOEPCTL=0x%08x",
3023 in = readl(regs + S3C_DIEPTSIZ(idx));
3024 out = readl(regs + S3C_DOEPTSIZ(idx));
3026 seq_printf(seq, ", DIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x",
3029 seq_printf(seq, "\n");
3035 static int state_open(struct inode *inode, struct file *file)
3037 return single_open(file, state_show, inode->i_private);
3040 static const struct file_operations state_fops = {
3041 .owner = THIS_MODULE,
3044 .llseek = seq_lseek,
3045 .release = single_release,
3049 * fifo_show - debugfs: show the fifo information
3050 * @seq: The seq_file to write data to.
3051 * @v: Unused parameter.
3053 * Show the FIFO information for the overall fifo and all the
3054 * periodic transmission FIFOs.
3056 static int fifo_show(struct seq_file *seq, void *v)
3058 struct s3c_hsotg *hsotg = seq->private;
3059 void __iomem *regs = hsotg->regs;
3063 seq_printf(seq, "Non-periodic FIFOs:\n");
3064 seq_printf(seq, "RXFIFO: Size %d\n", readl(regs + S3C_GRXFSIZ));
3066 val = readl(regs + S3C_GNPTXFSIZ);
3067 seq_printf(seq, "NPTXFIFO: Size %d, Start 0x%08x\n",
3068 val >> S3C_GNPTXFSIZ_NPTxFDep_SHIFT,
3069 val & S3C_GNPTXFSIZ_NPTxFStAddr_MASK);
3071 seq_printf(seq, "\nPeriodic TXFIFOs:\n");
3073 for (idx = 1; idx <= 15; idx++) {
3074 val = readl(regs + S3C_DPTXFSIZn(idx));
3076 seq_printf(seq, "\tDPTXFIFO%2d: Size %d, Start 0x%08x\n", idx,
3077 val >> S3C_DPTXFSIZn_DPTxFSize_SHIFT,
3078 val & S3C_DPTXFSIZn_DPTxFStAddr_MASK);
3084 static int fifo_open(struct inode *inode, struct file *file)
3086 return single_open(file, fifo_show, inode->i_private);
3089 static const struct file_operations fifo_fops = {
3090 .owner = THIS_MODULE,
3093 .llseek = seq_lseek,
3094 .release = single_release,
3098 static const char *decode_direction(int is_in)
3100 return is_in ? "in" : "out";
3104 * ep_show - debugfs: show the state of an endpoint.
3105 * @seq: The seq_file to write data to.
3106 * @v: Unused parameter.
3108 * This debugfs entry shows the state of the given endpoint (one is
3109 * registered for each available).
3111 static int ep_show(struct seq_file *seq, void *v)
3113 struct s3c_hsotg_ep *ep = seq->private;
3114 struct s3c_hsotg *hsotg = ep->parent;
3115 struct s3c_hsotg_req *req;
3116 void __iomem *regs = hsotg->regs;
3117 int index = ep->index;
3118 int show_limit = 15;
3119 unsigned long flags;
3121 seq_printf(seq, "Endpoint index %d, named %s, dir %s:\n",
3122 ep->index, ep->ep.name, decode_direction(ep->dir_in));
3124 /* first show the register state */
3126 seq_printf(seq, "\tDIEPCTL=0x%08x, DOEPCTL=0x%08x\n",
3127 readl(regs + S3C_DIEPCTL(index)),
3128 readl(regs + S3C_DOEPCTL(index)));
3130 seq_printf(seq, "\tDIEPDMA=0x%08x, DOEPDMA=0x%08x\n",
3131 readl(regs + S3C_DIEPDMA(index)),
3132 readl(regs + S3C_DOEPDMA(index)));
3134 seq_printf(seq, "\tDIEPINT=0x%08x, DOEPINT=0x%08x\n",
3135 readl(regs + S3C_DIEPINT(index)),
3136 readl(regs + S3C_DOEPINT(index)));
3138 seq_printf(seq, "\tDIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x\n",
3139 readl(regs + S3C_DIEPTSIZ(index)),
3140 readl(regs + S3C_DOEPTSIZ(index)));
3142 seq_printf(seq, "\n");
3143 seq_printf(seq, "mps %d\n", ep->ep.maxpacket);
3144 seq_printf(seq, "total_data=%ld\n", ep->total_data);
3146 seq_printf(seq, "request list (%p,%p):\n",
3147 ep->queue.next, ep->queue.prev);
3149 spin_lock_irqsave(&ep->lock, flags);
3151 list_for_each_entry(req, &ep->queue, queue) {
3152 if (--show_limit < 0) {
3153 seq_printf(seq, "not showing more requests...\n");
3157 seq_printf(seq, "%c req %p: %d bytes @%p, ",
3158 req == ep->req ? '*' : ' ',
3159 req, req->req.length, req->req.buf);
3160 seq_printf(seq, "%d done, res %d\n",
3161 req->req.actual, req->req.status);
3164 spin_unlock_irqrestore(&ep->lock, flags);
3169 static int ep_open(struct inode *inode, struct file *file)
3171 return single_open(file, ep_show, inode->i_private);
3174 static const struct file_operations ep_fops = {
3175 .owner = THIS_MODULE,
3178 .llseek = seq_lseek,
3179 .release = single_release,
3183 * s3c_hsotg_create_debug - create debugfs directory and files
3184 * @hsotg: The driver state
3186 * Create the debugfs files to allow the user to get information
3187 * about the state of the system. The directory name is created
3188 * with the same name as the device itself, in case we end up
3189 * with multiple blocks in future systems.
3191 static void __devinit s3c_hsotg_create_debug(struct s3c_hsotg *hsotg)
3193 struct dentry *root;
3196 root = debugfs_create_dir(dev_name(hsotg->dev), NULL);
3197 hsotg->debug_root = root;
3199 dev_err(hsotg->dev, "cannot create debug root\n");
3203 /* create general state file */
3205 hsotg->debug_file = debugfs_create_file("state", 0444, root,
3206 hsotg, &state_fops);
3208 if (IS_ERR(hsotg->debug_file))
3209 dev_err(hsotg->dev, "%s: failed to create state\n", __func__);
3211 hsotg->debug_fifo = debugfs_create_file("fifo", 0444, root,
3214 if (IS_ERR(hsotg->debug_fifo))
3215 dev_err(hsotg->dev, "%s: failed to create fifo\n", __func__);
3217 /* create one file for each endpoint */
3219 for (epidx = 0; epidx < S3C_HSOTG_EPS; epidx++) {
3220 struct s3c_hsotg_ep *ep = &hsotg->eps[epidx];
3222 ep->debugfs = debugfs_create_file(ep->name, 0444,
3223 root, ep, &ep_fops);
3225 if (IS_ERR(ep->debugfs))
3226 dev_err(hsotg->dev, "failed to create %s debug file\n",
3232 * s3c_hsotg_delete_debug - cleanup debugfs entries
3233 * @hsotg: The driver state
3235 * Cleanup (remove) the debugfs files for use on module exit.
3237 static void __devexit s3c_hsotg_delete_debug(struct s3c_hsotg *hsotg)
3241 for (epidx = 0; epidx < S3C_HSOTG_EPS; epidx++) {
3242 struct s3c_hsotg_ep *ep = &hsotg->eps[epidx];
3243 debugfs_remove(ep->debugfs);
3246 debugfs_remove(hsotg->debug_file);
3247 debugfs_remove(hsotg->debug_fifo);
3248 debugfs_remove(hsotg->debug_root);
3251 static int __devinit s3c_hsotg_probe(struct platform_device *pdev)
3253 struct s3c_hsotg_plat *plat = pdev->dev.platform_data;
3254 struct device *dev = &pdev->dev;
3255 struct s3c_hsotg *hsotg;
3256 struct resource *res;
3260 plat = pdev->dev.platform_data;
3262 dev_err(&pdev->dev, "no platform data defined\n");
3266 hsotg = kzalloc(sizeof(struct s3c_hsotg) +
3267 sizeof(struct s3c_hsotg_ep) * S3C_HSOTG_EPS,
3270 dev_err(dev, "cannot get memory\n");
3277 hsotg->clk = clk_get(&pdev->dev, "otg");
3278 if (IS_ERR(hsotg->clk)) {
3279 dev_err(dev, "cannot get otg clock\n");
3280 ret = PTR_ERR(hsotg->clk);
3284 platform_set_drvdata(pdev, hsotg);
3286 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3288 dev_err(dev, "cannot find register resource 0\n");
3293 hsotg->regs_res = request_mem_region(res->start, resource_size(res),
3295 if (!hsotg->regs_res) {
3296 dev_err(dev, "cannot reserve registers\n");
3301 hsotg->regs = ioremap(res->start, resource_size(res));
3303 dev_err(dev, "cannot map registers\n");
3308 ret = platform_get_irq(pdev, 0);
3310 dev_err(dev, "cannot find IRQ\n");
3316 ret = request_irq(ret, s3c_hsotg_irq, 0, dev_name(dev), hsotg);
3318 dev_err(dev, "cannot claim IRQ\n");
3322 dev_info(dev, "regs %p, irq %d\n", hsotg->regs, hsotg->irq);
3324 device_initialize(&hsotg->gadget.dev);
3326 dev_set_name(&hsotg->gadget.dev, "gadget");
3328 hsotg->gadget.max_speed = USB_SPEED_HIGH;
3329 hsotg->gadget.ops = &s3c_hsotg_gadget_ops;
3330 hsotg->gadget.name = dev_name(dev);
3332 hsotg->gadget.dev.parent = dev;
3333 hsotg->gadget.dev.dma_mask = dev->dma_mask;
3335 /* setup endpoint information */
3337 INIT_LIST_HEAD(&hsotg->gadget.ep_list);
3338 hsotg->gadget.ep0 = &hsotg->eps[0].ep;
3340 /* allocate EP0 request */
3342 hsotg->ctrl_req = s3c_hsotg_ep_alloc_request(&hsotg->eps[0].ep,
3344 if (!hsotg->ctrl_req) {
3345 dev_err(dev, "failed to allocate ctrl req\n");
3349 /* reset the system */
3351 clk_enable(hsotg->clk);
3353 /* usb phy enable */
3354 s3c_hsotg_phy_enable(hsotg);
3356 s3c_hsotg_corereset(hsotg);
3357 s3c_hsotg_init(hsotg);
3359 /* initialise the endpoints now the core has been initialised */
3360 for (epnum = 0; epnum < S3C_HSOTG_EPS; epnum++)
3361 s3c_hsotg_initep(hsotg, &hsotg->eps[epnum], epnum);
3363 ret = usb_add_gadget_udc(&pdev->dev, &hsotg->gadget);
3367 s3c_hsotg_create_debug(hsotg);
3369 s3c_hsotg_dump(hsotg);
3375 s3c_hsotg_phy_disable(hsotg);
3377 clk_disable(hsotg->clk);
3378 clk_put(hsotg->clk);
3381 iounmap(hsotg->regs);
3384 release_resource(hsotg->regs_res);
3385 kfree(hsotg->regs_res);
3387 clk_put(hsotg->clk);
3393 static int __devexit s3c_hsotg_remove(struct platform_device *pdev)
3395 struct s3c_hsotg *hsotg = platform_get_drvdata(pdev);
3397 usb_del_gadget_udc(&hsotg->gadget);
3399 s3c_hsotg_delete_debug(hsotg);
3401 usb_gadget_unregister_driver(hsotg->driver);
3403 free_irq(hsotg->irq, hsotg);
3404 iounmap(hsotg->regs);
3406 release_resource(hsotg->regs_res);
3407 kfree(hsotg->regs_res);
3409 s3c_hsotg_phy_disable(hsotg);
3411 clk_disable(hsotg->clk);
3412 clk_put(hsotg->clk);
3419 #define s3c_hsotg_suspend NULL
3420 #define s3c_hsotg_resume NULL
3423 static struct platform_driver s3c_hsotg_driver = {
3425 .name = "s3c-hsotg",
3426 .owner = THIS_MODULE,
3428 .probe = s3c_hsotg_probe,
3429 .remove = __devexit_p(s3c_hsotg_remove),
3430 .suspend = s3c_hsotg_suspend,
3431 .resume = s3c_hsotg_resume,
3434 module_platform_driver(s3c_hsotg_driver);
3436 MODULE_DESCRIPTION("Samsung S3C USB High-speed/OtG device");
3437 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
3438 MODULE_LICENSE("GPL");
3439 MODULE_ALIAS("platform:s3c-hsotg");