1 /* linux/drivers/usb/gadget/s3c-hsotg.c
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * Copyright 2008 Openmoko, Inc.
7 * Copyright 2008 Simtec Electronics
8 * Ben Dooks <ben@simtec.co.uk>
9 * http://armlinux.simtec.co.uk/
11 * S3C USB2.0 High-speed / OtG driver
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/spinlock.h>
21 #include <linux/interrupt.h>
22 #include <linux/platform_device.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/debugfs.h>
25 #include <linux/seq_file.h>
26 #include <linux/delay.h>
28 #include <linux/slab.h>
29 #include <linux/clk.h>
30 #include <linux/regulator/consumer.h>
32 #include <linux/usb/ch9.h>
33 #include <linux/usb/gadget.h>
37 #include "s3c-hsotg.h"
38 #include <linux/platform_data/s3c-hsotg.h>
40 #define DMA_ADDR_INVALID (~((dma_addr_t)0))
42 static const char * const s3c_hsotg_supply_names[] = {
43 "vusb_d", /* digital USB supply, 1.2V */
44 "vusb_a", /* analog USB supply, 1.1V */
49 * Unfortunately there seems to be a limit of the amount of data that can
50 * be transferred by IN transactions on EP0. This is either 127 bytes or 3
51 * packets (which practically means 1 packet and 63 bytes of data) when the
54 * This means if we are wanting to move >127 bytes of data, we need to
55 * split the transactions up, but just doing one packet at a time does
56 * not work (this may be an implicit DATA0 PID on first packet of the
57 * transaction) and doing 2 packets is outside the controller's limits.
59 * If we try to lower the MPS size for EP0, then no transfers work properly
60 * for EP0, and the system will fail basic enumeration. As no cause for this
61 * has currently been found, we cannot support any large IN transfers for
64 #define EP0_MPS_LIMIT 64
70 * struct s3c_hsotg_ep - driver endpoint definition.
71 * @ep: The gadget layer representation of the endpoint.
72 * @name: The driver generated name for the endpoint.
73 * @queue: Queue of requests for this endpoint.
74 * @parent: Reference back to the parent device structure.
75 * @req: The current request that the endpoint is processing. This is
76 * used to indicate an request has been loaded onto the endpoint
77 * and has yet to be completed (maybe due to data move, or simply
78 * awaiting an ack from the core all the data has been completed).
79 * @debugfs: File entry for debugfs file for this endpoint.
80 * @lock: State lock to protect contents of endpoint.
81 * @dir_in: Set to true if this endpoint is of the IN direction, which
82 * means that it is sending data to the Host.
83 * @index: The index for the endpoint registers.
84 * @name: The name array passed to the USB core.
85 * @halted: Set if the endpoint has been halted.
86 * @periodic: Set if this is a periodic ep, such as Interrupt
87 * @sent_zlp: Set if we've sent a zero-length packet.
88 * @total_data: The total number of data bytes done.
89 * @fifo_size: The size of the FIFO (for periodic IN endpoints)
90 * @fifo_load: The amount of data loaded into the FIFO (periodic IN)
91 * @last_load: The offset of data for the last start of request.
92 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN
94 * This is the driver's state for each registered enpoint, allowing it
95 * to keep track of transactions that need doing. Each endpoint has a
96 * lock to protect the state, to try and avoid using an overall lock
97 * for the host controller as much as possible.
99 * For periodic IN endpoints, we have fifo_size and fifo_load to try
100 * and keep track of the amount of data in the periodic FIFO for each
101 * of these as we don't have a status register that tells us how much
102 * is in each of them. (note, this may actually be useless information
103 * as in shared-fifo mode periodic in acts like a single-frame packet
104 * buffer than a fifo)
106 struct s3c_hsotg_ep {
108 struct list_head queue;
109 struct s3c_hsotg *parent;
110 struct s3c_hsotg_req *req;
111 struct dentry *debugfs;
115 unsigned long total_data;
116 unsigned int size_loaded;
117 unsigned int last_load;
118 unsigned int fifo_load;
119 unsigned short fifo_size;
121 unsigned char dir_in;
124 unsigned int halted:1;
125 unsigned int periodic:1;
126 unsigned int sent_zlp:1;
131 #define S3C_HSOTG_EPS (8+1) /* limit to 9 for the moment */
134 * struct s3c_hsotg - driver state.
135 * @dev: The parent device supplied to the probe function
136 * @driver: USB gadget driver
137 * @plat: The platform specific configuration data.
138 * @regs: The memory area mapped for accessing registers.
139 * @regs_res: The resource that was allocated when claiming register space.
140 * @irq: The IRQ number we are using
141 * @supplies: Definition of USB power supplies
142 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos.
143 * @debug_root: root directrory for debugfs.
144 * @debug_file: main status file for debugfs.
145 * @debug_fifo: FIFO status file for debugfs.
146 * @ep0_reply: Request used for ep0 reply.
147 * @ep0_buff: Buffer for EP0 reply data, if needed.
148 * @ctrl_buff: Buffer for EP0 control requests.
149 * @ctrl_req: Request for EP0 control packets.
150 * @eps: The endpoints being supplied to the gadget framework
154 struct usb_gadget_driver *driver;
155 struct s3c_hsotg_plat *plat;
158 struct resource *regs_res;
162 struct regulator_bulk_data supplies[ARRAY_SIZE(s3c_hsotg_supply_names)];
164 unsigned int dedicated_fifos:1;
166 struct dentry *debug_root;
167 struct dentry *debug_file;
168 struct dentry *debug_fifo;
170 struct usb_request *ep0_reply;
171 struct usb_request *ctrl_req;
175 struct usb_gadget gadget;
176 struct s3c_hsotg_ep eps[];
180 * struct s3c_hsotg_req - data transfer request
181 * @req: The USB gadget request
182 * @queue: The list of requests for the endpoint this is queued for.
183 * @in_progress: Has already had size/packets written to core
184 * @mapped: DMA buffer for this request has been mapped via dma_map_single().
186 struct s3c_hsotg_req {
187 struct usb_request req;
188 struct list_head queue;
189 unsigned char in_progress;
190 unsigned char mapped;
193 /* conversion functions */
194 static inline struct s3c_hsotg_req *our_req(struct usb_request *req)
196 return container_of(req, struct s3c_hsotg_req, req);
199 static inline struct s3c_hsotg_ep *our_ep(struct usb_ep *ep)
201 return container_of(ep, struct s3c_hsotg_ep, ep);
204 static inline struct s3c_hsotg *to_hsotg(struct usb_gadget *gadget)
206 return container_of(gadget, struct s3c_hsotg, gadget);
209 static inline void __orr32(void __iomem *ptr, u32 val)
211 writel(readl(ptr) | val, ptr);
214 static inline void __bic32(void __iomem *ptr, u32 val)
216 writel(readl(ptr) & ~val, ptr);
219 /* forward decleration of functions */
220 static void s3c_hsotg_dump(struct s3c_hsotg *hsotg);
223 * using_dma - return the DMA status of the driver.
224 * @hsotg: The driver state.
226 * Return true if we're using DMA.
228 * Currently, we have the DMA support code worked into everywhere
229 * that needs it, but the AMBA DMA implementation in the hardware can
230 * only DMA from 32bit aligned addresses. This means that gadgets such
231 * as the CDC Ethernet cannot work as they often pass packets which are
234 * Unfortunately the choice to use DMA or not is global to the controller
235 * and seems to be only settable when the controller is being put through
236 * a core reset. This means we either need to fix the gadgets to take
237 * account of DMA alignment, or add bounce buffers (yuerk).
239 * Until this issue is sorted out, we always return 'false'.
241 static inline bool using_dma(struct s3c_hsotg *hsotg)
243 return false; /* support is not complete */
247 * s3c_hsotg_en_gsint - enable one or more of the general interrupt
248 * @hsotg: The device state
249 * @ints: A bitmask of the interrupts to enable
251 static void s3c_hsotg_en_gsint(struct s3c_hsotg *hsotg, u32 ints)
253 u32 gsintmsk = readl(hsotg->regs + S3C_GINTMSK);
256 new_gsintmsk = gsintmsk | ints;
258 if (new_gsintmsk != gsintmsk) {
259 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
260 writel(new_gsintmsk, hsotg->regs + S3C_GINTMSK);
265 * s3c_hsotg_disable_gsint - disable one or more of the general interrupt
266 * @hsotg: The device state
267 * @ints: A bitmask of the interrupts to enable
269 static void s3c_hsotg_disable_gsint(struct s3c_hsotg *hsotg, u32 ints)
271 u32 gsintmsk = readl(hsotg->regs + S3C_GINTMSK);
274 new_gsintmsk = gsintmsk & ~ints;
276 if (new_gsintmsk != gsintmsk)
277 writel(new_gsintmsk, hsotg->regs + S3C_GINTMSK);
281 * s3c_hsotg_ctrl_epint - enable/disable an endpoint irq
282 * @hsotg: The device state
283 * @ep: The endpoint index
284 * @dir_in: True if direction is in.
285 * @en: The enable value, true to enable
287 * Set or clear the mask for an individual endpoint's interrupt
290 static void s3c_hsotg_ctrl_epint(struct s3c_hsotg *hsotg,
291 unsigned int ep, unsigned int dir_in,
301 local_irq_save(flags);
302 daint = readl(hsotg->regs + S3C_DAINTMSK);
307 writel(daint, hsotg->regs + S3C_DAINTMSK);
308 local_irq_restore(flags);
312 * s3c_hsotg_init_fifo - initialise non-periodic FIFOs
313 * @hsotg: The device instance.
315 static void s3c_hsotg_init_fifo(struct s3c_hsotg *hsotg)
323 /* the ryu 2.6.24 release ahs
324 writel(0x1C0, hsotg->regs + S3C_GRXFSIZ);
325 writel(S3C_GNPTXFSIZ_NPTxFStAddr(0x200) |
326 S3C_GNPTXFSIZ_NPTxFDep(0x1C0),
327 hsotg->regs + S3C_GNPTXFSIZ);
330 /* set FIFO sizes to 2048/1024 */
332 writel(2048, hsotg->regs + S3C_GRXFSIZ);
333 writel(S3C_GNPTXFSIZ_NPTxFStAddr(2048) |
334 S3C_GNPTXFSIZ_NPTxFDep(1024),
335 hsotg->regs + S3C_GNPTXFSIZ);
337 /* arange all the rest of the TX FIFOs, as some versions of this
338 * block have overlapping default addresses. This also ensures
339 * that if the settings have been changed, then they are set to
342 /* start at the end of the GNPTXFSIZ, rounded up */
346 /* currently we allocate TX FIFOs for all possible endpoints,
347 * and assume that they are all the same size. */
349 for (ep = 1; ep <= 15; ep++) {
351 val |= size << S3C_DPTXFSIZn_DPTxFSize_SHIFT;
354 writel(val, hsotg->regs + S3C_DPTXFSIZn(ep));
357 /* according to p428 of the design guide, we need to ensure that
358 * all fifos are flushed before continuing */
360 writel(S3C_GRSTCTL_TxFNum(0x10) | S3C_GRSTCTL_TxFFlsh |
361 S3C_GRSTCTL_RxFFlsh, hsotg->regs + S3C_GRSTCTL);
363 /* wait until the fifos are both flushed */
366 val = readl(hsotg->regs + S3C_GRSTCTL);
368 if ((val & (S3C_GRSTCTL_TxFFlsh | S3C_GRSTCTL_RxFFlsh)) == 0)
371 if (--timeout == 0) {
373 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
380 dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout);
384 * @ep: USB endpoint to allocate request for.
385 * @flags: Allocation flags
387 * Allocate a new USB request structure appropriate for the specified endpoint
389 static struct usb_request *s3c_hsotg_ep_alloc_request(struct usb_ep *ep,
392 struct s3c_hsotg_req *req;
394 req = kzalloc(sizeof(struct s3c_hsotg_req), flags);
398 INIT_LIST_HEAD(&req->queue);
400 req->req.dma = DMA_ADDR_INVALID;
405 * is_ep_periodic - return true if the endpoint is in periodic mode.
406 * @hs_ep: The endpoint to query.
408 * Returns true if the endpoint is in periodic mode, meaning it is being
409 * used for an Interrupt or ISO transfer.
411 static inline int is_ep_periodic(struct s3c_hsotg_ep *hs_ep)
413 return hs_ep->periodic;
417 * s3c_hsotg_unmap_dma - unmap the DMA memory being used for the request
418 * @hsotg: The device state.
419 * @hs_ep: The endpoint for the request
420 * @hs_req: The request being processed.
422 * This is the reverse of s3c_hsotg_map_dma(), called for the completion
423 * of a request to ensure the buffer is ready for access by the caller.
425 static void s3c_hsotg_unmap_dma(struct s3c_hsotg *hsotg,
426 struct s3c_hsotg_ep *hs_ep,
427 struct s3c_hsotg_req *hs_req)
429 struct usb_request *req = &hs_req->req;
430 enum dma_data_direction dir;
432 dir = hs_ep->dir_in ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
434 /* ignore this if we're not moving any data */
435 if (hs_req->req.length == 0)
438 if (hs_req->mapped) {
439 /* we mapped this, so unmap and remove the dma */
441 dma_unmap_single(hsotg->dev, req->dma, req->length, dir);
443 req->dma = DMA_ADDR_INVALID;
446 dma_sync_single_for_cpu(hsotg->dev, req->dma, req->length, dir);
451 * s3c_hsotg_write_fifo - write packet Data to the TxFIFO
452 * @hsotg: The controller state.
453 * @hs_ep: The endpoint we're going to write for.
454 * @hs_req: The request to write data for.
456 * This is called when the TxFIFO has some space in it to hold a new
457 * transmission and we have something to give it. The actual setup of
458 * the data size is done elsewhere, so all we have to do is to actually
461 * The return value is zero if there is more space (or nothing was done)
462 * otherwise -ENOSPC is returned if the FIFO space was used up.
464 * This routine is only needed for PIO
466 static int s3c_hsotg_write_fifo(struct s3c_hsotg *hsotg,
467 struct s3c_hsotg_ep *hs_ep,
468 struct s3c_hsotg_req *hs_req)
470 bool periodic = is_ep_periodic(hs_ep);
471 u32 gnptxsts = readl(hsotg->regs + S3C_GNPTXSTS);
472 int buf_pos = hs_req->req.actual;
473 int to_write = hs_ep->size_loaded;
478 to_write -= (buf_pos - hs_ep->last_load);
480 /* if there's nothing to write, get out early */
484 if (periodic && !hsotg->dedicated_fifos) {
485 u32 epsize = readl(hsotg->regs + S3C_DIEPTSIZ(hs_ep->index));
489 /* work out how much data was loaded so we can calculate
490 * how much data is left in the fifo. */
492 size_left = S3C_DxEPTSIZ_XferSize_GET(epsize);
494 /* if shared fifo, we cannot write anything until the
495 * previous data has been completely sent.
497 if (hs_ep->fifo_load != 0) {
498 s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_PTxFEmp);
502 dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n",
504 hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size);
506 /* how much of the data has moved */
507 size_done = hs_ep->size_loaded - size_left;
509 /* how much data is left in the fifo */
510 can_write = hs_ep->fifo_load - size_done;
511 dev_dbg(hsotg->dev, "%s: => can_write1=%d\n",
512 __func__, can_write);
514 can_write = hs_ep->fifo_size - can_write;
515 dev_dbg(hsotg->dev, "%s: => can_write2=%d\n",
516 __func__, can_write);
518 if (can_write <= 0) {
519 s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_PTxFEmp);
522 } else if (hsotg->dedicated_fifos && hs_ep->index != 0) {
523 can_write = readl(hsotg->regs + S3C_DTXFSTS(hs_ep->index));
528 if (S3C_GNPTXSTS_NPTxQSpcAvail_GET(gnptxsts) == 0) {
530 "%s: no queue slots available (0x%08x)\n",
533 s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_NPTxFEmp);
537 can_write = S3C_GNPTXSTS_NPTxFSpcAvail_GET(gnptxsts);
538 can_write *= 4; /* fifo size is in 32bit quantities. */
541 dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, mps %d\n",
542 __func__, gnptxsts, can_write, to_write, hs_ep->ep.maxpacket);
544 /* limit to 512 bytes of data, it seems at least on the non-periodic
545 * FIFO, requests of >512 cause the endpoint to get stuck with a
546 * fragment of the end of the transfer in it.
551 /* limit the write to one max-packet size worth of data, but allow
552 * the transfer to return that it did not run out of fifo space
554 if (to_write > hs_ep->ep.maxpacket) {
555 to_write = hs_ep->ep.maxpacket;
557 s3c_hsotg_en_gsint(hsotg,
558 periodic ? S3C_GINTSTS_PTxFEmp :
559 S3C_GINTSTS_NPTxFEmp);
562 /* see if we can write data */
564 if (to_write > can_write) {
565 to_write = can_write;
566 pkt_round = to_write % hs_ep->ep.maxpacket;
568 /* Not sure, but we probably shouldn't be writing partial
569 * packets into the FIFO, so round the write down to an
570 * exact number of packets.
572 * Note, we do not currently check to see if we can ever
573 * write a full packet or not to the FIFO.
577 to_write -= pkt_round;
579 /* enable correct FIFO interrupt to alert us when there
580 * is more room left. */
582 s3c_hsotg_en_gsint(hsotg,
583 periodic ? S3C_GINTSTS_PTxFEmp :
584 S3C_GINTSTS_NPTxFEmp);
587 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
588 to_write, hs_req->req.length, can_write, buf_pos);
593 hs_req->req.actual = buf_pos + to_write;
594 hs_ep->total_data += to_write;
597 hs_ep->fifo_load += to_write;
599 to_write = DIV_ROUND_UP(to_write, 4);
600 data = hs_req->req.buf + buf_pos;
602 writesl(hsotg->regs + S3C_EPFIFO(hs_ep->index), data, to_write);
604 return (to_write >= can_write) ? -ENOSPC : 0;
608 * get_ep_limit - get the maximum data legnth for this endpoint
609 * @hs_ep: The endpoint
611 * Return the maximum data that can be queued in one go on a given endpoint
612 * so that transfers that are too long can be split.
614 static unsigned get_ep_limit(struct s3c_hsotg_ep *hs_ep)
616 int index = hs_ep->index;
621 maxsize = S3C_DxEPTSIZ_XferSize_LIMIT + 1;
622 maxpkt = S3C_DxEPTSIZ_PktCnt_LIMIT + 1;
626 maxpkt = S3C_DIEPTSIZ0_PktCnt_LIMIT + 1;
631 /* we made the constant loading easier above by using +1 */
635 /* constrain by packet count if maxpkts*pktsize is greater
636 * than the length register size. */
638 if ((maxpkt * hs_ep->ep.maxpacket) < maxsize)
639 maxsize = maxpkt * hs_ep->ep.maxpacket;
645 * s3c_hsotg_start_req - start a USB request from an endpoint's queue
646 * @hsotg: The controller state.
647 * @hs_ep: The endpoint to process a request for
648 * @hs_req: The request to start.
649 * @continuing: True if we are doing more for the current request.
651 * Start the given request running by setting the endpoint registers
652 * appropriately, and writing any data to the FIFOs.
654 static void s3c_hsotg_start_req(struct s3c_hsotg *hsotg,
655 struct s3c_hsotg_ep *hs_ep,
656 struct s3c_hsotg_req *hs_req,
659 struct usb_request *ureq = &hs_req->req;
660 int index = hs_ep->index;
661 int dir_in = hs_ep->dir_in;
671 if (hs_ep->req && !continuing) {
672 dev_err(hsotg->dev, "%s: active request\n", __func__);
675 } else if (hs_ep->req != hs_req && continuing) {
677 "%s: continue different req\n", __func__);
683 epctrl_reg = dir_in ? S3C_DIEPCTL(index) : S3C_DOEPCTL(index);
684 epsize_reg = dir_in ? S3C_DIEPTSIZ(index) : S3C_DOEPTSIZ(index);
686 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
687 __func__, readl(hsotg->regs + epctrl_reg), index,
688 hs_ep->dir_in ? "in" : "out");
690 /* If endpoint is stalled, we will restart request later */
691 ctrl = readl(hsotg->regs + epctrl_reg);
693 if (ctrl & S3C_DxEPCTL_Stall) {
694 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
698 length = ureq->length - ureq->actual;
702 "REQ buf %p len %d dma 0x%08x noi=%d zp=%d snok=%d\n",
703 ureq->buf, length, ureq->dma,
704 ureq->no_interrupt, ureq->zero, ureq->short_not_ok);
706 maxreq = get_ep_limit(hs_ep);
707 if (length > maxreq) {
708 int round = maxreq % hs_ep->ep.maxpacket;
710 dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n",
711 __func__, length, maxreq, round);
713 /* round down to multiple of packets */
721 packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket);
723 packets = 1; /* send one packet if length is zero. */
725 if (dir_in && index != 0)
726 epsize = S3C_DxEPTSIZ_MC(1);
730 if (index != 0 && ureq->zero) {
731 /* test for the packets being exactly right for the
734 if (length == (packets * hs_ep->ep.maxpacket))
738 epsize |= S3C_DxEPTSIZ_PktCnt(packets);
739 epsize |= S3C_DxEPTSIZ_XferSize(length);
741 dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
742 __func__, packets, length, ureq->length, epsize, epsize_reg);
744 /* store the request as the current one we're doing */
747 /* write size / packets */
748 writel(epsize, hsotg->regs + epsize_reg);
750 if (using_dma(hsotg) && !continuing) {
751 unsigned int dma_reg;
753 /* write DMA address to control register, buffer already
754 * synced by s3c_hsotg_ep_queue(). */
756 dma_reg = dir_in ? S3C_DIEPDMA(index) : S3C_DOEPDMA(index);
757 writel(ureq->dma, hsotg->regs + dma_reg);
759 dev_dbg(hsotg->dev, "%s: 0x%08x => 0x%08x\n",
760 __func__, ureq->dma, dma_reg);
763 ctrl |= S3C_DxEPCTL_EPEna; /* ensure ep enabled */
764 ctrl |= S3C_DxEPCTL_USBActEp;
765 ctrl |= S3C_DxEPCTL_CNAK; /* clear NAK set by core */
767 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
768 writel(ctrl, hsotg->regs + epctrl_reg);
770 /* set these, it seems that DMA support increments past the end
771 * of the packet buffer so we need to calculate the length from
772 * this information. */
773 hs_ep->size_loaded = length;
774 hs_ep->last_load = ureq->actual;
776 if (dir_in && !using_dma(hsotg)) {
777 /* set these anyway, we may need them for non-periodic in */
778 hs_ep->fifo_load = 0;
780 s3c_hsotg_write_fifo(hsotg, hs_ep, hs_req);
783 /* clear the INTknTXFEmpMsk when we start request, more as a aide
784 * to debugging to see what is going on. */
786 writel(S3C_DIEPMSK_INTknTXFEmpMsk,
787 hsotg->regs + S3C_DIEPINT(index));
789 /* Note, trying to clear the NAK here causes problems with transmit
790 * on the S3C6400 ending up with the TXFIFO becoming full. */
792 /* check ep is enabled */
793 if (!(readl(hsotg->regs + epctrl_reg) & S3C_DxEPCTL_EPEna))
795 "ep%d: failed to become enabled (DxEPCTL=0x%08x)?\n",
796 index, readl(hsotg->regs + epctrl_reg));
798 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n",
799 __func__, readl(hsotg->regs + epctrl_reg));
803 * s3c_hsotg_map_dma - map the DMA memory being used for the request
804 * @hsotg: The device state.
805 * @hs_ep: The endpoint the request is on.
806 * @req: The request being processed.
808 * We've been asked to queue a request, so ensure that the memory buffer
809 * is correctly setup for DMA. If we've been passed an extant DMA address
810 * then ensure the buffer has been synced to memory. If our buffer has no
811 * DMA memory, then we map the memory and mark our request to allow us to
812 * cleanup on completion.
814 static int s3c_hsotg_map_dma(struct s3c_hsotg *hsotg,
815 struct s3c_hsotg_ep *hs_ep,
816 struct usb_request *req)
818 enum dma_data_direction dir;
819 struct s3c_hsotg_req *hs_req = our_req(req);
821 dir = hs_ep->dir_in ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
823 /* if the length is zero, ignore the DMA data */
824 if (hs_req->req.length == 0)
827 if (req->dma == DMA_ADDR_INVALID) {
830 dma = dma_map_single(hsotg->dev, req->buf, req->length, dir);
832 if (unlikely(dma_mapping_error(hsotg->dev, dma)))
836 dev_err(hsotg->dev, "%s: unaligned dma buffer\n",
839 dma_unmap_single(hsotg->dev, dma, req->length, dir);
846 dma_sync_single_for_cpu(hsotg->dev, req->dma, req->length, dir);
853 dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n",
854 __func__, req->buf, req->length);
859 static int s3c_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
862 struct s3c_hsotg_req *hs_req = our_req(req);
863 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
864 struct s3c_hsotg *hs = hs_ep->parent;
865 unsigned long irqflags;
868 dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
869 ep->name, req, req->length, req->buf, req->no_interrupt,
870 req->zero, req->short_not_ok);
872 /* initialise status of the request */
873 INIT_LIST_HEAD(&hs_req->queue);
875 req->status = -EINPROGRESS;
877 /* if we're using DMA, sync the buffers as necessary */
879 int ret = s3c_hsotg_map_dma(hs, hs_ep, req);
884 spin_lock_irqsave(&hs_ep->lock, irqflags);
886 first = list_empty(&hs_ep->queue);
887 list_add_tail(&hs_req->queue, &hs_ep->queue);
890 s3c_hsotg_start_req(hs, hs_ep, hs_req, false);
892 spin_unlock_irqrestore(&hs_ep->lock, irqflags);
897 static void s3c_hsotg_ep_free_request(struct usb_ep *ep,
898 struct usb_request *req)
900 struct s3c_hsotg_req *hs_req = our_req(req);
906 * s3c_hsotg_complete_oursetup - setup completion callback
907 * @ep: The endpoint the request was on.
908 * @req: The request completed.
910 * Called on completion of any requests the driver itself
911 * submitted that need cleaning up.
913 static void s3c_hsotg_complete_oursetup(struct usb_ep *ep,
914 struct usb_request *req)
916 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
917 struct s3c_hsotg *hsotg = hs_ep->parent;
919 dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req);
921 s3c_hsotg_ep_free_request(ep, req);
925 * ep_from_windex - convert control wIndex value to endpoint
926 * @hsotg: The driver state.
927 * @windex: The control request wIndex field (in host order).
929 * Convert the given wIndex into a pointer to an driver endpoint
930 * structure, or return NULL if it is not a valid endpoint.
932 static struct s3c_hsotg_ep *ep_from_windex(struct s3c_hsotg *hsotg,
935 struct s3c_hsotg_ep *ep = &hsotg->eps[windex & 0x7F];
936 int dir = (windex & USB_DIR_IN) ? 1 : 0;
937 int idx = windex & 0x7F;
942 if (idx > S3C_HSOTG_EPS)
945 if (idx && ep->dir_in != dir)
952 * s3c_hsotg_send_reply - send reply to control request
953 * @hsotg: The device state
955 * @buff: Buffer for request
956 * @length: Length of reply.
958 * Create a request and queue it on the given endpoint. This is useful as
959 * an internal method of sending replies to certain control requests, etc.
961 static int s3c_hsotg_send_reply(struct s3c_hsotg *hsotg,
962 struct s3c_hsotg_ep *ep,
966 struct usb_request *req;
969 dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length);
971 req = s3c_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC);
972 hsotg->ep0_reply = req;
974 dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__);
978 req->buf = hsotg->ep0_buff;
979 req->length = length;
980 req->zero = 1; /* always do zero-length final transfer */
981 req->complete = s3c_hsotg_complete_oursetup;
984 memcpy(req->buf, buff, length);
988 ret = s3c_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC);
990 dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__);
998 * s3c_hsotg_process_req_status - process request GET_STATUS
999 * @hsotg: The device state
1000 * @ctrl: USB control request
1002 static int s3c_hsotg_process_req_status(struct s3c_hsotg *hsotg,
1003 struct usb_ctrlrequest *ctrl)
1005 struct s3c_hsotg_ep *ep0 = &hsotg->eps[0];
1006 struct s3c_hsotg_ep *ep;
1010 dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__);
1013 dev_warn(hsotg->dev, "%s: direction out?\n", __func__);
1017 switch (ctrl->bRequestType & USB_RECIP_MASK) {
1018 case USB_RECIP_DEVICE:
1019 reply = cpu_to_le16(0); /* bit 0 => self powered,
1020 * bit 1 => remote wakeup */
1023 case USB_RECIP_INTERFACE:
1024 /* currently, the data result should be zero */
1025 reply = cpu_to_le16(0);
1028 case USB_RECIP_ENDPOINT:
1029 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
1033 reply = cpu_to_le16(ep->halted ? 1 : 0);
1040 if (le16_to_cpu(ctrl->wLength) != 2)
1043 ret = s3c_hsotg_send_reply(hsotg, ep0, &reply, 2);
1045 dev_err(hsotg->dev, "%s: failed to send reply\n", __func__);
1052 static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value);
1055 * get_ep_head - return the first request on the endpoint
1056 * @hs_ep: The controller endpoint to get
1058 * Get the first request on the endpoint.
1060 static struct s3c_hsotg_req *get_ep_head(struct s3c_hsotg_ep *hs_ep)
1062 if (list_empty(&hs_ep->queue))
1065 return list_first_entry(&hs_ep->queue, struct s3c_hsotg_req, queue);
1069 * s3c_hsotg_process_req_featire - process request {SET,CLEAR}_FEATURE
1070 * @hsotg: The device state
1071 * @ctrl: USB control request
1073 static int s3c_hsotg_process_req_feature(struct s3c_hsotg *hsotg,
1074 struct usb_ctrlrequest *ctrl)
1076 struct s3c_hsotg_ep *ep0 = &hsotg->eps[0];
1077 struct s3c_hsotg_req *hs_req;
1079 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
1080 struct s3c_hsotg_ep *ep;
1083 dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",
1084 __func__, set ? "SET" : "CLEAR");
1086 if (ctrl->bRequestType == USB_RECIP_ENDPOINT) {
1087 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
1089 dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n",
1090 __func__, le16_to_cpu(ctrl->wIndex));
1094 switch (le16_to_cpu(ctrl->wValue)) {
1095 case USB_ENDPOINT_HALT:
1096 s3c_hsotg_ep_sethalt(&ep->ep, set);
1098 ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0);
1101 "%s: failed to send reply\n", __func__);
1107 * If we have request in progress,
1113 list_del_init(&hs_req->queue);
1114 hs_req->req.complete(&ep->ep,
1118 /* If we have pending request, then start it */
1119 restart = !list_empty(&ep->queue);
1121 hs_req = get_ep_head(ep);
1122 s3c_hsotg_start_req(hsotg, ep,
1133 return -ENOENT; /* currently only deal with endpoint */
1139 * s3c_hsotg_process_control - process a control request
1140 * @hsotg: The device state
1141 * @ctrl: The control request received
1143 * The controller has received the SETUP phase of a control request, and
1144 * needs to work out what to do next (and whether to pass it on to the
1147 static void s3c_hsotg_process_control(struct s3c_hsotg *hsotg,
1148 struct usb_ctrlrequest *ctrl)
1150 struct s3c_hsotg_ep *ep0 = &hsotg->eps[0];
1156 dev_dbg(hsotg->dev, "ctrl Req=%02x, Type=%02x, V=%04x, L=%04x\n",
1157 ctrl->bRequest, ctrl->bRequestType,
1158 ctrl->wValue, ctrl->wLength);
1160 /* record the direction of the request, for later use when enquing
1161 * packets onto EP0. */
1163 ep0->dir_in = (ctrl->bRequestType & USB_DIR_IN) ? 1 : 0;
1164 dev_dbg(hsotg->dev, "ctrl: dir_in=%d\n", ep0->dir_in);
1166 /* if we've no data with this request, then the last part of the
1167 * transaction is going to implicitly be IN. */
1168 if (ctrl->wLength == 0)
1171 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1172 switch (ctrl->bRequest) {
1173 case USB_REQ_SET_ADDRESS:
1174 dcfg = readl(hsotg->regs + S3C_DCFG);
1175 dcfg &= ~S3C_DCFG_DevAddr_MASK;
1176 dcfg |= ctrl->wValue << S3C_DCFG_DevAddr_SHIFT;
1177 writel(dcfg, hsotg->regs + S3C_DCFG);
1179 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1181 ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0);
1184 case USB_REQ_GET_STATUS:
1185 ret = s3c_hsotg_process_req_status(hsotg, ctrl);
1188 case USB_REQ_CLEAR_FEATURE:
1189 case USB_REQ_SET_FEATURE:
1190 ret = s3c_hsotg_process_req_feature(hsotg, ctrl);
1195 /* as a fallback, try delivering it to the driver to deal with */
1197 if (ret == 0 && hsotg->driver) {
1198 ret = hsotg->driver->setup(&hsotg->gadget, ctrl);
1200 dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
1203 /* the request is either unhandlable, or is not formatted correctly
1204 * so respond with a STALL for the status stage to indicate failure.
1211 dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
1212 reg = (ep0->dir_in) ? S3C_DIEPCTL0 : S3C_DOEPCTL0;
1214 /* S3C_DxEPCTL_Stall will be cleared by EP once it has
1215 * taken effect, so no need to clear later. */
1217 ctrl = readl(hsotg->regs + reg);
1218 ctrl |= S3C_DxEPCTL_Stall;
1219 ctrl |= S3C_DxEPCTL_CNAK;
1220 writel(ctrl, hsotg->regs + reg);
1223 "written DxEPCTL=0x%08x to %08x (DxEPCTL=0x%08x)\n",
1224 ctrl, reg, readl(hsotg->regs + reg));
1226 /* don't believe we need to anything more to get the EP
1227 * to reply with a STALL packet */
1231 static void s3c_hsotg_enqueue_setup(struct s3c_hsotg *hsotg);
1234 * s3c_hsotg_complete_setup - completion of a setup transfer
1235 * @ep: The endpoint the request was on.
1236 * @req: The request completed.
1238 * Called on completion of any requests the driver itself submitted for
1241 static void s3c_hsotg_complete_setup(struct usb_ep *ep,
1242 struct usb_request *req)
1244 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
1245 struct s3c_hsotg *hsotg = hs_ep->parent;
1247 if (req->status < 0) {
1248 dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status);
1252 if (req->actual == 0)
1253 s3c_hsotg_enqueue_setup(hsotg);
1255 s3c_hsotg_process_control(hsotg, req->buf);
1259 * s3c_hsotg_enqueue_setup - start a request for EP0 packets
1260 * @hsotg: The device state.
1262 * Enqueue a request on EP0 if necessary to received any SETUP packets
1263 * received from the host.
1265 static void s3c_hsotg_enqueue_setup(struct s3c_hsotg *hsotg)
1267 struct usb_request *req = hsotg->ctrl_req;
1268 struct s3c_hsotg_req *hs_req = our_req(req);
1271 dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__);
1275 req->buf = hsotg->ctrl_buff;
1276 req->complete = s3c_hsotg_complete_setup;
1278 if (!list_empty(&hs_req->queue)) {
1279 dev_dbg(hsotg->dev, "%s already queued???\n", __func__);
1283 hsotg->eps[0].dir_in = 0;
1285 ret = s3c_hsotg_ep_queue(&hsotg->eps[0].ep, req, GFP_ATOMIC);
1287 dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret);
1288 /* Don't think there's much we can do other than watch the
1294 * s3c_hsotg_complete_request - complete a request given to us
1295 * @hsotg: The device state.
1296 * @hs_ep: The endpoint the request was on.
1297 * @hs_req: The request to complete.
1298 * @result: The result code (0 => Ok, otherwise errno)
1300 * The given request has finished, so call the necessary completion
1301 * if it has one and then look to see if we can start a new request
1304 * Note, expects the ep to already be locked as appropriate.
1306 static void s3c_hsotg_complete_request(struct s3c_hsotg *hsotg,
1307 struct s3c_hsotg_ep *hs_ep,
1308 struct s3c_hsotg_req *hs_req,
1314 dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__);
1318 dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n",
1319 hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete);
1321 /* only replace the status if we've not already set an error
1322 * from a previous transaction */
1324 if (hs_req->req.status == -EINPROGRESS)
1325 hs_req->req.status = result;
1328 list_del_init(&hs_req->queue);
1330 if (using_dma(hsotg))
1331 s3c_hsotg_unmap_dma(hsotg, hs_ep, hs_req);
1333 /* call the complete request with the locks off, just in case the
1334 * request tries to queue more work for this endpoint. */
1336 if (hs_req->req.complete) {
1337 spin_unlock(&hs_ep->lock);
1338 hs_req->req.complete(&hs_ep->ep, &hs_req->req);
1339 spin_lock(&hs_ep->lock);
1342 /* Look to see if there is anything else to do. Note, the completion
1343 * of the previous request may have caused a new request to be started
1344 * so be careful when doing this. */
1346 if (!hs_ep->req && result >= 0) {
1347 restart = !list_empty(&hs_ep->queue);
1349 hs_req = get_ep_head(hs_ep);
1350 s3c_hsotg_start_req(hsotg, hs_ep, hs_req, false);
1356 * s3c_hsotg_complete_request_lock - complete a request given to us (locked)
1357 * @hsotg: The device state.
1358 * @hs_ep: The endpoint the request was on.
1359 * @hs_req: The request to complete.
1360 * @result: The result code (0 => Ok, otherwise errno)
1362 * See s3c_hsotg_complete_request(), but called with the endpoint's
1365 static void s3c_hsotg_complete_request_lock(struct s3c_hsotg *hsotg,
1366 struct s3c_hsotg_ep *hs_ep,
1367 struct s3c_hsotg_req *hs_req,
1370 unsigned long flags;
1372 spin_lock_irqsave(&hs_ep->lock, flags);
1373 s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
1374 spin_unlock_irqrestore(&hs_ep->lock, flags);
1378 * s3c_hsotg_rx_data - receive data from the FIFO for an endpoint
1379 * @hsotg: The device state.
1380 * @ep_idx: The endpoint index for the data
1381 * @size: The size of data in the fifo, in bytes
1383 * The FIFO status shows there is data to read from the FIFO for a given
1384 * endpoint, so sort out whether we need to read the data into a request
1385 * that has been made for that endpoint.
1387 static void s3c_hsotg_rx_data(struct s3c_hsotg *hsotg, int ep_idx, int size)
1389 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[ep_idx];
1390 struct s3c_hsotg_req *hs_req = hs_ep->req;
1391 void __iomem *fifo = hsotg->regs + S3C_EPFIFO(ep_idx);
1397 u32 epctl = readl(hsotg->regs + S3C_DOEPCTL(ep_idx));
1400 dev_warn(hsotg->dev,
1401 "%s: FIFO %d bytes on ep%d but no req (DxEPCTl=0x%08x)\n",
1402 __func__, size, ep_idx, epctl);
1404 /* dump the data from the FIFO, we've nothing we can do */
1405 for (ptr = 0; ptr < size; ptr += 4)
1411 spin_lock(&hs_ep->lock);
1414 read_ptr = hs_req->req.actual;
1415 max_req = hs_req->req.length - read_ptr;
1417 dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n",
1418 __func__, to_read, max_req, read_ptr, hs_req->req.length);
1420 if (to_read > max_req) {
1421 /* more data appeared than we where willing
1422 * to deal with in this request.
1425 /* currently we don't deal this */
1429 hs_ep->total_data += to_read;
1430 hs_req->req.actual += to_read;
1431 to_read = DIV_ROUND_UP(to_read, 4);
1433 /* note, we might over-write the buffer end by 3 bytes depending on
1434 * alignment of the data. */
1435 readsl(fifo, hs_req->req.buf + read_ptr, to_read);
1437 spin_unlock(&hs_ep->lock);
1441 * s3c_hsotg_send_zlp - send zero-length packet on control endpoint
1442 * @hsotg: The device instance
1443 * @req: The request currently on this endpoint
1445 * Generate a zero-length IN packet request for terminating a SETUP
1448 * Note, since we don't write any data to the TxFIFO, then it is
1449 * currently believed that we do not need to wait for any space in
1452 static void s3c_hsotg_send_zlp(struct s3c_hsotg *hsotg,
1453 struct s3c_hsotg_req *req)
1458 dev_warn(hsotg->dev, "%s: no request?\n", __func__);
1462 if (req->req.length == 0) {
1463 hsotg->eps[0].sent_zlp = 1;
1464 s3c_hsotg_enqueue_setup(hsotg);
1468 hsotg->eps[0].dir_in = 1;
1469 hsotg->eps[0].sent_zlp = 1;
1471 dev_dbg(hsotg->dev, "sending zero-length packet\n");
1473 /* issue a zero-sized packet to terminate this */
1474 writel(S3C_DxEPTSIZ_MC(1) | S3C_DxEPTSIZ_PktCnt(1) |
1475 S3C_DxEPTSIZ_XferSize(0), hsotg->regs + S3C_DIEPTSIZ(0));
1477 ctrl = readl(hsotg->regs + S3C_DIEPCTL0);
1478 ctrl |= S3C_DxEPCTL_CNAK; /* clear NAK set by core */
1479 ctrl |= S3C_DxEPCTL_EPEna; /* ensure ep enabled */
1480 ctrl |= S3C_DxEPCTL_USBActEp;
1481 writel(ctrl, hsotg->regs + S3C_DIEPCTL0);
1485 * s3c_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
1486 * @hsotg: The device instance
1487 * @epnum: The endpoint received from
1488 * @was_setup: Set if processing a SetupDone event.
1490 * The RXFIFO has delivered an OutDone event, which means that the data
1491 * transfer for an OUT endpoint has been completed, either by a short
1492 * packet or by the finish of a transfer.
1494 static void s3c_hsotg_handle_outdone(struct s3c_hsotg *hsotg,
1495 int epnum, bool was_setup)
1497 u32 epsize = readl(hsotg->regs + S3C_DOEPTSIZ(epnum));
1498 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[epnum];
1499 struct s3c_hsotg_req *hs_req = hs_ep->req;
1500 struct usb_request *req = &hs_req->req;
1501 unsigned size_left = S3C_DxEPTSIZ_XferSize_GET(epsize);
1505 dev_dbg(hsotg->dev, "%s: no request active\n", __func__);
1509 if (using_dma(hsotg)) {
1512 /* Calculate the size of the transfer by checking how much
1513 * is left in the endpoint size register and then working it
1514 * out from the amount we loaded for the transfer.
1516 * We need to do this as DMA pointers are always 32bit aligned
1517 * so may overshoot/undershoot the transfer.
1520 size_done = hs_ep->size_loaded - size_left;
1521 size_done += hs_ep->last_load;
1523 req->actual = size_done;
1526 /* if there is more request to do, schedule new transfer */
1527 if (req->actual < req->length && size_left == 0) {
1528 s3c_hsotg_start_req(hsotg, hs_ep, hs_req, true);
1532 if (req->actual < req->length && req->short_not_ok) {
1533 dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",
1534 __func__, req->actual, req->length);
1536 /* todo - what should we return here? there's no one else
1537 * even bothering to check the status. */
1541 if (!was_setup && req->complete != s3c_hsotg_complete_setup)
1542 s3c_hsotg_send_zlp(hsotg, hs_req);
1545 s3c_hsotg_complete_request_lock(hsotg, hs_ep, hs_req, result);
1549 * s3c_hsotg_read_frameno - read current frame number
1550 * @hsotg: The device instance
1552 * Return the current frame number
1554 static u32 s3c_hsotg_read_frameno(struct s3c_hsotg *hsotg)
1558 dsts = readl(hsotg->regs + S3C_DSTS);
1559 dsts &= S3C_DSTS_SOFFN_MASK;
1560 dsts >>= S3C_DSTS_SOFFN_SHIFT;
1566 * s3c_hsotg_handle_rx - RX FIFO has data
1567 * @hsotg: The device instance
1569 * The IRQ handler has detected that the RX FIFO has some data in it
1570 * that requires processing, so find out what is in there and do the
1573 * The RXFIFO is a true FIFO, the packets coming out are still in packet
1574 * chunks, so if you have x packets received on an endpoint you'll get x
1575 * FIFO events delivered, each with a packet's worth of data in it.
1577 * When using DMA, we should not be processing events from the RXFIFO
1578 * as the actual data should be sent to the memory directly and we turn
1579 * on the completion interrupts to get notifications of transfer completion.
1581 static void s3c_hsotg_handle_rx(struct s3c_hsotg *hsotg)
1583 u32 grxstsr = readl(hsotg->regs + S3C_GRXSTSP);
1584 u32 epnum, status, size;
1586 WARN_ON(using_dma(hsotg));
1588 epnum = grxstsr & S3C_GRXSTS_EPNum_MASK;
1589 status = grxstsr & S3C_GRXSTS_PktSts_MASK;
1591 size = grxstsr & S3C_GRXSTS_ByteCnt_MASK;
1592 size >>= S3C_GRXSTS_ByteCnt_SHIFT;
1595 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
1596 __func__, grxstsr, size, epnum);
1598 #define __status(x) ((x) >> S3C_GRXSTS_PktSts_SHIFT)
1600 switch (status >> S3C_GRXSTS_PktSts_SHIFT) {
1601 case __status(S3C_GRXSTS_PktSts_GlobalOutNAK):
1602 dev_dbg(hsotg->dev, "GlobalOutNAK\n");
1605 case __status(S3C_GRXSTS_PktSts_OutDone):
1606 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
1607 s3c_hsotg_read_frameno(hsotg));
1609 if (!using_dma(hsotg))
1610 s3c_hsotg_handle_outdone(hsotg, epnum, false);
1613 case __status(S3C_GRXSTS_PktSts_SetupDone):
1615 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1616 s3c_hsotg_read_frameno(hsotg),
1617 readl(hsotg->regs + S3C_DOEPCTL(0)));
1619 s3c_hsotg_handle_outdone(hsotg, epnum, true);
1622 case __status(S3C_GRXSTS_PktSts_OutRX):
1623 s3c_hsotg_rx_data(hsotg, epnum, size);
1626 case __status(S3C_GRXSTS_PktSts_SetupRX):
1628 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1629 s3c_hsotg_read_frameno(hsotg),
1630 readl(hsotg->regs + S3C_DOEPCTL(0)));
1632 s3c_hsotg_rx_data(hsotg, epnum, size);
1636 dev_warn(hsotg->dev, "%s: unknown status %08x\n",
1639 s3c_hsotg_dump(hsotg);
1645 * s3c_hsotg_ep0_mps - turn max packet size into register setting
1646 * @mps: The maximum packet size in bytes.
1648 static u32 s3c_hsotg_ep0_mps(unsigned int mps)
1652 return S3C_D0EPCTL_MPS_64;
1654 return S3C_D0EPCTL_MPS_32;
1656 return S3C_D0EPCTL_MPS_16;
1658 return S3C_D0EPCTL_MPS_8;
1661 /* bad max packet size, warn and return invalid result */
1667 * s3c_hsotg_set_ep_maxpacket - set endpoint's max-packet field
1668 * @hsotg: The driver state.
1669 * @ep: The index number of the endpoint
1670 * @mps: The maximum packet size in bytes
1672 * Configure the maximum packet size for the given endpoint, updating
1673 * the hardware control registers to reflect this.
1675 static void s3c_hsotg_set_ep_maxpacket(struct s3c_hsotg *hsotg,
1676 unsigned int ep, unsigned int mps)
1678 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[ep];
1679 void __iomem *regs = hsotg->regs;
1684 /* EP0 is a special case */
1685 mpsval = s3c_hsotg_ep0_mps(mps);
1689 if (mps >= S3C_DxEPCTL_MPS_LIMIT+1)
1695 hs_ep->ep.maxpacket = mps;
1697 /* update both the in and out endpoint controldir_ registers, even
1698 * if one of the directions may not be in use. */
1700 reg = readl(regs + S3C_DIEPCTL(ep));
1701 reg &= ~S3C_DxEPCTL_MPS_MASK;
1703 writel(reg, regs + S3C_DIEPCTL(ep));
1706 reg = readl(regs + S3C_DOEPCTL(ep));
1707 reg &= ~S3C_DxEPCTL_MPS_MASK;
1709 writel(reg, regs + S3C_DOEPCTL(ep));
1715 dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps);
1719 * s3c_hsotg_txfifo_flush - flush Tx FIFO
1720 * @hsotg: The driver state
1721 * @idx: The index for the endpoint (0..15)
1723 static void s3c_hsotg_txfifo_flush(struct s3c_hsotg *hsotg, unsigned int idx)
1728 writel(S3C_GRSTCTL_TxFNum(idx) | S3C_GRSTCTL_TxFFlsh,
1729 hsotg->regs + S3C_GRSTCTL);
1731 /* wait until the fifo is flushed */
1735 val = readl(hsotg->regs + S3C_GRSTCTL);
1737 if ((val & (S3C_GRSTCTL_TxFFlsh)) == 0)
1740 if (--timeout == 0) {
1742 "%s: timeout flushing fifo (GRSTCTL=%08x)\n",
1751 * s3c_hsotg_trytx - check to see if anything needs transmitting
1752 * @hsotg: The driver state
1753 * @hs_ep: The driver endpoint to check.
1755 * Check to see if there is a request that has data to send, and if so
1756 * make an attempt to write data into the FIFO.
1758 static int s3c_hsotg_trytx(struct s3c_hsotg *hsotg,
1759 struct s3c_hsotg_ep *hs_ep)
1761 struct s3c_hsotg_req *hs_req = hs_ep->req;
1763 if (!hs_ep->dir_in || !hs_req)
1766 if (hs_req->req.actual < hs_req->req.length) {
1767 dev_dbg(hsotg->dev, "trying to write more for ep%d\n",
1769 return s3c_hsotg_write_fifo(hsotg, hs_ep, hs_req);
1776 * s3c_hsotg_complete_in - complete IN transfer
1777 * @hsotg: The device state.
1778 * @hs_ep: The endpoint that has just completed.
1780 * An IN transfer has been completed, update the transfer's state and then
1781 * call the relevant completion routines.
1783 static void s3c_hsotg_complete_in(struct s3c_hsotg *hsotg,
1784 struct s3c_hsotg_ep *hs_ep)
1786 struct s3c_hsotg_req *hs_req = hs_ep->req;
1787 u32 epsize = readl(hsotg->regs + S3C_DIEPTSIZ(hs_ep->index));
1788 int size_left, size_done;
1791 dev_dbg(hsotg->dev, "XferCompl but no req\n");
1795 /* Calculate the size of the transfer by checking how much is left
1796 * in the endpoint size register and then working it out from
1797 * the amount we loaded for the transfer.
1799 * We do this even for DMA, as the transfer may have incremented
1800 * past the end of the buffer (DMA transfers are always 32bit
1804 size_left = S3C_DxEPTSIZ_XferSize_GET(epsize);
1806 size_done = hs_ep->size_loaded - size_left;
1807 size_done += hs_ep->last_load;
1809 if (hs_req->req.actual != size_done)
1810 dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n",
1811 __func__, hs_req->req.actual, size_done);
1813 hs_req->req.actual = size_done;
1815 /* if we did all of the transfer, and there is more data left
1816 * around, then try restarting the rest of the request */
1818 if (!size_left && hs_req->req.actual < hs_req->req.length) {
1819 dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__);
1820 s3c_hsotg_start_req(hsotg, hs_ep, hs_req, true);
1822 s3c_hsotg_complete_request_lock(hsotg, hs_ep, hs_req, 0);
1826 * s3c_hsotg_epint - handle an in/out endpoint interrupt
1827 * @hsotg: The driver state
1828 * @idx: The index for the endpoint (0..15)
1829 * @dir_in: Set if this is an IN endpoint
1831 * Process and clear any interrupt pending for an individual endpoint
1833 static void s3c_hsotg_epint(struct s3c_hsotg *hsotg, unsigned int idx,
1836 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[idx];
1837 u32 epint_reg = dir_in ? S3C_DIEPINT(idx) : S3C_DOEPINT(idx);
1838 u32 epctl_reg = dir_in ? S3C_DIEPCTL(idx) : S3C_DOEPCTL(idx);
1839 u32 epsiz_reg = dir_in ? S3C_DIEPTSIZ(idx) : S3C_DOEPTSIZ(idx);
1842 ints = readl(hsotg->regs + epint_reg);
1844 /* Clear endpoint interrupts */
1845 writel(ints, hsotg->regs + epint_reg);
1847 dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
1848 __func__, idx, dir_in ? "in" : "out", ints);
1850 if (ints & S3C_DxEPINT_XferCompl) {
1852 "%s: XferCompl: DxEPCTL=0x%08x, DxEPTSIZ=%08x\n",
1853 __func__, readl(hsotg->regs + epctl_reg),
1854 readl(hsotg->regs + epsiz_reg));
1856 /* we get OutDone from the FIFO, so we only need to look
1857 * at completing IN requests here */
1859 s3c_hsotg_complete_in(hsotg, hs_ep);
1861 if (idx == 0 && !hs_ep->req)
1862 s3c_hsotg_enqueue_setup(hsotg);
1863 } else if (using_dma(hsotg)) {
1864 /* We're using DMA, we need to fire an OutDone here
1865 * as we ignore the RXFIFO. */
1867 s3c_hsotg_handle_outdone(hsotg, idx, false);
1871 if (ints & S3C_DxEPINT_EPDisbld) {
1872 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
1875 int epctl = readl(hsotg->regs + epctl_reg);
1877 s3c_hsotg_txfifo_flush(hsotg, idx);
1879 if ((epctl & S3C_DxEPCTL_Stall) &&
1880 (epctl & S3C_DxEPCTL_EPType_Bulk)) {
1881 int dctl = readl(hsotg->regs + S3C_DCTL);
1883 dctl |= S3C_DCTL_CGNPInNAK;
1884 writel(dctl, hsotg->regs + S3C_DCTL);
1889 if (ints & S3C_DxEPINT_AHBErr)
1890 dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
1892 if (ints & S3C_DxEPINT_Setup) { /* Setup or Timeout */
1893 dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__);
1895 if (using_dma(hsotg) && idx == 0) {
1896 /* this is the notification we've received a
1897 * setup packet. In non-DMA mode we'd get this
1898 * from the RXFIFO, instead we need to process
1899 * the setup here. */
1904 s3c_hsotg_handle_outdone(hsotg, 0, true);
1908 if (ints & S3C_DxEPINT_Back2BackSetup)
1909 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
1912 /* not sure if this is important, but we'll clear it anyway
1914 if (ints & S3C_DIEPMSK_INTknTXFEmpMsk) {
1915 dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
1919 /* this probably means something bad is happening */
1920 if (ints & S3C_DIEPMSK_INTknEPMisMsk) {
1921 dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
1925 /* FIFO has space or is empty (see GAHBCFG) */
1926 if (hsotg->dedicated_fifos &&
1927 ints & S3C_DIEPMSK_TxFIFOEmpty) {
1928 dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n",
1930 if (!using_dma(hsotg))
1931 s3c_hsotg_trytx(hsotg, hs_ep);
1937 * s3c_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
1938 * @hsotg: The device state.
1940 * Handle updating the device settings after the enumeration phase has
1943 static void s3c_hsotg_irq_enumdone(struct s3c_hsotg *hsotg)
1945 u32 dsts = readl(hsotg->regs + S3C_DSTS);
1946 int ep0_mps = 0, ep_mps;
1948 /* This should signal the finish of the enumeration phase
1949 * of the USB handshaking, so we should now know what rate
1950 * we connected at. */
1952 dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts);
1954 /* note, since we're limited by the size of transfer on EP0, and
1955 * it seems IN transfers must be a even number of packets we do
1956 * not advertise a 64byte MPS on EP0. */
1958 /* catch both EnumSpd_FS and EnumSpd_FS48 */
1959 switch (dsts & S3C_DSTS_EnumSpd_MASK) {
1960 case S3C_DSTS_EnumSpd_FS:
1961 case S3C_DSTS_EnumSpd_FS48:
1962 hsotg->gadget.speed = USB_SPEED_FULL;
1963 ep0_mps = EP0_MPS_LIMIT;
1967 case S3C_DSTS_EnumSpd_HS:
1968 hsotg->gadget.speed = USB_SPEED_HIGH;
1969 ep0_mps = EP0_MPS_LIMIT;
1973 case S3C_DSTS_EnumSpd_LS:
1974 hsotg->gadget.speed = USB_SPEED_LOW;
1975 /* note, we don't actually support LS in this driver at the
1976 * moment, and the documentation seems to imply that it isn't
1977 * supported by the PHYs on some of the devices.
1981 dev_info(hsotg->dev, "new device is %s\n",
1982 usb_speed_string(hsotg->gadget.speed));
1984 /* we should now know the maximum packet size for an
1985 * endpoint, so set the endpoints to a default value. */
1989 s3c_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps);
1990 for (i = 1; i < S3C_HSOTG_EPS; i++)
1991 s3c_hsotg_set_ep_maxpacket(hsotg, i, ep_mps);
1994 /* ensure after enumeration our EP0 is active */
1996 s3c_hsotg_enqueue_setup(hsotg);
1998 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
1999 readl(hsotg->regs + S3C_DIEPCTL0),
2000 readl(hsotg->regs + S3C_DOEPCTL0));
2004 * kill_all_requests - remove all requests from the endpoint's queue
2005 * @hsotg: The device state.
2006 * @ep: The endpoint the requests may be on.
2007 * @result: The result code to use.
2008 * @force: Force removal of any current requests
2010 * Go through the requests on the given endpoint and mark them
2011 * completed with the given result code.
2013 static void kill_all_requests(struct s3c_hsotg *hsotg,
2014 struct s3c_hsotg_ep *ep,
2015 int result, bool force)
2017 struct s3c_hsotg_req *req, *treq;
2018 unsigned long flags;
2020 spin_lock_irqsave(&ep->lock, flags);
2022 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
2023 /* currently, we can't do much about an already
2024 * running request on an in endpoint */
2026 if (ep->req == req && ep->dir_in && !force)
2029 s3c_hsotg_complete_request(hsotg, ep, req,
2033 spin_unlock_irqrestore(&ep->lock, flags);
2036 #define call_gadget(_hs, _entry) \
2037 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \
2038 (_hs)->driver && (_hs)->driver->_entry) \
2039 (_hs)->driver->_entry(&(_hs)->gadget);
2042 * s3c_hsotg_disconnect_irq - disconnect irq service
2043 * @hsotg: The device state.
2045 * A disconnect IRQ has been received, meaning that the host has
2046 * lost contact with the bus. Remove all current transactions
2047 * and signal the gadget driver that this has happened.
2049 static void s3c_hsotg_disconnect_irq(struct s3c_hsotg *hsotg)
2053 for (ep = 0; ep < S3C_HSOTG_EPS; ep++)
2054 kill_all_requests(hsotg, &hsotg->eps[ep], -ESHUTDOWN, true);
2056 call_gadget(hsotg, disconnect);
2060 * s3c_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
2061 * @hsotg: The device state:
2062 * @periodic: True if this is a periodic FIFO interrupt
2064 static void s3c_hsotg_irq_fifoempty(struct s3c_hsotg *hsotg, bool periodic)
2066 struct s3c_hsotg_ep *ep;
2069 /* look through for any more data to transmit */
2071 for (epno = 0; epno < S3C_HSOTG_EPS; epno++) {
2072 ep = &hsotg->eps[epno];
2077 if ((periodic && !ep->periodic) ||
2078 (!periodic && ep->periodic))
2081 ret = s3c_hsotg_trytx(hsotg, ep);
2087 static struct s3c_hsotg *our_hsotg;
2089 /* IRQ flags which will trigger a retry around the IRQ loop */
2090 #define IRQ_RETRY_MASK (S3C_GINTSTS_NPTxFEmp | \
2091 S3C_GINTSTS_PTxFEmp | \
2095 * s3c_hsotg_irq - handle device interrupt
2096 * @irq: The IRQ number triggered
2097 * @pw: The pw value when registered the handler.
2099 static irqreturn_t s3c_hsotg_irq(int irq, void *pw)
2101 struct s3c_hsotg *hsotg = pw;
2102 int retry_count = 8;
2107 gintsts = readl(hsotg->regs + S3C_GINTSTS);
2108 gintmsk = readl(hsotg->regs + S3C_GINTMSK);
2110 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
2111 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
2115 if (gintsts & S3C_GINTSTS_OTGInt) {
2116 u32 otgint = readl(hsotg->regs + S3C_GOTGINT);
2118 dev_info(hsotg->dev, "OTGInt: %08x\n", otgint);
2120 writel(otgint, hsotg->regs + S3C_GOTGINT);
2123 if (gintsts & S3C_GINTSTS_DisconnInt) {
2124 dev_dbg(hsotg->dev, "%s: DisconnInt\n", __func__);
2125 writel(S3C_GINTSTS_DisconnInt, hsotg->regs + S3C_GINTSTS);
2127 s3c_hsotg_disconnect_irq(hsotg);
2130 if (gintsts & S3C_GINTSTS_SessReqInt) {
2131 dev_dbg(hsotg->dev, "%s: SessReqInt\n", __func__);
2132 writel(S3C_GINTSTS_SessReqInt, hsotg->regs + S3C_GINTSTS);
2135 if (gintsts & S3C_GINTSTS_EnumDone) {
2136 writel(S3C_GINTSTS_EnumDone, hsotg->regs + S3C_GINTSTS);
2138 s3c_hsotg_irq_enumdone(hsotg);
2141 if (gintsts & S3C_GINTSTS_ConIDStsChng) {
2142 dev_dbg(hsotg->dev, "ConIDStsChg (DSTS=0x%08x, GOTCTL=%08x)\n",
2143 readl(hsotg->regs + S3C_DSTS),
2144 readl(hsotg->regs + S3C_GOTGCTL));
2146 writel(S3C_GINTSTS_ConIDStsChng, hsotg->regs + S3C_GINTSTS);
2149 if (gintsts & (S3C_GINTSTS_OEPInt | S3C_GINTSTS_IEPInt)) {
2150 u32 daint = readl(hsotg->regs + S3C_DAINT);
2151 u32 daint_out = daint >> S3C_DAINT_OutEP_SHIFT;
2152 u32 daint_in = daint & ~(daint_out << S3C_DAINT_OutEP_SHIFT);
2155 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
2157 for (ep = 0; ep < 15 && daint_out; ep++, daint_out >>= 1) {
2159 s3c_hsotg_epint(hsotg, ep, 0);
2162 for (ep = 0; ep < 15 && daint_in; ep++, daint_in >>= 1) {
2164 s3c_hsotg_epint(hsotg, ep, 1);
2168 if (gintsts & S3C_GINTSTS_USBRst) {
2169 dev_info(hsotg->dev, "%s: USBRst\n", __func__);
2170 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
2171 readl(hsotg->regs + S3C_GNPTXSTS));
2173 writel(S3C_GINTSTS_USBRst, hsotg->regs + S3C_GINTSTS);
2175 kill_all_requests(hsotg, &hsotg->eps[0], -ECONNRESET, true);
2177 /* it seems after a reset we can end up with a situation
2178 * where the TXFIFO still has data in it... the docs
2179 * suggest resetting all the fifos, so use the init_fifo
2180 * code to relayout and flush the fifos.
2183 s3c_hsotg_init_fifo(hsotg);
2185 s3c_hsotg_enqueue_setup(hsotg);
2188 /* check both FIFOs */
2190 if (gintsts & S3C_GINTSTS_NPTxFEmp) {
2191 dev_dbg(hsotg->dev, "NPTxFEmp\n");
2193 /* Disable the interrupt to stop it happening again
2194 * unless one of these endpoint routines decides that
2195 * it needs re-enabling */
2197 s3c_hsotg_disable_gsint(hsotg, S3C_GINTSTS_NPTxFEmp);
2198 s3c_hsotg_irq_fifoempty(hsotg, false);
2201 if (gintsts & S3C_GINTSTS_PTxFEmp) {
2202 dev_dbg(hsotg->dev, "PTxFEmp\n");
2204 /* See note in S3C_GINTSTS_NPTxFEmp */
2206 s3c_hsotg_disable_gsint(hsotg, S3C_GINTSTS_PTxFEmp);
2207 s3c_hsotg_irq_fifoempty(hsotg, true);
2210 if (gintsts & S3C_GINTSTS_RxFLvl) {
2211 /* note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
2212 * we need to retry s3c_hsotg_handle_rx if this is still
2215 s3c_hsotg_handle_rx(hsotg);
2218 if (gintsts & S3C_GINTSTS_ModeMis) {
2219 dev_warn(hsotg->dev, "warning, mode mismatch triggered\n");
2220 writel(S3C_GINTSTS_ModeMis, hsotg->regs + S3C_GINTSTS);
2223 if (gintsts & S3C_GINTSTS_USBSusp) {
2224 dev_info(hsotg->dev, "S3C_GINTSTS_USBSusp\n");
2225 writel(S3C_GINTSTS_USBSusp, hsotg->regs + S3C_GINTSTS);
2227 call_gadget(hsotg, suspend);
2230 if (gintsts & S3C_GINTSTS_WkUpInt) {
2231 dev_info(hsotg->dev, "S3C_GINTSTS_WkUpIn\n");
2232 writel(S3C_GINTSTS_WkUpInt, hsotg->regs + S3C_GINTSTS);
2234 call_gadget(hsotg, resume);
2237 if (gintsts & S3C_GINTSTS_ErlySusp) {
2238 dev_dbg(hsotg->dev, "S3C_GINTSTS_ErlySusp\n");
2239 writel(S3C_GINTSTS_ErlySusp, hsotg->regs + S3C_GINTSTS);
2242 /* these next two seem to crop-up occasionally causing the core
2243 * to shutdown the USB transfer, so try clearing them and logging
2244 * the occurrence. */
2246 if (gintsts & S3C_GINTSTS_GOUTNakEff) {
2247 dev_info(hsotg->dev, "GOUTNakEff triggered\n");
2249 writel(S3C_DCTL_CGOUTNak, hsotg->regs + S3C_DCTL);
2251 s3c_hsotg_dump(hsotg);
2254 if (gintsts & S3C_GINTSTS_GINNakEff) {
2255 dev_info(hsotg->dev, "GINNakEff triggered\n");
2257 writel(S3C_DCTL_CGNPInNAK, hsotg->regs + S3C_DCTL);
2259 s3c_hsotg_dump(hsotg);
2262 /* if we've had fifo events, we should try and go around the
2263 * loop again to see if there's any point in returning yet. */
2265 if (gintsts & IRQ_RETRY_MASK && --retry_count > 0)
2272 * s3c_hsotg_ep_enable - enable the given endpoint
2273 * @ep: The USB endpint to configure
2274 * @desc: The USB endpoint descriptor to configure with.
2276 * This is called from the USB gadget code's usb_ep_enable().
2278 static int s3c_hsotg_ep_enable(struct usb_ep *ep,
2279 const struct usb_endpoint_descriptor *desc)
2281 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2282 struct s3c_hsotg *hsotg = hs_ep->parent;
2283 unsigned long flags;
2284 int index = hs_ep->index;
2292 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
2293 __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes,
2294 desc->wMaxPacketSize, desc->bInterval);
2296 /* not to be called for EP0 */
2297 WARN_ON(index == 0);
2299 dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
2300 if (dir_in != hs_ep->dir_in) {
2301 dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__);
2305 mps = usb_endpoint_maxp(desc);
2307 /* note, we handle this here instead of s3c_hsotg_set_ep_maxpacket */
2309 epctrl_reg = dir_in ? S3C_DIEPCTL(index) : S3C_DOEPCTL(index);
2310 epctrl = readl(hsotg->regs + epctrl_reg);
2312 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
2313 __func__, epctrl, epctrl_reg);
2315 spin_lock_irqsave(&hs_ep->lock, flags);
2317 epctrl &= ~(S3C_DxEPCTL_EPType_MASK | S3C_DxEPCTL_MPS_MASK);
2318 epctrl |= S3C_DxEPCTL_MPS(mps);
2320 /* mark the endpoint as active, otherwise the core may ignore
2321 * transactions entirely for this endpoint */
2322 epctrl |= S3C_DxEPCTL_USBActEp;
2324 /* set the NAK status on the endpoint, otherwise we might try and
2325 * do something with data that we've yet got a request to process
2326 * since the RXFIFO will take data for an endpoint even if the
2327 * size register hasn't been set.
2330 epctrl |= S3C_DxEPCTL_SNAK;
2332 /* update the endpoint state */
2333 hs_ep->ep.maxpacket = mps;
2335 /* default, set to non-periodic */
2336 hs_ep->periodic = 0;
2338 switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
2339 case USB_ENDPOINT_XFER_ISOC:
2340 dev_err(hsotg->dev, "no current ISOC support\n");
2344 case USB_ENDPOINT_XFER_BULK:
2345 epctrl |= S3C_DxEPCTL_EPType_Bulk;
2348 case USB_ENDPOINT_XFER_INT:
2350 /* Allocate our TxFNum by simply using the index
2351 * of the endpoint for the moment. We could do
2352 * something better if the host indicates how
2353 * many FIFOs we are expecting to use. */
2355 hs_ep->periodic = 1;
2356 epctrl |= S3C_DxEPCTL_TxFNum(index);
2359 epctrl |= S3C_DxEPCTL_EPType_Intterupt;
2362 case USB_ENDPOINT_XFER_CONTROL:
2363 epctrl |= S3C_DxEPCTL_EPType_Control;
2367 /* if the hardware has dedicated fifos, we must give each IN EP
2368 * a unique tx-fifo even if it is non-periodic.
2370 if (dir_in && hsotg->dedicated_fifos)
2371 epctrl |= S3C_DxEPCTL_TxFNum(index);
2373 /* for non control endpoints, set PID to D0 */
2375 epctrl |= S3C_DxEPCTL_SetD0PID;
2377 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
2380 writel(epctrl, hsotg->regs + epctrl_reg);
2381 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
2382 __func__, readl(hsotg->regs + epctrl_reg));
2384 /* enable the endpoint interrupt */
2385 s3c_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
2388 spin_unlock_irqrestore(&hs_ep->lock, flags);
2392 static int s3c_hsotg_ep_disable(struct usb_ep *ep)
2394 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2395 struct s3c_hsotg *hsotg = hs_ep->parent;
2396 int dir_in = hs_ep->dir_in;
2397 int index = hs_ep->index;
2398 unsigned long flags;
2402 dev_info(hsotg->dev, "%s(ep %p)\n", __func__, ep);
2404 if (ep == &hsotg->eps[0].ep) {
2405 dev_err(hsotg->dev, "%s: called for ep0\n", __func__);
2409 epctrl_reg = dir_in ? S3C_DIEPCTL(index) : S3C_DOEPCTL(index);
2411 /* terminate all requests with shutdown */
2412 kill_all_requests(hsotg, hs_ep, -ESHUTDOWN, false);
2414 spin_lock_irqsave(&hs_ep->lock, flags);
2416 ctrl = readl(hsotg->regs + epctrl_reg);
2417 ctrl &= ~S3C_DxEPCTL_EPEna;
2418 ctrl &= ~S3C_DxEPCTL_USBActEp;
2419 ctrl |= S3C_DxEPCTL_SNAK;
2421 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
2422 writel(ctrl, hsotg->regs + epctrl_reg);
2424 /* disable endpoint interrupts */
2425 s3c_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
2427 spin_unlock_irqrestore(&hs_ep->lock, flags);
2432 * on_list - check request is on the given endpoint
2433 * @ep: The endpoint to check.
2434 * @test: The request to test if it is on the endpoint.
2436 static bool on_list(struct s3c_hsotg_ep *ep, struct s3c_hsotg_req *test)
2438 struct s3c_hsotg_req *req, *treq;
2440 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
2448 static int s3c_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
2450 struct s3c_hsotg_req *hs_req = our_req(req);
2451 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2452 struct s3c_hsotg *hs = hs_ep->parent;
2453 unsigned long flags;
2455 dev_info(hs->dev, "ep_dequeue(%p,%p)\n", ep, req);
2457 spin_lock_irqsave(&hs_ep->lock, flags);
2459 if (!on_list(hs_ep, hs_req)) {
2460 spin_unlock_irqrestore(&hs_ep->lock, flags);
2464 s3c_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET);
2465 spin_unlock_irqrestore(&hs_ep->lock, flags);
2470 static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value)
2472 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2473 struct s3c_hsotg *hs = hs_ep->parent;
2474 int index = hs_ep->index;
2475 unsigned long irqflags;
2480 dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value);
2482 spin_lock_irqsave(&hs_ep->lock, irqflags);
2484 /* write both IN and OUT control registers */
2486 epreg = S3C_DIEPCTL(index);
2487 epctl = readl(hs->regs + epreg);
2490 epctl |= S3C_DxEPCTL_Stall + S3C_DxEPCTL_SNAK;
2491 if (epctl & S3C_DxEPCTL_EPEna)
2492 epctl |= S3C_DxEPCTL_EPDis;
2494 epctl &= ~S3C_DxEPCTL_Stall;
2495 xfertype = epctl & S3C_DxEPCTL_EPType_MASK;
2496 if (xfertype == S3C_DxEPCTL_EPType_Bulk ||
2497 xfertype == S3C_DxEPCTL_EPType_Intterupt)
2498 epctl |= S3C_DxEPCTL_SetD0PID;
2501 writel(epctl, hs->regs + epreg);
2503 epreg = S3C_DOEPCTL(index);
2504 epctl = readl(hs->regs + epreg);
2507 epctl |= S3C_DxEPCTL_Stall;
2509 epctl &= ~S3C_DxEPCTL_Stall;
2510 xfertype = epctl & S3C_DxEPCTL_EPType_MASK;
2511 if (xfertype == S3C_DxEPCTL_EPType_Bulk ||
2512 xfertype == S3C_DxEPCTL_EPType_Intterupt)
2513 epctl |= S3C_DxEPCTL_SetD0PID;
2516 writel(epctl, hs->regs + epreg);
2518 spin_unlock_irqrestore(&hs_ep->lock, irqflags);
2523 static struct usb_ep_ops s3c_hsotg_ep_ops = {
2524 .enable = s3c_hsotg_ep_enable,
2525 .disable = s3c_hsotg_ep_disable,
2526 .alloc_request = s3c_hsotg_ep_alloc_request,
2527 .free_request = s3c_hsotg_ep_free_request,
2528 .queue = s3c_hsotg_ep_queue,
2529 .dequeue = s3c_hsotg_ep_dequeue,
2530 .set_halt = s3c_hsotg_ep_sethalt,
2531 /* note, don't believe we have any call for the fifo routines */
2535 * s3c_hsotg_corereset - issue softreset to the core
2536 * @hsotg: The device state
2538 * Issue a soft reset to the core, and await the core finishing it.
2540 static int s3c_hsotg_corereset(struct s3c_hsotg *hsotg)
2545 dev_dbg(hsotg->dev, "resetting core\n");
2547 /* issue soft reset */
2548 writel(S3C_GRSTCTL_CSftRst, hsotg->regs + S3C_GRSTCTL);
2552 grstctl = readl(hsotg->regs + S3C_GRSTCTL);
2553 } while ((grstctl & S3C_GRSTCTL_CSftRst) && timeout-- > 0);
2555 if (grstctl & S3C_GRSTCTL_CSftRst) {
2556 dev_err(hsotg->dev, "Failed to get CSftRst asserted\n");
2563 u32 grstctl = readl(hsotg->regs + S3C_GRSTCTL);
2565 if (timeout-- < 0) {
2566 dev_info(hsotg->dev,
2567 "%s: reset failed, GRSTCTL=%08x\n",
2572 if (!(grstctl & S3C_GRSTCTL_AHBIdle))
2575 break; /* reset done */
2578 dev_dbg(hsotg->dev, "reset successful\n");
2583 * s3c_hsotg_phy_enable - enable platform phy dev
2585 * @param: The driver state
2587 * A wrapper for platform code responsible for controlling
2588 * low-level USB code
2590 static void s3c_hsotg_phy_enable(struct s3c_hsotg *hsotg)
2592 struct platform_device *pdev = to_platform_device(hsotg->dev);
2594 dev_dbg(hsotg->dev, "pdev 0x%p\n", pdev);
2595 if (hsotg->plat->phy_init)
2596 hsotg->plat->phy_init(pdev, hsotg->plat->phy_type);
2600 * s3c_hsotg_phy_disable - disable platform phy dev
2602 * @param: The driver state
2604 * A wrapper for platform code responsible for controlling
2605 * low-level USB code
2607 static void s3c_hsotg_phy_disable(struct s3c_hsotg *hsotg)
2609 struct platform_device *pdev = to_platform_device(hsotg->dev);
2611 if (hsotg->plat->phy_exit)
2612 hsotg->plat->phy_exit(pdev, hsotg->plat->phy_type);
2615 static int s3c_hsotg_start(struct usb_gadget_driver *driver,
2616 int (*bind)(struct usb_gadget *))
2618 struct s3c_hsotg *hsotg = our_hsotg;
2622 printk(KERN_ERR "%s: called with no device\n", __func__);
2627 dev_err(hsotg->dev, "%s: no driver\n", __func__);
2631 if (driver->max_speed < USB_SPEED_FULL)
2632 dev_err(hsotg->dev, "%s: bad speed\n", __func__);
2634 if (!bind || !driver->setup) {
2635 dev_err(hsotg->dev, "%s: missing entry points\n", __func__);
2639 WARN_ON(hsotg->driver);
2641 driver->driver.bus = NULL;
2642 hsotg->driver = driver;
2643 hsotg->gadget.dev.driver = &driver->driver;
2644 hsotg->gadget.dev.dma_mask = hsotg->dev->dma_mask;
2645 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
2647 ret = device_add(&hsotg->gadget.dev);
2649 dev_err(hsotg->dev, "failed to register gadget device\n");
2653 ret = bind(&hsotg->gadget);
2655 dev_err(hsotg->dev, "failed bind %s\n", driver->driver.name);
2657 hsotg->gadget.dev.driver = NULL;
2658 hsotg->driver = NULL;
2662 /* we must now enable ep0 ready for host detection and then
2663 * set configuration. */
2665 s3c_hsotg_corereset(hsotg);
2667 /* set the PLL on, remove the HNP/SRP and set the PHY */
2668 writel(S3C_GUSBCFG_PHYIf16 | S3C_GUSBCFG_TOutCal(7) |
2669 (0x5 << 10), hsotg->regs + S3C_GUSBCFG);
2671 /* looks like soft-reset changes state of FIFOs */
2672 s3c_hsotg_init_fifo(hsotg);
2674 __orr32(hsotg->regs + S3C_DCTL, S3C_DCTL_SftDiscon);
2676 writel(1 << 18 | S3C_DCFG_DevSpd_HS, hsotg->regs + S3C_DCFG);
2678 /* Clear any pending OTG interrupts */
2679 writel(0xffffffff, hsotg->regs + S3C_GOTGINT);
2681 /* Clear any pending interrupts */
2682 writel(0xffffffff, hsotg->regs + S3C_GINTSTS);
2684 writel(S3C_GINTSTS_DisconnInt | S3C_GINTSTS_SessReqInt |
2685 S3C_GINTSTS_ConIDStsChng | S3C_GINTSTS_USBRst |
2686 S3C_GINTSTS_EnumDone | S3C_GINTSTS_OTGInt |
2687 S3C_GINTSTS_USBSusp | S3C_GINTSTS_WkUpInt |
2688 S3C_GINTSTS_GOUTNakEff | S3C_GINTSTS_GINNakEff |
2689 S3C_GINTSTS_ErlySusp,
2690 hsotg->regs + S3C_GINTMSK);
2692 if (using_dma(hsotg))
2693 writel(S3C_GAHBCFG_GlblIntrEn | S3C_GAHBCFG_DMAEn |
2694 S3C_GAHBCFG_HBstLen_Incr4,
2695 hsotg->regs + S3C_GAHBCFG);
2697 writel(S3C_GAHBCFG_GlblIntrEn, hsotg->regs + S3C_GAHBCFG);
2699 /* Enabling INTknTXFEmpMsk here seems to be a big mistake, we end
2700 * up being flooded with interrupts if the host is polling the
2701 * endpoint to try and read data. */
2703 writel(S3C_DIEPMSK_TimeOUTMsk | S3C_DIEPMSK_AHBErrMsk |
2704 S3C_DIEPMSK_INTknEPMisMsk |
2705 S3C_DIEPMSK_EPDisbldMsk | S3C_DIEPMSK_XferComplMsk |
2706 ((hsotg->dedicated_fifos) ? S3C_DIEPMSK_TxFIFOEmpty : 0),
2707 hsotg->regs + S3C_DIEPMSK);
2709 /* don't need XferCompl, we get that from RXFIFO in slave mode. In
2710 * DMA mode we may need this. */
2711 writel(S3C_DOEPMSK_SetupMsk | S3C_DOEPMSK_AHBErrMsk |
2712 S3C_DOEPMSK_EPDisbldMsk |
2713 (using_dma(hsotg) ? (S3C_DIEPMSK_XferComplMsk |
2714 S3C_DIEPMSK_TimeOUTMsk) : 0),
2715 hsotg->regs + S3C_DOEPMSK);
2717 writel(0, hsotg->regs + S3C_DAINTMSK);
2719 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2720 readl(hsotg->regs + S3C_DIEPCTL0),
2721 readl(hsotg->regs + S3C_DOEPCTL0));
2723 /* enable in and out endpoint interrupts */
2724 s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_OEPInt | S3C_GINTSTS_IEPInt);
2726 /* Enable the RXFIFO when in slave mode, as this is how we collect
2727 * the data. In DMA mode, we get events from the FIFO but also
2728 * things we cannot process, so do not use it. */
2729 if (!using_dma(hsotg))
2730 s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_RxFLvl);
2732 /* Enable interrupts for EP0 in and out */
2733 s3c_hsotg_ctrl_epint(hsotg, 0, 0, 1);
2734 s3c_hsotg_ctrl_epint(hsotg, 0, 1, 1);
2736 __orr32(hsotg->regs + S3C_DCTL, S3C_DCTL_PWROnPrgDone);
2737 udelay(10); /* see openiboot */
2738 __bic32(hsotg->regs + S3C_DCTL, S3C_DCTL_PWROnPrgDone);
2740 dev_dbg(hsotg->dev, "DCTL=0x%08x\n", readl(hsotg->regs + S3C_DCTL));
2742 /* S3C_DxEPCTL_USBActEp says RO in manual, but seems to be set by
2743 writing to the EPCTL register.. */
2745 /* set to read 1 8byte packet */
2746 writel(S3C_DxEPTSIZ_MC(1) | S3C_DxEPTSIZ_PktCnt(1) |
2747 S3C_DxEPTSIZ_XferSize(8), hsotg->regs + DOEPTSIZ0);
2749 writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) |
2750 S3C_DxEPCTL_CNAK | S3C_DxEPCTL_EPEna |
2751 S3C_DxEPCTL_USBActEp,
2752 hsotg->regs + S3C_DOEPCTL0);
2754 /* enable, but don't activate EP0in */
2755 writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) |
2756 S3C_DxEPCTL_USBActEp, hsotg->regs + S3C_DIEPCTL0);
2758 s3c_hsotg_enqueue_setup(hsotg);
2760 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2761 readl(hsotg->regs + S3C_DIEPCTL0),
2762 readl(hsotg->regs + S3C_DOEPCTL0));
2764 /* clear global NAKs */
2765 writel(S3C_DCTL_CGOUTNak | S3C_DCTL_CGNPInNAK,
2766 hsotg->regs + S3C_DCTL);
2768 /* must be at-least 3ms to allow bus to see disconnect */
2771 /* remove the soft-disconnect and let's go */
2772 __bic32(hsotg->regs + S3C_DCTL, S3C_DCTL_SftDiscon);
2774 /* report to the user, and return */
2776 dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
2780 hsotg->driver = NULL;
2781 hsotg->gadget.dev.driver = NULL;
2785 static int s3c_hsotg_stop(struct usb_gadget_driver *driver)
2787 struct s3c_hsotg *hsotg = our_hsotg;
2793 if (!driver || driver != hsotg->driver || !driver->unbind)
2796 /* all endpoints should be shutdown */
2797 for (ep = 0; ep < S3C_HSOTG_EPS; ep++)
2798 s3c_hsotg_ep_disable(&hsotg->eps[ep].ep);
2800 call_gadget(hsotg, disconnect);
2802 driver->unbind(&hsotg->gadget);
2803 hsotg->driver = NULL;
2804 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
2806 device_del(&hsotg->gadget.dev);
2808 dev_info(hsotg->dev, "unregistered gadget driver '%s'\n",
2809 driver->driver.name);
2814 static int s3c_hsotg_gadget_getframe(struct usb_gadget *gadget)
2816 return s3c_hsotg_read_frameno(to_hsotg(gadget));
2819 static struct usb_gadget_ops s3c_hsotg_gadget_ops = {
2820 .get_frame = s3c_hsotg_gadget_getframe,
2821 .start = s3c_hsotg_start,
2822 .stop = s3c_hsotg_stop,
2826 * s3c_hsotg_initep - initialise a single endpoint
2827 * @hsotg: The device state.
2828 * @hs_ep: The endpoint to be initialised.
2829 * @epnum: The endpoint number
2831 * Initialise the given endpoint (as part of the probe and device state
2832 * creation) to give to the gadget driver. Setup the endpoint name, any
2833 * direction information and other state that may be required.
2835 static void __devinit s3c_hsotg_initep(struct s3c_hsotg *hsotg,
2836 struct s3c_hsotg_ep *hs_ep,
2844 else if ((epnum % 2) == 0) {
2851 hs_ep->index = epnum;
2853 snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir);
2855 INIT_LIST_HEAD(&hs_ep->queue);
2856 INIT_LIST_HEAD(&hs_ep->ep.ep_list);
2858 spin_lock_init(&hs_ep->lock);
2860 /* add to the list of endpoints known by the gadget driver */
2862 list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list);
2864 hs_ep->parent = hsotg;
2865 hs_ep->ep.name = hs_ep->name;
2866 hs_ep->ep.maxpacket = epnum ? 512 : EP0_MPS_LIMIT;
2867 hs_ep->ep.ops = &s3c_hsotg_ep_ops;
2869 /* Read the FIFO size for the Periodic TX FIFO, even if we're
2870 * an OUT endpoint, we may as well do this if in future the
2871 * code is changed to make each endpoint's direction changeable.
2874 ptxfifo = readl(hsotg->regs + S3C_DPTXFSIZn(epnum));
2875 hs_ep->fifo_size = S3C_DPTXFSIZn_DPTxFSize_GET(ptxfifo) * 4;
2877 /* if we're using dma, we need to set the next-endpoint pointer
2878 * to be something valid.
2881 if (using_dma(hsotg)) {
2882 u32 next = S3C_DxEPCTL_NextEp((epnum + 1) % 15);
2883 writel(next, hsotg->regs + S3C_DIEPCTL(epnum));
2884 writel(next, hsotg->regs + S3C_DOEPCTL(epnum));
2888 static void s3c_hsotg_init(struct s3c_hsotg *hsotg)
2892 /* unmask subset of endpoint interrupts */
2894 writel(S3C_DIEPMSK_TimeOUTMsk | S3C_DIEPMSK_AHBErrMsk |
2895 S3C_DIEPMSK_EPDisbldMsk | S3C_DIEPMSK_XferComplMsk,
2896 hsotg->regs + S3C_DIEPMSK);
2898 writel(S3C_DOEPMSK_SetupMsk | S3C_DOEPMSK_AHBErrMsk |
2899 S3C_DOEPMSK_EPDisbldMsk | S3C_DOEPMSK_XferComplMsk,
2900 hsotg->regs + S3C_DOEPMSK);
2902 writel(0, hsotg->regs + S3C_DAINTMSK);
2904 /* Be in disconnected state until gadget is registered */
2905 __orr32(hsotg->regs + S3C_DCTL, S3C_DCTL_SftDiscon);
2908 /* post global nak until we're ready */
2909 writel(S3C_DCTL_SGNPInNAK | S3C_DCTL_SGOUTNak,
2910 hsotg->regs + S3C_DCTL);
2915 dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
2916 readl(hsotg->regs + S3C_GRXFSIZ),
2917 readl(hsotg->regs + S3C_GNPTXFSIZ));
2919 s3c_hsotg_init_fifo(hsotg);
2921 /* set the PLL on, remove the HNP/SRP and set the PHY */
2922 writel(S3C_GUSBCFG_PHYIf16 | S3C_GUSBCFG_TOutCal(7) | (0x5 << 10),
2923 hsotg->regs + S3C_GUSBCFG);
2925 writel(using_dma(hsotg) ? S3C_GAHBCFG_DMAEn : 0x0,
2926 hsotg->regs + S3C_GAHBCFG);
2928 /* check hardware configuration */
2930 cfg4 = readl(hsotg->regs + 0x50);
2931 hsotg->dedicated_fifos = (cfg4 >> 25) & 1;
2933 dev_info(hsotg->dev, "%s fifos\n",
2934 hsotg->dedicated_fifos ? "dedicated" : "shared");
2937 static void s3c_hsotg_dump(struct s3c_hsotg *hsotg)
2940 struct device *dev = hsotg->dev;
2941 void __iomem *regs = hsotg->regs;
2945 dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
2946 readl(regs + S3C_DCFG), readl(regs + S3C_DCTL),
2947 readl(regs + S3C_DIEPMSK));
2949 dev_info(dev, "GAHBCFG=0x%08x, 0x44=0x%08x\n",
2950 readl(regs + S3C_GAHBCFG), readl(regs + 0x44));
2952 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
2953 readl(regs + S3C_GRXFSIZ), readl(regs + S3C_GNPTXFSIZ));
2955 /* show periodic fifo settings */
2957 for (idx = 1; idx <= 15; idx++) {
2958 val = readl(regs + S3C_DPTXFSIZn(idx));
2959 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
2960 val >> S3C_DPTXFSIZn_DPTxFSize_SHIFT,
2961 val & S3C_DPTXFSIZn_DPTxFStAddr_MASK);
2964 for (idx = 0; idx < 15; idx++) {
2966 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
2967 readl(regs + S3C_DIEPCTL(idx)),
2968 readl(regs + S3C_DIEPTSIZ(idx)),
2969 readl(regs + S3C_DIEPDMA(idx)));
2971 val = readl(regs + S3C_DOEPCTL(idx));
2973 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
2974 idx, readl(regs + S3C_DOEPCTL(idx)),
2975 readl(regs + S3C_DOEPTSIZ(idx)),
2976 readl(regs + S3C_DOEPDMA(idx)));
2980 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
2981 readl(regs + S3C_DVBUSDIS), readl(regs + S3C_DVBUSPULSE));
2987 * state_show - debugfs: show overall driver and device state.
2988 * @seq: The seq file to write to.
2989 * @v: Unused parameter.
2991 * This debugfs entry shows the overall state of the hardware and
2992 * some general information about each of the endpoints available
2995 static int state_show(struct seq_file *seq, void *v)
2997 struct s3c_hsotg *hsotg = seq->private;
2998 void __iomem *regs = hsotg->regs;
3001 seq_printf(seq, "DCFG=0x%08x, DCTL=0x%08x, DSTS=0x%08x\n",
3002 readl(regs + S3C_DCFG),
3003 readl(regs + S3C_DCTL),
3004 readl(regs + S3C_DSTS));
3006 seq_printf(seq, "DIEPMSK=0x%08x, DOEPMASK=0x%08x\n",
3007 readl(regs + S3C_DIEPMSK), readl(regs + S3C_DOEPMSK));
3009 seq_printf(seq, "GINTMSK=0x%08x, GINTSTS=0x%08x\n",
3010 readl(regs + S3C_GINTMSK),
3011 readl(regs + S3C_GINTSTS));
3013 seq_printf(seq, "DAINTMSK=0x%08x, DAINT=0x%08x\n",
3014 readl(regs + S3C_DAINTMSK),
3015 readl(regs + S3C_DAINT));
3017 seq_printf(seq, "GNPTXSTS=0x%08x, GRXSTSR=%08x\n",
3018 readl(regs + S3C_GNPTXSTS),
3019 readl(regs + S3C_GRXSTSR));
3021 seq_printf(seq, "\nEndpoint status:\n");
3023 for (idx = 0; idx < 15; idx++) {
3026 in = readl(regs + S3C_DIEPCTL(idx));
3027 out = readl(regs + S3C_DOEPCTL(idx));
3029 seq_printf(seq, "ep%d: DIEPCTL=0x%08x, DOEPCTL=0x%08x",
3032 in = readl(regs + S3C_DIEPTSIZ(idx));
3033 out = readl(regs + S3C_DOEPTSIZ(idx));
3035 seq_printf(seq, ", DIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x",
3038 seq_printf(seq, "\n");
3044 static int state_open(struct inode *inode, struct file *file)
3046 return single_open(file, state_show, inode->i_private);
3049 static const struct file_operations state_fops = {
3050 .owner = THIS_MODULE,
3053 .llseek = seq_lseek,
3054 .release = single_release,
3058 * fifo_show - debugfs: show the fifo information
3059 * @seq: The seq_file to write data to.
3060 * @v: Unused parameter.
3062 * Show the FIFO information for the overall fifo and all the
3063 * periodic transmission FIFOs.
3065 static int fifo_show(struct seq_file *seq, void *v)
3067 struct s3c_hsotg *hsotg = seq->private;
3068 void __iomem *regs = hsotg->regs;
3072 seq_printf(seq, "Non-periodic FIFOs:\n");
3073 seq_printf(seq, "RXFIFO: Size %d\n", readl(regs + S3C_GRXFSIZ));
3075 val = readl(regs + S3C_GNPTXFSIZ);
3076 seq_printf(seq, "NPTXFIFO: Size %d, Start 0x%08x\n",
3077 val >> S3C_GNPTXFSIZ_NPTxFDep_SHIFT,
3078 val & S3C_GNPTXFSIZ_NPTxFStAddr_MASK);
3080 seq_printf(seq, "\nPeriodic TXFIFOs:\n");
3082 for (idx = 1; idx <= 15; idx++) {
3083 val = readl(regs + S3C_DPTXFSIZn(idx));
3085 seq_printf(seq, "\tDPTXFIFO%2d: Size %d, Start 0x%08x\n", idx,
3086 val >> S3C_DPTXFSIZn_DPTxFSize_SHIFT,
3087 val & S3C_DPTXFSIZn_DPTxFStAddr_MASK);
3093 static int fifo_open(struct inode *inode, struct file *file)
3095 return single_open(file, fifo_show, inode->i_private);
3098 static const struct file_operations fifo_fops = {
3099 .owner = THIS_MODULE,
3102 .llseek = seq_lseek,
3103 .release = single_release,
3107 static const char *decode_direction(int is_in)
3109 return is_in ? "in" : "out";
3113 * ep_show - debugfs: show the state of an endpoint.
3114 * @seq: The seq_file to write data to.
3115 * @v: Unused parameter.
3117 * This debugfs entry shows the state of the given endpoint (one is
3118 * registered for each available).
3120 static int ep_show(struct seq_file *seq, void *v)
3122 struct s3c_hsotg_ep *ep = seq->private;
3123 struct s3c_hsotg *hsotg = ep->parent;
3124 struct s3c_hsotg_req *req;
3125 void __iomem *regs = hsotg->regs;
3126 int index = ep->index;
3127 int show_limit = 15;
3128 unsigned long flags;
3130 seq_printf(seq, "Endpoint index %d, named %s, dir %s:\n",
3131 ep->index, ep->ep.name, decode_direction(ep->dir_in));
3133 /* first show the register state */
3135 seq_printf(seq, "\tDIEPCTL=0x%08x, DOEPCTL=0x%08x\n",
3136 readl(regs + S3C_DIEPCTL(index)),
3137 readl(regs + S3C_DOEPCTL(index)));
3139 seq_printf(seq, "\tDIEPDMA=0x%08x, DOEPDMA=0x%08x\n",
3140 readl(regs + S3C_DIEPDMA(index)),
3141 readl(regs + S3C_DOEPDMA(index)));
3143 seq_printf(seq, "\tDIEPINT=0x%08x, DOEPINT=0x%08x\n",
3144 readl(regs + S3C_DIEPINT(index)),
3145 readl(regs + S3C_DOEPINT(index)));
3147 seq_printf(seq, "\tDIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x\n",
3148 readl(regs + S3C_DIEPTSIZ(index)),
3149 readl(regs + S3C_DOEPTSIZ(index)));
3151 seq_printf(seq, "\n");
3152 seq_printf(seq, "mps %d\n", ep->ep.maxpacket);
3153 seq_printf(seq, "total_data=%ld\n", ep->total_data);
3155 seq_printf(seq, "request list (%p,%p):\n",
3156 ep->queue.next, ep->queue.prev);
3158 spin_lock_irqsave(&ep->lock, flags);
3160 list_for_each_entry(req, &ep->queue, queue) {
3161 if (--show_limit < 0) {
3162 seq_printf(seq, "not showing more requests...\n");
3166 seq_printf(seq, "%c req %p: %d bytes @%p, ",
3167 req == ep->req ? '*' : ' ',
3168 req, req->req.length, req->req.buf);
3169 seq_printf(seq, "%d done, res %d\n",
3170 req->req.actual, req->req.status);
3173 spin_unlock_irqrestore(&ep->lock, flags);
3178 static int ep_open(struct inode *inode, struct file *file)
3180 return single_open(file, ep_show, inode->i_private);
3183 static const struct file_operations ep_fops = {
3184 .owner = THIS_MODULE,
3187 .llseek = seq_lseek,
3188 .release = single_release,
3192 * s3c_hsotg_create_debug - create debugfs directory and files
3193 * @hsotg: The driver state
3195 * Create the debugfs files to allow the user to get information
3196 * about the state of the system. The directory name is created
3197 * with the same name as the device itself, in case we end up
3198 * with multiple blocks in future systems.
3200 static void __devinit s3c_hsotg_create_debug(struct s3c_hsotg *hsotg)
3202 struct dentry *root;
3205 root = debugfs_create_dir(dev_name(hsotg->dev), NULL);
3206 hsotg->debug_root = root;
3208 dev_err(hsotg->dev, "cannot create debug root\n");
3212 /* create general state file */
3214 hsotg->debug_file = debugfs_create_file("state", 0444, root,
3215 hsotg, &state_fops);
3217 if (IS_ERR(hsotg->debug_file))
3218 dev_err(hsotg->dev, "%s: failed to create state\n", __func__);
3220 hsotg->debug_fifo = debugfs_create_file("fifo", 0444, root,
3223 if (IS_ERR(hsotg->debug_fifo))
3224 dev_err(hsotg->dev, "%s: failed to create fifo\n", __func__);
3226 /* create one file for each endpoint */
3228 for (epidx = 0; epidx < S3C_HSOTG_EPS; epidx++) {
3229 struct s3c_hsotg_ep *ep = &hsotg->eps[epidx];
3231 ep->debugfs = debugfs_create_file(ep->name, 0444,
3232 root, ep, &ep_fops);
3234 if (IS_ERR(ep->debugfs))
3235 dev_err(hsotg->dev, "failed to create %s debug file\n",
3241 * s3c_hsotg_delete_debug - cleanup debugfs entries
3242 * @hsotg: The driver state
3244 * Cleanup (remove) the debugfs files for use on module exit.
3246 static void __devexit s3c_hsotg_delete_debug(struct s3c_hsotg *hsotg)
3250 for (epidx = 0; epidx < S3C_HSOTG_EPS; epidx++) {
3251 struct s3c_hsotg_ep *ep = &hsotg->eps[epidx];
3252 debugfs_remove(ep->debugfs);
3255 debugfs_remove(hsotg->debug_file);
3256 debugfs_remove(hsotg->debug_fifo);
3257 debugfs_remove(hsotg->debug_root);
3260 static int __devinit s3c_hsotg_probe(struct platform_device *pdev)
3262 struct s3c_hsotg_plat *plat = pdev->dev.platform_data;
3263 struct device *dev = &pdev->dev;
3264 struct s3c_hsotg *hsotg;
3265 struct resource *res;
3270 plat = pdev->dev.platform_data;
3272 dev_err(&pdev->dev, "no platform data defined\n");
3276 hsotg = kzalloc(sizeof(struct s3c_hsotg) +
3277 sizeof(struct s3c_hsotg_ep) * S3C_HSOTG_EPS,
3280 dev_err(dev, "cannot get memory\n");
3287 hsotg->clk = clk_get(&pdev->dev, "otg");
3288 if (IS_ERR(hsotg->clk)) {
3289 dev_err(dev, "cannot get otg clock\n");
3290 ret = PTR_ERR(hsotg->clk);
3294 platform_set_drvdata(pdev, hsotg);
3296 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3298 dev_err(dev, "cannot find register resource 0\n");
3303 hsotg->regs_res = request_mem_region(res->start, resource_size(res),
3305 if (!hsotg->regs_res) {
3306 dev_err(dev, "cannot reserve registers\n");
3311 hsotg->regs = ioremap(res->start, resource_size(res));
3313 dev_err(dev, "cannot map registers\n");
3318 ret = platform_get_irq(pdev, 0);
3320 dev_err(dev, "cannot find IRQ\n");
3326 ret = request_irq(ret, s3c_hsotg_irq, 0, dev_name(dev), hsotg);
3328 dev_err(dev, "cannot claim IRQ\n");
3332 dev_info(dev, "regs %p, irq %d\n", hsotg->regs, hsotg->irq);
3334 device_initialize(&hsotg->gadget.dev);
3336 dev_set_name(&hsotg->gadget.dev, "gadget");
3338 hsotg->gadget.max_speed = USB_SPEED_HIGH;
3339 hsotg->gadget.ops = &s3c_hsotg_gadget_ops;
3340 hsotg->gadget.name = dev_name(dev);
3342 hsotg->gadget.dev.parent = dev;
3343 hsotg->gadget.dev.dma_mask = dev->dma_mask;
3345 /* setup endpoint information */
3347 INIT_LIST_HEAD(&hsotg->gadget.ep_list);
3348 hsotg->gadget.ep0 = &hsotg->eps[0].ep;
3350 /* allocate EP0 request */
3352 hsotg->ctrl_req = s3c_hsotg_ep_alloc_request(&hsotg->eps[0].ep,
3354 if (!hsotg->ctrl_req) {
3355 dev_err(dev, "failed to allocate ctrl req\n");
3359 /* reset the system */
3361 clk_enable(hsotg->clk);
3365 for (i = 0; i < ARRAY_SIZE(hsotg->supplies); i++)
3366 hsotg->supplies[i].supply = s3c_hsotg_supply_names[i];
3368 ret = regulator_bulk_get(dev, ARRAY_SIZE(hsotg->supplies),
3371 dev_err(dev, "failed to request supplies: %d\n", ret);
3375 ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies),
3379 dev_err(hsotg->dev, "failed to enable supplies: %d\n", ret);
3383 /* usb phy enable */
3384 s3c_hsotg_phy_enable(hsotg);
3386 s3c_hsotg_corereset(hsotg);
3387 s3c_hsotg_init(hsotg);
3389 /* initialise the endpoints now the core has been initialised */
3390 for (epnum = 0; epnum < S3C_HSOTG_EPS; epnum++)
3391 s3c_hsotg_initep(hsotg, &hsotg->eps[epnum], epnum);
3393 ret = usb_add_gadget_udc(&pdev->dev, &hsotg->gadget);
3397 s3c_hsotg_create_debug(hsotg);
3399 s3c_hsotg_dump(hsotg);
3405 s3c_hsotg_phy_disable(hsotg);
3407 regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies), hsotg->supplies);
3408 regulator_bulk_free(ARRAY_SIZE(hsotg->supplies), hsotg->supplies);
3410 clk_disable(hsotg->clk);
3411 clk_put(hsotg->clk);
3414 iounmap(hsotg->regs);
3417 release_resource(hsotg->regs_res);
3418 kfree(hsotg->regs_res);
3420 clk_put(hsotg->clk);
3426 static int __devexit s3c_hsotg_remove(struct platform_device *pdev)
3428 struct s3c_hsotg *hsotg = platform_get_drvdata(pdev);
3430 usb_del_gadget_udc(&hsotg->gadget);
3432 s3c_hsotg_delete_debug(hsotg);
3434 usb_gadget_unregister_driver(hsotg->driver);
3436 free_irq(hsotg->irq, hsotg);
3437 iounmap(hsotg->regs);
3439 release_resource(hsotg->regs_res);
3440 kfree(hsotg->regs_res);
3442 s3c_hsotg_phy_disable(hsotg);
3445 regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies), hsotg->supplies);
3446 regulator_bulk_free(ARRAY_SIZE(hsotg->supplies), hsotg->supplies);
3448 clk_disable(hsotg->clk);
3449 clk_put(hsotg->clk);
3456 #define s3c_hsotg_suspend NULL
3457 #define s3c_hsotg_resume NULL
3460 static struct platform_driver s3c_hsotg_driver = {
3462 .name = "s3c-hsotg",
3463 .owner = THIS_MODULE,
3465 .probe = s3c_hsotg_probe,
3466 .remove = __devexit_p(s3c_hsotg_remove),
3467 .suspend = s3c_hsotg_suspend,
3468 .resume = s3c_hsotg_resume,
3471 module_platform_driver(s3c_hsotg_driver);
3473 MODULE_DESCRIPTION("Samsung S3C USB High-speed/OtG device");
3474 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
3475 MODULE_LICENSE("GPL");
3476 MODULE_ALIAS("platform:s3c-hsotg");