1 /* linux/drivers/usb/gadget/s3c-hsotg.c
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
8 * S3C USB2.0 High-speed / OtG driver
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/spinlock.h>
20 #include <linux/interrupt.h>
21 #include <linux/platform_device.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/debugfs.h>
24 #include <linux/seq_file.h>
25 #include <linux/delay.h>
27 #include <linux/slab.h>
28 #include <linux/clk.h>
30 #include <linux/usb/ch9.h>
31 #include <linux/usb/gadget.h>
35 #include <plat/regs-usb-hsotg-phy.h>
36 #include <plat/regs-usb-hsotg.h>
37 #include <mach/regs-sys.h>
38 #include <plat/udc-hs.h>
41 #define DMA_ADDR_INVALID (~((dma_addr_t)0))
45 * Unfortunately there seems to be a limit of the amount of data that can
46 * be transfered by IN transactions on EP0. This is either 127 bytes or 3
47 * packets (which practially means 1 packet and 63 bytes of data) when the
50 * This means if we are wanting to move >127 bytes of data, we need to
51 * split the transactions up, but just doing one packet at a time does
52 * not work (this may be an implicit DATA0 PID on first packet of the
53 * transaction) and doing 2 packets is outside the controller's limits.
55 * If we try to lower the MPS size for EP0, then no transfers work properly
56 * for EP0, and the system will fail basic enumeration. As no cause for this
57 * has currently been found, we cannot support any large IN transfers for
60 #define EP0_MPS_LIMIT 64
66 * struct s3c_hsotg_ep - driver endpoint definition.
67 * @ep: The gadget layer representation of the endpoint.
68 * @name: The driver generated name for the endpoint.
69 * @queue: Queue of requests for this endpoint.
70 * @parent: Reference back to the parent device structure.
71 * @req: The current request that the endpoint is processing. This is
72 * used to indicate an request has been loaded onto the endpoint
73 * and has yet to be completed (maybe due to data move, or simply
74 * awaiting an ack from the core all the data has been completed).
75 * @debugfs: File entry for debugfs file for this endpoint.
76 * @lock: State lock to protect contents of endpoint.
77 * @dir_in: Set to true if this endpoint is of the IN direction, which
78 * means that it is sending data to the Host.
79 * @index: The index for the endpoint registers.
80 * @name: The name array passed to the USB core.
81 * @halted: Set if the endpoint has been halted.
82 * @periodic: Set if this is a periodic ep, such as Interrupt
83 * @sent_zlp: Set if we've sent a zero-length packet.
84 * @total_data: The total number of data bytes done.
85 * @fifo_size: The size of the FIFO (for periodic IN endpoints)
86 * @fifo_load: The amount of data loaded into the FIFO (periodic IN)
87 * @last_load: The offset of data for the last start of request.
88 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN
90 * This is the driver's state for each registered enpoint, allowing it
91 * to keep track of transactions that need doing. Each endpoint has a
92 * lock to protect the state, to try and avoid using an overall lock
93 * for the host controller as much as possible.
95 * For periodic IN endpoints, we have fifo_size and fifo_load to try
96 * and keep track of the amount of data in the periodic FIFO for each
97 * of these as we don't have a status register that tells us how much
98 * is in each of them. (note, this may actually be useless information
99 * as in shared-fifo mode periodic in acts like a single-frame packet
100 * buffer than a fifo)
102 struct s3c_hsotg_ep {
104 struct list_head queue;
105 struct s3c_hsotg *parent;
106 struct s3c_hsotg_req *req;
107 struct dentry *debugfs;
111 unsigned long total_data;
112 unsigned int size_loaded;
113 unsigned int last_load;
114 unsigned int fifo_load;
115 unsigned short fifo_size;
117 unsigned char dir_in;
120 unsigned int halted:1;
121 unsigned int periodic:1;
122 unsigned int sent_zlp:1;
127 #define S3C_HSOTG_EPS (8+1) /* limit to 9 for the moment */
130 * struct s3c_hsotg - driver state.
131 * @dev: The parent device supplied to the probe function
132 * @driver: USB gadget driver
133 * @plat: The platform specific configuration data.
134 * @regs: The memory area mapped for accessing registers.
135 * @regs_res: The resource that was allocated when claiming register space.
136 * @irq: The IRQ number we are using
137 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos.
138 * @debug_root: root directrory for debugfs.
139 * @debug_file: main status file for debugfs.
140 * @debug_fifo: FIFO status file for debugfs.
141 * @ep0_reply: Request used for ep0 reply.
142 * @ep0_buff: Buffer for EP0 reply data, if needed.
143 * @ctrl_buff: Buffer for EP0 control requests.
144 * @ctrl_req: Request for EP0 control packets.
145 * @eps: The endpoints being supplied to the gadget framework
149 struct usb_gadget_driver *driver;
150 struct s3c_hsotg_plat *plat;
153 struct resource *regs_res;
157 unsigned int dedicated_fifos:1;
159 struct dentry *debug_root;
160 struct dentry *debug_file;
161 struct dentry *debug_fifo;
163 struct usb_request *ep0_reply;
164 struct usb_request *ctrl_req;
168 struct usb_gadget gadget;
169 struct s3c_hsotg_ep eps[];
173 * struct s3c_hsotg_req - data transfer request
174 * @req: The USB gadget request
175 * @queue: The list of requests for the endpoint this is queued for.
176 * @in_progress: Has already had size/packets written to core
177 * @mapped: DMA buffer for this request has been mapped via dma_map_single().
179 struct s3c_hsotg_req {
180 struct usb_request req;
181 struct list_head queue;
182 unsigned char in_progress;
183 unsigned char mapped;
186 /* conversion functions */
187 static inline struct s3c_hsotg_req *our_req(struct usb_request *req)
189 return container_of(req, struct s3c_hsotg_req, req);
192 static inline struct s3c_hsotg_ep *our_ep(struct usb_ep *ep)
194 return container_of(ep, struct s3c_hsotg_ep, ep);
197 static inline struct s3c_hsotg *to_hsotg(struct usb_gadget *gadget)
199 return container_of(gadget, struct s3c_hsotg, gadget);
202 static inline void __orr32(void __iomem *ptr, u32 val)
204 writel(readl(ptr) | val, ptr);
207 static inline void __bic32(void __iomem *ptr, u32 val)
209 writel(readl(ptr) & ~val, ptr);
212 /* forward decleration of functions */
213 static void s3c_hsotg_dump(struct s3c_hsotg *hsotg);
216 * using_dma - return the DMA status of the driver.
217 * @hsotg: The driver state.
219 * Return true if we're using DMA.
221 * Currently, we have the DMA support code worked into everywhere
222 * that needs it, but the AMBA DMA implementation in the hardware can
223 * only DMA from 32bit aligned addresses. This means that gadgets such
224 * as the CDC Ethernet cannot work as they often pass packets which are
227 * Unfortunately the choice to use DMA or not is global to the controller
228 * and seems to be only settable when the controller is being put through
229 * a core reset. This means we either need to fix the gadgets to take
230 * account of DMA alignment, or add bounce buffers (yuerk).
232 * Until this issue is sorted out, we always return 'false'.
234 static inline bool using_dma(struct s3c_hsotg *hsotg)
236 return false; /* support is not complete */
240 * s3c_hsotg_en_gsint - enable one or more of the general interrupt
241 * @hsotg: The device state
242 * @ints: A bitmask of the interrupts to enable
244 static void s3c_hsotg_en_gsint(struct s3c_hsotg *hsotg, u32 ints)
246 u32 gsintmsk = readl(hsotg->regs + S3C_GINTMSK);
249 new_gsintmsk = gsintmsk | ints;
251 if (new_gsintmsk != gsintmsk) {
252 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
253 writel(new_gsintmsk, hsotg->regs + S3C_GINTMSK);
258 * s3c_hsotg_disable_gsint - disable one or more of the general interrupt
259 * @hsotg: The device state
260 * @ints: A bitmask of the interrupts to enable
262 static void s3c_hsotg_disable_gsint(struct s3c_hsotg *hsotg, u32 ints)
264 u32 gsintmsk = readl(hsotg->regs + S3C_GINTMSK);
267 new_gsintmsk = gsintmsk & ~ints;
269 if (new_gsintmsk != gsintmsk)
270 writel(new_gsintmsk, hsotg->regs + S3C_GINTMSK);
274 * s3c_hsotg_ctrl_epint - enable/disable an endpoint irq
275 * @hsotg: The device state
276 * @ep: The endpoint index
277 * @dir_in: True if direction is in.
278 * @en: The enable value, true to enable
280 * Set or clear the mask for an individual endpoint's interrupt
283 static void s3c_hsotg_ctrl_epint(struct s3c_hsotg *hsotg,
284 unsigned int ep, unsigned int dir_in,
294 local_irq_save(flags);
295 daint = readl(hsotg->regs + S3C_DAINTMSK);
300 writel(daint, hsotg->regs + S3C_DAINTMSK);
301 local_irq_restore(flags);
305 * s3c_hsotg_init_fifo - initialise non-periodic FIFOs
306 * @hsotg: The device instance.
308 static void s3c_hsotg_init_fifo(struct s3c_hsotg *hsotg)
316 /* the ryu 2.6.24 release ahs
317 writel(0x1C0, hsotg->regs + S3C_GRXFSIZ);
318 writel(S3C_GNPTXFSIZ_NPTxFStAddr(0x200) |
319 S3C_GNPTXFSIZ_NPTxFDep(0x1C0),
320 hsotg->regs + S3C_GNPTXFSIZ);
323 /* set FIFO sizes to 2048/1024 */
325 writel(2048, hsotg->regs + S3C_GRXFSIZ);
326 writel(S3C_GNPTXFSIZ_NPTxFStAddr(2048) |
327 S3C_GNPTXFSIZ_NPTxFDep(1024),
328 hsotg->regs + S3C_GNPTXFSIZ);
330 /* arange all the rest of the TX FIFOs, as some versions of this
331 * block have overlapping default addresses. This also ensures
332 * that if the settings have been changed, then they are set to
335 /* start at the end of the GNPTXFSIZ, rounded up */
339 /* currently we allocate TX FIFOs for all possible endpoints,
340 * and assume that they are all the same size. */
342 for (ep = 0; ep <= 15; ep++) {
344 val |= size << S3C_DPTXFSIZn_DPTxFSize_SHIFT;
347 writel(val, hsotg->regs + S3C_DPTXFSIZn(ep));
350 /* according to p428 of the design guide, we need to ensure that
351 * all fifos are flushed before continuing */
353 writel(S3C_GRSTCTL_TxFNum(0x10) | S3C_GRSTCTL_TxFFlsh |
354 S3C_GRSTCTL_RxFFlsh, hsotg->regs + S3C_GRSTCTL);
356 /* wait until the fifos are both flushed */
359 val = readl(hsotg->regs + S3C_GRSTCTL);
361 if ((val & (S3C_GRSTCTL_TxFFlsh | S3C_GRSTCTL_RxFFlsh)) == 0)
364 if (--timeout == 0) {
366 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
373 dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout);
377 * @ep: USB endpoint to allocate request for.
378 * @flags: Allocation flags
380 * Allocate a new USB request structure appropriate for the specified endpoint
382 static struct usb_request *s3c_hsotg_ep_alloc_request(struct usb_ep *ep,
385 struct s3c_hsotg_req *req;
387 req = kzalloc(sizeof(struct s3c_hsotg_req), flags);
391 INIT_LIST_HEAD(&req->queue);
393 req->req.dma = DMA_ADDR_INVALID;
398 * is_ep_periodic - return true if the endpoint is in periodic mode.
399 * @hs_ep: The endpoint to query.
401 * Returns true if the endpoint is in periodic mode, meaning it is being
402 * used for an Interrupt or ISO transfer.
404 static inline int is_ep_periodic(struct s3c_hsotg_ep *hs_ep)
406 return hs_ep->periodic;
410 * s3c_hsotg_unmap_dma - unmap the DMA memory being used for the request
411 * @hsotg: The device state.
412 * @hs_ep: The endpoint for the request
413 * @hs_req: The request being processed.
415 * This is the reverse of s3c_hsotg_map_dma(), called for the completion
416 * of a request to ensure the buffer is ready for access by the caller.
418 static void s3c_hsotg_unmap_dma(struct s3c_hsotg *hsotg,
419 struct s3c_hsotg_ep *hs_ep,
420 struct s3c_hsotg_req *hs_req)
422 struct usb_request *req = &hs_req->req;
423 enum dma_data_direction dir;
425 dir = hs_ep->dir_in ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
427 /* ignore this if we're not moving any data */
428 if (hs_req->req.length == 0)
431 if (hs_req->mapped) {
432 /* we mapped this, so unmap and remove the dma */
434 dma_unmap_single(hsotg->dev, req->dma, req->length, dir);
436 req->dma = DMA_ADDR_INVALID;
439 dma_sync_single_for_cpu(hsotg->dev, req->dma, req->length, dir);
444 * s3c_hsotg_write_fifo - write packet Data to the TxFIFO
445 * @hsotg: The controller state.
446 * @hs_ep: The endpoint we're going to write for.
447 * @hs_req: The request to write data for.
449 * This is called when the TxFIFO has some space in it to hold a new
450 * transmission and we have something to give it. The actual setup of
451 * the data size is done elsewhere, so all we have to do is to actually
454 * The return value is zero if there is more space (or nothing was done)
455 * otherwise -ENOSPC is returned if the FIFO space was used up.
457 * This routine is only needed for PIO
459 static int s3c_hsotg_write_fifo(struct s3c_hsotg *hsotg,
460 struct s3c_hsotg_ep *hs_ep,
461 struct s3c_hsotg_req *hs_req)
463 bool periodic = is_ep_periodic(hs_ep);
464 u32 gnptxsts = readl(hsotg->regs + S3C_GNPTXSTS);
465 int buf_pos = hs_req->req.actual;
466 int to_write = hs_ep->size_loaded;
471 to_write -= (buf_pos - hs_ep->last_load);
473 /* if there's nothing to write, get out early */
477 if (periodic && !hsotg->dedicated_fifos) {
478 u32 epsize = readl(hsotg->regs + S3C_DIEPTSIZ(hs_ep->index));
482 /* work out how much data was loaded so we can calculate
483 * how much data is left in the fifo. */
485 size_left = S3C_DxEPTSIZ_XferSize_GET(epsize);
487 /* if shared fifo, we cannot write anything until the
488 * previous data has been completely sent.
490 if (hs_ep->fifo_load != 0) {
491 s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_PTxFEmp);
495 dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n",
497 hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size);
499 /* how much of the data has moved */
500 size_done = hs_ep->size_loaded - size_left;
502 /* how much data is left in the fifo */
503 can_write = hs_ep->fifo_load - size_done;
504 dev_dbg(hsotg->dev, "%s: => can_write1=%d\n",
505 __func__, can_write);
507 can_write = hs_ep->fifo_size - can_write;
508 dev_dbg(hsotg->dev, "%s: => can_write2=%d\n",
509 __func__, can_write);
511 if (can_write <= 0) {
512 s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_PTxFEmp);
515 } else if (hsotg->dedicated_fifos && hs_ep->index != 0) {
516 can_write = readl(hsotg->regs + S3C_DTXFSTS(hs_ep->index));
521 if (S3C_GNPTXSTS_NPTxQSpcAvail_GET(gnptxsts) == 0) {
523 "%s: no queue slots available (0x%08x)\n",
526 s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_NPTxFEmp);
530 can_write = S3C_GNPTXSTS_NPTxFSpcAvail_GET(gnptxsts);
531 can_write *= 4; /* fifo size is in 32bit quantities. */
534 dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, mps %d\n",
535 __func__, gnptxsts, can_write, to_write, hs_ep->ep.maxpacket);
537 /* limit to 512 bytes of data, it seems at least on the non-periodic
538 * FIFO, requests of >512 cause the endpoint to get stuck with a
539 * fragment of the end of the transfer in it.
544 /* limit the write to one max-packet size worth of data, but allow
545 * the transfer to return that it did not run out of fifo space
547 if (to_write > hs_ep->ep.maxpacket) {
548 to_write = hs_ep->ep.maxpacket;
550 s3c_hsotg_en_gsint(hsotg,
551 periodic ? S3C_GINTSTS_PTxFEmp :
552 S3C_GINTSTS_NPTxFEmp);
555 /* see if we can write data */
557 if (to_write > can_write) {
558 to_write = can_write;
559 pkt_round = to_write % hs_ep->ep.maxpacket;
561 /* Not sure, but we probably shouldn't be writing partial
562 * packets into the FIFO, so round the write down to an
563 * exact number of packets.
565 * Note, we do not currently check to see if we can ever
566 * write a full packet or not to the FIFO.
570 to_write -= pkt_round;
572 /* enable correct FIFO interrupt to alert us when there
573 * is more room left. */
575 s3c_hsotg_en_gsint(hsotg,
576 periodic ? S3C_GINTSTS_PTxFEmp :
577 S3C_GINTSTS_NPTxFEmp);
580 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
581 to_write, hs_req->req.length, can_write, buf_pos);
586 hs_req->req.actual = buf_pos + to_write;
587 hs_ep->total_data += to_write;
590 hs_ep->fifo_load += to_write;
592 to_write = DIV_ROUND_UP(to_write, 4);
593 data = hs_req->req.buf + buf_pos;
595 writesl(hsotg->regs + S3C_EPFIFO(hs_ep->index), data, to_write);
597 return (to_write >= can_write) ? -ENOSPC : 0;
601 * get_ep_limit - get the maximum data legnth for this endpoint
602 * @hs_ep: The endpoint
604 * Return the maximum data that can be queued in one go on a given endpoint
605 * so that transfers that are too long can be split.
607 static unsigned get_ep_limit(struct s3c_hsotg_ep *hs_ep)
609 int index = hs_ep->index;
614 maxsize = S3C_DxEPTSIZ_XferSize_LIMIT + 1;
615 maxpkt = S3C_DxEPTSIZ_PktCnt_LIMIT + 1;
619 maxpkt = S3C_DIEPTSIZ0_PktCnt_LIMIT + 1;
625 /* we made the constant loading easier above by using +1 */
629 /* constrain by packet count if maxpkts*pktsize is greater
630 * than the length register size. */
632 if ((maxpkt * hs_ep->ep.maxpacket) < maxsize)
633 maxsize = maxpkt * hs_ep->ep.maxpacket;
639 * s3c_hsotg_start_req - start a USB request from an endpoint's queue
640 * @hsotg: The controller state.
641 * @hs_ep: The endpoint to process a request for
642 * @hs_req: The request to start.
643 * @continuing: True if we are doing more for the current request.
645 * Start the given request running by setting the endpoint registers
646 * appropriately, and writing any data to the FIFOs.
648 static void s3c_hsotg_start_req(struct s3c_hsotg *hsotg,
649 struct s3c_hsotg_ep *hs_ep,
650 struct s3c_hsotg_req *hs_req,
653 struct usb_request *ureq = &hs_req->req;
654 int index = hs_ep->index;
655 int dir_in = hs_ep->dir_in;
665 if (hs_ep->req && !continuing) {
666 dev_err(hsotg->dev, "%s: active request\n", __func__);
669 } else if (hs_ep->req != hs_req && continuing) {
671 "%s: continue different req\n", __func__);
677 epctrl_reg = dir_in ? S3C_DIEPCTL(index) : S3C_DOEPCTL(index);
678 epsize_reg = dir_in ? S3C_DIEPTSIZ(index) : S3C_DOEPTSIZ(index);
680 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
681 __func__, readl(hsotg->regs + epctrl_reg), index,
682 hs_ep->dir_in ? "in" : "out");
684 length = ureq->length - ureq->actual;
688 "REQ buf %p len %d dma 0x%08x noi=%d zp=%d snok=%d\n",
689 ureq->buf, length, ureq->dma,
690 ureq->no_interrupt, ureq->zero, ureq->short_not_ok);
692 maxreq = get_ep_limit(hs_ep);
693 if (length > maxreq) {
694 int round = maxreq % hs_ep->ep.maxpacket;
696 dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n",
697 __func__, length, maxreq, round);
699 /* round down to multiple of packets */
707 packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket);
709 packets = 1; /* send one packet if length is zero. */
711 if (dir_in && index != 0)
712 epsize = S3C_DxEPTSIZ_MC(1);
716 if (index != 0 && ureq->zero) {
717 /* test for the packets being exactly right for the
720 if (length == (packets * hs_ep->ep.maxpacket))
724 epsize |= S3C_DxEPTSIZ_PktCnt(packets);
725 epsize |= S3C_DxEPTSIZ_XferSize(length);
727 dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
728 __func__, packets, length, ureq->length, epsize, epsize_reg);
730 /* store the request as the current one we're doing */
733 /* write size / packets */
734 writel(epsize, hsotg->regs + epsize_reg);
736 ctrl = readl(hsotg->regs + epctrl_reg);
738 if (ctrl & S3C_DxEPCTL_Stall) {
739 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
741 /* not sure what we can do here, if it is EP0 then we should
742 * get this cleared once the endpoint has transmitted the
743 * STALL packet, otherwise it needs to be cleared by the
748 if (using_dma(hsotg)) {
749 unsigned int dma_reg;
751 /* write DMA address to control register, buffer already
752 * synced by s3c_hsotg_ep_queue(). */
754 dma_reg = dir_in ? S3C_DIEPDMA(index) : S3C_DOEPDMA(index);
755 writel(ureq->dma, hsotg->regs + dma_reg);
757 dev_dbg(hsotg->dev, "%s: 0x%08x => 0x%08x\n",
758 __func__, ureq->dma, dma_reg);
761 ctrl |= S3C_DxEPCTL_EPEna; /* ensure ep enabled */
762 ctrl |= S3C_DxEPCTL_USBActEp;
763 ctrl |= S3C_DxEPCTL_CNAK; /* clear NAK set by core */
765 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
766 writel(ctrl, hsotg->regs + epctrl_reg);
768 /* set these, it seems that DMA support increments past the end
769 * of the packet buffer so we need to calculate the length from
770 * this information. */
771 hs_ep->size_loaded = length;
772 hs_ep->last_load = ureq->actual;
774 if (dir_in && !using_dma(hsotg)) {
775 /* set these anyway, we may need them for non-periodic in */
776 hs_ep->fifo_load = 0;
778 s3c_hsotg_write_fifo(hsotg, hs_ep, hs_req);
781 /* clear the INTknTXFEmpMsk when we start request, more as a aide
782 * to debugging to see what is going on. */
784 writel(S3C_DIEPMSK_INTknTXFEmpMsk,
785 hsotg->regs + S3C_DIEPINT(index));
787 /* Note, trying to clear the NAK here causes problems with transmit
788 * on the S3C6400 ending up with the TXFIFO becomming full. */
790 /* check ep is enabled */
791 if (!(readl(hsotg->regs + epctrl_reg) & S3C_DxEPCTL_EPEna))
793 "ep%d: failed to become enabled (DxEPCTL=0x%08x)?\n",
794 index, readl(hsotg->regs + epctrl_reg));
796 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n",
797 __func__, readl(hsotg->regs + epctrl_reg));
801 * s3c_hsotg_map_dma - map the DMA memory being used for the request
802 * @hsotg: The device state.
803 * @hs_ep: The endpoint the request is on.
804 * @req: The request being processed.
806 * We've been asked to queue a request, so ensure that the memory buffer
807 * is correctly setup for DMA. If we've been passed an extant DMA address
808 * then ensure the buffer has been synced to memory. If our buffer has no
809 * DMA memory, then we map the memory and mark our request to allow us to
810 * cleanup on completion.
812 static int s3c_hsotg_map_dma(struct s3c_hsotg *hsotg,
813 struct s3c_hsotg_ep *hs_ep,
814 struct usb_request *req)
816 enum dma_data_direction dir;
817 struct s3c_hsotg_req *hs_req = our_req(req);
819 dir = hs_ep->dir_in ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
821 /* if the length is zero, ignore the DMA data */
822 if (hs_req->req.length == 0)
825 if (req->dma == DMA_ADDR_INVALID) {
828 dma = dma_map_single(hsotg->dev, req->buf, req->length, dir);
830 if (unlikely(dma_mapping_error(hsotg->dev, dma)))
834 dev_err(hsotg->dev, "%s: unaligned dma buffer\n",
837 dma_unmap_single(hsotg->dev, dma, req->length, dir);
844 dma_sync_single_for_cpu(hsotg->dev, req->dma, req->length, dir);
851 dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n",
852 __func__, req->buf, req->length);
857 static int s3c_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
860 struct s3c_hsotg_req *hs_req = our_req(req);
861 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
862 struct s3c_hsotg *hs = hs_ep->parent;
863 unsigned long irqflags;
866 dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
867 ep->name, req, req->length, req->buf, req->no_interrupt,
868 req->zero, req->short_not_ok);
870 /* initialise status of the request */
871 INIT_LIST_HEAD(&hs_req->queue);
873 req->status = -EINPROGRESS;
875 /* if we're using DMA, sync the buffers as necessary */
877 int ret = s3c_hsotg_map_dma(hs, hs_ep, req);
882 spin_lock_irqsave(&hs_ep->lock, irqflags);
884 first = list_empty(&hs_ep->queue);
885 list_add_tail(&hs_req->queue, &hs_ep->queue);
888 s3c_hsotg_start_req(hs, hs_ep, hs_req, false);
890 spin_unlock_irqrestore(&hs_ep->lock, irqflags);
895 static void s3c_hsotg_ep_free_request(struct usb_ep *ep,
896 struct usb_request *req)
898 struct s3c_hsotg_req *hs_req = our_req(req);
904 * s3c_hsotg_complete_oursetup - setup completion callback
905 * @ep: The endpoint the request was on.
906 * @req: The request completed.
908 * Called on completion of any requests the driver itself
909 * submitted that need cleaning up.
911 static void s3c_hsotg_complete_oursetup(struct usb_ep *ep,
912 struct usb_request *req)
914 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
915 struct s3c_hsotg *hsotg = hs_ep->parent;
917 dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req);
919 s3c_hsotg_ep_free_request(ep, req);
923 * ep_from_windex - convert control wIndex value to endpoint
924 * @hsotg: The driver state.
925 * @windex: The control request wIndex field (in host order).
927 * Convert the given wIndex into a pointer to an driver endpoint
928 * structure, or return NULL if it is not a valid endpoint.
930 static struct s3c_hsotg_ep *ep_from_windex(struct s3c_hsotg *hsotg,
933 struct s3c_hsotg_ep *ep = &hsotg->eps[windex & 0x7F];
934 int dir = (windex & USB_DIR_IN) ? 1 : 0;
935 int idx = windex & 0x7F;
940 if (idx > S3C_HSOTG_EPS)
943 if (idx && ep->dir_in != dir)
950 * s3c_hsotg_send_reply - send reply to control request
951 * @hsotg: The device state
953 * @buff: Buffer for request
954 * @length: Length of reply.
956 * Create a request and queue it on the given endpoint. This is useful as
957 * an internal method of sending replies to certain control requests, etc.
959 static int s3c_hsotg_send_reply(struct s3c_hsotg *hsotg,
960 struct s3c_hsotg_ep *ep,
964 struct usb_request *req;
967 dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length);
969 req = s3c_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC);
970 hsotg->ep0_reply = req;
972 dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__);
976 req->buf = hsotg->ep0_buff;
977 req->length = length;
978 req->zero = 1; /* always do zero-length final transfer */
979 req->complete = s3c_hsotg_complete_oursetup;
982 memcpy(req->buf, buff, length);
986 ret = s3c_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC);
988 dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__);
996 * s3c_hsotg_process_req_status - process request GET_STATUS
997 * @hsotg: The device state
998 * @ctrl: USB control request
1000 static int s3c_hsotg_process_req_status(struct s3c_hsotg *hsotg,
1001 struct usb_ctrlrequest *ctrl)
1003 struct s3c_hsotg_ep *ep0 = &hsotg->eps[0];
1004 struct s3c_hsotg_ep *ep;
1008 dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__);
1011 dev_warn(hsotg->dev, "%s: direction out?\n", __func__);
1015 switch (ctrl->bRequestType & USB_RECIP_MASK) {
1016 case USB_RECIP_DEVICE:
1017 reply = cpu_to_le16(0); /* bit 0 => self powered,
1018 * bit 1 => remote wakeup */
1021 case USB_RECIP_INTERFACE:
1022 /* currently, the data result should be zero */
1023 reply = cpu_to_le16(0);
1026 case USB_RECIP_ENDPOINT:
1027 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
1031 reply = cpu_to_le16(ep->halted ? 1 : 0);
1038 if (le16_to_cpu(ctrl->wLength) != 2)
1041 ret = s3c_hsotg_send_reply(hsotg, ep0, &reply, 2);
1043 dev_err(hsotg->dev, "%s: failed to send reply\n", __func__);
1050 static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value);
1053 * s3c_hsotg_process_req_featire - process request {SET,CLEAR}_FEATURE
1054 * @hsotg: The device state
1055 * @ctrl: USB control request
1057 static int s3c_hsotg_process_req_feature(struct s3c_hsotg *hsotg,
1058 struct usb_ctrlrequest *ctrl)
1060 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
1061 struct s3c_hsotg_ep *ep;
1063 dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",
1064 __func__, set ? "SET" : "CLEAR");
1066 if (ctrl->bRequestType == USB_RECIP_ENDPOINT) {
1067 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
1069 dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n",
1070 __func__, le16_to_cpu(ctrl->wIndex));
1074 switch (le16_to_cpu(ctrl->wValue)) {
1075 case USB_ENDPOINT_HALT:
1076 s3c_hsotg_ep_sethalt(&ep->ep, set);
1083 return -ENOENT; /* currently only deal with endpoint */
1089 * s3c_hsotg_process_control - process a control request
1090 * @hsotg: The device state
1091 * @ctrl: The control request received
1093 * The controller has received the SETUP phase of a control request, and
1094 * needs to work out what to do next (and whether to pass it on to the
1097 static void s3c_hsotg_process_control(struct s3c_hsotg *hsotg,
1098 struct usb_ctrlrequest *ctrl)
1100 struct s3c_hsotg_ep *ep0 = &hsotg->eps[0];
1106 dev_dbg(hsotg->dev, "ctrl Req=%02x, Type=%02x, V=%04x, L=%04x\n",
1107 ctrl->bRequest, ctrl->bRequestType,
1108 ctrl->wValue, ctrl->wLength);
1110 /* record the direction of the request, for later use when enquing
1111 * packets onto EP0. */
1113 ep0->dir_in = (ctrl->bRequestType & USB_DIR_IN) ? 1 : 0;
1114 dev_dbg(hsotg->dev, "ctrl: dir_in=%d\n", ep0->dir_in);
1116 /* if we've no data with this request, then the last part of the
1117 * transaction is going to implicitly be IN. */
1118 if (ctrl->wLength == 0)
1121 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1122 switch (ctrl->bRequest) {
1123 case USB_REQ_SET_ADDRESS:
1124 dcfg = readl(hsotg->regs + S3C_DCFG);
1125 dcfg &= ~S3C_DCFG_DevAddr_MASK;
1126 dcfg |= ctrl->wValue << S3C_DCFG_DevAddr_SHIFT;
1127 writel(dcfg, hsotg->regs + S3C_DCFG);
1129 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1131 ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0);
1134 case USB_REQ_GET_STATUS:
1135 ret = s3c_hsotg_process_req_status(hsotg, ctrl);
1138 case USB_REQ_CLEAR_FEATURE:
1139 case USB_REQ_SET_FEATURE:
1140 ret = s3c_hsotg_process_req_feature(hsotg, ctrl);
1145 /* as a fallback, try delivering it to the driver to deal with */
1147 if (ret == 0 && hsotg->driver) {
1148 ret = hsotg->driver->setup(&hsotg->gadget, ctrl);
1150 dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
1155 /* need to generate zlp in reply or take data */
1156 /* todo - deal with any data we might be sent? */
1157 ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0);
1161 /* the request is either unhandlable, or is not formatted correctly
1162 * so respond with a STALL for the status stage to indicate failure.
1169 dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
1170 reg = (ep0->dir_in) ? S3C_DIEPCTL0 : S3C_DOEPCTL0;
1172 /* S3C_DxEPCTL_Stall will be cleared by EP once it has
1173 * taken effect, so no need to clear later. */
1175 ctrl = readl(hsotg->regs + reg);
1176 ctrl |= S3C_DxEPCTL_Stall;
1177 ctrl |= S3C_DxEPCTL_CNAK;
1178 writel(ctrl, hsotg->regs + reg);
1181 "writen DxEPCTL=0x%08x to %08x (DxEPCTL=0x%08x)\n",
1182 ctrl, reg, readl(hsotg->regs + reg));
1184 /* don't belive we need to anything more to get the EP
1185 * to reply with a STALL packet */
1189 static void s3c_hsotg_enqueue_setup(struct s3c_hsotg *hsotg);
1192 * s3c_hsotg_complete_setup - completion of a setup transfer
1193 * @ep: The endpoint the request was on.
1194 * @req: The request completed.
1196 * Called on completion of any requests the driver itself submitted for
1199 static void s3c_hsotg_complete_setup(struct usb_ep *ep,
1200 struct usb_request *req)
1202 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
1203 struct s3c_hsotg *hsotg = hs_ep->parent;
1205 if (req->status < 0) {
1206 dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status);
1210 if (req->actual == 0)
1211 s3c_hsotg_enqueue_setup(hsotg);
1213 s3c_hsotg_process_control(hsotg, req->buf);
1217 * s3c_hsotg_enqueue_setup - start a request for EP0 packets
1218 * @hsotg: The device state.
1220 * Enqueue a request on EP0 if necessary to received any SETUP packets
1221 * received from the host.
1223 static void s3c_hsotg_enqueue_setup(struct s3c_hsotg *hsotg)
1225 struct usb_request *req = hsotg->ctrl_req;
1226 struct s3c_hsotg_req *hs_req = our_req(req);
1229 dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__);
1233 req->buf = hsotg->ctrl_buff;
1234 req->complete = s3c_hsotg_complete_setup;
1236 if (!list_empty(&hs_req->queue)) {
1237 dev_dbg(hsotg->dev, "%s already queued???\n", __func__);
1241 hsotg->eps[0].dir_in = 0;
1243 ret = s3c_hsotg_ep_queue(&hsotg->eps[0].ep, req, GFP_ATOMIC);
1245 dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret);
1246 /* Don't think there's much we can do other than watch the
1252 * get_ep_head - return the first request on the endpoint
1253 * @hs_ep: The controller endpoint to get
1255 * Get the first request on the endpoint.
1257 static struct s3c_hsotg_req *get_ep_head(struct s3c_hsotg_ep *hs_ep)
1259 if (list_empty(&hs_ep->queue))
1262 return list_first_entry(&hs_ep->queue, struct s3c_hsotg_req, queue);
1266 * s3c_hsotg_complete_request - complete a request given to us
1267 * @hsotg: The device state.
1268 * @hs_ep: The endpoint the request was on.
1269 * @hs_req: The request to complete.
1270 * @result: The result code (0 => Ok, otherwise errno)
1272 * The given request has finished, so call the necessary completion
1273 * if it has one and then look to see if we can start a new request
1276 * Note, expects the ep to already be locked as appropriate.
1278 static void s3c_hsotg_complete_request(struct s3c_hsotg *hsotg,
1279 struct s3c_hsotg_ep *hs_ep,
1280 struct s3c_hsotg_req *hs_req,
1286 dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__);
1290 dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n",
1291 hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete);
1293 /* only replace the status if we've not already set an error
1294 * from a previous transaction */
1296 if (hs_req->req.status == -EINPROGRESS)
1297 hs_req->req.status = result;
1300 list_del_init(&hs_req->queue);
1302 if (using_dma(hsotg))
1303 s3c_hsotg_unmap_dma(hsotg, hs_ep, hs_req);
1305 /* call the complete request with the locks off, just in case the
1306 * request tries to queue more work for this endpoint. */
1308 if (hs_req->req.complete) {
1309 spin_unlock(&hs_ep->lock);
1310 hs_req->req.complete(&hs_ep->ep, &hs_req->req);
1311 spin_lock(&hs_ep->lock);
1314 /* Look to see if there is anything else to do. Note, the completion
1315 * of the previous request may have caused a new request to be started
1316 * so be careful when doing this. */
1318 if (!hs_ep->req && result >= 0) {
1319 restart = !list_empty(&hs_ep->queue);
1321 hs_req = get_ep_head(hs_ep);
1322 s3c_hsotg_start_req(hsotg, hs_ep, hs_req, false);
1328 * s3c_hsotg_complete_request_lock - complete a request given to us (locked)
1329 * @hsotg: The device state.
1330 * @hs_ep: The endpoint the request was on.
1331 * @hs_req: The request to complete.
1332 * @result: The result code (0 => Ok, otherwise errno)
1334 * See s3c_hsotg_complete_request(), but called with the endpoint's
1337 static void s3c_hsotg_complete_request_lock(struct s3c_hsotg *hsotg,
1338 struct s3c_hsotg_ep *hs_ep,
1339 struct s3c_hsotg_req *hs_req,
1342 unsigned long flags;
1344 spin_lock_irqsave(&hs_ep->lock, flags);
1345 s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
1346 spin_unlock_irqrestore(&hs_ep->lock, flags);
1350 * s3c_hsotg_rx_data - receive data from the FIFO for an endpoint
1351 * @hsotg: The device state.
1352 * @ep_idx: The endpoint index for the data
1353 * @size: The size of data in the fifo, in bytes
1355 * The FIFO status shows there is data to read from the FIFO for a given
1356 * endpoint, so sort out whether we need to read the data into a request
1357 * that has been made for that endpoint.
1359 static void s3c_hsotg_rx_data(struct s3c_hsotg *hsotg, int ep_idx, int size)
1361 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[ep_idx];
1362 struct s3c_hsotg_req *hs_req = hs_ep->req;
1363 void __iomem *fifo = hsotg->regs + S3C_EPFIFO(ep_idx);
1369 u32 epctl = readl(hsotg->regs + S3C_DOEPCTL(ep_idx));
1372 dev_warn(hsotg->dev,
1373 "%s: FIFO %d bytes on ep%d but no req (DxEPCTl=0x%08x)\n",
1374 __func__, size, ep_idx, epctl);
1376 /* dump the data from the FIFO, we've nothing we can do */
1377 for (ptr = 0; ptr < size; ptr += 4)
1383 spin_lock(&hs_ep->lock);
1386 read_ptr = hs_req->req.actual;
1387 max_req = hs_req->req.length - read_ptr;
1389 dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n",
1390 __func__, to_read, max_req, read_ptr, hs_req->req.length);
1392 if (to_read > max_req) {
1393 /* more data appeared than we where willing
1394 * to deal with in this request.
1397 /* currently we don't deal this */
1401 hs_ep->total_data += to_read;
1402 hs_req->req.actual += to_read;
1403 to_read = DIV_ROUND_UP(to_read, 4);
1405 /* note, we might over-write the buffer end by 3 bytes depending on
1406 * alignment of the data. */
1407 readsl(fifo, hs_req->req.buf + read_ptr, to_read);
1409 spin_unlock(&hs_ep->lock);
1413 * s3c_hsotg_send_zlp - send zero-length packet on control endpoint
1414 * @hsotg: The device instance
1415 * @req: The request currently on this endpoint
1417 * Generate a zero-length IN packet request for terminating a SETUP
1420 * Note, since we don't write any data to the TxFIFO, then it is
1421 * currently belived that we do not need to wait for any space in
1424 static void s3c_hsotg_send_zlp(struct s3c_hsotg *hsotg,
1425 struct s3c_hsotg_req *req)
1430 dev_warn(hsotg->dev, "%s: no request?\n", __func__);
1434 if (req->req.length == 0) {
1435 hsotg->eps[0].sent_zlp = 1;
1436 s3c_hsotg_enqueue_setup(hsotg);
1440 hsotg->eps[0].dir_in = 1;
1441 hsotg->eps[0].sent_zlp = 1;
1443 dev_dbg(hsotg->dev, "sending zero-length packet\n");
1445 /* issue a zero-sized packet to terminate this */
1446 writel(S3C_DxEPTSIZ_MC(1) | S3C_DxEPTSIZ_PktCnt(1) |
1447 S3C_DxEPTSIZ_XferSize(0), hsotg->regs + S3C_DIEPTSIZ(0));
1449 ctrl = readl(hsotg->regs + S3C_DIEPCTL0);
1450 ctrl |= S3C_DxEPCTL_CNAK; /* clear NAK set by core */
1451 ctrl |= S3C_DxEPCTL_EPEna; /* ensure ep enabled */
1452 ctrl |= S3C_DxEPCTL_USBActEp;
1453 writel(ctrl, hsotg->regs + S3C_DIEPCTL0);
1457 * s3c_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
1458 * @hsotg: The device instance
1459 * @epnum: The endpoint received from
1460 * @was_setup: Set if processing a SetupDone event.
1462 * The RXFIFO has delivered an OutDone event, which means that the data
1463 * transfer for an OUT endpoint has been completed, either by a short
1464 * packet or by the finish of a transfer.
1466 static void s3c_hsotg_handle_outdone(struct s3c_hsotg *hsotg,
1467 int epnum, bool was_setup)
1469 u32 epsize = readl(hsotg->regs + S3C_DOEPTSIZ(epnum));
1470 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[epnum];
1471 struct s3c_hsotg_req *hs_req = hs_ep->req;
1472 struct usb_request *req = &hs_req->req;
1473 unsigned size_left = S3C_DxEPTSIZ_XferSize_GET(epsize);
1477 dev_dbg(hsotg->dev, "%s: no request active\n", __func__);
1481 if (using_dma(hsotg)) {
1484 /* Calculate the size of the transfer by checking how much
1485 * is left in the endpoint size register and then working it
1486 * out from the amount we loaded for the transfer.
1488 * We need to do this as DMA pointers are always 32bit aligned
1489 * so may overshoot/undershoot the transfer.
1492 size_done = hs_ep->size_loaded - size_left;
1493 size_done += hs_ep->last_load;
1495 req->actual = size_done;
1498 /* if there is more request to do, schedule new transfer */
1499 if (req->actual < req->length && size_left == 0) {
1500 s3c_hsotg_start_req(hsotg, hs_ep, hs_req, true);
1504 if (req->actual < req->length && req->short_not_ok) {
1505 dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",
1506 __func__, req->actual, req->length);
1508 /* todo - what should we return here? there's no one else
1509 * even bothering to check the status. */
1513 if (!was_setup && req->complete != s3c_hsotg_complete_setup)
1514 s3c_hsotg_send_zlp(hsotg, hs_req);
1517 s3c_hsotg_complete_request_lock(hsotg, hs_ep, hs_req, result);
1521 * s3c_hsotg_read_frameno - read current frame number
1522 * @hsotg: The device instance
1524 * Return the current frame number
1526 static u32 s3c_hsotg_read_frameno(struct s3c_hsotg *hsotg)
1530 dsts = readl(hsotg->regs + S3C_DSTS);
1531 dsts &= S3C_DSTS_SOFFN_MASK;
1532 dsts >>= S3C_DSTS_SOFFN_SHIFT;
1538 * s3c_hsotg_handle_rx - RX FIFO has data
1539 * @hsotg: The device instance
1541 * The IRQ handler has detected that the RX FIFO has some data in it
1542 * that requires processing, so find out what is in there and do the
1545 * The RXFIFO is a true FIFO, the packets comming out are still in packet
1546 * chunks, so if you have x packets received on an endpoint you'll get x
1547 * FIFO events delivered, each with a packet's worth of data in it.
1549 * When using DMA, we should not be processing events from the RXFIFO
1550 * as the actual data should be sent to the memory directly and we turn
1551 * on the completion interrupts to get notifications of transfer completion.
1553 static void s3c_hsotg_handle_rx(struct s3c_hsotg *hsotg)
1555 u32 grxstsr = readl(hsotg->regs + S3C_GRXSTSP);
1556 u32 epnum, status, size;
1558 WARN_ON(using_dma(hsotg));
1560 epnum = grxstsr & S3C_GRXSTS_EPNum_MASK;
1561 status = grxstsr & S3C_GRXSTS_PktSts_MASK;
1563 size = grxstsr & S3C_GRXSTS_ByteCnt_MASK;
1564 size >>= S3C_GRXSTS_ByteCnt_SHIFT;
1567 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
1568 __func__, grxstsr, size, epnum);
1570 #define __status(x) ((x) >> S3C_GRXSTS_PktSts_SHIFT)
1572 switch (status >> S3C_GRXSTS_PktSts_SHIFT) {
1573 case __status(S3C_GRXSTS_PktSts_GlobalOutNAK):
1574 dev_dbg(hsotg->dev, "GlobalOutNAK\n");
1577 case __status(S3C_GRXSTS_PktSts_OutDone):
1578 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
1579 s3c_hsotg_read_frameno(hsotg));
1581 if (!using_dma(hsotg))
1582 s3c_hsotg_handle_outdone(hsotg, epnum, false);
1585 case __status(S3C_GRXSTS_PktSts_SetupDone):
1587 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1588 s3c_hsotg_read_frameno(hsotg),
1589 readl(hsotg->regs + S3C_DOEPCTL(0)));
1591 s3c_hsotg_handle_outdone(hsotg, epnum, true);
1594 case __status(S3C_GRXSTS_PktSts_OutRX):
1595 s3c_hsotg_rx_data(hsotg, epnum, size);
1598 case __status(S3C_GRXSTS_PktSts_SetupRX):
1600 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1601 s3c_hsotg_read_frameno(hsotg),
1602 readl(hsotg->regs + S3C_DOEPCTL(0)));
1604 s3c_hsotg_rx_data(hsotg, epnum, size);
1608 dev_warn(hsotg->dev, "%s: unknown status %08x\n",
1611 s3c_hsotg_dump(hsotg);
1617 * s3c_hsotg_ep0_mps - turn max packet size into register setting
1618 * @mps: The maximum packet size in bytes.
1620 static u32 s3c_hsotg_ep0_mps(unsigned int mps)
1624 return S3C_D0EPCTL_MPS_64;
1626 return S3C_D0EPCTL_MPS_32;
1628 return S3C_D0EPCTL_MPS_16;
1630 return S3C_D0EPCTL_MPS_8;
1633 /* bad max packet size, warn and return invalid result */
1639 * s3c_hsotg_set_ep_maxpacket - set endpoint's max-packet field
1640 * @hsotg: The driver state.
1641 * @ep: The index number of the endpoint
1642 * @mps: The maximum packet size in bytes
1644 * Configure the maximum packet size for the given endpoint, updating
1645 * the hardware control registers to reflect this.
1647 static void s3c_hsotg_set_ep_maxpacket(struct s3c_hsotg *hsotg,
1648 unsigned int ep, unsigned int mps)
1650 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[ep];
1651 void __iomem *regs = hsotg->regs;
1656 /* EP0 is a special case */
1657 mpsval = s3c_hsotg_ep0_mps(mps);
1661 if (mps >= S3C_DxEPCTL_MPS_LIMIT+1)
1667 hs_ep->ep.maxpacket = mps;
1669 /* update both the in and out endpoint controldir_ registers, even
1670 * if one of the directions may not be in use. */
1672 reg = readl(regs + S3C_DIEPCTL(ep));
1673 reg &= ~S3C_DxEPCTL_MPS_MASK;
1675 writel(reg, regs + S3C_DIEPCTL(ep));
1677 reg = readl(regs + S3C_DOEPCTL(ep));
1678 reg &= ~S3C_DxEPCTL_MPS_MASK;
1680 writel(reg, regs + S3C_DOEPCTL(ep));
1685 dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps);
1690 * s3c_hsotg_trytx - check to see if anything needs transmitting
1691 * @hsotg: The driver state
1692 * @hs_ep: The driver endpoint to check.
1694 * Check to see if there is a request that has data to send, and if so
1695 * make an attempt to write data into the FIFO.
1697 static int s3c_hsotg_trytx(struct s3c_hsotg *hsotg,
1698 struct s3c_hsotg_ep *hs_ep)
1700 struct s3c_hsotg_req *hs_req = hs_ep->req;
1702 if (!hs_ep->dir_in || !hs_req)
1705 if (hs_req->req.actual < hs_req->req.length) {
1706 dev_dbg(hsotg->dev, "trying to write more for ep%d\n",
1708 return s3c_hsotg_write_fifo(hsotg, hs_ep, hs_req);
1715 * s3c_hsotg_complete_in - complete IN transfer
1716 * @hsotg: The device state.
1717 * @hs_ep: The endpoint that has just completed.
1719 * An IN transfer has been completed, update the transfer's state and then
1720 * call the relevant completion routines.
1722 static void s3c_hsotg_complete_in(struct s3c_hsotg *hsotg,
1723 struct s3c_hsotg_ep *hs_ep)
1725 struct s3c_hsotg_req *hs_req = hs_ep->req;
1726 u32 epsize = readl(hsotg->regs + S3C_DIEPTSIZ(hs_ep->index));
1727 int size_left, size_done;
1730 dev_dbg(hsotg->dev, "XferCompl but no req\n");
1734 /* Calculate the size of the transfer by checking how much is left
1735 * in the endpoint size register and then working it out from
1736 * the amount we loaded for the transfer.
1738 * We do this even for DMA, as the transfer may have incremented
1739 * past the end of the buffer (DMA transfers are always 32bit
1743 size_left = S3C_DxEPTSIZ_XferSize_GET(epsize);
1745 size_done = hs_ep->size_loaded - size_left;
1746 size_done += hs_ep->last_load;
1748 if (hs_req->req.actual != size_done)
1749 dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n",
1750 __func__, hs_req->req.actual, size_done);
1752 hs_req->req.actual = size_done;
1754 /* if we did all of the transfer, and there is more data left
1755 * around, then try restarting the rest of the request */
1757 if (!size_left && hs_req->req.actual < hs_req->req.length) {
1758 dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__);
1759 s3c_hsotg_start_req(hsotg, hs_ep, hs_req, true);
1761 s3c_hsotg_complete_request_lock(hsotg, hs_ep, hs_req, 0);
1765 * s3c_hsotg_epint - handle an in/out endpoint interrupt
1766 * @hsotg: The driver state
1767 * @idx: The index for the endpoint (0..15)
1768 * @dir_in: Set if this is an IN endpoint
1770 * Process and clear any interrupt pending for an individual endpoint
1772 static void s3c_hsotg_epint(struct s3c_hsotg *hsotg, unsigned int idx,
1775 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[idx];
1776 u32 epint_reg = dir_in ? S3C_DIEPINT(idx) : S3C_DOEPINT(idx);
1777 u32 epctl_reg = dir_in ? S3C_DIEPCTL(idx) : S3C_DOEPCTL(idx);
1778 u32 epsiz_reg = dir_in ? S3C_DIEPTSIZ(idx) : S3C_DOEPTSIZ(idx);
1782 ints = readl(hsotg->regs + epint_reg);
1784 dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
1785 __func__, idx, dir_in ? "in" : "out", ints);
1787 if (ints & S3C_DxEPINT_XferCompl) {
1789 "%s: XferCompl: DxEPCTL=0x%08x, DxEPTSIZ=%08x\n",
1790 __func__, readl(hsotg->regs + epctl_reg),
1791 readl(hsotg->regs + epsiz_reg));
1793 /* we get OutDone from the FIFO, so we only need to look
1794 * at completing IN requests here */
1796 s3c_hsotg_complete_in(hsotg, hs_ep);
1798 if (idx == 0 && !hs_ep->req)
1799 s3c_hsotg_enqueue_setup(hsotg);
1800 } else if (using_dma(hsotg)) {
1801 /* We're using DMA, we need to fire an OutDone here
1802 * as we ignore the RXFIFO. */
1804 s3c_hsotg_handle_outdone(hsotg, idx, false);
1807 clear |= S3C_DxEPINT_XferCompl;
1810 if (ints & S3C_DxEPINT_EPDisbld) {
1811 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
1812 clear |= S3C_DxEPINT_EPDisbld;
1815 if (ints & S3C_DxEPINT_AHBErr) {
1816 dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
1817 clear |= S3C_DxEPINT_AHBErr;
1820 if (ints & S3C_DxEPINT_Setup) { /* Setup or Timeout */
1821 dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__);
1823 if (using_dma(hsotg) && idx == 0) {
1824 /* this is the notification we've received a
1825 * setup packet. In non-DMA mode we'd get this
1826 * from the RXFIFO, instead we need to process
1827 * the setup here. */
1832 s3c_hsotg_handle_outdone(hsotg, 0, true);
1835 clear |= S3C_DxEPINT_Setup;
1838 if (ints & S3C_DxEPINT_Back2BackSetup) {
1839 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
1840 clear |= S3C_DxEPINT_Back2BackSetup;
1844 /* not sure if this is important, but we'll clear it anyway
1846 if (ints & S3C_DIEPMSK_INTknTXFEmpMsk) {
1847 dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
1849 clear |= S3C_DIEPMSK_INTknTXFEmpMsk;
1852 /* this probably means something bad is happening */
1853 if (ints & S3C_DIEPMSK_INTknEPMisMsk) {
1854 dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
1856 clear |= S3C_DIEPMSK_INTknEPMisMsk;
1859 /* FIFO has space or is empty (see GAHBCFG) */
1860 if (hsotg->dedicated_fifos &&
1861 ints & S3C_DIEPMSK_TxFIFOEmpty) {
1862 dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n",
1864 s3c_hsotg_trytx(hsotg, hs_ep);
1865 clear |= S3C_DIEPMSK_TxFIFOEmpty;
1869 writel(clear, hsotg->regs + epint_reg);
1873 * s3c_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
1874 * @hsotg: The device state.
1876 * Handle updating the device settings after the enumeration phase has
1879 static void s3c_hsotg_irq_enumdone(struct s3c_hsotg *hsotg)
1881 u32 dsts = readl(hsotg->regs + S3C_DSTS);
1882 int ep0_mps = 0, ep_mps;
1884 /* This should signal the finish of the enumeration phase
1885 * of the USB handshaking, so we should now know what rate
1886 * we connected at. */
1888 dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts);
1890 /* note, since we're limited by the size of transfer on EP0, and
1891 * it seems IN transfers must be a even number of packets we do
1892 * not advertise a 64byte MPS on EP0. */
1894 /* catch both EnumSpd_FS and EnumSpd_FS48 */
1895 switch (dsts & S3C_DSTS_EnumSpd_MASK) {
1896 case S3C_DSTS_EnumSpd_FS:
1897 case S3C_DSTS_EnumSpd_FS48:
1898 hsotg->gadget.speed = USB_SPEED_FULL;
1899 dev_info(hsotg->dev, "new device is full-speed\n");
1901 ep0_mps = EP0_MPS_LIMIT;
1905 case S3C_DSTS_EnumSpd_HS:
1906 dev_info(hsotg->dev, "new device is high-speed\n");
1907 hsotg->gadget.speed = USB_SPEED_HIGH;
1909 ep0_mps = EP0_MPS_LIMIT;
1913 case S3C_DSTS_EnumSpd_LS:
1914 hsotg->gadget.speed = USB_SPEED_LOW;
1915 dev_info(hsotg->dev, "new device is low-speed\n");
1917 /* note, we don't actually support LS in this driver at the
1918 * moment, and the documentation seems to imply that it isn't
1919 * supported by the PHYs on some of the devices.
1924 /* we should now know the maximum packet size for an
1925 * endpoint, so set the endpoints to a default value. */
1929 s3c_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps);
1930 for (i = 1; i < S3C_HSOTG_EPS; i++)
1931 s3c_hsotg_set_ep_maxpacket(hsotg, i, ep_mps);
1934 /* ensure after enumeration our EP0 is active */
1936 s3c_hsotg_enqueue_setup(hsotg);
1938 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
1939 readl(hsotg->regs + S3C_DIEPCTL0),
1940 readl(hsotg->regs + S3C_DOEPCTL0));
1944 * kill_all_requests - remove all requests from the endpoint's queue
1945 * @hsotg: The device state.
1946 * @ep: The endpoint the requests may be on.
1947 * @result: The result code to use.
1948 * @force: Force removal of any current requests
1950 * Go through the requests on the given endpoint and mark them
1951 * completed with the given result code.
1953 static void kill_all_requests(struct s3c_hsotg *hsotg,
1954 struct s3c_hsotg_ep *ep,
1955 int result, bool force)
1957 struct s3c_hsotg_req *req, *treq;
1958 unsigned long flags;
1960 spin_lock_irqsave(&ep->lock, flags);
1962 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
1963 /* currently, we can't do much about an already
1964 * running request on an in endpoint */
1966 if (ep->req == req && ep->dir_in && !force)
1969 s3c_hsotg_complete_request(hsotg, ep, req,
1973 spin_unlock_irqrestore(&ep->lock, flags);
1976 #define call_gadget(_hs, _entry) \
1977 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \
1978 (_hs)->driver && (_hs)->driver->_entry) \
1979 (_hs)->driver->_entry(&(_hs)->gadget);
1982 * s3c_hsotg_disconnect_irq - disconnect irq service
1983 * @hsotg: The device state.
1985 * A disconnect IRQ has been received, meaning that the host has
1986 * lost contact with the bus. Remove all current transactions
1987 * and signal the gadget driver that this has happened.
1989 static void s3c_hsotg_disconnect_irq(struct s3c_hsotg *hsotg)
1993 for (ep = 0; ep < S3C_HSOTG_EPS; ep++)
1994 kill_all_requests(hsotg, &hsotg->eps[ep], -ESHUTDOWN, true);
1996 call_gadget(hsotg, disconnect);
2000 * s3c_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
2001 * @hsotg: The device state:
2002 * @periodic: True if this is a periodic FIFO interrupt
2004 static void s3c_hsotg_irq_fifoempty(struct s3c_hsotg *hsotg, bool periodic)
2006 struct s3c_hsotg_ep *ep;
2009 /* look through for any more data to transmit */
2011 for (epno = 0; epno < S3C_HSOTG_EPS; epno++) {
2012 ep = &hsotg->eps[epno];
2017 if ((periodic && !ep->periodic) ||
2018 (!periodic && ep->periodic))
2021 ret = s3c_hsotg_trytx(hsotg, ep);
2027 static struct s3c_hsotg *our_hsotg;
2029 /* IRQ flags which will trigger a retry around the IRQ loop */
2030 #define IRQ_RETRY_MASK (S3C_GINTSTS_NPTxFEmp | \
2031 S3C_GINTSTS_PTxFEmp | \
2035 * s3c_hsotg_irq - handle device interrupt
2036 * @irq: The IRQ number triggered
2037 * @pw: The pw value when registered the handler.
2039 static irqreturn_t s3c_hsotg_irq(int irq, void *pw)
2041 struct s3c_hsotg *hsotg = pw;
2042 int retry_count = 8;
2047 gintsts = readl(hsotg->regs + S3C_GINTSTS);
2048 gintmsk = readl(hsotg->regs + S3C_GINTMSK);
2050 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
2051 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
2055 if (gintsts & S3C_GINTSTS_OTGInt) {
2056 u32 otgint = readl(hsotg->regs + S3C_GOTGINT);
2058 dev_info(hsotg->dev, "OTGInt: %08x\n", otgint);
2060 writel(otgint, hsotg->regs + S3C_GOTGINT);
2061 writel(S3C_GINTSTS_OTGInt, hsotg->regs + S3C_GINTSTS);
2064 if (gintsts & S3C_GINTSTS_DisconnInt) {
2065 dev_dbg(hsotg->dev, "%s: DisconnInt\n", __func__);
2066 writel(S3C_GINTSTS_DisconnInt, hsotg->regs + S3C_GINTSTS);
2068 s3c_hsotg_disconnect_irq(hsotg);
2071 if (gintsts & S3C_GINTSTS_SessReqInt) {
2072 dev_dbg(hsotg->dev, "%s: SessReqInt\n", __func__);
2073 writel(S3C_GINTSTS_SessReqInt, hsotg->regs + S3C_GINTSTS);
2076 if (gintsts & S3C_GINTSTS_EnumDone) {
2077 s3c_hsotg_irq_enumdone(hsotg);
2078 writel(S3C_GINTSTS_EnumDone, hsotg->regs + S3C_GINTSTS);
2081 if (gintsts & S3C_GINTSTS_ConIDStsChng) {
2082 dev_dbg(hsotg->dev, "ConIDStsChg (DSTS=0x%08x, GOTCTL=%08x)\n",
2083 readl(hsotg->regs + S3C_DSTS),
2084 readl(hsotg->regs + S3C_GOTGCTL));
2086 writel(S3C_GINTSTS_ConIDStsChng, hsotg->regs + S3C_GINTSTS);
2089 if (gintsts & (S3C_GINTSTS_OEPInt | S3C_GINTSTS_IEPInt)) {
2090 u32 daint = readl(hsotg->regs + S3C_DAINT);
2091 u32 daint_out = daint >> S3C_DAINT_OutEP_SHIFT;
2092 u32 daint_in = daint & ~(daint_out << S3C_DAINT_OutEP_SHIFT);
2095 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
2097 for (ep = 0; ep < 15 && daint_out; ep++, daint_out >>= 1) {
2099 s3c_hsotg_epint(hsotg, ep, 0);
2102 for (ep = 0; ep < 15 && daint_in; ep++, daint_in >>= 1) {
2104 s3c_hsotg_epint(hsotg, ep, 1);
2107 writel(daint, hsotg->regs + S3C_DAINT);
2108 writel(gintsts & (S3C_GINTSTS_OEPInt | S3C_GINTSTS_IEPInt),
2109 hsotg->regs + S3C_GINTSTS);
2112 if (gintsts & S3C_GINTSTS_USBRst) {
2113 dev_info(hsotg->dev, "%s: USBRst\n", __func__);
2114 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
2115 readl(hsotg->regs + S3C_GNPTXSTS));
2117 kill_all_requests(hsotg, &hsotg->eps[0], -ECONNRESET, true);
2119 /* it seems after a reset we can end up with a situation
2120 * where the TXFIFO still has data in it... the docs
2121 * suggest resetting all the fifos, so use the init_fifo
2122 * code to relayout and flush the fifos.
2125 s3c_hsotg_init_fifo(hsotg);
2127 s3c_hsotg_enqueue_setup(hsotg);
2129 writel(S3C_GINTSTS_USBRst, hsotg->regs + S3C_GINTSTS);
2132 /* check both FIFOs */
2134 if (gintsts & S3C_GINTSTS_NPTxFEmp) {
2135 dev_dbg(hsotg->dev, "NPTxFEmp\n");
2137 /* Disable the interrupt to stop it happening again
2138 * unless one of these endpoint routines decides that
2139 * it needs re-enabling */
2141 s3c_hsotg_disable_gsint(hsotg, S3C_GINTSTS_NPTxFEmp);
2142 s3c_hsotg_irq_fifoempty(hsotg, false);
2144 writel(S3C_GINTSTS_NPTxFEmp, hsotg->regs + S3C_GINTSTS);
2147 if (gintsts & S3C_GINTSTS_PTxFEmp) {
2148 dev_dbg(hsotg->dev, "PTxFEmp\n");
2150 /* See note in S3C_GINTSTS_NPTxFEmp */
2152 s3c_hsotg_disable_gsint(hsotg, S3C_GINTSTS_PTxFEmp);
2153 s3c_hsotg_irq_fifoempty(hsotg, true);
2155 writel(S3C_GINTSTS_PTxFEmp, hsotg->regs + S3C_GINTSTS);
2158 if (gintsts & S3C_GINTSTS_RxFLvl) {
2159 /* note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
2160 * we need to retry s3c_hsotg_handle_rx if this is still
2163 s3c_hsotg_handle_rx(hsotg);
2164 writel(S3C_GINTSTS_RxFLvl, hsotg->regs + S3C_GINTSTS);
2167 if (gintsts & S3C_GINTSTS_ModeMis) {
2168 dev_warn(hsotg->dev, "warning, mode mismatch triggered\n");
2169 writel(S3C_GINTSTS_ModeMis, hsotg->regs + S3C_GINTSTS);
2172 if (gintsts & S3C_GINTSTS_USBSusp) {
2173 dev_info(hsotg->dev, "S3C_GINTSTS_USBSusp\n");
2174 writel(S3C_GINTSTS_USBSusp, hsotg->regs + S3C_GINTSTS);
2176 call_gadget(hsotg, suspend);
2179 if (gintsts & S3C_GINTSTS_WkUpInt) {
2180 dev_info(hsotg->dev, "S3C_GINTSTS_WkUpIn\n");
2181 writel(S3C_GINTSTS_WkUpInt, hsotg->regs + S3C_GINTSTS);
2183 call_gadget(hsotg, resume);
2186 if (gintsts & S3C_GINTSTS_ErlySusp) {
2187 dev_dbg(hsotg->dev, "S3C_GINTSTS_ErlySusp\n");
2188 writel(S3C_GINTSTS_ErlySusp, hsotg->regs + S3C_GINTSTS);
2191 /* these next two seem to crop-up occasionally causing the core
2192 * to shutdown the USB transfer, so try clearing them and logging
2195 if (gintsts & S3C_GINTSTS_GOUTNakEff) {
2196 dev_info(hsotg->dev, "GOUTNakEff triggered\n");
2198 s3c_hsotg_dump(hsotg);
2200 writel(S3C_DCTL_CGOUTNak, hsotg->regs + S3C_DCTL);
2201 writel(S3C_GINTSTS_GOUTNakEff, hsotg->regs + S3C_GINTSTS);
2204 if (gintsts & S3C_GINTSTS_GINNakEff) {
2205 dev_info(hsotg->dev, "GINNakEff triggered\n");
2207 s3c_hsotg_dump(hsotg);
2209 writel(S3C_DCTL_CGNPInNAK, hsotg->regs + S3C_DCTL);
2210 writel(S3C_GINTSTS_GINNakEff, hsotg->regs + S3C_GINTSTS);
2213 /* if we've had fifo events, we should try and go around the
2214 * loop again to see if there's any point in returning yet. */
2216 if (gintsts & IRQ_RETRY_MASK && --retry_count > 0)
2223 * s3c_hsotg_ep_enable - enable the given endpoint
2224 * @ep: The USB endpint to configure
2225 * @desc: The USB endpoint descriptor to configure with.
2227 * This is called from the USB gadget code's usb_ep_enable().
2229 static int s3c_hsotg_ep_enable(struct usb_ep *ep,
2230 const struct usb_endpoint_descriptor *desc)
2232 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2233 struct s3c_hsotg *hsotg = hs_ep->parent;
2234 unsigned long flags;
2235 int index = hs_ep->index;
2243 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
2244 __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes,
2245 desc->wMaxPacketSize, desc->bInterval);
2247 /* not to be called for EP0 */
2248 WARN_ON(index == 0);
2250 dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
2251 if (dir_in != hs_ep->dir_in) {
2252 dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__);
2256 mps = le16_to_cpu(desc->wMaxPacketSize);
2258 /* note, we handle this here instead of s3c_hsotg_set_ep_maxpacket */
2260 epctrl_reg = dir_in ? S3C_DIEPCTL(index) : S3C_DOEPCTL(index);
2261 epctrl = readl(hsotg->regs + epctrl_reg);
2263 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
2264 __func__, epctrl, epctrl_reg);
2266 spin_lock_irqsave(&hs_ep->lock, flags);
2268 epctrl &= ~(S3C_DxEPCTL_EPType_MASK | S3C_DxEPCTL_MPS_MASK);
2269 epctrl |= S3C_DxEPCTL_MPS(mps);
2271 /* mark the endpoint as active, otherwise the core may ignore
2272 * transactions entirely for this endpoint */
2273 epctrl |= S3C_DxEPCTL_USBActEp;
2275 /* set the NAK status on the endpoint, otherwise we might try and
2276 * do something with data that we've yet got a request to process
2277 * since the RXFIFO will take data for an endpoint even if the
2278 * size register hasn't been set.
2281 epctrl |= S3C_DxEPCTL_SNAK;
2283 /* update the endpoint state */
2284 hs_ep->ep.maxpacket = mps;
2286 /* default, set to non-periodic */
2287 hs_ep->periodic = 0;
2289 switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
2290 case USB_ENDPOINT_XFER_ISOC:
2291 dev_err(hsotg->dev, "no current ISOC support\n");
2295 case USB_ENDPOINT_XFER_BULK:
2296 epctrl |= S3C_DxEPCTL_EPType_Bulk;
2299 case USB_ENDPOINT_XFER_INT:
2301 /* Allocate our TxFNum by simply using the index
2302 * of the endpoint for the moment. We could do
2303 * something better if the host indicates how
2304 * many FIFOs we are expecting to use. */
2306 hs_ep->periodic = 1;
2307 epctrl |= S3C_DxEPCTL_TxFNum(index);
2310 epctrl |= S3C_DxEPCTL_EPType_Intterupt;
2313 case USB_ENDPOINT_XFER_CONTROL:
2314 epctrl |= S3C_DxEPCTL_EPType_Control;
2318 /* if the hardware has dedicated fifos, we must give each IN EP
2319 * a unique tx-fifo even if it is non-periodic.
2321 if (dir_in && hsotg->dedicated_fifos)
2322 epctrl |= S3C_DxEPCTL_TxFNum(index);
2324 /* for non control endpoints, set PID to D0 */
2326 epctrl |= S3C_DxEPCTL_SetD0PID;
2328 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
2331 writel(epctrl, hsotg->regs + epctrl_reg);
2332 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
2333 __func__, readl(hsotg->regs + epctrl_reg));
2335 /* enable the endpoint interrupt */
2336 s3c_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
2339 spin_unlock_irqrestore(&hs_ep->lock, flags);
2343 static int s3c_hsotg_ep_disable(struct usb_ep *ep)
2345 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2346 struct s3c_hsotg *hsotg = hs_ep->parent;
2347 int dir_in = hs_ep->dir_in;
2348 int index = hs_ep->index;
2349 unsigned long flags;
2353 dev_info(hsotg->dev, "%s(ep %p)\n", __func__, ep);
2355 if (ep == &hsotg->eps[0].ep) {
2356 dev_err(hsotg->dev, "%s: called for ep0\n", __func__);
2360 epctrl_reg = dir_in ? S3C_DIEPCTL(index) : S3C_DOEPCTL(index);
2362 /* terminate all requests with shutdown */
2363 kill_all_requests(hsotg, hs_ep, -ESHUTDOWN, false);
2365 spin_lock_irqsave(&hs_ep->lock, flags);
2367 ctrl = readl(hsotg->regs + epctrl_reg);
2368 ctrl &= ~S3C_DxEPCTL_EPEna;
2369 ctrl &= ~S3C_DxEPCTL_USBActEp;
2370 ctrl |= S3C_DxEPCTL_SNAK;
2372 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
2373 writel(ctrl, hsotg->regs + epctrl_reg);
2375 /* disable endpoint interrupts */
2376 s3c_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
2378 spin_unlock_irqrestore(&hs_ep->lock, flags);
2383 * on_list - check request is on the given endpoint
2384 * @ep: The endpoint to check.
2385 * @test: The request to test if it is on the endpoint.
2387 static bool on_list(struct s3c_hsotg_ep *ep, struct s3c_hsotg_req *test)
2389 struct s3c_hsotg_req *req, *treq;
2391 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
2399 static int s3c_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
2401 struct s3c_hsotg_req *hs_req = our_req(req);
2402 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2403 struct s3c_hsotg *hs = hs_ep->parent;
2404 unsigned long flags;
2406 dev_info(hs->dev, "ep_dequeue(%p,%p)\n", ep, req);
2408 if (hs_req == hs_ep->req) {
2409 dev_dbg(hs->dev, "%s: already in progress\n", __func__);
2410 return -EINPROGRESS;
2413 spin_lock_irqsave(&hs_ep->lock, flags);
2415 if (!on_list(hs_ep, hs_req)) {
2416 spin_unlock_irqrestore(&hs_ep->lock, flags);
2420 s3c_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET);
2421 spin_unlock_irqrestore(&hs_ep->lock, flags);
2426 static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value)
2428 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2429 struct s3c_hsotg *hs = hs_ep->parent;
2430 int index = hs_ep->index;
2431 unsigned long irqflags;
2435 dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value);
2437 spin_lock_irqsave(&hs_ep->lock, irqflags);
2439 /* write both IN and OUT control registers */
2441 epreg = S3C_DIEPCTL(index);
2442 epctl = readl(hs->regs + epreg);
2445 epctl |= S3C_DxEPCTL_Stall;
2447 epctl &= ~S3C_DxEPCTL_Stall;
2449 writel(epctl, hs->regs + epreg);
2451 epreg = S3C_DOEPCTL(index);
2452 epctl = readl(hs->regs + epreg);
2455 epctl |= S3C_DxEPCTL_Stall;
2457 epctl &= ~S3C_DxEPCTL_Stall;
2459 writel(epctl, hs->regs + epreg);
2461 spin_unlock_irqrestore(&hs_ep->lock, irqflags);
2466 static struct usb_ep_ops s3c_hsotg_ep_ops = {
2467 .enable = s3c_hsotg_ep_enable,
2468 .disable = s3c_hsotg_ep_disable,
2469 .alloc_request = s3c_hsotg_ep_alloc_request,
2470 .free_request = s3c_hsotg_ep_free_request,
2471 .queue = s3c_hsotg_ep_queue,
2472 .dequeue = s3c_hsotg_ep_dequeue,
2473 .set_halt = s3c_hsotg_ep_sethalt,
2474 /* note, don't belive we have any call for the fifo routines */
2478 * s3c_hsotg_corereset - issue softreset to the core
2479 * @hsotg: The device state
2481 * Issue a soft reset to the core, and await the core finishing it.
2483 static int s3c_hsotg_corereset(struct s3c_hsotg *hsotg)
2488 dev_dbg(hsotg->dev, "resetting core\n");
2490 /* issue soft reset */
2491 writel(S3C_GRSTCTL_CSftRst, hsotg->regs + S3C_GRSTCTL);
2495 grstctl = readl(hsotg->regs + S3C_GRSTCTL);
2496 } while (!(grstctl & S3C_GRSTCTL_CSftRst) && timeout-- > 0);
2498 if (!(grstctl & S3C_GRSTCTL_CSftRst)) {
2499 dev_err(hsotg->dev, "Failed to get CSftRst asserted\n");
2506 u32 grstctl = readl(hsotg->regs + S3C_GRSTCTL);
2508 if (timeout-- < 0) {
2509 dev_info(hsotg->dev,
2510 "%s: reset failed, GRSTCTL=%08x\n",
2515 if (grstctl & S3C_GRSTCTL_CSftRst)
2518 if (!(grstctl & S3C_GRSTCTL_AHBIdle))
2521 break; /* reset done */
2524 dev_dbg(hsotg->dev, "reset successful\n");
2528 int usb_gadget_register_driver(struct usb_gadget_driver *driver)
2530 struct s3c_hsotg *hsotg = our_hsotg;
2534 printk(KERN_ERR "%s: called with no device\n", __func__);
2539 dev_err(hsotg->dev, "%s: no driver\n", __func__);
2543 if (driver->speed != USB_SPEED_HIGH &&
2544 driver->speed != USB_SPEED_FULL) {
2545 dev_err(hsotg->dev, "%s: bad speed\n", __func__);
2548 if (!driver->bind || !driver->setup) {
2549 dev_err(hsotg->dev, "%s: missing entry points\n", __func__);
2553 WARN_ON(hsotg->driver);
2555 driver->driver.bus = NULL;
2556 hsotg->driver = driver;
2557 hsotg->gadget.dev.driver = &driver->driver;
2558 hsotg->gadget.dev.dma_mask = hsotg->dev->dma_mask;
2559 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
2561 ret = device_add(&hsotg->gadget.dev);
2563 dev_err(hsotg->dev, "failed to register gadget device\n");
2567 ret = driver->bind(&hsotg->gadget);
2569 dev_err(hsotg->dev, "failed bind %s\n", driver->driver.name);
2571 hsotg->gadget.dev.driver = NULL;
2572 hsotg->driver = NULL;
2576 /* we must now enable ep0 ready for host detection and then
2577 * set configuration. */
2579 s3c_hsotg_corereset(hsotg);
2581 /* set the PLL on, remove the HNP/SRP and set the PHY */
2582 writel(S3C_GUSBCFG_PHYIf16 | S3C_GUSBCFG_TOutCal(7) |
2583 (0x5 << 10), hsotg->regs + S3C_GUSBCFG);
2585 /* looks like soft-reset changes state of FIFOs */
2586 s3c_hsotg_init_fifo(hsotg);
2588 __orr32(hsotg->regs + S3C_DCTL, S3C_DCTL_SftDiscon);
2590 writel(1 << 18 | S3C_DCFG_DevSpd_HS, hsotg->regs + S3C_DCFG);
2592 writel(S3C_GINTSTS_DisconnInt | S3C_GINTSTS_SessReqInt |
2593 S3C_GINTSTS_ConIDStsChng | S3C_GINTSTS_USBRst |
2594 S3C_GINTSTS_EnumDone | S3C_GINTSTS_OTGInt |
2595 S3C_GINTSTS_USBSusp | S3C_GINTSTS_WkUpInt |
2596 S3C_GINTSTS_GOUTNakEff | S3C_GINTSTS_GINNakEff |
2597 S3C_GINTSTS_ErlySusp,
2598 hsotg->regs + S3C_GINTMSK);
2600 if (using_dma(hsotg))
2601 writel(S3C_GAHBCFG_GlblIntrEn | S3C_GAHBCFG_DMAEn |
2602 S3C_GAHBCFG_HBstLen_Incr4,
2603 hsotg->regs + S3C_GAHBCFG);
2605 writel(S3C_GAHBCFG_GlblIntrEn, hsotg->regs + S3C_GAHBCFG);
2607 /* Enabling INTknTXFEmpMsk here seems to be a big mistake, we end
2608 * up being flooded with interrupts if the host is polling the
2609 * endpoint to try and read data. */
2611 writel(S3C_DIEPMSK_TimeOUTMsk | S3C_DIEPMSK_AHBErrMsk |
2612 S3C_DIEPMSK_INTknEPMisMsk |
2613 S3C_DIEPMSK_EPDisbldMsk | S3C_DIEPMSK_XferComplMsk |
2614 ((hsotg->dedicated_fifos) ? S3C_DIEPMSK_TxFIFOEmpty : 0),
2615 hsotg->regs + S3C_DIEPMSK);
2617 /* don't need XferCompl, we get that from RXFIFO in slave mode. In
2618 * DMA mode we may need this. */
2619 writel(S3C_DOEPMSK_SetupMsk | S3C_DOEPMSK_AHBErrMsk |
2620 S3C_DOEPMSK_EPDisbldMsk |
2621 (using_dma(hsotg) ? (S3C_DIEPMSK_XferComplMsk |
2622 S3C_DIEPMSK_TimeOUTMsk) : 0),
2623 hsotg->regs + S3C_DOEPMSK);
2625 writel(0, hsotg->regs + S3C_DAINTMSK);
2627 dev_info(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2628 readl(hsotg->regs + S3C_DIEPCTL0),
2629 readl(hsotg->regs + S3C_DOEPCTL0));
2631 /* enable in and out endpoint interrupts */
2632 s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_OEPInt | S3C_GINTSTS_IEPInt);
2634 /* Enable the RXFIFO when in slave mode, as this is how we collect
2635 * the data. In DMA mode, we get events from the FIFO but also
2636 * things we cannot process, so do not use it. */
2637 if (!using_dma(hsotg))
2638 s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_RxFLvl);
2640 /* Enable interrupts for EP0 in and out */
2641 s3c_hsotg_ctrl_epint(hsotg, 0, 0, 1);
2642 s3c_hsotg_ctrl_epint(hsotg, 0, 1, 1);
2644 __orr32(hsotg->regs + S3C_DCTL, S3C_DCTL_PWROnPrgDone);
2645 udelay(10); /* see openiboot */
2646 __bic32(hsotg->regs + S3C_DCTL, S3C_DCTL_PWROnPrgDone);
2648 dev_info(hsotg->dev, "DCTL=0x%08x\n", readl(hsotg->regs + S3C_DCTL));
2650 /* S3C_DxEPCTL_USBActEp says RO in manual, but seems to be set by
2651 writing to the EPCTL register.. */
2653 /* set to read 1 8byte packet */
2654 writel(S3C_DxEPTSIZ_MC(1) | S3C_DxEPTSIZ_PktCnt(1) |
2655 S3C_DxEPTSIZ_XferSize(8), hsotg->regs + DOEPTSIZ0);
2657 writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) |
2658 S3C_DxEPCTL_CNAK | S3C_DxEPCTL_EPEna |
2659 S3C_DxEPCTL_USBActEp,
2660 hsotg->regs + S3C_DOEPCTL0);
2662 /* enable, but don't activate EP0in */
2663 writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) |
2664 S3C_DxEPCTL_USBActEp, hsotg->regs + S3C_DIEPCTL0);
2666 s3c_hsotg_enqueue_setup(hsotg);
2668 dev_info(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2669 readl(hsotg->regs + S3C_DIEPCTL0),
2670 readl(hsotg->regs + S3C_DOEPCTL0));
2672 /* clear global NAKs */
2673 writel(S3C_DCTL_CGOUTNak | S3C_DCTL_CGNPInNAK,
2674 hsotg->regs + S3C_DCTL);
2676 /* must be at-least 3ms to allow bus to see disconnect */
2679 /* remove the soft-disconnect and let's go */
2680 __bic32(hsotg->regs + S3C_DCTL, S3C_DCTL_SftDiscon);
2682 /* report to the user, and return */
2684 dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
2688 hsotg->driver = NULL;
2689 hsotg->gadget.dev.driver = NULL;
2692 EXPORT_SYMBOL(usb_gadget_register_driver);
2694 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
2696 struct s3c_hsotg *hsotg = our_hsotg;
2702 if (!driver || driver != hsotg->driver || !driver->unbind)
2705 /* all endpoints should be shutdown */
2706 for (ep = 0; ep < S3C_HSOTG_EPS; ep++)
2707 s3c_hsotg_ep_disable(&hsotg->eps[ep].ep);
2709 call_gadget(hsotg, disconnect);
2711 driver->unbind(&hsotg->gadget);
2712 hsotg->driver = NULL;
2713 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
2715 device_del(&hsotg->gadget.dev);
2717 dev_info(hsotg->dev, "unregistered gadget driver '%s'\n",
2718 driver->driver.name);
2722 EXPORT_SYMBOL(usb_gadget_unregister_driver);
2724 static int s3c_hsotg_gadget_getframe(struct usb_gadget *gadget)
2726 return s3c_hsotg_read_frameno(to_hsotg(gadget));
2729 static struct usb_gadget_ops s3c_hsotg_gadget_ops = {
2730 .get_frame = s3c_hsotg_gadget_getframe,
2734 * s3c_hsotg_initep - initialise a single endpoint
2735 * @hsotg: The device state.
2736 * @hs_ep: The endpoint to be initialised.
2737 * @epnum: The endpoint number
2739 * Initialise the given endpoint (as part of the probe and device state
2740 * creation) to give to the gadget driver. Setup the endpoint name, any
2741 * direction information and other state that may be required.
2743 static void __devinit s3c_hsotg_initep(struct s3c_hsotg *hsotg,
2744 struct s3c_hsotg_ep *hs_ep,
2752 else if ((epnum % 2) == 0) {
2759 hs_ep->index = epnum;
2761 snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir);
2763 INIT_LIST_HEAD(&hs_ep->queue);
2764 INIT_LIST_HEAD(&hs_ep->ep.ep_list);
2766 spin_lock_init(&hs_ep->lock);
2768 /* add to the list of endpoints known by the gadget driver */
2770 list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list);
2772 hs_ep->parent = hsotg;
2773 hs_ep->ep.name = hs_ep->name;
2774 hs_ep->ep.maxpacket = epnum ? 512 : EP0_MPS_LIMIT;
2775 hs_ep->ep.ops = &s3c_hsotg_ep_ops;
2777 /* Read the FIFO size for the Periodic TX FIFO, even if we're
2778 * an OUT endpoint, we may as well do this if in future the
2779 * code is changed to make each endpoint's direction changeable.
2782 ptxfifo = readl(hsotg->regs + S3C_DPTXFSIZn(epnum));
2783 hs_ep->fifo_size = S3C_DPTXFSIZn_DPTxFSize_GET(ptxfifo) * 4;
2785 /* if we're using dma, we need to set the next-endpoint pointer
2786 * to be something valid.
2789 if (using_dma(hsotg)) {
2790 u32 next = S3C_DxEPCTL_NextEp((epnum + 1) % 15);
2791 writel(next, hsotg->regs + S3C_DIEPCTL(epnum));
2792 writel(next, hsotg->regs + S3C_DOEPCTL(epnum));
2797 * s3c_hsotg_otgreset - reset the OtG phy block
2798 * @hsotg: The host state.
2800 * Power up the phy, set the basic configuration and start the PHY.
2802 static void s3c_hsotg_otgreset(struct s3c_hsotg *hsotg)
2804 struct clk *xusbxti;
2807 pwr = readl(S3C_PHYPWR);
2809 writel(pwr, S3C_PHYPWR);
2812 osc = hsotg->plat->is_osc ? S3C_PHYCLK_EXT_OSC : 0;
2814 xusbxti = clk_get(hsotg->dev, "xusbxti");
2815 if (xusbxti && !IS_ERR(xusbxti)) {
2816 switch (clk_get_rate(xusbxti)) {
2818 osc |= S3C_PHYCLK_CLKSEL_12M;
2821 osc |= S3C_PHYCLK_CLKSEL_24M;
2825 /* default reference clock */
2831 writel(osc | 0x10, S3C_PHYCLK);
2833 /* issue a full set of resets to the otg and core */
2835 writel(S3C_RSTCON_PHY, S3C_RSTCON);
2836 udelay(20); /* at-least 10uS */
2837 writel(0, S3C_RSTCON);
2841 static void s3c_hsotg_init(struct s3c_hsotg *hsotg)
2845 /* unmask subset of endpoint interrupts */
2847 writel(S3C_DIEPMSK_TimeOUTMsk | S3C_DIEPMSK_AHBErrMsk |
2848 S3C_DIEPMSK_EPDisbldMsk | S3C_DIEPMSK_XferComplMsk,
2849 hsotg->regs + S3C_DIEPMSK);
2851 writel(S3C_DOEPMSK_SetupMsk | S3C_DOEPMSK_AHBErrMsk |
2852 S3C_DOEPMSK_EPDisbldMsk | S3C_DOEPMSK_XferComplMsk,
2853 hsotg->regs + S3C_DOEPMSK);
2855 writel(0, hsotg->regs + S3C_DAINTMSK);
2857 /* Be in disconnected state until gadget is registered */
2858 __orr32(hsotg->regs + S3C_DCTL, S3C_DCTL_SftDiscon);
2861 /* post global nak until we're ready */
2862 writel(S3C_DCTL_SGNPInNAK | S3C_DCTL_SGOUTNak,
2863 hsotg->regs + S3C_DCTL);
2868 dev_info(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
2869 readl(hsotg->regs + S3C_GRXFSIZ),
2870 readl(hsotg->regs + S3C_GNPTXFSIZ));
2872 s3c_hsotg_init_fifo(hsotg);
2874 /* set the PLL on, remove the HNP/SRP and set the PHY */
2875 writel(S3C_GUSBCFG_PHYIf16 | S3C_GUSBCFG_TOutCal(7) | (0x5 << 10),
2876 hsotg->regs + S3C_GUSBCFG);
2878 writel(using_dma(hsotg) ? S3C_GAHBCFG_DMAEn : 0x0,
2879 hsotg->regs + S3C_GAHBCFG);
2881 /* check hardware configuration */
2883 cfg4 = readl(hsotg->regs + 0x50);
2884 hsotg->dedicated_fifos = (cfg4 >> 25) & 1;
2886 dev_info(hsotg->dev, "%s fifos\n",
2887 hsotg->dedicated_fifos ? "dedicated" : "shared");
2890 static void s3c_hsotg_dump(struct s3c_hsotg *hsotg)
2892 struct device *dev = hsotg->dev;
2893 void __iomem *regs = hsotg->regs;
2897 dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
2898 readl(regs + S3C_DCFG), readl(regs + S3C_DCTL),
2899 readl(regs + S3C_DIEPMSK));
2901 dev_info(dev, "GAHBCFG=0x%08x, 0x44=0x%08x\n",
2902 readl(regs + S3C_GAHBCFG), readl(regs + 0x44));
2904 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
2905 readl(regs + S3C_GRXFSIZ), readl(regs + S3C_GNPTXFSIZ));
2907 /* show periodic fifo settings */
2909 for (idx = 1; idx <= 15; idx++) {
2910 val = readl(regs + S3C_DPTXFSIZn(idx));
2911 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
2912 val >> S3C_DPTXFSIZn_DPTxFSize_SHIFT,
2913 val & S3C_DPTXFSIZn_DPTxFStAddr_MASK);
2916 for (idx = 0; idx < 15; idx++) {
2918 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
2919 readl(regs + S3C_DIEPCTL(idx)),
2920 readl(regs + S3C_DIEPTSIZ(idx)),
2921 readl(regs + S3C_DIEPDMA(idx)));
2923 val = readl(regs + S3C_DOEPCTL(idx));
2925 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
2926 idx, readl(regs + S3C_DOEPCTL(idx)),
2927 readl(regs + S3C_DOEPTSIZ(idx)),
2928 readl(regs + S3C_DOEPDMA(idx)));
2932 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
2933 readl(regs + S3C_DVBUSDIS), readl(regs + S3C_DVBUSPULSE));
2938 * state_show - debugfs: show overall driver and device state.
2939 * @seq: The seq file to write to.
2940 * @v: Unused parameter.
2942 * This debugfs entry shows the overall state of the hardware and
2943 * some general information about each of the endpoints available
2946 static int state_show(struct seq_file *seq, void *v)
2948 struct s3c_hsotg *hsotg = seq->private;
2949 void __iomem *regs = hsotg->regs;
2952 seq_printf(seq, "DCFG=0x%08x, DCTL=0x%08x, DSTS=0x%08x\n",
2953 readl(regs + S3C_DCFG),
2954 readl(regs + S3C_DCTL),
2955 readl(regs + S3C_DSTS));
2957 seq_printf(seq, "DIEPMSK=0x%08x, DOEPMASK=0x%08x\n",
2958 readl(regs + S3C_DIEPMSK), readl(regs + S3C_DOEPMSK));
2960 seq_printf(seq, "GINTMSK=0x%08x, GINTSTS=0x%08x\n",
2961 readl(regs + S3C_GINTMSK),
2962 readl(regs + S3C_GINTSTS));
2964 seq_printf(seq, "DAINTMSK=0x%08x, DAINT=0x%08x\n",
2965 readl(regs + S3C_DAINTMSK),
2966 readl(regs + S3C_DAINT));
2968 seq_printf(seq, "GNPTXSTS=0x%08x, GRXSTSR=%08x\n",
2969 readl(regs + S3C_GNPTXSTS),
2970 readl(regs + S3C_GRXSTSR));
2972 seq_printf(seq, "\nEndpoint status:\n");
2974 for (idx = 0; idx < 15; idx++) {
2977 in = readl(regs + S3C_DIEPCTL(idx));
2978 out = readl(regs + S3C_DOEPCTL(idx));
2980 seq_printf(seq, "ep%d: DIEPCTL=0x%08x, DOEPCTL=0x%08x",
2983 in = readl(regs + S3C_DIEPTSIZ(idx));
2984 out = readl(regs + S3C_DOEPTSIZ(idx));
2986 seq_printf(seq, ", DIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x",
2989 seq_printf(seq, "\n");
2995 static int state_open(struct inode *inode, struct file *file)
2997 return single_open(file, state_show, inode->i_private);
3000 static const struct file_operations state_fops = {
3001 .owner = THIS_MODULE,
3004 .llseek = seq_lseek,
3005 .release = single_release,
3009 * fifo_show - debugfs: show the fifo information
3010 * @seq: The seq_file to write data to.
3011 * @v: Unused parameter.
3013 * Show the FIFO information for the overall fifo and all the
3014 * periodic transmission FIFOs.
3016 static int fifo_show(struct seq_file *seq, void *v)
3018 struct s3c_hsotg *hsotg = seq->private;
3019 void __iomem *regs = hsotg->regs;
3023 seq_printf(seq, "Non-periodic FIFOs:\n");
3024 seq_printf(seq, "RXFIFO: Size %d\n", readl(regs + S3C_GRXFSIZ));
3026 val = readl(regs + S3C_GNPTXFSIZ);
3027 seq_printf(seq, "NPTXFIFO: Size %d, Start 0x%08x\n",
3028 val >> S3C_GNPTXFSIZ_NPTxFDep_SHIFT,
3029 val & S3C_GNPTXFSIZ_NPTxFStAddr_MASK);
3031 seq_printf(seq, "\nPeriodic TXFIFOs:\n");
3033 for (idx = 1; idx <= 15; idx++) {
3034 val = readl(regs + S3C_DPTXFSIZn(idx));
3036 seq_printf(seq, "\tDPTXFIFO%2d: Size %d, Start 0x%08x\n", idx,
3037 val >> S3C_DPTXFSIZn_DPTxFSize_SHIFT,
3038 val & S3C_DPTXFSIZn_DPTxFStAddr_MASK);
3044 static int fifo_open(struct inode *inode, struct file *file)
3046 return single_open(file, fifo_show, inode->i_private);
3049 static const struct file_operations fifo_fops = {
3050 .owner = THIS_MODULE,
3053 .llseek = seq_lseek,
3054 .release = single_release,
3058 static const char *decode_direction(int is_in)
3060 return is_in ? "in" : "out";
3064 * ep_show - debugfs: show the state of an endpoint.
3065 * @seq: The seq_file to write data to.
3066 * @v: Unused parameter.
3068 * This debugfs entry shows the state of the given endpoint (one is
3069 * registered for each available).
3071 static int ep_show(struct seq_file *seq, void *v)
3073 struct s3c_hsotg_ep *ep = seq->private;
3074 struct s3c_hsotg *hsotg = ep->parent;
3075 struct s3c_hsotg_req *req;
3076 void __iomem *regs = hsotg->regs;
3077 int index = ep->index;
3078 int show_limit = 15;
3079 unsigned long flags;
3081 seq_printf(seq, "Endpoint index %d, named %s, dir %s:\n",
3082 ep->index, ep->ep.name, decode_direction(ep->dir_in));
3084 /* first show the register state */
3086 seq_printf(seq, "\tDIEPCTL=0x%08x, DOEPCTL=0x%08x\n",
3087 readl(regs + S3C_DIEPCTL(index)),
3088 readl(regs + S3C_DOEPCTL(index)));
3090 seq_printf(seq, "\tDIEPDMA=0x%08x, DOEPDMA=0x%08x\n",
3091 readl(regs + S3C_DIEPDMA(index)),
3092 readl(regs + S3C_DOEPDMA(index)));
3094 seq_printf(seq, "\tDIEPINT=0x%08x, DOEPINT=0x%08x\n",
3095 readl(regs + S3C_DIEPINT(index)),
3096 readl(regs + S3C_DOEPINT(index)));
3098 seq_printf(seq, "\tDIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x\n",
3099 readl(regs + S3C_DIEPTSIZ(index)),
3100 readl(regs + S3C_DOEPTSIZ(index)));
3102 seq_printf(seq, "\n");
3103 seq_printf(seq, "mps %d\n", ep->ep.maxpacket);
3104 seq_printf(seq, "total_data=%ld\n", ep->total_data);
3106 seq_printf(seq, "request list (%p,%p):\n",
3107 ep->queue.next, ep->queue.prev);
3109 spin_lock_irqsave(&ep->lock, flags);
3111 list_for_each_entry(req, &ep->queue, queue) {
3112 if (--show_limit < 0) {
3113 seq_printf(seq, "not showing more requests...\n");
3117 seq_printf(seq, "%c req %p: %d bytes @%p, ",
3118 req == ep->req ? '*' : ' ',
3119 req, req->req.length, req->req.buf);
3120 seq_printf(seq, "%d done, res %d\n",
3121 req->req.actual, req->req.status);
3124 spin_unlock_irqrestore(&ep->lock, flags);
3129 static int ep_open(struct inode *inode, struct file *file)
3131 return single_open(file, ep_show, inode->i_private);
3134 static const struct file_operations ep_fops = {
3135 .owner = THIS_MODULE,
3138 .llseek = seq_lseek,
3139 .release = single_release,
3143 * s3c_hsotg_create_debug - create debugfs directory and files
3144 * @hsotg: The driver state
3146 * Create the debugfs files to allow the user to get information
3147 * about the state of the system. The directory name is created
3148 * with the same name as the device itself, in case we end up
3149 * with multiple blocks in future systems.
3151 static void __devinit s3c_hsotg_create_debug(struct s3c_hsotg *hsotg)
3153 struct dentry *root;
3156 root = debugfs_create_dir(dev_name(hsotg->dev), NULL);
3157 hsotg->debug_root = root;
3159 dev_err(hsotg->dev, "cannot create debug root\n");
3163 /* create general state file */
3165 hsotg->debug_file = debugfs_create_file("state", 0444, root,
3166 hsotg, &state_fops);
3168 if (IS_ERR(hsotg->debug_file))
3169 dev_err(hsotg->dev, "%s: failed to create state\n", __func__);
3171 hsotg->debug_fifo = debugfs_create_file("fifo", 0444, root,
3174 if (IS_ERR(hsotg->debug_fifo))
3175 dev_err(hsotg->dev, "%s: failed to create fifo\n", __func__);
3177 /* create one file for each endpoint */
3179 for (epidx = 0; epidx < S3C_HSOTG_EPS; epidx++) {
3180 struct s3c_hsotg_ep *ep = &hsotg->eps[epidx];
3182 ep->debugfs = debugfs_create_file(ep->name, 0444,
3183 root, ep, &ep_fops);
3185 if (IS_ERR(ep->debugfs))
3186 dev_err(hsotg->dev, "failed to create %s debug file\n",
3192 * s3c_hsotg_delete_debug - cleanup debugfs entries
3193 * @hsotg: The driver state
3195 * Cleanup (remove) the debugfs files for use on module exit.
3197 static void __devexit s3c_hsotg_delete_debug(struct s3c_hsotg *hsotg)
3201 for (epidx = 0; epidx < S3C_HSOTG_EPS; epidx++) {
3202 struct s3c_hsotg_ep *ep = &hsotg->eps[epidx];
3203 debugfs_remove(ep->debugfs);
3206 debugfs_remove(hsotg->debug_file);
3207 debugfs_remove(hsotg->debug_fifo);
3208 debugfs_remove(hsotg->debug_root);
3212 * s3c_hsotg_gate - set the hardware gate for the block
3213 * @pdev: The device we bound to
3216 * Set the hardware gate setting into the block. If we end up on
3217 * something other than an S3C64XX, then we might need to change this
3218 * to using a platform data callback, or some other mechanism.
3220 static void s3c_hsotg_gate(struct platform_device *pdev, bool on)
3222 unsigned long flags;
3225 local_irq_save(flags);
3227 others = __raw_readl(S3C64XX_OTHERS);
3229 others |= S3C64XX_OTHERS_USBMASK;
3231 others &= ~S3C64XX_OTHERS_USBMASK;
3232 __raw_writel(others, S3C64XX_OTHERS);
3234 local_irq_restore(flags);
3237 static struct s3c_hsotg_plat s3c_hsotg_default_pdata;
3239 static int __devinit s3c_hsotg_probe(struct platform_device *pdev)
3241 struct s3c_hsotg_plat *plat = pdev->dev.platform_data;
3242 struct device *dev = &pdev->dev;
3243 struct s3c_hsotg *hsotg;
3244 struct resource *res;
3249 plat = &s3c_hsotg_default_pdata;
3251 hsotg = kzalloc(sizeof(struct s3c_hsotg) +
3252 sizeof(struct s3c_hsotg_ep) * S3C_HSOTG_EPS,
3255 dev_err(dev, "cannot get memory\n");
3262 hsotg->clk = clk_get(&pdev->dev, "otg");
3263 if (IS_ERR(hsotg->clk)) {
3264 dev_err(dev, "cannot get otg clock\n");
3269 platform_set_drvdata(pdev, hsotg);
3271 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3273 dev_err(dev, "cannot find register resource 0\n");
3278 hsotg->regs_res = request_mem_region(res->start, resource_size(res),
3280 if (!hsotg->regs_res) {
3281 dev_err(dev, "cannot reserve registers\n");
3286 hsotg->regs = ioremap(res->start, resource_size(res));
3288 dev_err(dev, "cannot map registers\n");
3293 ret = platform_get_irq(pdev, 0);
3295 dev_err(dev, "cannot find IRQ\n");
3301 ret = request_irq(ret, s3c_hsotg_irq, 0, dev_name(dev), hsotg);
3303 dev_err(dev, "cannot claim IRQ\n");
3307 dev_info(dev, "regs %p, irq %d\n", hsotg->regs, hsotg->irq);
3309 device_initialize(&hsotg->gadget.dev);
3311 dev_set_name(&hsotg->gadget.dev, "gadget");
3313 hsotg->gadget.is_dualspeed = 1;
3314 hsotg->gadget.ops = &s3c_hsotg_gadget_ops;
3315 hsotg->gadget.name = dev_name(dev);
3317 hsotg->gadget.dev.parent = dev;
3318 hsotg->gadget.dev.dma_mask = dev->dma_mask;
3320 /* setup endpoint information */
3322 INIT_LIST_HEAD(&hsotg->gadget.ep_list);
3323 hsotg->gadget.ep0 = &hsotg->eps[0].ep;
3325 /* allocate EP0 request */
3327 hsotg->ctrl_req = s3c_hsotg_ep_alloc_request(&hsotg->eps[0].ep,
3329 if (!hsotg->ctrl_req) {
3330 dev_err(dev, "failed to allocate ctrl req\n");
3334 /* reset the system */
3336 clk_enable(hsotg->clk);
3338 s3c_hsotg_gate(pdev, true);
3340 s3c_hsotg_otgreset(hsotg);
3341 s3c_hsotg_corereset(hsotg);
3342 s3c_hsotg_init(hsotg);
3344 /* initialise the endpoints now the core has been initialised */
3345 for (epnum = 0; epnum < S3C_HSOTG_EPS; epnum++)
3346 s3c_hsotg_initep(hsotg, &hsotg->eps[epnum], epnum);
3348 s3c_hsotg_create_debug(hsotg);
3350 s3c_hsotg_dump(hsotg);
3356 iounmap(hsotg->regs);
3359 release_resource(hsotg->regs_res);
3360 kfree(hsotg->regs_res);
3362 clk_put(hsotg->clk);
3368 static int __devexit s3c_hsotg_remove(struct platform_device *pdev)
3370 struct s3c_hsotg *hsotg = platform_get_drvdata(pdev);
3372 s3c_hsotg_delete_debug(hsotg);
3374 usb_gadget_unregister_driver(hsotg->driver);
3376 free_irq(hsotg->irq, hsotg);
3377 iounmap(hsotg->regs);
3379 release_resource(hsotg->regs_res);
3380 kfree(hsotg->regs_res);
3382 s3c_hsotg_gate(pdev, false);
3384 clk_disable(hsotg->clk);
3385 clk_put(hsotg->clk);
3392 #define s3c_hsotg_suspend NULL
3393 #define s3c_hsotg_resume NULL
3396 static struct platform_driver s3c_hsotg_driver = {
3398 .name = "s3c-hsotg",
3399 .owner = THIS_MODULE,
3401 .probe = s3c_hsotg_probe,
3402 .remove = __devexit_p(s3c_hsotg_remove),
3403 .suspend = s3c_hsotg_suspend,
3404 .resume = s3c_hsotg_resume,
3407 static int __init s3c_hsotg_modinit(void)
3409 return platform_driver_register(&s3c_hsotg_driver);
3412 static void __exit s3c_hsotg_modexit(void)
3414 platform_driver_unregister(&s3c_hsotg_driver);
3417 module_init(s3c_hsotg_modinit);
3418 module_exit(s3c_hsotg_modexit);
3420 MODULE_DESCRIPTION("Samsung S3C USB High-speed/OtG device");
3421 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
3422 MODULE_LICENSE("GPL");
3423 MODULE_ALIAS("platform:s3c-hsotg");