drivers/usb/gadget/s3c_udc_otg_xfer_dma.c

   1 /*
   2  * drivers/usb/gadget/s3c_udc_otg_xfer_dma.c
   3  * Samsung S3C on-chip full/high speed USB OTG 2.0 device controllers
   4  *
   5  * Copyright (C) 2009 for Samsung Electronics
   6  *
   7  * BSP Support for Samsung's UDC driver
   8  * available at:
   9  * git://git.kernel.org/pub/scm/linux/kernel/git/kki_ap/linux-2.6-samsung.git
  10  *
  11  * State machine bugfixes:
  12  * Marek Szyprowski <m.szyprowski@samsung.com>
  13  *
  14  * Ported to u-boot:
  15  * Marek Szyprowski <m.szyprowski@samsung.com>
  16  * Lukasz Majewski <l.majewski@samsumg.com>
  17  *
  18  * SPDX-License-Identifier:     GPL-2.0+
  19  */
  20
  21 static u8 clear_feature_num;
  22 int clear_feature_flag;
  23
  24 /* Bulk-Only Mass Storage Reset (class-specific request) */
  25 #define GET_MAX_LUN_REQUEST     0xFE
  26 #define BOT_RESET_REQUEST       0xFF
  27
  28 static inline void s3c_udc_ep0_zlp(struct s3c_udc *dev)
  29 {
  30         u32 ep_ctrl;
  31
  32         writel(usb_ctrl_dma_addr, &reg->in_endp[EP0_CON].diepdma);
  33         writel(DIEPT_SIZ_PKT_CNT(1), &reg->in_endp[EP0_CON].dieptsiz);
  34
  35         ep_ctrl = readl(&reg->in_endp[EP0_CON].diepctl);
  36         writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK,
  37                &reg->in_endp[EP0_CON].diepctl);
  38
  39         debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
  40                 __func__, readl(&reg->in_endp[EP0_CON].diepctl));
  41         dev->ep0state = WAIT_FOR_IN_COMPLETE;
  42 }
  43
  44 void s3c_udc_pre_setup(void)
  45 {
  46         u32 ep_ctrl;
  47
  48         debug_cond(DEBUG_IN_EP,
  49                    "%s : Prepare Setup packets.\n", __func__);
  50
  51         writel(DOEPT_SIZ_PKT_CNT(1) | sizeof(struct usb_ctrlrequest),
  52                &reg->out_endp[EP0_CON].doeptsiz);
  53         writel(usb_ctrl_dma_addr, &reg->out_endp[EP0_CON].doepdma);
  54
  55         ep_ctrl = readl(&reg->out_endp[EP0_CON].doepctl);
  56         writel(ep_ctrl|DEPCTL_EPENA, &reg->out_endp[EP0_CON].doepctl);
  57
  58         debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
  59                 __func__, readl(&reg->in_endp[EP0_CON].diepctl));
  60         debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
  61                 __func__, readl(&reg->out_endp[EP0_CON].doepctl));
  62
  63 }
  64
  65 static inline void s3c_ep0_complete_out(void)
  66 {
  67         u32 ep_ctrl;
  68
  69         debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
  70                 __func__, readl(&reg->in_endp[EP0_CON].diepctl));
  71         debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
  72                 __func__, readl(&reg->out_endp[EP0_CON].doepctl));
  73
  74         debug_cond(DEBUG_IN_EP,
  75                 "%s : Prepare Complete Out packet.\n", __func__);
  76
  77         writel(DOEPT_SIZ_PKT_CNT(1) | sizeof(struct usb_ctrlrequest),
  78                &reg->out_endp[EP0_CON].doeptsiz);
  79         writel(usb_ctrl_dma_addr, &reg->out_endp[EP0_CON].doepdma);
  80
  81         ep_ctrl = readl(&reg->out_endp[EP0_CON].doepctl);
  82         writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK,
  83                &reg->out_endp[EP0_CON].doepctl);
  84
  85         debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
  86                 __func__, readl(&reg->in_endp[EP0_CON].diepctl));
  87         debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
  88                 __func__, readl(&reg->out_endp[EP0_CON].doepctl));
  89
  90 }
  91
  92
  93 static int setdma_rx(struct s3c_ep *ep, struct s3c_request *req)
  94 {
  95         u32 *buf, ctrl;
  96         u32 length, pktcnt;
  97         u32 ep_num = ep_index(ep);
  98
  99         buf = req->req.buf + req->req.actual;
 100
 101         length = min(req->req.length - req->req.actual, (int)ep->ep.maxpacket);
 102
 103         ep->len = length;
 104         ep->dma_buf = buf;
 105
 106         if (length == 0)
 107                 pktcnt = 1;
 108         else
 109                 pktcnt = (length - 1)/(ep->ep.maxpacket) + 1;
 110
 111         pktcnt = 1;
 112         ctrl =  readl(&reg->out_endp[ep_num].doepctl);
 113
 114         writel(the_controller->dma_addr[ep_index(ep)+1],
 115                &reg->out_endp[ep_num].doepdma);
 116         writel(DOEPT_SIZ_PKT_CNT(pktcnt) | DOEPT_SIZ_XFER_SIZE(length),
 117                &reg->out_endp[ep_num].doeptsiz);
 118         writel(DEPCTL_EPENA|DEPCTL_CNAK|ctrl, &reg->out_endp[ep_num].doepctl);
 119
 120         debug_cond(DEBUG_OUT_EP != 0,
 121                    "%s: EP%d RX DMA start : DOEPDMA = 0x%x,"
 122                    "DOEPTSIZ = 0x%x, DOEPCTL = 0x%x\n"
 123                    "\tbuf = 0x%p, pktcnt = %d, xfersize = %d\n",
 124                    __func__, ep_num,
 125                    readl(&reg->out_endp[ep_num].doepdma),
 126                    readl(&reg->out_endp[ep_num].doeptsiz),
 127                    readl(&reg->out_endp[ep_num].doepctl),
 128                    buf, pktcnt, length);
 129         return 0;
 130
 131 }
 132
 133 int setdma_tx(struct s3c_ep *ep, struct s3c_request *req)
 134 {
 135         u32 *buf, ctrl = 0;
 136         u32 length, pktcnt;
 137         u32 ep_num = ep_index(ep);
 138         u32 *p = the_controller->dma_buf[ep_index(ep)+1];
 139
 140         buf = req->req.buf + req->req.actual;
 141         length = req->req.length - req->req.actual;
 142
 143         if (ep_num == EP0_CON)
 144                 length = min(length, (u32)ep_maxpacket(ep));
 145
 146         ep->len = length;
 147         ep->dma_buf = buf;
 148         memcpy(p, ep->dma_buf, length);
 149
 150         flush_dcache_range((unsigned long) p ,
 151                            (unsigned long) p + DMA_BUFFER_SIZE);
 152
 153         if (length == 0)
 154                 pktcnt = 1;
 155         else
 156                 pktcnt = (length - 1)/(ep->ep.maxpacket) + 1;
 157
 158         /* Flush the endpoint's Tx FIFO */
 159         writel(TX_FIFO_NUMBER(ep->fifo_num), &reg->grstctl);
 160         writel(TX_FIFO_NUMBER(ep->fifo_num) | TX_FIFO_FLUSH, &reg->grstctl);
 161         while (readl(&reg->grstctl) & TX_FIFO_FLUSH)
 162                 ;
 163
 164         writel(the_controller->dma_addr[ep_index(ep)+1],
 165                &reg->in_endp[ep_num].diepdma);
 166         writel(DIEPT_SIZ_PKT_CNT(pktcnt) | DIEPT_SIZ_XFER_SIZE(length),
 167                &reg->in_endp[ep_num].dieptsiz);
 168
 169         ctrl = readl(&reg->in_endp[ep_num].diepctl);
 170
 171         /* Write the FIFO number to be used for this endpoint */
 172         ctrl &= DIEPCTL_TX_FIFO_NUM_MASK;
 173         ctrl |= DIEPCTL_TX_FIFO_NUM(ep->fifo_num);
 174
 175         /* Clear reserved (Next EP) bits */
 176         ctrl = (ctrl&~(EP_MASK<<DEPCTL_NEXT_EP_BIT));
 177
 178         writel(DEPCTL_EPENA|DEPCTL_CNAK|ctrl, &reg->in_endp[ep_num].diepctl);
 179
 180         debug_cond(DEBUG_IN_EP,
 181                 "%s:EP%d TX DMA start : DIEPDMA0 = 0x%x,"
 182                 "DIEPTSIZ0 = 0x%x, DIEPCTL0 = 0x%x\n"
 183                 "\tbuf = 0x%p, pktcnt = %d, xfersize = %d\n",
 184                 __func__, ep_num,
 185                 readl(&reg->in_endp[ep_num].diepdma),
 186                 readl(&reg->in_endp[ep_num].dieptsiz),
 187                 readl(&reg->in_endp[ep_num].diepctl),
 188                 buf, pktcnt, length);
 189
 190         return length;
 191 }
 192
 193 static void complete_rx(struct s3c_udc *dev, u8 ep_num)
 194 {
 195         struct s3c_ep *ep = &dev->ep[ep_num];
 196         struct s3c_request *req = NULL;
 197         u32 ep_tsr = 0, xfer_size = 0, is_short = 0;
 198         u32 *p = the_controller->dma_buf[ep_index(ep)+1];
 199
 200         if (list_empty(&ep->queue)) {
 201                 debug_cond(DEBUG_OUT_EP != 0,
 202                            "%s: RX DMA done : NULL REQ on OUT EP-%d\n",
 203                            __func__, ep_num);
 204                 return;
 205
 206         }
 207
 208         req = list_entry(ep->queue.next, struct s3c_request, queue);
 209         ep_tsr = readl(&reg->out_endp[ep_num].doeptsiz);
 210
 211         if (ep_num == EP0_CON)
 212                 xfer_size = (ep_tsr & DOEPT_SIZ_XFER_SIZE_MAX_EP0);
 213         else
 214                 xfer_size = (ep_tsr & DOEPT_SIZ_XFER_SIZE_MAX_EP);
 215
 216         xfer_size = ep->len - xfer_size;
 217
 218         invalidate_dcache_range((unsigned long) p,
 219                                 (unsigned long) p + DMA_BUFFER_SIZE);
 220
 221         memcpy(ep->dma_buf, p, ep->len);
 222
 223         req->req.actual += min(xfer_size, req->req.length - req->req.actual);
 224         is_short = (xfer_size < ep->ep.maxpacket);
 225
 226         debug_cond(DEBUG_OUT_EP != 0,
 227                    "%s: RX DMA done : ep = %d, rx bytes = %d/%d, "
 228                    "is_short = %d, DOEPTSIZ = 0x%x, remained bytes = %d\n",
 229                    __func__, ep_num, req->req.actual, req->req.length,
 230                    is_short, ep_tsr, xfer_size);
 231
 232         if (is_short || req->req.actual == req->req.length) {
 233                 if (ep_num == EP0_CON && dev->ep0state == DATA_STATE_RECV) {
 234                         debug_cond(DEBUG_OUT_EP != 0, " => Send ZLP\n");
 235                         s3c_udc_ep0_zlp(dev);
 236                         /* packet will be completed in complete_tx() */
 237                         dev->ep0state = WAIT_FOR_IN_COMPLETE;
 238                 } else {
 239                         done(ep, req, 0);
 240
 241                         if (!list_empty(&ep->queue)) {
 242                                 req = list_entry(ep->queue.next,
 243                                         struct s3c_request, queue);
 244                                 debug_cond(DEBUG_OUT_EP != 0,
 245                                            "%s: Next Rx request start...\n",
 246                                            __func__);
 247                                 setdma_rx(ep, req);
 248                         }
 249                 }
 250         } else
 251                 setdma_rx(ep, req);
 252 }
 253
 254 static void complete_tx(struct s3c_udc *dev, u8 ep_num)
 255 {
 256         struct s3c_ep *ep = &dev->ep[ep_num];
 257         struct s3c_request *req;
 258         u32 ep_tsr = 0, xfer_size = 0, is_short = 0;
 259         u32 last;
 260
 261         if (dev->ep0state == WAIT_FOR_NULL_COMPLETE) {
 262                 dev->ep0state = WAIT_FOR_OUT_COMPLETE;
 263                 s3c_ep0_complete_out();
 264                 return;
 265         }
 266
 267         if (list_empty(&ep->queue)) {
 268                 debug_cond(DEBUG_IN_EP,
 269                         "%s: TX DMA done : NULL REQ on IN EP-%d\n",
 270                         __func__, ep_num);
 271                 return;
 272
 273         }
 274
 275         req = list_entry(ep->queue.next, struct s3c_request, queue);
 276
 277         ep_tsr = readl(&reg->in_endp[ep_num].dieptsiz);
 278
 279         xfer_size = ep->len;
 280         is_short = (xfer_size < ep->ep.maxpacket);
 281         req->req.actual += min(xfer_size, req->req.length - req->req.actual);
 282
 283         debug_cond(DEBUG_IN_EP,
 284                 "%s: TX DMA done : ep = %d, tx bytes = %d/%d, "
 285                 "is_short = %d, DIEPTSIZ = 0x%x, remained bytes = %d\n",
 286                 __func__, ep_num, req->req.actual, req->req.length,
 287                 is_short, ep_tsr, xfer_size);
 288
 289         if (ep_num == 0) {
 290                 if (dev->ep0state == DATA_STATE_XMIT) {
 291                         debug_cond(DEBUG_IN_EP,
 292                                 "%s: ep_num = %d, ep0stat =="
 293                                 "DATA_STATE_XMIT\n",
 294                                 __func__, ep_num);
 295                         last = write_fifo_ep0(ep, req);
 296                         if (last)
 297                                 dev->ep0state = WAIT_FOR_COMPLETE;
 298                 } else if (dev->ep0state == WAIT_FOR_IN_COMPLETE) {
 299                         debug_cond(DEBUG_IN_EP,
 300                                 "%s: ep_num = %d, completing request\n",
 301                                 __func__, ep_num);
 302                         done(ep, req, 0);
 303                         dev->ep0state = WAIT_FOR_SETUP;
 304                 } else if (dev->ep0state == WAIT_FOR_COMPLETE) {
 305                         debug_cond(DEBUG_IN_EP,
 306                                 "%s: ep_num = %d, completing request\n",
 307                                 __func__, ep_num);
 308                         done(ep, req, 0);
 309                         dev->ep0state = WAIT_FOR_OUT_COMPLETE;
 310                         s3c_ep0_complete_out();
 311                 } else {
 312                         debug_cond(DEBUG_IN_EP,
 313                                 "%s: ep_num = %d, invalid ep state\n",
 314                                 __func__, ep_num);
 315                 }
 316                 return;
 317         }
 318
 319         if (req->req.actual == req->req.length)
 320                 done(ep, req, 0);
 321
 322         if (!list_empty(&ep->queue)) {
 323                 req = list_entry(ep->queue.next, struct s3c_request, queue);
 324                 debug_cond(DEBUG_IN_EP,
 325                         "%s: Next Tx request start...\n", __func__);
 326                 setdma_tx(ep, req);
 327         }
 328 }
 329
 330 static inline void s3c_udc_check_tx_queue(struct s3c_udc *dev, u8 ep_num)
 331 {
 332         struct s3c_ep *ep = &dev->ep[ep_num];
 333         struct s3c_request *req;
 334
 335         debug_cond(DEBUG_IN_EP,
 336                 "%s: Check queue, ep_num = %d\n", __func__, ep_num);
 337
 338         if (!list_empty(&ep->queue)) {
 339                 req = list_entry(ep->queue.next, struct s3c_request, queue);
 340                 debug_cond(DEBUG_IN_EP,
 341                         "%s: Next Tx request(0x%p) start...\n",
 342                         __func__, req);
 343
 344                 if (ep_is_in(ep))
 345                         setdma_tx(ep, req);
 346                 else
 347                         setdma_rx(ep, req);
 348         } else {
 349                 debug_cond(DEBUG_IN_EP,
 350                         "%s: NULL REQ on IN EP-%d\n", __func__, ep_num);
 351
 352                 return;
 353         }
 354
 355 }
 356
 357 static void process_ep_in_intr(struct s3c_udc *dev)
 358 {
 359         u32 ep_intr, ep_intr_status;
 360         u8 ep_num = 0;
 361
 362         ep_intr = readl(&reg->daint);
 363         debug_cond(DEBUG_IN_EP,
 364                 "*** %s: EP In interrupt : DAINT = 0x%x\n", __func__, ep_intr);
 365
 366         ep_intr &= DAINT_MASK;
 367
 368         while (ep_intr) {
 369                 if (ep_intr & DAINT_IN_EP_INT(1)) {
 370                         ep_intr_status = readl(&reg->in_endp[ep_num].diepint);
 371                         debug_cond(DEBUG_IN_EP,
 372                                    "\tEP%d-IN : DIEPINT = 0x%x\n",
 373                                    ep_num, ep_intr_status);
 374
 375                         /* Interrupt Clear */
 376                         writel(ep_intr_status, &reg->in_endp[ep_num].diepint);
 377
 378                         if (ep_intr_status & TRANSFER_DONE) {
 379                                 complete_tx(dev, ep_num);
 380
 381                                 if (ep_num == 0) {
 382                                         if (dev->ep0state ==
 383                                             WAIT_FOR_IN_COMPLETE)
 384                                                 dev->ep0state = WAIT_FOR_SETUP;
 385
 386                                         if (dev->ep0state == WAIT_FOR_SETUP)
 387                                                 s3c_udc_pre_setup();
 388
 389                                         /* continue transfer after
 390                                            set_clear_halt for DMA mode */
 391                                         if (clear_feature_flag == 1) {
 392                                                 s3c_udc_check_tx_queue(dev,
 393                                                         clear_feature_num);
 394                                                 clear_feature_flag = 0;
 395                                         }
 396                                 }
 397                         }
 398                 }
 399                 ep_num++;
 400                 ep_intr >>= 1;
 401         }
 402 }
 403
 404 static void process_ep_out_intr(struct s3c_udc *dev)
 405 {
 406         u32 ep_intr, ep_intr_status;
 407         u8 ep_num = 0;
 408
 409         ep_intr = readl(&reg->daint);
 410         debug_cond(DEBUG_OUT_EP != 0,
 411                    "*** %s: EP OUT interrupt : DAINT = 0x%x\n",
 412                    __func__, ep_intr);
 413
 414         ep_intr = (ep_intr >> DAINT_OUT_BIT) & DAINT_MASK;
 415
 416         while (ep_intr) {
 417                 if (ep_intr & 0x1) {
 418                         ep_intr_status = readl(&reg->out_endp[ep_num].doepint);
 419                         debug_cond(DEBUG_OUT_EP != 0,
 420                                    "\tEP%d-OUT : DOEPINT = 0x%x\n",
 421                                    ep_num, ep_intr_status);
 422
 423                         /* Interrupt Clear */
 424                         writel(ep_intr_status, &reg->out_endp[ep_num].doepint);
 425
 426                         if (ep_num == 0) {
 427                                 if (ep_intr_status & TRANSFER_DONE) {
 428                                         if (dev->ep0state !=
 429                                             WAIT_FOR_OUT_COMPLETE)
 430                                                 complete_rx(dev, ep_num);
 431                                         else {
 432                                                 dev->ep0state = WAIT_FOR_SETUP;
 433                                                 s3c_udc_pre_setup();
 434                                         }
 435                                 }
 436
 437                                 if (ep_intr_status &
 438                                     CTRL_OUT_EP_SETUP_PHASE_DONE) {
 439                                         debug_cond(DEBUG_OUT_EP != 0,
 440                                                    "SETUP packet arrived\n");
 441                                         s3c_handle_ep0(dev);
 442                                 }
 443                         } else {
 444                                 if (ep_intr_status & TRANSFER_DONE)
 445                                         complete_rx(dev, ep_num);
 446                         }
 447                 }
 448                 ep_num++;
 449                 ep_intr >>= 1;
 450         }
 451 }
 452
 453 /*
 454  *      usb client interrupt handler.
 455  */
 456 static int s3c_udc_irq(int irq, void *_dev)
 457 {
 458         struct s3c_udc *dev = _dev;
 459         u32 intr_status;
 460         u32 usb_status, gintmsk;
 461         unsigned long flags;
 462
 463         spin_lock_irqsave(&dev->lock, flags);
 464
 465         intr_status = readl(&reg->gintsts);
 466         gintmsk = readl(&reg->gintmsk);
 467
 468         debug_cond(DEBUG_ISR,
 469                   "\n*** %s : GINTSTS=0x%x(on state %s), GINTMSK : 0x%x,"
 470                   "DAINT : 0x%x, DAINTMSK : 0x%x\n",
 471                   __func__, intr_status, state_names[dev->ep0state], gintmsk,
 472                   readl(&reg->daint), readl(&reg->daintmsk));
 473
 474         if (!intr_status) {
 475                 spin_unlock_irqrestore(&dev->lock, flags);
 476                 return IRQ_HANDLED;
 477         }
 478
 479         if (intr_status & INT_ENUMDONE) {
 480                 debug_cond(DEBUG_ISR, "\tSpeed Detection interrupt\n");
 481
 482                 writel(INT_ENUMDONE, &reg->gintsts);
 483                 usb_status = (readl(&reg->dsts) & 0x6);
 484
 485                 if (usb_status & (USB_FULL_30_60MHZ | USB_FULL_48MHZ)) {
 486                         debug_cond(DEBUG_ISR,
 487                                    "\t\tFull Speed Detection\n");
 488                         set_max_pktsize(dev, USB_SPEED_FULL);
 489
 490                 } else {
 491                         debug_cond(DEBUG_ISR,
 492                                 "\t\tHigh Speed Detection : 0x%x\n",
 493                                 usb_status);
 494                         set_max_pktsize(dev, USB_SPEED_HIGH);
 495                 }
 496         }
 497
 498         if (intr_status & INT_EARLY_SUSPEND) {
 499                 debug_cond(DEBUG_ISR, "\tEarly suspend interrupt\n");
 500                 writel(INT_EARLY_SUSPEND, &reg->gintsts);
 501         }
 502
 503         if (intr_status & INT_SUSPEND) {
 504                 usb_status = readl(&reg->dsts);
 505                 debug_cond(DEBUG_ISR,
 506                         "\tSuspend interrupt :(DSTS):0x%x\n", usb_status);
 507                 writel(INT_SUSPEND, &reg->gintsts);
 508
 509                 if (dev->gadget.speed != USB_SPEED_UNKNOWN
 510                     && dev->driver) {
 511                         if (dev->driver->suspend)
 512                                 dev->driver->suspend(&dev->gadget);
 513
 514                         /* HACK to let gadget detect disconnected state */
 515                         if (dev->driver->disconnect) {
 516                                 spin_unlock_irqrestore(&dev->lock, flags);
 517                                 dev->driver->disconnect(&dev->gadget);
 518                                 spin_lock_irqsave(&dev->lock, flags);
 519                         }
 520                 }
 521         }
 522
 523         if (intr_status & INT_RESUME) {
 524                 debug_cond(DEBUG_ISR, "\tResume interrupt\n");
 525                 writel(INT_RESUME, &reg->gintsts);
 526
 527                 if (dev->gadget.speed != USB_SPEED_UNKNOWN
 528                     && dev->driver
 529                     && dev->driver->resume) {
 530
 531                         dev->driver->resume(&dev->gadget);
 532                 }
 533         }
 534
 535         if (intr_status & INT_RESET) {
 536                 usb_status = readl(&reg->gotgctl);
 537                 debug_cond(DEBUG_ISR,
 538                         "\tReset interrupt - (GOTGCTL):0x%x\n", usb_status);
 539                 writel(INT_RESET, &reg->gintsts);
 540
 541                 if ((usb_status & 0xc0000) == (0x3 << 18)) {
 542                         if (reset_available) {
 543                                 debug_cond(DEBUG_ISR,
 544                                         "\t\tOTG core got reset (%d)!!\n",
 545                                         reset_available);
 546                                 reconfig_usbd();
 547                                 dev->ep0state = WAIT_FOR_SETUP;
 548                                 reset_available = 0;
 549                                 s3c_udc_pre_setup();
 550                         } else
 551                                 reset_available = 1;
 552
 553                 } else {
 554                         reset_available = 1;
 555                         debug_cond(DEBUG_ISR,
 556                                    "\t\tRESET handling skipped\n");
 557                 }
 558         }
 559
 560         if (intr_status & INT_IN_EP)
 561                 process_ep_in_intr(dev);
 562
 563         if (intr_status & INT_OUT_EP)
 564                 process_ep_out_intr(dev);
 565
 566         spin_unlock_irqrestore(&dev->lock, flags);
 567
 568         return IRQ_HANDLED;
 569 }
 570
 571 /** Queue one request
 572  *  Kickstart transfer if needed
 573  */
 574 static int s3c_queue(struct usb_ep *_ep, struct usb_request *_req,
 575                          gfp_t gfp_flags)
 576 {
 577         struct s3c_request *req;
 578         struct s3c_ep *ep;
 579         struct s3c_udc *dev;
 580         unsigned long flags;
 581         u32 ep_num, gintsts;
 582
 583         req = container_of(_req, struct s3c_request, req);
 584         if (unlikely(!_req || !_req->complete || !_req->buf
 585                      || !list_empty(&req->queue))) {
 586
 587                 debug("%s: bad params\n", __func__);
 588                 return -EINVAL;
 589         }
 590
 591         ep = container_of(_ep, struct s3c_ep, ep);
 592
 593         if (unlikely(!_ep || (!ep->desc && ep->ep.name != ep0name))) {
 594
 595                 debug("%s: bad ep: %s, %d, %p\n", __func__,
 596                       ep->ep.name, !ep->desc, _ep);
 597                 return -EINVAL;
 598         }
 599
 600         ep_num = ep_index(ep);
 601         dev = ep->dev;
 602         if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
 603
 604                 debug("%s: bogus device state %p\n", __func__, dev->driver);
 605                 return -ESHUTDOWN;
 606         }
 607
 608         spin_lock_irqsave(&dev->lock, flags);
 609
 610         _req->status = -EINPROGRESS;
 611         _req->actual = 0;
 612
 613         /* kickstart this i/o queue? */
 614         debug("\n*** %s: %s-%s req = %p, len = %d, buf = %p"
 615                 "Q empty = %d, stopped = %d\n",
 616                 __func__, _ep->name, ep_is_in(ep) ? "in" : "out",
 617                 _req, _req->length, _req->buf,
 618                 list_empty(&ep->queue), ep->stopped);
 619
 620 #ifdef DEBUG
 621         {
 622                 int i, len = _req->length;
 623
 624                 printf("pkt = ");
 625                 if (len > 64)
 626                         len = 64;
 627                 for (i = 0; i < len; i++) {
 628                         printf("%02x", ((u8 *)_req->buf)[i]);
 629                         if ((i & 7) == 7)
 630                                 printf(" ");
 631                 }
 632                 printf("\n");
 633         }
 634 #endif
 635
 636         if (list_empty(&ep->queue) && !ep->stopped) {
 637
 638                 if (ep_num == 0) {
 639                         /* EP0 */
 640                         list_add_tail(&req->queue, &ep->queue);
 641                         s3c_ep0_kick(dev, ep);
 642                         req = 0;
 643
 644                 } else if (ep_is_in(ep)) {
 645                         gintsts = readl(&reg->gintsts);
 646                         debug_cond(DEBUG_IN_EP,
 647                                    "%s: ep_is_in, S3C_UDC_OTG_GINTSTS=0x%x\n",
 648                                    __func__, gintsts);
 649
 650                         setdma_tx(ep, req);
 651                 } else {
 652                         gintsts = readl(&reg->gintsts);
 653                         debug_cond(DEBUG_OUT_EP != 0,
 654                                    "%s:ep_is_out, S3C_UDC_OTG_GINTSTS=0x%x\n",
 655                                    __func__, gintsts);
 656
 657                         setdma_rx(ep, req);
 658                 }
 659         }
 660
 661         /* pio or dma irq handler advances the queue. */
 662         if (likely(req != 0))
 663                 list_add_tail(&req->queue, &ep->queue);
 664
 665         spin_unlock_irqrestore(&dev->lock, flags);
 666
 667         return 0;
 668 }
 669
 670 /****************************************************************/
 671 /* End Point 0 related functions                                */
 672 /****************************************************************/
 673
 674 /* return:  0 = still running, 1 = completed, negative = errno */
 675 static int write_fifo_ep0(struct s3c_ep *ep, struct s3c_request *req)
 676 {
 677         u32 max;
 678         unsigned count;
 679         int is_last;
 680
 681         max = ep_maxpacket(ep);
 682
 683         debug_cond(DEBUG_EP0 != 0, "%s: max = %d\n", __func__, max);
 684
 685         count = setdma_tx(ep, req);
 686
 687         /* last packet is usually short (or a zlp) */
 688         if (likely(count != max))
 689                 is_last = 1;
 690         else {
 691                 if (likely(req->req.length != req->req.actual + count)
 692                     || req->req.zero)
 693                         is_last = 0;
 694                 else
 695                         is_last = 1;
 696         }
 697
 698         debug_cond(DEBUG_EP0 != 0,
 699                    "%s: wrote %s %d bytes%s %d left %p\n", __func__,
 700                    ep->ep.name, count,
 701                    is_last ? "/L" : "",
 702                    req->req.length - req->req.actual - count, req);
 703
 704         /* requests complete when all IN data is in the FIFO */
 705         if (is_last) {
 706                 ep->dev->ep0state = WAIT_FOR_SETUP;
 707                 return 1;
 708         }
 709
 710         return 0;
 711 }
 712
 713 int s3c_fifo_read(struct s3c_ep *ep, u32 *cp, int max)
 714 {
 715         u32 bytes;
 716
 717         bytes = sizeof(struct usb_ctrlrequest);
 718
 719         invalidate_dcache_range((unsigned long) ep->dev->dma_buf[ep_index(ep)],
 720                                 (unsigned long) ep->dev->dma_buf[ep_index(ep)]
 721                                 + DMA_BUFFER_SIZE);
 722
 723         debug_cond(DEBUG_EP0 != 0,
 724                    "%s: bytes=%d, ep_index=%d %p\n", __func__,
 725                    bytes, ep_index(ep), ep->dev->dma_buf[ep_index(ep)]);
 726
 727         return bytes;
 728 }
 729
 730 /**
 731  * udc_set_address - set the USB address for this device
 732  * @address:
 733  *
 734  * Called from control endpoint function
 735  * after it decodes a set address setup packet.
 736  */
 737 static void udc_set_address(struct s3c_udc *dev, unsigned char address)
 738 {
 739         u32 ctrl = readl(&reg->dcfg);
 740         writel(DEVICE_ADDRESS(address) | ctrl, &reg->dcfg);
 741
 742         s3c_udc_ep0_zlp(dev);
 743
 744         debug_cond(DEBUG_EP0 != 0,
 745                    "%s: USB OTG 2.0 Device address=%d, DCFG=0x%x\n",
 746                    __func__, address, readl(&reg->dcfg));
 747
 748         dev->usb_address = address;
 749 }
 750
 751 static inline void s3c_udc_ep0_set_stall(struct s3c_ep *ep)
 752 {
 753         struct s3c_udc *dev;
 754         u32             ep_ctrl = 0;
 755
 756         dev = ep->dev;
 757         ep_ctrl = readl(&reg->in_endp[EP0_CON].diepctl);
 758
 759         /* set the disable and stall bits */
 760         if (ep_ctrl & DEPCTL_EPENA)
 761                 ep_ctrl |= DEPCTL_EPDIS;
 762
 763         ep_ctrl |= DEPCTL_STALL;
 764
 765         writel(ep_ctrl, &reg->in_endp[EP0_CON].diepctl);
 766
 767         debug_cond(DEBUG_EP0 != 0,
 768                    "%s: set ep%d stall, DIEPCTL0 = 0x%p\n",
 769                    __func__, ep_index(ep), &reg->in_endp[EP0_CON].diepctl);
 770         /*
 771          * The application can only set this bit, and the core clears it,
 772          * when a SETUP token is received for this endpoint
 773          */
 774         dev->ep0state = WAIT_FOR_SETUP;
 775
 776         s3c_udc_pre_setup();
 777 }
 778
 779 static void s3c_ep0_read(struct s3c_udc *dev)
 780 {
 781         struct s3c_request *req;
 782         struct s3c_ep *ep = &dev->ep[0];
 783
 784         if (!list_empty(&ep->queue)) {
 785                 req = list_entry(ep->queue.next, struct s3c_request, queue);
 786
 787         } else {
 788                 debug("%s: ---> BUG\n", __func__);
 789                 BUG();
 790                 return;
 791         }
 792
 793         debug_cond(DEBUG_EP0 != 0,
 794                    "%s: req = %p, req.length = 0x%x, req.actual = 0x%x\n",
 795                    __func__, req, req->req.length, req->req.actual);
 796
 797         if (req->req.length == 0) {
 798                 /* zlp for Set_configuration, Set_interface,
 799                  * or Bulk-Only mass storge reset */
 800
 801                 ep->len = 0;
 802                 s3c_udc_ep0_zlp(dev);
 803
 804                 debug_cond(DEBUG_EP0 != 0,
 805                            "%s: req.length = 0, bRequest = %d\n",
 806                            __func__, usb_ctrl->bRequest);
 807                 return;
 808         }
 809
 810         setdma_rx(ep, req);
 811 }
 812
 813 /*
 814  * DATA_STATE_XMIT
 815  */
 816 static int s3c_ep0_write(struct s3c_udc *dev)
 817 {
 818         struct s3c_request *req;
 819         struct s3c_ep *ep = &dev->ep[0];
 820         int ret, need_zlp = 0;
 821
 822         if (list_empty(&ep->queue))
 823                 req = 0;
 824         else
 825                 req = list_entry(ep->queue.next, struct s3c_request, queue);
 826
 827         if (!req) {
 828                 debug_cond(DEBUG_EP0 != 0, "%s: NULL REQ\n", __func__);
 829                 return 0;
 830         }
 831
 832         debug_cond(DEBUG_EP0 != 0,
 833                    "%s: req = %p, req.length = 0x%x, req.actual = 0x%x\n",
 834                    __func__, req, req->req.length, req->req.actual);
 835
 836         if (req->req.length - req->req.actual == ep0_fifo_size) {
 837                 /* Next write will end with the packet size, */
 838                 /* so we need Zero-length-packet */
 839                 need_zlp = 1;
 840         }
 841
 842         ret = write_fifo_ep0(ep, req);
 843
 844         if ((ret == 1) && !need_zlp) {
 845                 /* Last packet */
 846                 dev->ep0state = WAIT_FOR_COMPLETE;
 847                 debug_cond(DEBUG_EP0 != 0,
 848                            "%s: finished, waiting for status\n", __func__);
 849
 850         } else {
 851                 dev->ep0state = DATA_STATE_XMIT;
 852                 debug_cond(DEBUG_EP0 != 0,
 853                            "%s: not finished\n", __func__);
 854         }
 855
 856         return 1;
 857 }
 858
 859 u16     g_status;
 860
 861 int s3c_udc_get_status(struct s3c_udc *dev,
 862                 struct usb_ctrlrequest *crq)
 863 {
 864         u8 ep_num = crq->wIndex & 0x7F;
 865         u32 ep_ctrl;
 866         u32 *p = the_controller->dma_buf[1];
 867
 868         debug_cond(DEBUG_SETUP != 0,
 869                    "%s: *** USB_REQ_GET_STATUS\n", __func__);
 870         printf("crq->brequest:0x%x\n", crq->bRequestType & USB_RECIP_MASK);
 871         switch (crq->bRequestType & USB_RECIP_MASK) {
 872         case USB_RECIP_INTERFACE:
 873                 g_status = 0;
 874                 debug_cond(DEBUG_SETUP != 0,
 875                            "\tGET_STATUS:USB_RECIP_INTERFACE, g_stauts = %d\n",
 876                            g_status);
 877                 break;
 878
 879         case USB_RECIP_DEVICE:
 880                 g_status = 0x1; /* Self powered */
 881                 debug_cond(DEBUG_SETUP != 0,
 882                            "\tGET_STATUS: USB_RECIP_DEVICE, g_stauts = %d\n",
 883                            g_status);
 884                 break;
 885
 886         case USB_RECIP_ENDPOINT:
 887                 if (crq->wLength > 2) {
 888                         debug_cond(DEBUG_SETUP != 0,
 889                                    "\tGET_STATUS:Not support EP or wLength\n");
 890                         return 1;
 891                 }
 892
 893                 g_status = dev->ep[ep_num].stopped;
 894                 debug_cond(DEBUG_SETUP != 0,
 895                            "\tGET_STATUS: USB_RECIP_ENDPOINT, g_stauts = %d\n",
 896                            g_status);
 897
 898                 break;
 899
 900         default:
 901                 return 1;
 902         }
 903
 904         memcpy(p, &g_status, sizeof(g_status));
 905
 906         flush_dcache_range((unsigned long) p,
 907                            (unsigned long) p + DMA_BUFFER_SIZE);
 908
 909         writel(the_controller->dma_addr[1], &reg->in_endp[EP0_CON].diepdma);
 910         writel(DIEPT_SIZ_PKT_CNT(1) | DIEPT_SIZ_XFER_SIZE(2),
 911                &reg->in_endp[EP0_CON].dieptsiz);
 912
 913         ep_ctrl = readl(&reg->in_endp[EP0_CON].diepctl);
 914         writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK,
 915                &reg->in_endp[EP0_CON].diepctl);
 916         dev->ep0state = WAIT_FOR_NULL_COMPLETE;
 917
 918         return 0;
 919 }
 920
 921 static void s3c_udc_set_nak(struct s3c_ep *ep)
 922 {
 923         u8              ep_num;
 924         u32             ep_ctrl = 0;
 925
 926         ep_num = ep_index(ep);
 927         debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type);
 928
 929         if (ep_is_in(ep)) {
 930                 ep_ctrl = readl(&reg->in_endp[ep_num].diepctl);
 931                 ep_ctrl |= DEPCTL_SNAK;
 932                 writel(ep_ctrl, &reg->in_endp[ep_num].diepctl);
 933                 debug("%s: set NAK, DIEPCTL%d = 0x%x\n",
 934                         __func__, ep_num, readl(&reg->in_endp[ep_num].diepctl));
 935         } else {
 936                 ep_ctrl = readl(&reg->out_endp[ep_num].doepctl);
 937                 ep_ctrl |= DEPCTL_SNAK;
 938                 writel(ep_ctrl, &reg->out_endp[ep_num].doepctl);
 939                 debug("%s: set NAK, DOEPCTL%d = 0x%x\n",
 940                       __func__, ep_num, readl(&reg->out_endp[ep_num].doepctl));
 941         }
 942
 943         return;
 944 }
 945
 946
 947 void s3c_udc_ep_set_stall(struct s3c_ep *ep)
 948 {
 949         u8              ep_num;
 950         u32             ep_ctrl = 0;
 951
 952         ep_num = ep_index(ep);
 953         debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type);
 954
 955         if (ep_is_in(ep)) {
 956                 ep_ctrl = readl(&reg->in_endp[ep_num].diepctl);
 957
 958                 /* set the disable and stall bits */
 959                 if (ep_ctrl & DEPCTL_EPENA)
 960                         ep_ctrl |= DEPCTL_EPDIS;
 961
 962                 ep_ctrl |= DEPCTL_STALL;
 963
 964                 writel(ep_ctrl, &reg->in_endp[ep_num].diepctl);
 965                 debug("%s: set stall, DIEPCTL%d = 0x%x\n",
 966                       __func__, ep_num, readl(&reg->in_endp[ep_num].diepctl));
 967
 968         } else {
 969                 ep_ctrl = readl(&reg->out_endp[ep_num].doepctl);
 970
 971                 /* set the stall bit */
 972                 ep_ctrl |= DEPCTL_STALL;
 973
 974                 writel(ep_ctrl, &reg->out_endp[ep_num].doepctl);
 975                 debug("%s: set stall, DOEPCTL%d = 0x%x\n",
 976                       __func__, ep_num, readl(&reg->out_endp[ep_num].doepctl));
 977         }
 978
 979         return;
 980 }
 981
 982 void s3c_udc_ep_clear_stall(struct s3c_ep *ep)
 983 {
 984         u8              ep_num;
 985         u32             ep_ctrl = 0;
 986
 987         ep_num = ep_index(ep);
 988         debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type);
 989
 990         if (ep_is_in(ep)) {
 991                 ep_ctrl = readl(&reg->in_endp[ep_num].diepctl);
 992
 993                 /* clear stall bit */
 994                 ep_ctrl &= ~DEPCTL_STALL;
 995
 996                 /*
 997                  * USB Spec 9.4.5: For endpoints using data toggle, regardless
 998                  * of whether an endpoint has the Halt feature set, a
 999                  * ClearFeature(ENDPOINT_HALT) request always results in the
1000                  * data toggle being reinitialized to DATA0.
1001                  */
1002                 if (ep->bmAttributes == USB_ENDPOINT_XFER_INT
1003                     || ep->bmAttributes == USB_ENDPOINT_XFER_BULK) {
1004                         ep_ctrl |= DEPCTL_SETD0PID; /* DATA0 */
1005                 }
1006
1007                 writel(ep_ctrl, &reg->in_endp[ep_num].diepctl);
1008                 debug("%s: cleared stall, DIEPCTL%d = 0x%x\n",
1009                         __func__, ep_num, readl(&reg->in_endp[ep_num].diepctl));
1010
1011         } else {
1012                 ep_ctrl = readl(&reg->out_endp[ep_num].doepctl);
1013
1014                 /* clear stall bit */
1015                 ep_ctrl &= ~DEPCTL_STALL;
1016
1017                 if (ep->bmAttributes == USB_ENDPOINT_XFER_INT
1018                     || ep->bmAttributes == USB_ENDPOINT_XFER_BULK) {
1019                         ep_ctrl |= DEPCTL_SETD0PID; /* DATA0 */
1020                 }
1021
1022                 writel(ep_ctrl, &reg->out_endp[ep_num].doepctl);
1023                 debug("%s: cleared stall, DOEPCTL%d = 0x%x\n",
1024                       __func__, ep_num, readl(&reg->out_endp[ep_num].doepctl));
1025         }
1026
1027         return;
1028 }
1029
1030 static int s3c_udc_set_halt(struct usb_ep *_ep, int value)
1031 {
1032         struct s3c_ep   *ep;
1033         struct s3c_udc  *dev;
1034         unsigned long   flags;
1035         u8              ep_num;
1036
1037         ep = container_of(_ep, struct s3c_ep, ep);
1038         ep_num = ep_index(ep);
1039
1040         if (unlikely(!_ep || !ep->desc || ep_num == EP0_CON ||
1041                      ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC)) {
1042                 debug("%s: %s bad ep or descriptor\n", __func__, ep->ep.name);
1043                 return -EINVAL;
1044         }
1045
1046         /* Attempt to halt IN ep will fail if any transfer requests
1047          * are still queue */
1048         if (value && ep_is_in(ep) && !list_empty(&ep->queue)) {
1049                 debug("%s: %s queue not empty, req = %p\n",
1050                         __func__, ep->ep.name,
1051                         list_entry(ep->queue.next, struct s3c_request, queue));
1052
1053                 return -EAGAIN;
1054         }
1055
1056         dev = ep->dev;
1057         debug("%s: ep_num = %d, value = %d\n", __func__, ep_num, value);
1058
1059         spin_lock_irqsave(&dev->lock, flags);
1060
1061         if (value == 0) {
1062                 ep->stopped = 0;
1063                 s3c_udc_ep_clear_stall(ep);
1064         } else {
1065                 if (ep_num == 0)
1066                         dev->ep0state = WAIT_FOR_SETUP;
1067
1068                 ep->stopped = 1;
1069                 s3c_udc_ep_set_stall(ep);
1070         }
1071
1072         spin_unlock_irqrestore(&dev->lock, flags);
1073
1074         return 0;
1075 }
1076
1077 void s3c_udc_ep_activate(struct s3c_ep *ep)
1078 {
1079         u8 ep_num;
1080         u32 ep_ctrl = 0, daintmsk = 0;
1081
1082         ep_num = ep_index(ep);
1083
1084         /* Read DEPCTLn register */
1085         if (ep_is_in(ep)) {
1086                 ep_ctrl = readl(&reg->in_endp[ep_num].diepctl);
1087                 daintmsk = 1 << ep_num;
1088         } else {
1089                 ep_ctrl = readl(&reg->out_endp[ep_num].doepctl);
1090                 daintmsk = (1 << ep_num) << DAINT_OUT_BIT;
1091         }
1092
1093         debug("%s: EPCTRL%d = 0x%x, ep_is_in = %d\n",
1094                 __func__, ep_num, ep_ctrl, ep_is_in(ep));
1095
1096         /* If the EP is already active don't change the EP Control
1097          * register. */
1098         if (!(ep_ctrl & DEPCTL_USBACTEP)) {
1099                 ep_ctrl = (ep_ctrl & ~DEPCTL_TYPE_MASK) |
1100                         (ep->bmAttributes << DEPCTL_TYPE_BIT);
1101                 ep_ctrl = (ep_ctrl & ~DEPCTL_MPS_MASK) |
1102                         (ep->ep.maxpacket << DEPCTL_MPS_BIT);
1103                 ep_ctrl |= (DEPCTL_SETD0PID | DEPCTL_USBACTEP | DEPCTL_SNAK);
1104
1105                 if (ep_is_in(ep)) {
1106                         writel(ep_ctrl, &reg->in_endp[ep_num].diepctl);
1107                         debug("%s: USB Ative EP%d, DIEPCTRL%d = 0x%x\n",
1108                               __func__, ep_num, ep_num,
1109                               readl(&reg->in_endp[ep_num].diepctl));
1110                 } else {
1111                         writel(ep_ctrl, &reg->out_endp[ep_num].doepctl);
1112                         debug("%s: USB Ative EP%d, DOEPCTRL%d = 0x%x\n",
1113                               __func__, ep_num, ep_num,
1114                               readl(&reg->out_endp[ep_num].doepctl));
1115                 }
1116         }
1117
1118         /* Unmask EP Interrtupt */
1119         writel(readl(&reg->daintmsk)|daintmsk, &reg->daintmsk);
1120         debug("%s: DAINTMSK = 0x%x\n", __func__, readl(&reg->daintmsk));
1121
1122 }
1123
1124 static int s3c_udc_clear_feature(struct usb_ep *_ep)
1125 {
1126         struct s3c_udc  *dev;
1127         struct s3c_ep   *ep;
1128         u8              ep_num;
1129
1130         ep = container_of(_ep, struct s3c_ep, ep);
1131         ep_num = ep_index(ep);
1132
1133         dev = ep->dev;
1134         debug_cond(DEBUG_SETUP != 0,
1135                    "%s: ep_num = %d, is_in = %d, clear_feature_flag = %d\n",
1136                    __func__, ep_num, ep_is_in(ep), clear_feature_flag);
1137
1138         if (usb_ctrl->wLength != 0) {
1139                 debug_cond(DEBUG_SETUP != 0,
1140                            "\tCLEAR_FEATURE: wLength is not zero.....\n");
1141                 return 1;
1142         }
1143
1144         switch (usb_ctrl->bRequestType & USB_RECIP_MASK) {
1145         case USB_RECIP_DEVICE:
1146                 switch (usb_ctrl->wValue) {
1147                 case USB_DEVICE_REMOTE_WAKEUP:
1148                         debug_cond(DEBUG_SETUP != 0,
1149                                    "\tOFF:USB_DEVICE_REMOTE_WAKEUP\n");
1150                         break;
1151
1152                 case USB_DEVICE_TEST_MODE:
1153                         debug_cond(DEBUG_SETUP != 0,
1154                                    "\tCLEAR_FEATURE: USB_DEVICE_TEST_MODE\n");
1155                         /** @todo Add CLEAR_FEATURE for TEST modes. */
1156                         break;
1157                 }
1158
1159                 s3c_udc_ep0_zlp(dev);
1160                 break;
1161
1162         case USB_RECIP_ENDPOINT:
1163                 debug_cond(DEBUG_SETUP != 0,
1164                            "\tCLEAR_FEATURE:USB_RECIP_ENDPOINT, wValue = %d\n",
1165                            usb_ctrl->wValue);
1166
1167                 if (usb_ctrl->wValue == USB_ENDPOINT_HALT) {
1168                         if (ep_num == 0) {
1169                                 s3c_udc_ep0_set_stall(ep);
1170                                 return 0;
1171                         }
1172
1173                         s3c_udc_ep0_zlp(dev);
1174
1175                         s3c_udc_ep_clear_stall(ep);
1176                         s3c_udc_ep_activate(ep);
1177                         ep->stopped = 0;
1178
1179                         clear_feature_num = ep_num;
1180                         clear_feature_flag = 1;
1181                 }
1182                 break;
1183         }
1184
1185         return 0;
1186 }
1187
1188 static int s3c_udc_set_feature(struct usb_ep *_ep)
1189 {
1190         struct s3c_udc  *dev;
1191         struct s3c_ep   *ep;
1192         u8              ep_num;
1193
1194         ep = container_of(_ep, struct s3c_ep, ep);
1195         ep_num = ep_index(ep);
1196         dev = ep->dev;
1197
1198         debug_cond(DEBUG_SETUP != 0,
1199                    "%s: *** USB_REQ_SET_FEATURE , ep_num = %d\n",
1200                     __func__, ep_num);
1201
1202         if (usb_ctrl->wLength != 0) {
1203                 debug_cond(DEBUG_SETUP != 0,
1204                            "\tSET_FEATURE: wLength is not zero.....\n");
1205                 return 1;
1206         }
1207
1208         switch (usb_ctrl->bRequestType & USB_RECIP_MASK) {
1209         case USB_RECIP_DEVICE:
1210                 switch (usb_ctrl->wValue) {
1211                 case USB_DEVICE_REMOTE_WAKEUP:
1212                         debug_cond(DEBUG_SETUP != 0,
1213                                    "\tSET_FEATURE:USB_DEVICE_REMOTE_WAKEUP\n");
1214                         break;
1215                 case USB_DEVICE_B_HNP_ENABLE:
1216                         debug_cond(DEBUG_SETUP != 0,
1217                                    "\tSET_FEATURE: USB_DEVICE_B_HNP_ENABLE\n");
1218                         break;
1219
1220                 case USB_DEVICE_A_HNP_SUPPORT:
1221                         /* RH port supports HNP */
1222                         debug_cond(DEBUG_SETUP != 0,
1223                                    "\tSET_FEATURE:USB_DEVICE_A_HNP_SUPPORT\n");
1224                         break;
1225
1226                 case USB_DEVICE_A_ALT_HNP_SUPPORT:
1227                         /* other RH port does */
1228                         debug_cond(DEBUG_SETUP != 0,
1229                                    "\tSET: USB_DEVICE_A_ALT_HNP_SUPPORT\n");
1230                         break;
1231                 }
1232
1233                 s3c_udc_ep0_zlp(dev);
1234                 return 0;
1235
1236         case USB_RECIP_INTERFACE:
1237                 debug_cond(DEBUG_SETUP != 0,
1238                            "\tSET_FEATURE: USB_RECIP_INTERFACE\n");
1239                 break;
1240
1241         case USB_RECIP_ENDPOINT:
1242                 debug_cond(DEBUG_SETUP != 0,
1243                            "\tSET_FEATURE: USB_RECIP_ENDPOINT\n");
1244                 if (usb_ctrl->wValue == USB_ENDPOINT_HALT) {
1245                         if (ep_num == 0) {
1246                                 s3c_udc_ep0_set_stall(ep);
1247                                 return 0;
1248                         }
1249                         ep->stopped = 1;
1250                         s3c_udc_ep_set_stall(ep);
1251                 }
1252
1253                 s3c_udc_ep0_zlp(dev);
1254                 return 0;
1255         }
1256
1257         return 1;
1258 }
1259
1260 /*
1261  * WAIT_FOR_SETUP (OUT_PKT_RDY)
1262  */
1263 void s3c_ep0_setup(struct s3c_udc *dev)
1264 {
1265         struct s3c_ep *ep = &dev->ep[0];
1266         int i;
1267         u8 ep_num;
1268
1269         /* Nuke all previous transfers */
1270         nuke(ep, -EPROTO);
1271
1272         /* read control req from fifo (8 bytes) */
1273         s3c_fifo_read(ep, (u32 *)usb_ctrl, 8);
1274
1275         debug_cond(DEBUG_SETUP != 0,
1276                    "%s: bRequestType = 0x%x(%s), bRequest = 0x%x"
1277                    "\twLength = 0x%x, wValue = 0x%x, wIndex= 0x%x\n",
1278                    __func__, usb_ctrl->bRequestType,
1279                    (usb_ctrl->bRequestType & USB_DIR_IN) ? "IN" : "OUT",
1280                    usb_ctrl->bRequest,
1281                    usb_ctrl->wLength, usb_ctrl->wValue, usb_ctrl->wIndex);
1282
1283 #ifdef DEBUG
1284         {
1285                 int i, len = sizeof(*usb_ctrl);
1286                 char *p = (char *)usb_ctrl;
1287
1288                 printf("pkt = ");
1289                 for (i = 0; i < len; i++) {
1290                         printf("%02x", ((u8 *)p)[i]);
1291                         if ((i & 7) == 7)
1292                                 printf(" ");
1293                 }
1294                 printf("\n");
1295         }
1296 #endif
1297
1298         if (usb_ctrl->bRequest == GET_MAX_LUN_REQUEST &&
1299             usb_ctrl->wLength != 1) {
1300                 debug_cond(DEBUG_SETUP != 0,
1301                            "\t%s:GET_MAX_LUN_REQUEST:invalid",
1302                            __func__);
1303                 debug_cond(DEBUG_SETUP != 0,
1304                            "wLength = %d, setup returned\n",
1305                            usb_ctrl->wLength);
1306
1307                 s3c_udc_ep0_set_stall(ep);
1308                 dev->ep0state = WAIT_FOR_SETUP;
1309
1310                 return;
1311         } else if (usb_ctrl->bRequest == BOT_RESET_REQUEST &&
1312                  usb_ctrl->wLength != 0) {
1313                 /* Bulk-Only *mass storge reset of class-specific request */
1314                 debug_cond(DEBUG_SETUP != 0,
1315                            "%s:BOT Rest:invalid wLength =%d, setup returned\n",
1316                            __func__, usb_ctrl->wLength);
1317
1318                 s3c_udc_ep0_set_stall(ep);
1319                 dev->ep0state = WAIT_FOR_SETUP;
1320
1321                 return;
1322         }
1323
1324         /* Set direction of EP0 */
1325         if (likely(usb_ctrl->bRequestType & USB_DIR_IN)) {
1326                 ep->bEndpointAddress |= USB_DIR_IN;
1327         } else {
1328                 ep->bEndpointAddress &= ~USB_DIR_IN;
1329         }
1330         /* cope with automagic for some standard requests. */
1331         dev->req_std = (usb_ctrl->bRequestType & USB_TYPE_MASK)
1332                 == USB_TYPE_STANDARD;
1333
1334         dev->req_pending = 1;
1335
1336         /* Handle some SETUP packets ourselves */
1337         if (dev->req_std) {
1338                 switch (usb_ctrl->bRequest) {
1339                 case USB_REQ_SET_ADDRESS:
1340                 debug_cond(DEBUG_SETUP != 0,
1341                            "%s: *** USB_REQ_SET_ADDRESS (%d)\n",
1342                            __func__, usb_ctrl->wValue);
1343                         if (usb_ctrl->bRequestType
1344                                 != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1345                                 break;
1346
1347                         udc_set_address(dev, usb_ctrl->wValue);
1348                         return;
1349
1350                 case USB_REQ_SET_CONFIGURATION:
1351                         debug_cond(DEBUG_SETUP != 0,
1352                                    "=====================================\n");
1353                         debug_cond(DEBUG_SETUP != 0,
1354                                    "%s: USB_REQ_SET_CONFIGURATION (%d)\n",
1355                                    __func__, usb_ctrl->wValue);
1356
1357                         if (usb_ctrl->bRequestType == USB_RECIP_DEVICE)
1358                                 reset_available = 1;
1359
1360                         break;
1361
1362                 case USB_REQ_GET_DESCRIPTOR:
1363                         debug_cond(DEBUG_SETUP != 0,
1364                                    "%s: *** USB_REQ_GET_DESCRIPTOR\n",
1365                                    __func__);
1366                         break;
1367
1368                 case USB_REQ_SET_INTERFACE:
1369                         debug_cond(DEBUG_SETUP != 0,
1370                                    "%s: *** USB_REQ_SET_INTERFACE (%d)\n",
1371                                    __func__, usb_ctrl->wValue);
1372
1373                         if (usb_ctrl->bRequestType == USB_RECIP_INTERFACE)
1374                                 reset_available = 1;
1375
1376                         break;
1377
1378                 case USB_REQ_GET_CONFIGURATION:
1379                         debug_cond(DEBUG_SETUP != 0,
1380                                    "%s: *** USB_REQ_GET_CONFIGURATION\n",
1381                                    __func__);
1382                         break;
1383
1384                 case USB_REQ_GET_STATUS:
1385                         if (!s3c_udc_get_status(dev, usb_ctrl))
1386                                 return;
1387
1388                         break;
1389
1390                 case USB_REQ_CLEAR_FEATURE:
1391                         ep_num = usb_ctrl->wIndex & 0x7f;
1392
1393                         if (!s3c_udc_clear_feature(&dev->ep[ep_num].ep))
1394                                 return;
1395
1396                         break;
1397
1398                 case USB_REQ_SET_FEATURE:
1399                         ep_num = usb_ctrl->wIndex & 0x7f;
1400
1401                         if (!s3c_udc_set_feature(&dev->ep[ep_num].ep))
1402                                 return;
1403
1404                         break;
1405
1406                 default:
1407                         debug_cond(DEBUG_SETUP != 0,
1408                                    "%s: *** Default of usb_ctrl->bRequest=0x%x"
1409                                    "happened.\n", __func__, usb_ctrl->bRequest);
1410                         break;
1411                 }
1412         }
1413
1414
1415         if (likely(dev->driver)) {
1416                 /* device-2-host (IN) or no data setup command,
1417                  * process immediately */
1418                 debug_cond(DEBUG_SETUP != 0,
1419                            "%s:usb_ctrlreq will be passed to fsg_setup()\n",
1420                             __func__);
1421
1422                 spin_unlock(&dev->lock);
1423                 i = dev->driver->setup(&dev->gadget, usb_ctrl);
1424                 spin_lock(&dev->lock);
1425
1426                 if (i < 0) {
1427                         /* setup processing failed, force stall */
1428                         s3c_udc_ep0_set_stall(ep);
1429                         dev->ep0state = WAIT_FOR_SETUP;
1430
1431                         debug_cond(DEBUG_SETUP != 0,
1432                                    "\tdev->driver->setup failed (%d),"
1433                                     " bRequest = %d\n",
1434                                 i, usb_ctrl->bRequest);
1435
1436
1437                 } else if (dev->req_pending) {
1438                         dev->req_pending = 0;
1439                         debug_cond(DEBUG_SETUP != 0,
1440                                    "\tdev->req_pending...\n");
1441                 }
1442
1443                 debug_cond(DEBUG_SETUP != 0,
1444                            "\tep0state = %s\n", state_names[dev->ep0state]);
1445
1446         }
1447 }
1448
1449 /*
1450  * handle ep0 interrupt
1451  */
1452 static void s3c_handle_ep0(struct s3c_udc *dev)
1453 {
1454         if (dev->ep0state == WAIT_FOR_SETUP) {
1455                 debug_cond(DEBUG_OUT_EP != 0,
1456                            "%s: WAIT_FOR_SETUP\n", __func__);
1457                 s3c_ep0_setup(dev);
1458
1459         } else {
1460                 debug_cond(DEBUG_OUT_EP != 0,
1461                            "%s: strange state!!(state = %s)\n",
1462                         __func__, state_names[dev->ep0state]);
1463         }
1464 }
1465
1466 static void s3c_ep0_kick(struct s3c_udc *dev, struct s3c_ep *ep)
1467 {
1468         debug_cond(DEBUG_EP0 != 0,
1469                    "%s: ep_is_in = %d\n", __func__, ep_is_in(ep));
1470         if (ep_is_in(ep)) {
1471                 dev->ep0state = DATA_STATE_XMIT;
1472                 s3c_ep0_write(dev);
1473
1474         } else {
1475                 dev->ep0state = DATA_STATE_RECV;
1476                 s3c_ep0_read(dev);
1477         }
1478 }