2 * drivers/usb/gadget/s3c_udc_otg_xfer_dma.c
3 * Samsung S3C on-chip full/high speed USB OTG 2.0 device controllers
5 * Copyright (C) 2009 for Samsung Electronics
7 * BSP Support for Samsung's UDC driver
9 * git://git.kernel.org/pub/scm/linux/kernel/git/kki_ap/linux-2.6-samsung.git
11 * State machine bugfixes:
12 * Marek Szyprowski <m.szyprowski@samsung.com>
15 * Marek Szyprowski <m.szyprowski@samsung.com>
16 * Lukasz Majewski <l.majewski@samsumg.com>
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 2 of the License, or
21 * (at your option) any later version.
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
34 static u8 clear_feature_num;
35 int clear_feature_flag;
37 /* Bulk-Only Mass Storage Reset (class-specific request) */
38 #define GET_MAX_LUN_REQUEST 0xFE
39 #define BOT_RESET_REQUEST 0xFF
41 static inline void s3c_udc_ep0_zlp(struct s3c_udc *dev)
45 flush_dcache_range((unsigned long) usb_ctrl_dma_addr,
46 (unsigned long) usb_ctrl_dma_addr
49 writel(usb_ctrl_dma_addr, ®->in_endp[EP0_CON].diepdma);
50 writel(DIEPT_SIZ_PKT_CNT(1), ®->in_endp[EP0_CON].dieptsiz);
52 ep_ctrl = readl(®->in_endp[EP0_CON].diepctl);
53 writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK,
54 ®->in_endp[EP0_CON].diepctl);
56 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
57 __func__, readl(®->in_endp[EP0_CON].diepctl));
58 dev->ep0state = WAIT_FOR_IN_COMPLETE;
61 void s3c_udc_pre_setup(void)
65 debug_cond(DEBUG_IN_EP,
66 "%s : Prepare Setup packets.\n", __func__);
68 invalidate_dcache_range((unsigned long) usb_ctrl_dma_addr,
69 (unsigned long) usb_ctrl_dma_addr
72 writel(DOEPT_SIZ_PKT_CNT(1) | sizeof(struct usb_ctrlrequest),
73 ®->out_endp[EP0_CON].doeptsiz);
74 writel(usb_ctrl_dma_addr, ®->out_endp[EP0_CON].doepdma);
76 ep_ctrl = readl(®->out_endp[EP0_CON].doepctl);
77 writel(ep_ctrl|DEPCTL_EPENA, ®->out_endp[EP0_CON].doepctl);
79 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
80 __func__, readl(®->in_endp[EP0_CON].diepctl));
81 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
82 __func__, readl(®->out_endp[EP0_CON].doepctl));
86 static inline void s3c_ep0_complete_out(void)
90 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
91 __func__, readl(®->in_endp[EP0_CON].diepctl));
92 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
93 __func__, readl(®->out_endp[EP0_CON].doepctl));
95 debug_cond(DEBUG_IN_EP,
96 "%s : Prepare Complete Out packet.\n", __func__);
98 invalidate_dcache_range((unsigned long) usb_ctrl_dma_addr,
99 (unsigned long) usb_ctrl_dma_addr
102 writel(DOEPT_SIZ_PKT_CNT(1) | sizeof(struct usb_ctrlrequest),
103 ®->out_endp[EP0_CON].doeptsiz);
104 writel(usb_ctrl_dma_addr, ®->out_endp[EP0_CON].doepdma);
106 ep_ctrl = readl(®->out_endp[EP0_CON].doepctl);
107 writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK,
108 ®->out_endp[EP0_CON].doepctl);
110 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
111 __func__, readl(®->in_endp[EP0_CON].diepctl));
112 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
113 __func__, readl(®->out_endp[EP0_CON].doepctl));
118 static int setdma_rx(struct s3c_ep *ep, struct s3c_request *req)
122 u32 ep_num = ep_index(ep);
124 buf = req->req.buf + req->req.actual;
126 length = min(req->req.length - req->req.actual, (int)ep->ep.maxpacket);
131 invalidate_dcache_range((unsigned long) ep->dev->dma_buf[ep_num],
132 (unsigned long) ep->dev->dma_buf[ep_num]
138 pktcnt = (length - 1)/(ep->ep.maxpacket) + 1;
141 ctrl = readl(®->out_endp[ep_num].doepctl);
143 writel(the_controller->dma_addr[ep_index(ep)+1],
144 ®->out_endp[ep_num].doepdma);
145 writel(DOEPT_SIZ_PKT_CNT(pktcnt) | DOEPT_SIZ_XFER_SIZE(length),
146 ®->out_endp[ep_num].doeptsiz);
147 writel(DEPCTL_EPENA|DEPCTL_CNAK|ctrl, ®->out_endp[ep_num].doepctl);
149 debug_cond(DEBUG_OUT_EP != 0,
150 "%s: EP%d RX DMA start : DOEPDMA = 0x%x,"
151 "DOEPTSIZ = 0x%x, DOEPCTL = 0x%x\n"
152 "\tbuf = 0x%p, pktcnt = %d, xfersize = %d\n",
154 readl(®->out_endp[ep_num].doepdma),
155 readl(®->out_endp[ep_num].doeptsiz),
156 readl(®->out_endp[ep_num].doepctl),
157 buf, pktcnt, length);
162 int setdma_tx(struct s3c_ep *ep, struct s3c_request *req)
166 u32 ep_num = ep_index(ep);
167 u32 *p = the_controller->dma_buf[ep_index(ep)+1];
169 buf = req->req.buf + req->req.actual;
170 length = req->req.length - req->req.actual;
172 if (ep_num == EP0_CON)
173 length = min(length, (u32)ep_maxpacket(ep));
177 memcpy(p, ep->dma_buf, length);
179 flush_dcache_range((unsigned long) p ,
180 (unsigned long) p + DMA_BUFFER_SIZE);
185 pktcnt = (length - 1)/(ep->ep.maxpacket) + 1;
187 /* Flush the endpoint's Tx FIFO */
188 writel(TX_FIFO_NUMBER(ep->fifo_num), ®->grstctl);
189 writel(TX_FIFO_NUMBER(ep->fifo_num) | TX_FIFO_FLUSH, ®->grstctl);
190 while (readl(®->grstctl) & TX_FIFO_FLUSH)
193 writel(the_controller->dma_addr[ep_index(ep)+1],
194 ®->in_endp[ep_num].diepdma);
195 writel(DIEPT_SIZ_PKT_CNT(pktcnt) | DIEPT_SIZ_XFER_SIZE(length),
196 ®->in_endp[ep_num].dieptsiz);
198 ctrl = readl(®->in_endp[ep_num].diepctl);
200 /* Write the FIFO number to be used for this endpoint */
201 ctrl &= DIEPCTL_TX_FIFO_NUM_MASK;
202 ctrl |= DIEPCTL_TX_FIFO_NUM(ep->fifo_num);
204 /* Clear reserved (Next EP) bits */
205 ctrl = (ctrl&~(EP_MASK<<DEPCTL_NEXT_EP_BIT));
207 writel(DEPCTL_EPENA|DEPCTL_CNAK|ctrl, ®->in_endp[ep_num].diepctl);
209 debug_cond(DEBUG_IN_EP,
210 "%s:EP%d TX DMA start : DIEPDMA0 = 0x%x,"
211 "DIEPTSIZ0 = 0x%x, DIEPCTL0 = 0x%x\n"
212 "\tbuf = 0x%p, pktcnt = %d, xfersize = %d\n",
214 readl(®->in_endp[ep_num].diepdma),
215 readl(®->in_endp[ep_num].dieptsiz),
216 readl(®->in_endp[ep_num].diepctl),
217 buf, pktcnt, length);
222 static void complete_rx(struct s3c_udc *dev, u8 ep_num)
224 struct s3c_ep *ep = &dev->ep[ep_num];
225 struct s3c_request *req = NULL;
226 u32 ep_tsr = 0, xfer_size = 0, is_short = 0;
227 u32 *p = the_controller->dma_buf[ep_index(ep)+1];
229 if (list_empty(&ep->queue)) {
230 debug_cond(DEBUG_OUT_EP != 0,
231 "%s: RX DMA done : NULL REQ on OUT EP-%d\n",
237 req = list_entry(ep->queue.next, struct s3c_request, queue);
238 ep_tsr = readl(®->out_endp[ep_num].doeptsiz);
240 if (ep_num == EP0_CON)
241 xfer_size = (ep_tsr & DOEPT_SIZ_XFER_SIZE_MAX_EP0);
243 xfer_size = (ep_tsr & DOEPT_SIZ_XFER_SIZE_MAX_EP);
245 xfer_size = ep->len - xfer_size;
247 invalidate_dcache_range((unsigned long) p,
248 (unsigned long) p + DMA_BUFFER_SIZE);
250 memcpy(ep->dma_buf, p, ep->len);
252 req->req.actual += min(xfer_size, req->req.length - req->req.actual);
253 is_short = (xfer_size < ep->ep.maxpacket);
255 debug_cond(DEBUG_OUT_EP != 0,
256 "%s: RX DMA done : ep = %d, rx bytes = %d/%d, "
257 "is_short = %d, DOEPTSIZ = 0x%x, remained bytes = %d\n",
258 __func__, ep_num, req->req.actual, req->req.length,
259 is_short, ep_tsr, xfer_size);
261 if (is_short || req->req.actual == req->req.length) {
262 if (ep_num == EP0_CON && dev->ep0state == DATA_STATE_RECV) {
263 debug_cond(DEBUG_OUT_EP != 0, " => Send ZLP\n");
264 s3c_udc_ep0_zlp(dev);
265 /* packet will be completed in complete_tx() */
266 dev->ep0state = WAIT_FOR_IN_COMPLETE;
270 if (!list_empty(&ep->queue)) {
271 req = list_entry(ep->queue.next,
272 struct s3c_request, queue);
273 debug_cond(DEBUG_OUT_EP != 0,
274 "%s: Next Rx request start...\n",
283 static void complete_tx(struct s3c_udc *dev, u8 ep_num)
285 struct s3c_ep *ep = &dev->ep[ep_num];
286 struct s3c_request *req;
287 u32 ep_tsr = 0, xfer_size = 0, is_short = 0;
290 if (dev->ep0state == WAIT_FOR_NULL_COMPLETE) {
291 dev->ep0state = WAIT_FOR_OUT_COMPLETE;
292 s3c_ep0_complete_out();
296 if (list_empty(&ep->queue)) {
297 debug_cond(DEBUG_IN_EP,
298 "%s: TX DMA done : NULL REQ on IN EP-%d\n",
304 req = list_entry(ep->queue.next, struct s3c_request, queue);
306 ep_tsr = readl(®->in_endp[ep_num].dieptsiz);
309 is_short = (xfer_size < ep->ep.maxpacket);
310 req->req.actual += min(xfer_size, req->req.length - req->req.actual);
312 debug_cond(DEBUG_IN_EP,
313 "%s: TX DMA done : ep = %d, tx bytes = %d/%d, "
314 "is_short = %d, DIEPTSIZ = 0x%x, remained bytes = %d\n",
315 __func__, ep_num, req->req.actual, req->req.length,
316 is_short, ep_tsr, xfer_size);
319 if (dev->ep0state == DATA_STATE_XMIT) {
320 debug_cond(DEBUG_IN_EP,
321 "%s: ep_num = %d, ep0stat =="
324 last = write_fifo_ep0(ep, req);
326 dev->ep0state = WAIT_FOR_COMPLETE;
327 } else if (dev->ep0state == WAIT_FOR_IN_COMPLETE) {
328 debug_cond(DEBUG_IN_EP,
329 "%s: ep_num = %d, completing request\n",
332 dev->ep0state = WAIT_FOR_SETUP;
333 } else if (dev->ep0state == WAIT_FOR_COMPLETE) {
334 debug_cond(DEBUG_IN_EP,
335 "%s: ep_num = %d, completing request\n",
338 dev->ep0state = WAIT_FOR_OUT_COMPLETE;
339 s3c_ep0_complete_out();
341 debug_cond(DEBUG_IN_EP,
342 "%s: ep_num = %d, invalid ep state\n",
348 if (req->req.actual == req->req.length)
351 if (!list_empty(&ep->queue)) {
352 req = list_entry(ep->queue.next, struct s3c_request, queue);
353 debug_cond(DEBUG_IN_EP,
354 "%s: Next Tx request start...\n", __func__);
359 static inline void s3c_udc_check_tx_queue(struct s3c_udc *dev, u8 ep_num)
361 struct s3c_ep *ep = &dev->ep[ep_num];
362 struct s3c_request *req;
364 debug_cond(DEBUG_IN_EP,
365 "%s: Check queue, ep_num = %d\n", __func__, ep_num);
367 if (!list_empty(&ep->queue)) {
368 req = list_entry(ep->queue.next, struct s3c_request, queue);
369 debug_cond(DEBUG_IN_EP,
370 "%s: Next Tx request(0x%p) start...\n",
378 debug_cond(DEBUG_IN_EP,
379 "%s: NULL REQ on IN EP-%d\n", __func__, ep_num);
386 static void process_ep_in_intr(struct s3c_udc *dev)
388 u32 ep_intr, ep_intr_status;
391 ep_intr = readl(®->daint);
392 debug_cond(DEBUG_IN_EP,
393 "*** %s: EP In interrupt : DAINT = 0x%x\n", __func__, ep_intr);
395 ep_intr &= DAINT_MASK;
398 if (ep_intr & DAINT_IN_EP_INT(1)) {
399 ep_intr_status = readl(®->in_endp[ep_num].diepint);
400 debug_cond(DEBUG_IN_EP,
401 "\tEP%d-IN : DIEPINT = 0x%x\n",
402 ep_num, ep_intr_status);
404 /* Interrupt Clear */
405 writel(ep_intr_status, ®->in_endp[ep_num].diepint);
407 if (ep_intr_status & TRANSFER_DONE) {
408 complete_tx(dev, ep_num);
412 WAIT_FOR_IN_COMPLETE)
413 dev->ep0state = WAIT_FOR_SETUP;
415 if (dev->ep0state == WAIT_FOR_SETUP)
418 /* continue transfer after
419 set_clear_halt for DMA mode */
420 if (clear_feature_flag == 1) {
421 s3c_udc_check_tx_queue(dev,
423 clear_feature_flag = 0;
433 static void process_ep_out_intr(struct s3c_udc *dev)
435 u32 ep_intr, ep_intr_status;
438 ep_intr = readl(®->daint);
439 debug_cond(DEBUG_OUT_EP != 0,
440 "*** %s: EP OUT interrupt : DAINT = 0x%x\n",
443 ep_intr = (ep_intr >> DAINT_OUT_BIT) & DAINT_MASK;
447 ep_intr_status = readl(®->out_endp[ep_num].doepint);
448 debug_cond(DEBUG_OUT_EP != 0,
449 "\tEP%d-OUT : DOEPINT = 0x%x\n",
450 ep_num, ep_intr_status);
452 /* Interrupt Clear */
453 writel(ep_intr_status, ®->out_endp[ep_num].doepint);
456 if (ep_intr_status & TRANSFER_DONE) {
458 WAIT_FOR_OUT_COMPLETE)
459 complete_rx(dev, ep_num);
461 dev->ep0state = WAIT_FOR_SETUP;
467 CTRL_OUT_EP_SETUP_PHASE_DONE) {
468 debug_cond(DEBUG_OUT_EP != 0,
469 "SETUP packet arrived\n");
473 if (ep_intr_status & TRANSFER_DONE)
474 complete_rx(dev, ep_num);
483 * usb client interrupt handler.
485 static int s3c_udc_irq(int irq, void *_dev)
487 struct s3c_udc *dev = _dev;
489 u32 usb_status, gintmsk;
492 spin_lock_irqsave(&dev->lock, flags);
494 intr_status = readl(®->gintsts);
495 gintmsk = readl(®->gintmsk);
497 debug_cond(DEBUG_ISR,
498 "\n*** %s : GINTSTS=0x%x(on state %s), GINTMSK : 0x%x,"
499 "DAINT : 0x%x, DAINTMSK : 0x%x\n",
500 __func__, intr_status, state_names[dev->ep0state], gintmsk,
501 readl(®->daint), readl(®->daintmsk));
504 spin_unlock_irqrestore(&dev->lock, flags);
508 if (intr_status & INT_ENUMDONE) {
509 debug_cond(DEBUG_ISR, "\tSpeed Detection interrupt\n");
511 writel(INT_ENUMDONE, ®->gintsts);
512 usb_status = (readl(®->dsts) & 0x6);
514 if (usb_status & (USB_FULL_30_60MHZ | USB_FULL_48MHZ)) {
515 debug_cond(DEBUG_ISR,
516 "\t\tFull Speed Detection\n");
517 set_max_pktsize(dev, USB_SPEED_FULL);
520 debug_cond(DEBUG_ISR,
521 "\t\tHigh Speed Detection : 0x%x\n",
523 set_max_pktsize(dev, USB_SPEED_HIGH);
527 if (intr_status & INT_EARLY_SUSPEND) {
528 debug_cond(DEBUG_ISR, "\tEarly suspend interrupt\n");
529 writel(INT_EARLY_SUSPEND, ®->gintsts);
532 if (intr_status & INT_SUSPEND) {
533 usb_status = readl(®->dsts);
534 debug_cond(DEBUG_ISR,
535 "\tSuspend interrupt :(DSTS):0x%x\n", usb_status);
536 writel(INT_SUSPEND, ®->gintsts);
538 if (dev->gadget.speed != USB_SPEED_UNKNOWN
540 if (dev->driver->suspend)
541 dev->driver->suspend(&dev->gadget);
543 /* HACK to let gadget detect disconnected state */
544 if (dev->driver->disconnect) {
545 spin_unlock_irqrestore(&dev->lock, flags);
546 dev->driver->disconnect(&dev->gadget);
547 spin_lock_irqsave(&dev->lock, flags);
552 if (intr_status & INT_RESUME) {
553 debug_cond(DEBUG_ISR, "\tResume interrupt\n");
554 writel(INT_RESUME, ®->gintsts);
556 if (dev->gadget.speed != USB_SPEED_UNKNOWN
558 && dev->driver->resume) {
560 dev->driver->resume(&dev->gadget);
564 if (intr_status & INT_RESET) {
565 usb_status = readl(®->gotgctl);
566 debug_cond(DEBUG_ISR,
567 "\tReset interrupt - (GOTGCTL):0x%x\n", usb_status);
568 writel(INT_RESET, ®->gintsts);
570 if ((usb_status & 0xc0000) == (0x3 << 18)) {
571 if (reset_available) {
572 debug_cond(DEBUG_ISR,
573 "\t\tOTG core got reset (%d)!!\n",
576 dev->ep0state = WAIT_FOR_SETUP;
584 debug_cond(DEBUG_ISR,
585 "\t\tRESET handling skipped\n");
589 if (intr_status & INT_IN_EP)
590 process_ep_in_intr(dev);
592 if (intr_status & INT_OUT_EP)
593 process_ep_out_intr(dev);
595 spin_unlock_irqrestore(&dev->lock, flags);
600 /** Queue one request
601 * Kickstart transfer if needed
603 static int s3c_queue(struct usb_ep *_ep, struct usb_request *_req,
606 struct s3c_request *req;
612 req = container_of(_req, struct s3c_request, req);
613 if (unlikely(!_req || !_req->complete || !_req->buf
614 || !list_empty(&req->queue))) {
616 debug("%s: bad params\n", __func__);
620 ep = container_of(_ep, struct s3c_ep, ep);
622 if (unlikely(!_ep || (!ep->desc && ep->ep.name != ep0name))) {
624 debug("%s: bad ep: %s, %d, %p\n", __func__,
625 ep->ep.name, !ep->desc, _ep);
629 ep_num = ep_index(ep);
631 if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
633 debug("%s: bogus device state %p\n", __func__, dev->driver);
637 spin_lock_irqsave(&dev->lock, flags);
639 _req->status = -EINPROGRESS;
642 /* kickstart this i/o queue? */
643 debug("\n*** %s: %s-%s req = %p, len = %d, buf = %p"
644 "Q empty = %d, stopped = %d\n",
645 __func__, _ep->name, ep_is_in(ep) ? "in" : "out",
646 _req, _req->length, _req->buf,
647 list_empty(&ep->queue), ep->stopped);
651 int i, len = _req->length;
656 for (i = 0; i < len; i++) {
657 printf("%02x", ((u8 *)_req->buf)[i]);
665 if (list_empty(&ep->queue) && !ep->stopped) {
669 list_add_tail(&req->queue, &ep->queue);
670 s3c_ep0_kick(dev, ep);
673 } else if (ep_is_in(ep)) {
674 gintsts = readl(®->gintsts);
675 debug_cond(DEBUG_IN_EP,
676 "%s: ep_is_in, S3C_UDC_OTG_GINTSTS=0x%x\n",
681 gintsts = readl(®->gintsts);
682 debug_cond(DEBUG_OUT_EP != 0,
683 "%s:ep_is_out, S3C_UDC_OTG_GINTSTS=0x%x\n",
690 /* pio or dma irq handler advances the queue. */
691 if (likely(req != 0))
692 list_add_tail(&req->queue, &ep->queue);
694 spin_unlock_irqrestore(&dev->lock, flags);
699 /****************************************************************/
700 /* End Point 0 related functions */
701 /****************************************************************/
703 /* return: 0 = still running, 1 = completed, negative = errno */
704 static int write_fifo_ep0(struct s3c_ep *ep, struct s3c_request *req)
710 max = ep_maxpacket(ep);
712 debug_cond(DEBUG_EP0 != 0, "%s: max = %d\n", __func__, max);
714 count = setdma_tx(ep, req);
716 /* last packet is usually short (or a zlp) */
717 if (likely(count != max))
720 if (likely(req->req.length != req->req.actual + count)
727 debug_cond(DEBUG_EP0 != 0,
728 "%s: wrote %s %d bytes%s %d left %p\n", __func__,
731 req->req.length - req->req.actual - count, req);
733 /* requests complete when all IN data is in the FIFO */
735 ep->dev->ep0state = WAIT_FOR_SETUP;
742 int s3c_fifo_read(struct s3c_ep *ep, u32 *cp, int max)
746 bytes = sizeof(struct usb_ctrlrequest);
748 invalidate_dcache_range((unsigned long) ep->dev->dma_buf[ep_index(ep)],
749 (unsigned long) ep->dev->dma_buf[ep_index(ep)]
752 debug_cond(DEBUG_EP0 != 0,
753 "%s: bytes=%d, ep_index=%d %p\n", __func__,
754 bytes, ep_index(ep), ep->dev->dma_buf[ep_index(ep)]);
760 * udc_set_address - set the USB address for this device
763 * Called from control endpoint function
764 * after it decodes a set address setup packet.
766 static void udc_set_address(struct s3c_udc *dev, unsigned char address)
768 u32 ctrl = readl(®->dcfg);
769 writel(DEVICE_ADDRESS(address) | ctrl, ®->dcfg);
771 s3c_udc_ep0_zlp(dev);
773 debug_cond(DEBUG_EP0 != 0,
774 "%s: USB OTG 2.0 Device address=%d, DCFG=0x%x\n",
775 __func__, address, readl(®->dcfg));
777 dev->usb_address = address;
780 static inline void s3c_udc_ep0_set_stall(struct s3c_ep *ep)
786 ep_ctrl = readl(®->in_endp[EP0_CON].diepctl);
788 /* set the disable and stall bits */
789 if (ep_ctrl & DEPCTL_EPENA)
790 ep_ctrl |= DEPCTL_EPDIS;
792 ep_ctrl |= DEPCTL_STALL;
794 writel(ep_ctrl, ®->in_endp[EP0_CON].diepctl);
796 debug_cond(DEBUG_EP0 != 0,
797 "%s: set ep%d stall, DIEPCTL0 = 0x%p\n",
798 __func__, ep_index(ep), ®->in_endp[EP0_CON].diepctl);
800 * The application can only set this bit, and the core clears it,
801 * when a SETUP token is received for this endpoint
803 dev->ep0state = WAIT_FOR_SETUP;
808 static void s3c_ep0_read(struct s3c_udc *dev)
810 struct s3c_request *req;
811 struct s3c_ep *ep = &dev->ep[0];
813 if (!list_empty(&ep->queue)) {
814 req = list_entry(ep->queue.next, struct s3c_request, queue);
817 debug("%s: ---> BUG\n", __func__);
822 debug_cond(DEBUG_EP0 != 0,
823 "%s: req = %p, req.length = 0x%x, req.actual = 0x%x\n",
824 __func__, req, req->req.length, req->req.actual);
826 if (req->req.length == 0) {
827 /* zlp for Set_configuration, Set_interface,
828 * or Bulk-Only mass storge reset */
831 s3c_udc_ep0_zlp(dev);
833 debug_cond(DEBUG_EP0 != 0,
834 "%s: req.length = 0, bRequest = %d\n",
835 __func__, usb_ctrl->bRequest);
845 static int s3c_ep0_write(struct s3c_udc *dev)
847 struct s3c_request *req;
848 struct s3c_ep *ep = &dev->ep[0];
849 int ret, need_zlp = 0;
851 if (list_empty(&ep->queue))
854 req = list_entry(ep->queue.next, struct s3c_request, queue);
857 debug_cond(DEBUG_EP0 != 0, "%s: NULL REQ\n", __func__);
861 debug_cond(DEBUG_EP0 != 0,
862 "%s: req = %p, req.length = 0x%x, req.actual = 0x%x\n",
863 __func__, req, req->req.length, req->req.actual);
865 if (req->req.length - req->req.actual == ep0_fifo_size) {
866 /* Next write will end with the packet size, */
867 /* so we need Zero-length-packet */
871 ret = write_fifo_ep0(ep, req);
873 if ((ret == 1) && !need_zlp) {
875 dev->ep0state = WAIT_FOR_COMPLETE;
876 debug_cond(DEBUG_EP0 != 0,
877 "%s: finished, waiting for status\n", __func__);
880 dev->ep0state = DATA_STATE_XMIT;
881 debug_cond(DEBUG_EP0 != 0,
882 "%s: not finished\n", __func__);
890 int s3c_udc_get_status(struct s3c_udc *dev,
891 struct usb_ctrlrequest *crq)
893 u8 ep_num = crq->wIndex & 0x7F;
895 u32 *p = the_controller->dma_buf[1];
897 debug_cond(DEBUG_SETUP != 0,
898 "%s: *** USB_REQ_GET_STATUS\n", __func__);
899 printf("crq->brequest:0x%x\n", crq->bRequestType & USB_RECIP_MASK);
900 switch (crq->bRequestType & USB_RECIP_MASK) {
901 case USB_RECIP_INTERFACE:
903 debug_cond(DEBUG_SETUP != 0,
904 "\tGET_STATUS:USB_RECIP_INTERFACE, g_stauts = %d\n",
908 case USB_RECIP_DEVICE:
909 g_status = 0x1; /* Self powered */
910 debug_cond(DEBUG_SETUP != 0,
911 "\tGET_STATUS: USB_RECIP_DEVICE, g_stauts = %d\n",
915 case USB_RECIP_ENDPOINT:
916 if (crq->wLength > 2) {
917 debug_cond(DEBUG_SETUP != 0,
918 "\tGET_STATUS:Not support EP or wLength\n");
922 g_status = dev->ep[ep_num].stopped;
923 debug_cond(DEBUG_SETUP != 0,
924 "\tGET_STATUS: USB_RECIP_ENDPOINT, g_stauts = %d\n",
933 memcpy(p, &g_status, sizeof(g_status));
935 flush_dcache_range((unsigned long) p,
936 (unsigned long) p + DMA_BUFFER_SIZE);
938 writel(the_controller->dma_addr[1], ®->in_endp[EP0_CON].diepdma);
939 writel(DIEPT_SIZ_PKT_CNT(1) | DIEPT_SIZ_XFER_SIZE(2),
940 ®->in_endp[EP0_CON].dieptsiz);
942 ep_ctrl = readl(®->in_endp[EP0_CON].diepctl);
943 writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK,
944 ®->in_endp[EP0_CON].diepctl);
945 dev->ep0state = WAIT_FOR_NULL_COMPLETE;
950 static void s3c_udc_set_nak(struct s3c_ep *ep)
955 ep_num = ep_index(ep);
956 debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type);
959 ep_ctrl = readl(®->in_endp[ep_num].diepctl);
960 ep_ctrl |= DEPCTL_SNAK;
961 writel(ep_ctrl, ®->in_endp[ep_num].diepctl);
962 debug("%s: set NAK, DIEPCTL%d = 0x%x\n",
963 __func__, ep_num, readl(®->in_endp[ep_num].diepctl));
965 ep_ctrl = readl(®->out_endp[ep_num].doepctl);
966 ep_ctrl |= DEPCTL_SNAK;
967 writel(ep_ctrl, ®->out_endp[ep_num].doepctl);
968 debug("%s: set NAK, DOEPCTL%d = 0x%x\n",
969 __func__, ep_num, readl(®->out_endp[ep_num].doepctl));
976 void s3c_udc_ep_set_stall(struct s3c_ep *ep)
981 ep_num = ep_index(ep);
982 debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type);
985 ep_ctrl = readl(®->in_endp[ep_num].diepctl);
987 /* set the disable and stall bits */
988 if (ep_ctrl & DEPCTL_EPENA)
989 ep_ctrl |= DEPCTL_EPDIS;
991 ep_ctrl |= DEPCTL_STALL;
993 writel(ep_ctrl, ®->in_endp[ep_num].diepctl);
994 debug("%s: set stall, DIEPCTL%d = 0x%x\n",
995 __func__, ep_num, readl(®->in_endp[ep_num].diepctl));
998 ep_ctrl = readl(®->out_endp[ep_num].doepctl);
1000 /* set the stall bit */
1001 ep_ctrl |= DEPCTL_STALL;
1003 writel(ep_ctrl, ®->out_endp[ep_num].doepctl);
1004 debug("%s: set stall, DOEPCTL%d = 0x%x\n",
1005 __func__, ep_num, readl(®->out_endp[ep_num].doepctl));
1011 void s3c_udc_ep_clear_stall(struct s3c_ep *ep)
1016 ep_num = ep_index(ep);
1017 debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type);
1020 ep_ctrl = readl(®->in_endp[ep_num].diepctl);
1022 /* clear stall bit */
1023 ep_ctrl &= ~DEPCTL_STALL;
1026 * USB Spec 9.4.5: For endpoints using data toggle, regardless
1027 * of whether an endpoint has the Halt feature set, a
1028 * ClearFeature(ENDPOINT_HALT) request always results in the
1029 * data toggle being reinitialized to DATA0.
1031 if (ep->bmAttributes == USB_ENDPOINT_XFER_INT
1032 || ep->bmAttributes == USB_ENDPOINT_XFER_BULK) {
1033 ep_ctrl |= DEPCTL_SETD0PID; /* DATA0 */
1036 writel(ep_ctrl, ®->in_endp[ep_num].diepctl);
1037 debug("%s: cleared stall, DIEPCTL%d = 0x%x\n",
1038 __func__, ep_num, readl(®->in_endp[ep_num].diepctl));
1041 ep_ctrl = readl(®->out_endp[ep_num].doepctl);
1043 /* clear stall bit */
1044 ep_ctrl &= ~DEPCTL_STALL;
1046 if (ep->bmAttributes == USB_ENDPOINT_XFER_INT
1047 || ep->bmAttributes == USB_ENDPOINT_XFER_BULK) {
1048 ep_ctrl |= DEPCTL_SETD0PID; /* DATA0 */
1051 writel(ep_ctrl, ®->out_endp[ep_num].doepctl);
1052 debug("%s: cleared stall, DOEPCTL%d = 0x%x\n",
1053 __func__, ep_num, readl(®->out_endp[ep_num].doepctl));
1059 static int s3c_udc_set_halt(struct usb_ep *_ep, int value)
1062 struct s3c_udc *dev;
1063 unsigned long flags;
1066 ep = container_of(_ep, struct s3c_ep, ep);
1067 ep_num = ep_index(ep);
1069 if (unlikely(!_ep || !ep->desc || ep_num == EP0_CON ||
1070 ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC)) {
1071 debug("%s: %s bad ep or descriptor\n", __func__, ep->ep.name);
1075 /* Attempt to halt IN ep will fail if any transfer requests
1076 * are still queue */
1077 if (value && ep_is_in(ep) && !list_empty(&ep->queue)) {
1078 debug("%s: %s queue not empty, req = %p\n",
1079 __func__, ep->ep.name,
1080 list_entry(ep->queue.next, struct s3c_request, queue));
1086 debug("%s: ep_num = %d, value = %d\n", __func__, ep_num, value);
1088 spin_lock_irqsave(&dev->lock, flags);
1092 s3c_udc_ep_clear_stall(ep);
1095 dev->ep0state = WAIT_FOR_SETUP;
1098 s3c_udc_ep_set_stall(ep);
1101 spin_unlock_irqrestore(&dev->lock, flags);
1106 void s3c_udc_ep_activate(struct s3c_ep *ep)
1109 u32 ep_ctrl = 0, daintmsk = 0;
1111 ep_num = ep_index(ep);
1113 /* Read DEPCTLn register */
1115 ep_ctrl = readl(®->in_endp[ep_num].diepctl);
1116 daintmsk = 1 << ep_num;
1118 ep_ctrl = readl(®->out_endp[ep_num].doepctl);
1119 daintmsk = (1 << ep_num) << DAINT_OUT_BIT;
1122 debug("%s: EPCTRL%d = 0x%x, ep_is_in = %d\n",
1123 __func__, ep_num, ep_ctrl, ep_is_in(ep));
1125 /* If the EP is already active don't change the EP Control
1127 if (!(ep_ctrl & DEPCTL_USBACTEP)) {
1128 ep_ctrl = (ep_ctrl & ~DEPCTL_TYPE_MASK) |
1129 (ep->bmAttributes << DEPCTL_TYPE_BIT);
1130 ep_ctrl = (ep_ctrl & ~DEPCTL_MPS_MASK) |
1131 (ep->ep.maxpacket << DEPCTL_MPS_BIT);
1132 ep_ctrl |= (DEPCTL_SETD0PID | DEPCTL_USBACTEP | DEPCTL_SNAK);
1135 writel(ep_ctrl, ®->in_endp[ep_num].diepctl);
1136 debug("%s: USB Ative EP%d, DIEPCTRL%d = 0x%x\n",
1137 __func__, ep_num, ep_num,
1138 readl(®->in_endp[ep_num].diepctl));
1140 writel(ep_ctrl, ®->out_endp[ep_num].doepctl);
1141 debug("%s: USB Ative EP%d, DOEPCTRL%d = 0x%x\n",
1142 __func__, ep_num, ep_num,
1143 readl(®->out_endp[ep_num].doepctl));
1147 /* Unmask EP Interrtupt */
1148 writel(readl(®->daintmsk)|daintmsk, ®->daintmsk);
1149 debug("%s: DAINTMSK = 0x%x\n", __func__, readl(®->daintmsk));
1153 static int s3c_udc_clear_feature(struct usb_ep *_ep)
1155 struct s3c_udc *dev;
1159 ep = container_of(_ep, struct s3c_ep, ep);
1160 ep_num = ep_index(ep);
1163 debug_cond(DEBUG_SETUP != 0,
1164 "%s: ep_num = %d, is_in = %d, clear_feature_flag = %d\n",
1165 __func__, ep_num, ep_is_in(ep), clear_feature_flag);
1167 if (usb_ctrl->wLength != 0) {
1168 debug_cond(DEBUG_SETUP != 0,
1169 "\tCLEAR_FEATURE: wLength is not zero.....\n");
1173 switch (usb_ctrl->bRequestType & USB_RECIP_MASK) {
1174 case USB_RECIP_DEVICE:
1175 switch (usb_ctrl->wValue) {
1176 case USB_DEVICE_REMOTE_WAKEUP:
1177 debug_cond(DEBUG_SETUP != 0,
1178 "\tOFF:USB_DEVICE_REMOTE_WAKEUP\n");
1181 case USB_DEVICE_TEST_MODE:
1182 debug_cond(DEBUG_SETUP != 0,
1183 "\tCLEAR_FEATURE: USB_DEVICE_TEST_MODE\n");
1184 /** @todo Add CLEAR_FEATURE for TEST modes. */
1188 s3c_udc_ep0_zlp(dev);
1191 case USB_RECIP_ENDPOINT:
1192 debug_cond(DEBUG_SETUP != 0,
1193 "\tCLEAR_FEATURE:USB_RECIP_ENDPOINT, wValue = %d\n",
1196 if (usb_ctrl->wValue == USB_ENDPOINT_HALT) {
1198 s3c_udc_ep0_set_stall(ep);
1202 s3c_udc_ep0_zlp(dev);
1204 s3c_udc_ep_clear_stall(ep);
1205 s3c_udc_ep_activate(ep);
1208 clear_feature_num = ep_num;
1209 clear_feature_flag = 1;
1217 static int s3c_udc_set_feature(struct usb_ep *_ep)
1219 struct s3c_udc *dev;
1223 ep = container_of(_ep, struct s3c_ep, ep);
1224 ep_num = ep_index(ep);
1227 debug_cond(DEBUG_SETUP != 0,
1228 "%s: *** USB_REQ_SET_FEATURE , ep_num = %d\n",
1231 if (usb_ctrl->wLength != 0) {
1232 debug_cond(DEBUG_SETUP != 0,
1233 "\tSET_FEATURE: wLength is not zero.....\n");
1237 switch (usb_ctrl->bRequestType & USB_RECIP_MASK) {
1238 case USB_RECIP_DEVICE:
1239 switch (usb_ctrl->wValue) {
1240 case USB_DEVICE_REMOTE_WAKEUP:
1241 debug_cond(DEBUG_SETUP != 0,
1242 "\tSET_FEATURE:USB_DEVICE_REMOTE_WAKEUP\n");
1244 case USB_DEVICE_B_HNP_ENABLE:
1245 debug_cond(DEBUG_SETUP != 0,
1246 "\tSET_FEATURE: USB_DEVICE_B_HNP_ENABLE\n");
1249 case USB_DEVICE_A_HNP_SUPPORT:
1250 /* RH port supports HNP */
1251 debug_cond(DEBUG_SETUP != 0,
1252 "\tSET_FEATURE:USB_DEVICE_A_HNP_SUPPORT\n");
1255 case USB_DEVICE_A_ALT_HNP_SUPPORT:
1256 /* other RH port does */
1257 debug_cond(DEBUG_SETUP != 0,
1258 "\tSET: USB_DEVICE_A_ALT_HNP_SUPPORT\n");
1262 s3c_udc_ep0_zlp(dev);
1265 case USB_RECIP_INTERFACE:
1266 debug_cond(DEBUG_SETUP != 0,
1267 "\tSET_FEATURE: USB_RECIP_INTERFACE\n");
1270 case USB_RECIP_ENDPOINT:
1271 debug_cond(DEBUG_SETUP != 0,
1272 "\tSET_FEATURE: USB_RECIP_ENDPOINT\n");
1273 if (usb_ctrl->wValue == USB_ENDPOINT_HALT) {
1275 s3c_udc_ep0_set_stall(ep);
1279 s3c_udc_ep_set_stall(ep);
1282 s3c_udc_ep0_zlp(dev);
1290 * WAIT_FOR_SETUP (OUT_PKT_RDY)
1292 void s3c_ep0_setup(struct s3c_udc *dev)
1294 struct s3c_ep *ep = &dev->ep[0];
1298 /* Nuke all previous transfers */
1301 /* read control req from fifo (8 bytes) */
1302 s3c_fifo_read(ep, (u32 *)usb_ctrl, 8);
1304 debug_cond(DEBUG_SETUP != 0,
1305 "%s: bRequestType = 0x%x(%s), bRequest = 0x%x"
1306 "\twLength = 0x%x, wValue = 0x%x, wIndex= 0x%x\n",
1307 __func__, usb_ctrl->bRequestType,
1308 (usb_ctrl->bRequestType & USB_DIR_IN) ? "IN" : "OUT",
1310 usb_ctrl->wLength, usb_ctrl->wValue, usb_ctrl->wIndex);
1314 int i, len = sizeof(*usb_ctrl);
1315 char *p = (char *)usb_ctrl;
1318 for (i = 0; i < len; i++) {
1319 printf("%02x", ((u8 *)p)[i]);
1327 if (usb_ctrl->bRequest == GET_MAX_LUN_REQUEST &&
1328 usb_ctrl->wLength != 1) {
1329 debug_cond(DEBUG_SETUP != 0,
1330 "\t%s:GET_MAX_LUN_REQUEST:invalid",
1332 debug_cond(DEBUG_SETUP != 0,
1333 "wLength = %d, setup returned\n",
1336 s3c_udc_ep0_set_stall(ep);
1337 dev->ep0state = WAIT_FOR_SETUP;
1340 } else if (usb_ctrl->bRequest == BOT_RESET_REQUEST &&
1341 usb_ctrl->wLength != 0) {
1342 /* Bulk-Only *mass storge reset of class-specific request */
1343 debug_cond(DEBUG_SETUP != 0,
1344 "%s:BOT Rest:invalid wLength =%d, setup returned\n",
1345 __func__, usb_ctrl->wLength);
1347 s3c_udc_ep0_set_stall(ep);
1348 dev->ep0state = WAIT_FOR_SETUP;
1353 /* Set direction of EP0 */
1354 if (likely(usb_ctrl->bRequestType & USB_DIR_IN)) {
1355 ep->bEndpointAddress |= USB_DIR_IN;
1357 ep->bEndpointAddress &= ~USB_DIR_IN;
1359 /* cope with automagic for some standard requests. */
1360 dev->req_std = (usb_ctrl->bRequestType & USB_TYPE_MASK)
1361 == USB_TYPE_STANDARD;
1363 dev->req_pending = 1;
1365 /* Handle some SETUP packets ourselves */
1367 switch (usb_ctrl->bRequest) {
1368 case USB_REQ_SET_ADDRESS:
1369 debug_cond(DEBUG_SETUP != 0,
1370 "%s: *** USB_REQ_SET_ADDRESS (%d)\n",
1371 __func__, usb_ctrl->wValue);
1372 if (usb_ctrl->bRequestType
1373 != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1376 udc_set_address(dev, usb_ctrl->wValue);
1379 case USB_REQ_SET_CONFIGURATION:
1380 debug_cond(DEBUG_SETUP != 0,
1381 "=====================================\n");
1382 debug_cond(DEBUG_SETUP != 0,
1383 "%s: USB_REQ_SET_CONFIGURATION (%d)\n",
1384 __func__, usb_ctrl->wValue);
1386 if (usb_ctrl->bRequestType == USB_RECIP_DEVICE)
1387 reset_available = 1;
1391 case USB_REQ_GET_DESCRIPTOR:
1392 debug_cond(DEBUG_SETUP != 0,
1393 "%s: *** USB_REQ_GET_DESCRIPTOR\n",
1397 case USB_REQ_SET_INTERFACE:
1398 debug_cond(DEBUG_SETUP != 0,
1399 "%s: *** USB_REQ_SET_INTERFACE (%d)\n",
1400 __func__, usb_ctrl->wValue);
1402 if (usb_ctrl->bRequestType == USB_RECIP_INTERFACE)
1403 reset_available = 1;
1407 case USB_REQ_GET_CONFIGURATION:
1408 debug_cond(DEBUG_SETUP != 0,
1409 "%s: *** USB_REQ_GET_CONFIGURATION\n",
1413 case USB_REQ_GET_STATUS:
1414 if (!s3c_udc_get_status(dev, usb_ctrl))
1419 case USB_REQ_CLEAR_FEATURE:
1420 ep_num = usb_ctrl->wIndex & 0x7f;
1422 if (!s3c_udc_clear_feature(&dev->ep[ep_num].ep))
1427 case USB_REQ_SET_FEATURE:
1428 ep_num = usb_ctrl->wIndex & 0x7f;
1430 if (!s3c_udc_set_feature(&dev->ep[ep_num].ep))
1436 debug_cond(DEBUG_SETUP != 0,
1437 "%s: *** Default of usb_ctrl->bRequest=0x%x"
1438 "happened.\n", __func__, usb_ctrl->bRequest);
1444 if (likely(dev->driver)) {
1445 /* device-2-host (IN) or no data setup command,
1446 * process immediately */
1447 debug_cond(DEBUG_SETUP != 0,
1448 "%s:usb_ctrlreq will be passed to fsg_setup()\n",
1451 spin_unlock(&dev->lock);
1452 i = dev->driver->setup(&dev->gadget, usb_ctrl);
1453 spin_lock(&dev->lock);
1456 /* setup processing failed, force stall */
1457 s3c_udc_ep0_set_stall(ep);
1458 dev->ep0state = WAIT_FOR_SETUP;
1460 debug_cond(DEBUG_SETUP != 0,
1461 "\tdev->driver->setup failed (%d),"
1463 i, usb_ctrl->bRequest);
1466 } else if (dev->req_pending) {
1467 dev->req_pending = 0;
1468 debug_cond(DEBUG_SETUP != 0,
1469 "\tdev->req_pending...\n");
1472 debug_cond(DEBUG_SETUP != 0,
1473 "\tep0state = %s\n", state_names[dev->ep0state]);
1479 * handle ep0 interrupt
1481 static void s3c_handle_ep0(struct s3c_udc *dev)
1483 if (dev->ep0state == WAIT_FOR_SETUP) {
1484 debug_cond(DEBUG_OUT_EP != 0,
1485 "%s: WAIT_FOR_SETUP\n", __func__);
1489 debug_cond(DEBUG_OUT_EP != 0,
1490 "%s: strange state!!(state = %s)\n",
1491 __func__, state_names[dev->ep0state]);
1495 static void s3c_ep0_kick(struct s3c_udc *dev, struct s3c_ep *ep)
1497 debug_cond(DEBUG_EP0 != 0,
1498 "%s: ep_is_in = %d\n", __func__, ep_is_in(ep));
1500 dev->ep0state = DATA_STATE_XMIT;
1504 dev->ep0state = DATA_STATE_RECV;