2 * drivers/usb/gadget/s3c_udc_otg_xfer_dma.c
3 * Samsung S3C on-chip full/high speed USB OTG 2.0 device controllers
5 * Copyright (C) 2009 for Samsung Electronics
7 * BSP Support for Samsung's UDC driver
9 * git://git.kernel.org/pub/scm/linux/kernel/git/kki_ap/linux-2.6-samsung.git
11 * State machine bugfixes:
12 * Marek Szyprowski <m.szyprowski@samsung.com>
15 * Marek Szyprowski <m.szyprowski@samsung.com>
16 * Lukasz Majewski <l.majewski@samsumg.com>
18 * SPDX-License-Identifier: GPL-2.0+
21 static u8 clear_feature_num;
22 int clear_feature_flag;
24 /* Bulk-Only Mass Storage Reset (class-specific request) */
25 #define GET_MAX_LUN_REQUEST 0xFE
26 #define BOT_RESET_REQUEST 0xFF
28 static inline void s3c_udc_ep0_zlp(struct s3c_udc *dev)
32 flush_dcache_range((unsigned long) usb_ctrl_dma_addr,
33 (unsigned long) usb_ctrl_dma_addr
36 writel(usb_ctrl_dma_addr, ®->in_endp[EP0_CON].diepdma);
37 writel(DIEPT_SIZ_PKT_CNT(1), ®->in_endp[EP0_CON].dieptsiz);
39 ep_ctrl = readl(®->in_endp[EP0_CON].diepctl);
40 writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK,
41 ®->in_endp[EP0_CON].diepctl);
43 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
44 __func__, readl(®->in_endp[EP0_CON].diepctl));
45 dev->ep0state = WAIT_FOR_IN_COMPLETE;
48 void s3c_udc_pre_setup(void)
52 debug_cond(DEBUG_IN_EP,
53 "%s : Prepare Setup packets.\n", __func__);
55 invalidate_dcache_range((unsigned long) usb_ctrl_dma_addr,
56 (unsigned long) usb_ctrl_dma_addr
59 writel(DOEPT_SIZ_PKT_CNT(1) | sizeof(struct usb_ctrlrequest),
60 ®->out_endp[EP0_CON].doeptsiz);
61 writel(usb_ctrl_dma_addr, ®->out_endp[EP0_CON].doepdma);
63 ep_ctrl = readl(®->out_endp[EP0_CON].doepctl);
64 writel(ep_ctrl|DEPCTL_EPENA, ®->out_endp[EP0_CON].doepctl);
66 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
67 __func__, readl(®->in_endp[EP0_CON].diepctl));
68 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
69 __func__, readl(®->out_endp[EP0_CON].doepctl));
73 static inline void s3c_ep0_complete_out(void)
77 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
78 __func__, readl(®->in_endp[EP0_CON].diepctl));
79 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
80 __func__, readl(®->out_endp[EP0_CON].doepctl));
82 debug_cond(DEBUG_IN_EP,
83 "%s : Prepare Complete Out packet.\n", __func__);
85 invalidate_dcache_range((unsigned long) usb_ctrl_dma_addr,
86 (unsigned long) usb_ctrl_dma_addr
89 writel(DOEPT_SIZ_PKT_CNT(1) | sizeof(struct usb_ctrlrequest),
90 ®->out_endp[EP0_CON].doeptsiz);
91 writel(usb_ctrl_dma_addr, ®->out_endp[EP0_CON].doepdma);
93 ep_ctrl = readl(®->out_endp[EP0_CON].doepctl);
94 writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK,
95 ®->out_endp[EP0_CON].doepctl);
97 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
98 __func__, readl(®->in_endp[EP0_CON].diepctl));
99 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
100 __func__, readl(®->out_endp[EP0_CON].doepctl));
105 static int setdma_rx(struct s3c_ep *ep, struct s3c_request *req)
109 u32 ep_num = ep_index(ep);
111 buf = req->req.buf + req->req.actual;
113 length = min(req->req.length - req->req.actual, (int)ep->ep.maxpacket);
118 invalidate_dcache_range((unsigned long) ep->dev->dma_buf[ep_num],
119 (unsigned long) ep->dev->dma_buf[ep_num]
120 + ROUND(ep->ep.maxpacket,
121 CONFIG_SYS_CACHELINE_SIZE));
126 pktcnt = (length - 1)/(ep->ep.maxpacket) + 1;
129 ctrl = readl(®->out_endp[ep_num].doepctl);
131 writel(the_controller->dma_addr[ep_index(ep)+1],
132 ®->out_endp[ep_num].doepdma);
133 writel(DOEPT_SIZ_PKT_CNT(pktcnt) | DOEPT_SIZ_XFER_SIZE(length),
134 ®->out_endp[ep_num].doeptsiz);
135 writel(DEPCTL_EPENA|DEPCTL_CNAK|ctrl, ®->out_endp[ep_num].doepctl);
137 debug_cond(DEBUG_OUT_EP != 0,
138 "%s: EP%d RX DMA start : DOEPDMA = 0x%x,"
139 "DOEPTSIZ = 0x%x, DOEPCTL = 0x%x\n"
140 "\tbuf = 0x%p, pktcnt = %d, xfersize = %d\n",
142 readl(®->out_endp[ep_num].doepdma),
143 readl(®->out_endp[ep_num].doeptsiz),
144 readl(®->out_endp[ep_num].doepctl),
145 buf, pktcnt, length);
150 int setdma_tx(struct s3c_ep *ep, struct s3c_request *req)
154 u32 ep_num = ep_index(ep);
155 u32 *p = the_controller->dma_buf[ep_index(ep)+1];
157 buf = req->req.buf + req->req.actual;
158 length = req->req.length - req->req.actual;
160 if (ep_num == EP0_CON)
161 length = min(length, (u32)ep_maxpacket(ep));
165 memcpy(p, ep->dma_buf, length);
167 flush_dcache_range((unsigned long) p ,
168 (unsigned long) p + DMA_BUFFER_SIZE);
173 pktcnt = (length - 1)/(ep->ep.maxpacket) + 1;
175 /* Flush the endpoint's Tx FIFO */
176 writel(TX_FIFO_NUMBER(ep->fifo_num), ®->grstctl);
177 writel(TX_FIFO_NUMBER(ep->fifo_num) | TX_FIFO_FLUSH, ®->grstctl);
178 while (readl(®->grstctl) & TX_FIFO_FLUSH)
181 writel(the_controller->dma_addr[ep_index(ep)+1],
182 ®->in_endp[ep_num].diepdma);
183 writel(DIEPT_SIZ_PKT_CNT(pktcnt) | DIEPT_SIZ_XFER_SIZE(length),
184 ®->in_endp[ep_num].dieptsiz);
186 ctrl = readl(®->in_endp[ep_num].diepctl);
188 /* Write the FIFO number to be used for this endpoint */
189 ctrl &= DIEPCTL_TX_FIFO_NUM_MASK;
190 ctrl |= DIEPCTL_TX_FIFO_NUM(ep->fifo_num);
192 /* Clear reserved (Next EP) bits */
193 ctrl = (ctrl&~(EP_MASK<<DEPCTL_NEXT_EP_BIT));
195 writel(DEPCTL_EPENA|DEPCTL_CNAK|ctrl, ®->in_endp[ep_num].diepctl);
197 debug_cond(DEBUG_IN_EP,
198 "%s:EP%d TX DMA start : DIEPDMA0 = 0x%x,"
199 "DIEPTSIZ0 = 0x%x, DIEPCTL0 = 0x%x\n"
200 "\tbuf = 0x%p, pktcnt = %d, xfersize = %d\n",
202 readl(®->in_endp[ep_num].diepdma),
203 readl(®->in_endp[ep_num].dieptsiz),
204 readl(®->in_endp[ep_num].diepctl),
205 buf, pktcnt, length);
210 static void complete_rx(struct s3c_udc *dev, u8 ep_num)
212 struct s3c_ep *ep = &dev->ep[ep_num];
213 struct s3c_request *req = NULL;
214 u32 ep_tsr = 0, xfer_size = 0, is_short = 0;
215 u32 *p = the_controller->dma_buf[ep_index(ep)+1];
217 if (list_empty(&ep->queue)) {
218 debug_cond(DEBUG_OUT_EP != 0,
219 "%s: RX DMA done : NULL REQ on OUT EP-%d\n",
225 req = list_entry(ep->queue.next, struct s3c_request, queue);
226 ep_tsr = readl(®->out_endp[ep_num].doeptsiz);
228 if (ep_num == EP0_CON)
229 xfer_size = (ep_tsr & DOEPT_SIZ_XFER_SIZE_MAX_EP0);
231 xfer_size = (ep_tsr & DOEPT_SIZ_XFER_SIZE_MAX_EP);
233 xfer_size = ep->len - xfer_size;
235 invalidate_dcache_range((unsigned long) p,
236 (unsigned long) p + DMA_BUFFER_SIZE);
238 memcpy(ep->dma_buf, p, ep->len);
240 req->req.actual += min(xfer_size, req->req.length - req->req.actual);
241 is_short = (xfer_size < ep->ep.maxpacket);
243 debug_cond(DEBUG_OUT_EP != 0,
244 "%s: RX DMA done : ep = %d, rx bytes = %d/%d, "
245 "is_short = %d, DOEPTSIZ = 0x%x, remained bytes = %d\n",
246 __func__, ep_num, req->req.actual, req->req.length,
247 is_short, ep_tsr, xfer_size);
249 if (is_short || req->req.actual == req->req.length) {
250 if (ep_num == EP0_CON && dev->ep0state == DATA_STATE_RECV) {
251 debug_cond(DEBUG_OUT_EP != 0, " => Send ZLP\n");
252 s3c_udc_ep0_zlp(dev);
253 /* packet will be completed in complete_tx() */
254 dev->ep0state = WAIT_FOR_IN_COMPLETE;
258 if (!list_empty(&ep->queue)) {
259 req = list_entry(ep->queue.next,
260 struct s3c_request, queue);
261 debug_cond(DEBUG_OUT_EP != 0,
262 "%s: Next Rx request start...\n",
271 static void complete_tx(struct s3c_udc *dev, u8 ep_num)
273 struct s3c_ep *ep = &dev->ep[ep_num];
274 struct s3c_request *req;
275 u32 ep_tsr = 0, xfer_size = 0, is_short = 0;
278 if (dev->ep0state == WAIT_FOR_NULL_COMPLETE) {
279 dev->ep0state = WAIT_FOR_OUT_COMPLETE;
280 s3c_ep0_complete_out();
284 if (list_empty(&ep->queue)) {
285 debug_cond(DEBUG_IN_EP,
286 "%s: TX DMA done : NULL REQ on IN EP-%d\n",
292 req = list_entry(ep->queue.next, struct s3c_request, queue);
294 ep_tsr = readl(®->in_endp[ep_num].dieptsiz);
297 is_short = (xfer_size < ep->ep.maxpacket);
298 req->req.actual += min(xfer_size, req->req.length - req->req.actual);
300 debug_cond(DEBUG_IN_EP,
301 "%s: TX DMA done : ep = %d, tx bytes = %d/%d, "
302 "is_short = %d, DIEPTSIZ = 0x%x, remained bytes = %d\n",
303 __func__, ep_num, req->req.actual, req->req.length,
304 is_short, ep_tsr, xfer_size);
307 if (dev->ep0state == DATA_STATE_XMIT) {
308 debug_cond(DEBUG_IN_EP,
309 "%s: ep_num = %d, ep0stat =="
312 last = write_fifo_ep0(ep, req);
314 dev->ep0state = WAIT_FOR_COMPLETE;
315 } else if (dev->ep0state == WAIT_FOR_IN_COMPLETE) {
316 debug_cond(DEBUG_IN_EP,
317 "%s: ep_num = %d, completing request\n",
320 dev->ep0state = WAIT_FOR_SETUP;
321 } else if (dev->ep0state == WAIT_FOR_COMPLETE) {
322 debug_cond(DEBUG_IN_EP,
323 "%s: ep_num = %d, completing request\n",
326 dev->ep0state = WAIT_FOR_OUT_COMPLETE;
327 s3c_ep0_complete_out();
329 debug_cond(DEBUG_IN_EP,
330 "%s: ep_num = %d, invalid ep state\n",
336 if (req->req.actual == req->req.length)
339 if (!list_empty(&ep->queue)) {
340 req = list_entry(ep->queue.next, struct s3c_request, queue);
341 debug_cond(DEBUG_IN_EP,
342 "%s: Next Tx request start...\n", __func__);
347 static inline void s3c_udc_check_tx_queue(struct s3c_udc *dev, u8 ep_num)
349 struct s3c_ep *ep = &dev->ep[ep_num];
350 struct s3c_request *req;
352 debug_cond(DEBUG_IN_EP,
353 "%s: Check queue, ep_num = %d\n", __func__, ep_num);
355 if (!list_empty(&ep->queue)) {
356 req = list_entry(ep->queue.next, struct s3c_request, queue);
357 debug_cond(DEBUG_IN_EP,
358 "%s: Next Tx request(0x%p) start...\n",
366 debug_cond(DEBUG_IN_EP,
367 "%s: NULL REQ on IN EP-%d\n", __func__, ep_num);
374 static void process_ep_in_intr(struct s3c_udc *dev)
376 u32 ep_intr, ep_intr_status;
379 ep_intr = readl(®->daint);
380 debug_cond(DEBUG_IN_EP,
381 "*** %s: EP In interrupt : DAINT = 0x%x\n", __func__, ep_intr);
383 ep_intr &= DAINT_MASK;
386 if (ep_intr & DAINT_IN_EP_INT(1)) {
387 ep_intr_status = readl(®->in_endp[ep_num].diepint);
388 debug_cond(DEBUG_IN_EP,
389 "\tEP%d-IN : DIEPINT = 0x%x\n",
390 ep_num, ep_intr_status);
392 /* Interrupt Clear */
393 writel(ep_intr_status, ®->in_endp[ep_num].diepint);
395 if (ep_intr_status & TRANSFER_DONE) {
396 complete_tx(dev, ep_num);
400 WAIT_FOR_IN_COMPLETE)
401 dev->ep0state = WAIT_FOR_SETUP;
403 if (dev->ep0state == WAIT_FOR_SETUP)
406 /* continue transfer after
407 set_clear_halt for DMA mode */
408 if (clear_feature_flag == 1) {
409 s3c_udc_check_tx_queue(dev,
411 clear_feature_flag = 0;
421 static void process_ep_out_intr(struct s3c_udc *dev)
423 u32 ep_intr, ep_intr_status;
426 ep_intr = readl(®->daint);
427 debug_cond(DEBUG_OUT_EP != 0,
428 "*** %s: EP OUT interrupt : DAINT = 0x%x\n",
431 ep_intr = (ep_intr >> DAINT_OUT_BIT) & DAINT_MASK;
435 ep_intr_status = readl(®->out_endp[ep_num].doepint);
436 debug_cond(DEBUG_OUT_EP != 0,
437 "\tEP%d-OUT : DOEPINT = 0x%x\n",
438 ep_num, ep_intr_status);
440 /* Interrupt Clear */
441 writel(ep_intr_status, ®->out_endp[ep_num].doepint);
444 if (ep_intr_status & TRANSFER_DONE) {
446 WAIT_FOR_OUT_COMPLETE)
447 complete_rx(dev, ep_num);
449 dev->ep0state = WAIT_FOR_SETUP;
455 CTRL_OUT_EP_SETUP_PHASE_DONE) {
456 debug_cond(DEBUG_OUT_EP != 0,
457 "SETUP packet arrived\n");
461 if (ep_intr_status & TRANSFER_DONE)
462 complete_rx(dev, ep_num);
471 * usb client interrupt handler.
473 static int s3c_udc_irq(int irq, void *_dev)
475 struct s3c_udc *dev = _dev;
477 u32 usb_status, gintmsk;
480 spin_lock_irqsave(&dev->lock, flags);
482 intr_status = readl(®->gintsts);
483 gintmsk = readl(®->gintmsk);
485 debug_cond(DEBUG_ISR,
486 "\n*** %s : GINTSTS=0x%x(on state %s), GINTMSK : 0x%x,"
487 "DAINT : 0x%x, DAINTMSK : 0x%x\n",
488 __func__, intr_status, state_names[dev->ep0state], gintmsk,
489 readl(®->daint), readl(®->daintmsk));
492 spin_unlock_irqrestore(&dev->lock, flags);
496 if (intr_status & INT_ENUMDONE) {
497 debug_cond(DEBUG_ISR, "\tSpeed Detection interrupt\n");
499 writel(INT_ENUMDONE, ®->gintsts);
500 usb_status = (readl(®->dsts) & 0x6);
502 if (usb_status & (USB_FULL_30_60MHZ | USB_FULL_48MHZ)) {
503 debug_cond(DEBUG_ISR,
504 "\t\tFull Speed Detection\n");
505 set_max_pktsize(dev, USB_SPEED_FULL);
508 debug_cond(DEBUG_ISR,
509 "\t\tHigh Speed Detection : 0x%x\n",
511 set_max_pktsize(dev, USB_SPEED_HIGH);
515 if (intr_status & INT_EARLY_SUSPEND) {
516 debug_cond(DEBUG_ISR, "\tEarly suspend interrupt\n");
517 writel(INT_EARLY_SUSPEND, ®->gintsts);
520 if (intr_status & INT_SUSPEND) {
521 usb_status = readl(®->dsts);
522 debug_cond(DEBUG_ISR,
523 "\tSuspend interrupt :(DSTS):0x%x\n", usb_status);
524 writel(INT_SUSPEND, ®->gintsts);
526 if (dev->gadget.speed != USB_SPEED_UNKNOWN
528 if (dev->driver->suspend)
529 dev->driver->suspend(&dev->gadget);
531 /* HACK to let gadget detect disconnected state */
532 if (dev->driver->disconnect) {
533 spin_unlock_irqrestore(&dev->lock, flags);
534 dev->driver->disconnect(&dev->gadget);
535 spin_lock_irqsave(&dev->lock, flags);
540 if (intr_status & INT_RESUME) {
541 debug_cond(DEBUG_ISR, "\tResume interrupt\n");
542 writel(INT_RESUME, ®->gintsts);
544 if (dev->gadget.speed != USB_SPEED_UNKNOWN
546 && dev->driver->resume) {
548 dev->driver->resume(&dev->gadget);
552 if (intr_status & INT_RESET) {
553 usb_status = readl(®->gotgctl);
554 debug_cond(DEBUG_ISR,
555 "\tReset interrupt - (GOTGCTL):0x%x\n", usb_status);
556 writel(INT_RESET, ®->gintsts);
558 if ((usb_status & 0xc0000) == (0x3 << 18)) {
559 if (reset_available) {
560 debug_cond(DEBUG_ISR,
561 "\t\tOTG core got reset (%d)!!\n",
564 dev->ep0state = WAIT_FOR_SETUP;
572 debug_cond(DEBUG_ISR,
573 "\t\tRESET handling skipped\n");
577 if (intr_status & INT_IN_EP)
578 process_ep_in_intr(dev);
580 if (intr_status & INT_OUT_EP)
581 process_ep_out_intr(dev);
583 spin_unlock_irqrestore(&dev->lock, flags);
588 /** Queue one request
589 * Kickstart transfer if needed
591 static int s3c_queue(struct usb_ep *_ep, struct usb_request *_req,
594 struct s3c_request *req;
600 req = container_of(_req, struct s3c_request, req);
601 if (unlikely(!_req || !_req->complete || !_req->buf
602 || !list_empty(&req->queue))) {
604 debug("%s: bad params\n", __func__);
608 ep = container_of(_ep, struct s3c_ep, ep);
610 if (unlikely(!_ep || (!ep->desc && ep->ep.name != ep0name))) {
612 debug("%s: bad ep: %s, %d, %p\n", __func__,
613 ep->ep.name, !ep->desc, _ep);
617 ep_num = ep_index(ep);
619 if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
621 debug("%s: bogus device state %p\n", __func__, dev->driver);
625 spin_lock_irqsave(&dev->lock, flags);
627 _req->status = -EINPROGRESS;
630 /* kickstart this i/o queue? */
631 debug("\n*** %s: %s-%s req = %p, len = %d, buf = %p"
632 "Q empty = %d, stopped = %d\n",
633 __func__, _ep->name, ep_is_in(ep) ? "in" : "out",
634 _req, _req->length, _req->buf,
635 list_empty(&ep->queue), ep->stopped);
639 int i, len = _req->length;
644 for (i = 0; i < len; i++) {
645 printf("%02x", ((u8 *)_req->buf)[i]);
653 if (list_empty(&ep->queue) && !ep->stopped) {
657 list_add_tail(&req->queue, &ep->queue);
658 s3c_ep0_kick(dev, ep);
661 } else if (ep_is_in(ep)) {
662 gintsts = readl(®->gintsts);
663 debug_cond(DEBUG_IN_EP,
664 "%s: ep_is_in, S3C_UDC_OTG_GINTSTS=0x%x\n",
669 gintsts = readl(®->gintsts);
670 debug_cond(DEBUG_OUT_EP != 0,
671 "%s:ep_is_out, S3C_UDC_OTG_GINTSTS=0x%x\n",
678 /* pio or dma irq handler advances the queue. */
679 if (likely(req != 0))
680 list_add_tail(&req->queue, &ep->queue);
682 spin_unlock_irqrestore(&dev->lock, flags);
687 /****************************************************************/
688 /* End Point 0 related functions */
689 /****************************************************************/
691 /* return: 0 = still running, 1 = completed, negative = errno */
692 static int write_fifo_ep0(struct s3c_ep *ep, struct s3c_request *req)
698 max = ep_maxpacket(ep);
700 debug_cond(DEBUG_EP0 != 0, "%s: max = %d\n", __func__, max);
702 count = setdma_tx(ep, req);
704 /* last packet is usually short (or a zlp) */
705 if (likely(count != max))
708 if (likely(req->req.length != req->req.actual + count)
715 debug_cond(DEBUG_EP0 != 0,
716 "%s: wrote %s %d bytes%s %d left %p\n", __func__,
719 req->req.length - req->req.actual - count, req);
721 /* requests complete when all IN data is in the FIFO */
723 ep->dev->ep0state = WAIT_FOR_SETUP;
730 int s3c_fifo_read(struct s3c_ep *ep, u32 *cp, int max)
734 bytes = sizeof(struct usb_ctrlrequest);
736 invalidate_dcache_range((unsigned long) ep->dev->dma_buf[ep_index(ep)],
737 (unsigned long) ep->dev->dma_buf[ep_index(ep)]
740 debug_cond(DEBUG_EP0 != 0,
741 "%s: bytes=%d, ep_index=%d %p\n", __func__,
742 bytes, ep_index(ep), ep->dev->dma_buf[ep_index(ep)]);
748 * udc_set_address - set the USB address for this device
751 * Called from control endpoint function
752 * after it decodes a set address setup packet.
754 static void udc_set_address(struct s3c_udc *dev, unsigned char address)
756 u32 ctrl = readl(®->dcfg);
757 writel(DEVICE_ADDRESS(address) | ctrl, ®->dcfg);
759 s3c_udc_ep0_zlp(dev);
761 debug_cond(DEBUG_EP0 != 0,
762 "%s: USB OTG 2.0 Device address=%d, DCFG=0x%x\n",
763 __func__, address, readl(®->dcfg));
765 dev->usb_address = address;
768 static inline void s3c_udc_ep0_set_stall(struct s3c_ep *ep)
774 ep_ctrl = readl(®->in_endp[EP0_CON].diepctl);
776 /* set the disable and stall bits */
777 if (ep_ctrl & DEPCTL_EPENA)
778 ep_ctrl |= DEPCTL_EPDIS;
780 ep_ctrl |= DEPCTL_STALL;
782 writel(ep_ctrl, ®->in_endp[EP0_CON].diepctl);
784 debug_cond(DEBUG_EP0 != 0,
785 "%s: set ep%d stall, DIEPCTL0 = 0x%p\n",
786 __func__, ep_index(ep), ®->in_endp[EP0_CON].diepctl);
788 * The application can only set this bit, and the core clears it,
789 * when a SETUP token is received for this endpoint
791 dev->ep0state = WAIT_FOR_SETUP;
796 static void s3c_ep0_read(struct s3c_udc *dev)
798 struct s3c_request *req;
799 struct s3c_ep *ep = &dev->ep[0];
801 if (!list_empty(&ep->queue)) {
802 req = list_entry(ep->queue.next, struct s3c_request, queue);
805 debug("%s: ---> BUG\n", __func__);
810 debug_cond(DEBUG_EP0 != 0,
811 "%s: req = %p, req.length = 0x%x, req.actual = 0x%x\n",
812 __func__, req, req->req.length, req->req.actual);
814 if (req->req.length == 0) {
815 /* zlp for Set_configuration, Set_interface,
816 * or Bulk-Only mass storge reset */
819 s3c_udc_ep0_zlp(dev);
821 debug_cond(DEBUG_EP0 != 0,
822 "%s: req.length = 0, bRequest = %d\n",
823 __func__, usb_ctrl->bRequest);
833 static int s3c_ep0_write(struct s3c_udc *dev)
835 struct s3c_request *req;
836 struct s3c_ep *ep = &dev->ep[0];
837 int ret, need_zlp = 0;
839 if (list_empty(&ep->queue))
842 req = list_entry(ep->queue.next, struct s3c_request, queue);
845 debug_cond(DEBUG_EP0 != 0, "%s: NULL REQ\n", __func__);
849 debug_cond(DEBUG_EP0 != 0,
850 "%s: req = %p, req.length = 0x%x, req.actual = 0x%x\n",
851 __func__, req, req->req.length, req->req.actual);
853 if (req->req.length - req->req.actual == ep0_fifo_size) {
854 /* Next write will end with the packet size, */
855 /* so we need Zero-length-packet */
859 ret = write_fifo_ep0(ep, req);
861 if ((ret == 1) && !need_zlp) {
863 dev->ep0state = WAIT_FOR_COMPLETE;
864 debug_cond(DEBUG_EP0 != 0,
865 "%s: finished, waiting for status\n", __func__);
868 dev->ep0state = DATA_STATE_XMIT;
869 debug_cond(DEBUG_EP0 != 0,
870 "%s: not finished\n", __func__);
878 int s3c_udc_get_status(struct s3c_udc *dev,
879 struct usb_ctrlrequest *crq)
881 u8 ep_num = crq->wIndex & 0x7F;
883 u32 *p = the_controller->dma_buf[1];
885 debug_cond(DEBUG_SETUP != 0,
886 "%s: *** USB_REQ_GET_STATUS\n", __func__);
887 printf("crq->brequest:0x%x\n", crq->bRequestType & USB_RECIP_MASK);
888 switch (crq->bRequestType & USB_RECIP_MASK) {
889 case USB_RECIP_INTERFACE:
891 debug_cond(DEBUG_SETUP != 0,
892 "\tGET_STATUS:USB_RECIP_INTERFACE, g_stauts = %d\n",
896 case USB_RECIP_DEVICE:
897 g_status = 0x1; /* Self powered */
898 debug_cond(DEBUG_SETUP != 0,
899 "\tGET_STATUS: USB_RECIP_DEVICE, g_stauts = %d\n",
903 case USB_RECIP_ENDPOINT:
904 if (crq->wLength > 2) {
905 debug_cond(DEBUG_SETUP != 0,
906 "\tGET_STATUS:Not support EP or wLength\n");
910 g_status = dev->ep[ep_num].stopped;
911 debug_cond(DEBUG_SETUP != 0,
912 "\tGET_STATUS: USB_RECIP_ENDPOINT, g_stauts = %d\n",
921 memcpy(p, &g_status, sizeof(g_status));
923 flush_dcache_range((unsigned long) p,
924 (unsigned long) p + DMA_BUFFER_SIZE);
926 writel(the_controller->dma_addr[1], ®->in_endp[EP0_CON].diepdma);
927 writel(DIEPT_SIZ_PKT_CNT(1) | DIEPT_SIZ_XFER_SIZE(2),
928 ®->in_endp[EP0_CON].dieptsiz);
930 ep_ctrl = readl(®->in_endp[EP0_CON].diepctl);
931 writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK,
932 ®->in_endp[EP0_CON].diepctl);
933 dev->ep0state = WAIT_FOR_NULL_COMPLETE;
938 static void s3c_udc_set_nak(struct s3c_ep *ep)
943 ep_num = ep_index(ep);
944 debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type);
947 ep_ctrl = readl(®->in_endp[ep_num].diepctl);
948 ep_ctrl |= DEPCTL_SNAK;
949 writel(ep_ctrl, ®->in_endp[ep_num].diepctl);
950 debug("%s: set NAK, DIEPCTL%d = 0x%x\n",
951 __func__, ep_num, readl(®->in_endp[ep_num].diepctl));
953 ep_ctrl = readl(®->out_endp[ep_num].doepctl);
954 ep_ctrl |= DEPCTL_SNAK;
955 writel(ep_ctrl, ®->out_endp[ep_num].doepctl);
956 debug("%s: set NAK, DOEPCTL%d = 0x%x\n",
957 __func__, ep_num, readl(®->out_endp[ep_num].doepctl));
964 void s3c_udc_ep_set_stall(struct s3c_ep *ep)
969 ep_num = ep_index(ep);
970 debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type);
973 ep_ctrl = readl(®->in_endp[ep_num].diepctl);
975 /* set the disable and stall bits */
976 if (ep_ctrl & DEPCTL_EPENA)
977 ep_ctrl |= DEPCTL_EPDIS;
979 ep_ctrl |= DEPCTL_STALL;
981 writel(ep_ctrl, ®->in_endp[ep_num].diepctl);
982 debug("%s: set stall, DIEPCTL%d = 0x%x\n",
983 __func__, ep_num, readl(®->in_endp[ep_num].diepctl));
986 ep_ctrl = readl(®->out_endp[ep_num].doepctl);
988 /* set the stall bit */
989 ep_ctrl |= DEPCTL_STALL;
991 writel(ep_ctrl, ®->out_endp[ep_num].doepctl);
992 debug("%s: set stall, DOEPCTL%d = 0x%x\n",
993 __func__, ep_num, readl(®->out_endp[ep_num].doepctl));
999 void s3c_udc_ep_clear_stall(struct s3c_ep *ep)
1004 ep_num = ep_index(ep);
1005 debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type);
1008 ep_ctrl = readl(®->in_endp[ep_num].diepctl);
1010 /* clear stall bit */
1011 ep_ctrl &= ~DEPCTL_STALL;
1014 * USB Spec 9.4.5: For endpoints using data toggle, regardless
1015 * of whether an endpoint has the Halt feature set, a
1016 * ClearFeature(ENDPOINT_HALT) request always results in the
1017 * data toggle being reinitialized to DATA0.
1019 if (ep->bmAttributes == USB_ENDPOINT_XFER_INT
1020 || ep->bmAttributes == USB_ENDPOINT_XFER_BULK) {
1021 ep_ctrl |= DEPCTL_SETD0PID; /* DATA0 */
1024 writel(ep_ctrl, ®->in_endp[ep_num].diepctl);
1025 debug("%s: cleared stall, DIEPCTL%d = 0x%x\n",
1026 __func__, ep_num, readl(®->in_endp[ep_num].diepctl));
1029 ep_ctrl = readl(®->out_endp[ep_num].doepctl);
1031 /* clear stall bit */
1032 ep_ctrl &= ~DEPCTL_STALL;
1034 if (ep->bmAttributes == USB_ENDPOINT_XFER_INT
1035 || ep->bmAttributes == USB_ENDPOINT_XFER_BULK) {
1036 ep_ctrl |= DEPCTL_SETD0PID; /* DATA0 */
1039 writel(ep_ctrl, ®->out_endp[ep_num].doepctl);
1040 debug("%s: cleared stall, DOEPCTL%d = 0x%x\n",
1041 __func__, ep_num, readl(®->out_endp[ep_num].doepctl));
1047 static int s3c_udc_set_halt(struct usb_ep *_ep, int value)
1050 struct s3c_udc *dev;
1051 unsigned long flags;
1054 ep = container_of(_ep, struct s3c_ep, ep);
1055 ep_num = ep_index(ep);
1057 if (unlikely(!_ep || !ep->desc || ep_num == EP0_CON ||
1058 ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC)) {
1059 debug("%s: %s bad ep or descriptor\n", __func__, ep->ep.name);
1063 /* Attempt to halt IN ep will fail if any transfer requests
1064 * are still queue */
1065 if (value && ep_is_in(ep) && !list_empty(&ep->queue)) {
1066 debug("%s: %s queue not empty, req = %p\n",
1067 __func__, ep->ep.name,
1068 list_entry(ep->queue.next, struct s3c_request, queue));
1074 debug("%s: ep_num = %d, value = %d\n", __func__, ep_num, value);
1076 spin_lock_irqsave(&dev->lock, flags);
1080 s3c_udc_ep_clear_stall(ep);
1083 dev->ep0state = WAIT_FOR_SETUP;
1086 s3c_udc_ep_set_stall(ep);
1089 spin_unlock_irqrestore(&dev->lock, flags);
1094 void s3c_udc_ep_activate(struct s3c_ep *ep)
1097 u32 ep_ctrl = 0, daintmsk = 0;
1099 ep_num = ep_index(ep);
1101 /* Read DEPCTLn register */
1103 ep_ctrl = readl(®->in_endp[ep_num].diepctl);
1104 daintmsk = 1 << ep_num;
1106 ep_ctrl = readl(®->out_endp[ep_num].doepctl);
1107 daintmsk = (1 << ep_num) << DAINT_OUT_BIT;
1110 debug("%s: EPCTRL%d = 0x%x, ep_is_in = %d\n",
1111 __func__, ep_num, ep_ctrl, ep_is_in(ep));
1113 /* If the EP is already active don't change the EP Control
1115 if (!(ep_ctrl & DEPCTL_USBACTEP)) {
1116 ep_ctrl = (ep_ctrl & ~DEPCTL_TYPE_MASK) |
1117 (ep->bmAttributes << DEPCTL_TYPE_BIT);
1118 ep_ctrl = (ep_ctrl & ~DEPCTL_MPS_MASK) |
1119 (ep->ep.maxpacket << DEPCTL_MPS_BIT);
1120 ep_ctrl |= (DEPCTL_SETD0PID | DEPCTL_USBACTEP | DEPCTL_SNAK);
1123 writel(ep_ctrl, ®->in_endp[ep_num].diepctl);
1124 debug("%s: USB Ative EP%d, DIEPCTRL%d = 0x%x\n",
1125 __func__, ep_num, ep_num,
1126 readl(®->in_endp[ep_num].diepctl));
1128 writel(ep_ctrl, ®->out_endp[ep_num].doepctl);
1129 debug("%s: USB Ative EP%d, DOEPCTRL%d = 0x%x\n",
1130 __func__, ep_num, ep_num,
1131 readl(®->out_endp[ep_num].doepctl));
1135 /* Unmask EP Interrtupt */
1136 writel(readl(®->daintmsk)|daintmsk, ®->daintmsk);
1137 debug("%s: DAINTMSK = 0x%x\n", __func__, readl(®->daintmsk));
1141 static int s3c_udc_clear_feature(struct usb_ep *_ep)
1143 struct s3c_udc *dev;
1147 ep = container_of(_ep, struct s3c_ep, ep);
1148 ep_num = ep_index(ep);
1151 debug_cond(DEBUG_SETUP != 0,
1152 "%s: ep_num = %d, is_in = %d, clear_feature_flag = %d\n",
1153 __func__, ep_num, ep_is_in(ep), clear_feature_flag);
1155 if (usb_ctrl->wLength != 0) {
1156 debug_cond(DEBUG_SETUP != 0,
1157 "\tCLEAR_FEATURE: wLength is not zero.....\n");
1161 switch (usb_ctrl->bRequestType & USB_RECIP_MASK) {
1162 case USB_RECIP_DEVICE:
1163 switch (usb_ctrl->wValue) {
1164 case USB_DEVICE_REMOTE_WAKEUP:
1165 debug_cond(DEBUG_SETUP != 0,
1166 "\tOFF:USB_DEVICE_REMOTE_WAKEUP\n");
1169 case USB_DEVICE_TEST_MODE:
1170 debug_cond(DEBUG_SETUP != 0,
1171 "\tCLEAR_FEATURE: USB_DEVICE_TEST_MODE\n");
1172 /** @todo Add CLEAR_FEATURE for TEST modes. */
1176 s3c_udc_ep0_zlp(dev);
1179 case USB_RECIP_ENDPOINT:
1180 debug_cond(DEBUG_SETUP != 0,
1181 "\tCLEAR_FEATURE:USB_RECIP_ENDPOINT, wValue = %d\n",
1184 if (usb_ctrl->wValue == USB_ENDPOINT_HALT) {
1186 s3c_udc_ep0_set_stall(ep);
1190 s3c_udc_ep0_zlp(dev);
1192 s3c_udc_ep_clear_stall(ep);
1193 s3c_udc_ep_activate(ep);
1196 clear_feature_num = ep_num;
1197 clear_feature_flag = 1;
1205 static int s3c_udc_set_feature(struct usb_ep *_ep)
1207 struct s3c_udc *dev;
1211 ep = container_of(_ep, struct s3c_ep, ep);
1212 ep_num = ep_index(ep);
1215 debug_cond(DEBUG_SETUP != 0,
1216 "%s: *** USB_REQ_SET_FEATURE , ep_num = %d\n",
1219 if (usb_ctrl->wLength != 0) {
1220 debug_cond(DEBUG_SETUP != 0,
1221 "\tSET_FEATURE: wLength is not zero.....\n");
1225 switch (usb_ctrl->bRequestType & USB_RECIP_MASK) {
1226 case USB_RECIP_DEVICE:
1227 switch (usb_ctrl->wValue) {
1228 case USB_DEVICE_REMOTE_WAKEUP:
1229 debug_cond(DEBUG_SETUP != 0,
1230 "\tSET_FEATURE:USB_DEVICE_REMOTE_WAKEUP\n");
1232 case USB_DEVICE_B_HNP_ENABLE:
1233 debug_cond(DEBUG_SETUP != 0,
1234 "\tSET_FEATURE: USB_DEVICE_B_HNP_ENABLE\n");
1237 case USB_DEVICE_A_HNP_SUPPORT:
1238 /* RH port supports HNP */
1239 debug_cond(DEBUG_SETUP != 0,
1240 "\tSET_FEATURE:USB_DEVICE_A_HNP_SUPPORT\n");
1243 case USB_DEVICE_A_ALT_HNP_SUPPORT:
1244 /* other RH port does */
1245 debug_cond(DEBUG_SETUP != 0,
1246 "\tSET: USB_DEVICE_A_ALT_HNP_SUPPORT\n");
1250 s3c_udc_ep0_zlp(dev);
1253 case USB_RECIP_INTERFACE:
1254 debug_cond(DEBUG_SETUP != 0,
1255 "\tSET_FEATURE: USB_RECIP_INTERFACE\n");
1258 case USB_RECIP_ENDPOINT:
1259 debug_cond(DEBUG_SETUP != 0,
1260 "\tSET_FEATURE: USB_RECIP_ENDPOINT\n");
1261 if (usb_ctrl->wValue == USB_ENDPOINT_HALT) {
1263 s3c_udc_ep0_set_stall(ep);
1267 s3c_udc_ep_set_stall(ep);
1270 s3c_udc_ep0_zlp(dev);
1278 * WAIT_FOR_SETUP (OUT_PKT_RDY)
1280 void s3c_ep0_setup(struct s3c_udc *dev)
1282 struct s3c_ep *ep = &dev->ep[0];
1286 /* Nuke all previous transfers */
1289 /* read control req from fifo (8 bytes) */
1290 s3c_fifo_read(ep, (u32 *)usb_ctrl, 8);
1292 debug_cond(DEBUG_SETUP != 0,
1293 "%s: bRequestType = 0x%x(%s), bRequest = 0x%x"
1294 "\twLength = 0x%x, wValue = 0x%x, wIndex= 0x%x\n",
1295 __func__, usb_ctrl->bRequestType,
1296 (usb_ctrl->bRequestType & USB_DIR_IN) ? "IN" : "OUT",
1298 usb_ctrl->wLength, usb_ctrl->wValue, usb_ctrl->wIndex);
1302 int i, len = sizeof(*usb_ctrl);
1303 char *p = (char *)usb_ctrl;
1306 for (i = 0; i < len; i++) {
1307 printf("%02x", ((u8 *)p)[i]);
1315 if (usb_ctrl->bRequest == GET_MAX_LUN_REQUEST &&
1316 usb_ctrl->wLength != 1) {
1317 debug_cond(DEBUG_SETUP != 0,
1318 "\t%s:GET_MAX_LUN_REQUEST:invalid",
1320 debug_cond(DEBUG_SETUP != 0,
1321 "wLength = %d, setup returned\n",
1324 s3c_udc_ep0_set_stall(ep);
1325 dev->ep0state = WAIT_FOR_SETUP;
1328 } else if (usb_ctrl->bRequest == BOT_RESET_REQUEST &&
1329 usb_ctrl->wLength != 0) {
1330 /* Bulk-Only *mass storge reset of class-specific request */
1331 debug_cond(DEBUG_SETUP != 0,
1332 "%s:BOT Rest:invalid wLength =%d, setup returned\n",
1333 __func__, usb_ctrl->wLength);
1335 s3c_udc_ep0_set_stall(ep);
1336 dev->ep0state = WAIT_FOR_SETUP;
1341 /* Set direction of EP0 */
1342 if (likely(usb_ctrl->bRequestType & USB_DIR_IN)) {
1343 ep->bEndpointAddress |= USB_DIR_IN;
1345 ep->bEndpointAddress &= ~USB_DIR_IN;
1347 /* cope with automagic for some standard requests. */
1348 dev->req_std = (usb_ctrl->bRequestType & USB_TYPE_MASK)
1349 == USB_TYPE_STANDARD;
1351 dev->req_pending = 1;
1353 /* Handle some SETUP packets ourselves */
1355 switch (usb_ctrl->bRequest) {
1356 case USB_REQ_SET_ADDRESS:
1357 debug_cond(DEBUG_SETUP != 0,
1358 "%s: *** USB_REQ_SET_ADDRESS (%d)\n",
1359 __func__, usb_ctrl->wValue);
1360 if (usb_ctrl->bRequestType
1361 != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1364 udc_set_address(dev, usb_ctrl->wValue);
1367 case USB_REQ_SET_CONFIGURATION:
1368 debug_cond(DEBUG_SETUP != 0,
1369 "=====================================\n");
1370 debug_cond(DEBUG_SETUP != 0,
1371 "%s: USB_REQ_SET_CONFIGURATION (%d)\n",
1372 __func__, usb_ctrl->wValue);
1374 if (usb_ctrl->bRequestType == USB_RECIP_DEVICE)
1375 reset_available = 1;
1379 case USB_REQ_GET_DESCRIPTOR:
1380 debug_cond(DEBUG_SETUP != 0,
1381 "%s: *** USB_REQ_GET_DESCRIPTOR\n",
1385 case USB_REQ_SET_INTERFACE:
1386 debug_cond(DEBUG_SETUP != 0,
1387 "%s: *** USB_REQ_SET_INTERFACE (%d)\n",
1388 __func__, usb_ctrl->wValue);
1390 if (usb_ctrl->bRequestType == USB_RECIP_INTERFACE)
1391 reset_available = 1;
1395 case USB_REQ_GET_CONFIGURATION:
1396 debug_cond(DEBUG_SETUP != 0,
1397 "%s: *** USB_REQ_GET_CONFIGURATION\n",
1401 case USB_REQ_GET_STATUS:
1402 if (!s3c_udc_get_status(dev, usb_ctrl))
1407 case USB_REQ_CLEAR_FEATURE:
1408 ep_num = usb_ctrl->wIndex & 0x7f;
1410 if (!s3c_udc_clear_feature(&dev->ep[ep_num].ep))
1415 case USB_REQ_SET_FEATURE:
1416 ep_num = usb_ctrl->wIndex & 0x7f;
1418 if (!s3c_udc_set_feature(&dev->ep[ep_num].ep))
1424 debug_cond(DEBUG_SETUP != 0,
1425 "%s: *** Default of usb_ctrl->bRequest=0x%x"
1426 "happened.\n", __func__, usb_ctrl->bRequest);
1432 if (likely(dev->driver)) {
1433 /* device-2-host (IN) or no data setup command,
1434 * process immediately */
1435 debug_cond(DEBUG_SETUP != 0,
1436 "%s:usb_ctrlreq will be passed to fsg_setup()\n",
1439 spin_unlock(&dev->lock);
1440 i = dev->driver->setup(&dev->gadget, usb_ctrl);
1441 spin_lock(&dev->lock);
1444 /* setup processing failed, force stall */
1445 s3c_udc_ep0_set_stall(ep);
1446 dev->ep0state = WAIT_FOR_SETUP;
1448 debug_cond(DEBUG_SETUP != 0,
1449 "\tdev->driver->setup failed (%d),"
1451 i, usb_ctrl->bRequest);
1454 } else if (dev->req_pending) {
1455 dev->req_pending = 0;
1456 debug_cond(DEBUG_SETUP != 0,
1457 "\tdev->req_pending...\n");
1460 debug_cond(DEBUG_SETUP != 0,
1461 "\tep0state = %s\n", state_names[dev->ep0state]);
1467 * handle ep0 interrupt
1469 static void s3c_handle_ep0(struct s3c_udc *dev)
1471 if (dev->ep0state == WAIT_FOR_SETUP) {
1472 debug_cond(DEBUG_OUT_EP != 0,
1473 "%s: WAIT_FOR_SETUP\n", __func__);
1477 debug_cond(DEBUG_OUT_EP != 0,
1478 "%s: strange state!!(state = %s)\n",
1479 __func__, state_names[dev->ep0state]);
1483 static void s3c_ep0_kick(struct s3c_udc *dev, struct s3c_ep *ep)
1485 debug_cond(DEBUG_EP0 != 0,
1486 "%s: ep_is_in = %d\n", __func__, ep_is_in(ep));
1488 dev->ep0state = DATA_STATE_XMIT;
1492 dev->ep0state = DATA_STATE_RECV;