2 * drivers/usb/gadget/s3c_udc_otg_xfer_dma.c
3 * Samsung S3C on-chip full/high speed USB OTG 2.0 device controllers
5 * Copyright (C) 2009 for Samsung Electronics
7 * BSP Support for Samsung's UDC driver
9 * git://git.kernel.org/pub/scm/linux/kernel/git/kki_ap/linux-2.6-samsung.git
11 * State machine bugfixes:
12 * Marek Szyprowski <m.szyprowski@samsung.com>
15 * Marek Szyprowski <m.szyprowski@samsung.com>
16 * Lukasz Majewski <l.majewski@samsumg.com>
18 * SPDX-License-Identifier: GPL-2.0+
21 static u8 clear_feature_num;
22 int clear_feature_flag;
24 /* Bulk-Only Mass Storage Reset (class-specific request) */
25 #define GET_MAX_LUN_REQUEST 0xFE
26 #define BOT_RESET_REQUEST 0xFF
28 static inline void s3c_udc_ep0_zlp(struct s3c_udc *dev)
32 flush_dcache_range((unsigned long) usb_ctrl_dma_addr,
33 (unsigned long) usb_ctrl_dma_addr
36 writel(usb_ctrl_dma_addr, ®->in_endp[EP0_CON].diepdma);
37 writel(DIEPT_SIZ_PKT_CNT(1), ®->in_endp[EP0_CON].dieptsiz);
39 ep_ctrl = readl(®->in_endp[EP0_CON].diepctl);
40 writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK,
41 ®->in_endp[EP0_CON].diepctl);
43 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
44 __func__, readl(®->in_endp[EP0_CON].diepctl));
45 dev->ep0state = WAIT_FOR_IN_COMPLETE;
48 void s3c_udc_pre_setup(void)
52 debug_cond(DEBUG_IN_EP,
53 "%s : Prepare Setup packets.\n", __func__);
55 invalidate_dcache_range((unsigned long) usb_ctrl_dma_addr,
56 (unsigned long) usb_ctrl_dma_addr
59 writel(DOEPT_SIZ_PKT_CNT(1) | sizeof(struct usb_ctrlrequest),
60 ®->out_endp[EP0_CON].doeptsiz);
61 writel(usb_ctrl_dma_addr, ®->out_endp[EP0_CON].doepdma);
63 ep_ctrl = readl(®->out_endp[EP0_CON].doepctl);
64 writel(ep_ctrl|DEPCTL_EPENA, ®->out_endp[EP0_CON].doepctl);
66 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
67 __func__, readl(®->in_endp[EP0_CON].diepctl));
68 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
69 __func__, readl(®->out_endp[EP0_CON].doepctl));
73 static inline void s3c_ep0_complete_out(void)
77 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
78 __func__, readl(®->in_endp[EP0_CON].diepctl));
79 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
80 __func__, readl(®->out_endp[EP0_CON].doepctl));
82 debug_cond(DEBUG_IN_EP,
83 "%s : Prepare Complete Out packet.\n", __func__);
85 invalidate_dcache_range((unsigned long) usb_ctrl_dma_addr,
86 (unsigned long) usb_ctrl_dma_addr
89 writel(DOEPT_SIZ_PKT_CNT(1) | sizeof(struct usb_ctrlrequest),
90 ®->out_endp[EP0_CON].doeptsiz);
91 writel(usb_ctrl_dma_addr, ®->out_endp[EP0_CON].doepdma);
93 ep_ctrl = readl(®->out_endp[EP0_CON].doepctl);
94 writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK,
95 ®->out_endp[EP0_CON].doepctl);
97 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
98 __func__, readl(®->in_endp[EP0_CON].diepctl));
99 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
100 __func__, readl(®->out_endp[EP0_CON].doepctl));
105 static int setdma_rx(struct s3c_ep *ep, struct s3c_request *req)
109 u32 ep_num = ep_index(ep);
111 buf = req->req.buf + req->req.actual;
113 length = min(req->req.length - req->req.actual, (int)ep->ep.maxpacket);
118 invalidate_dcache_range((unsigned long) ep->dev->dma_buf[ep_num],
119 (unsigned long) ep->dev->dma_buf[ep_num]
125 pktcnt = (length - 1)/(ep->ep.maxpacket) + 1;
128 ctrl = readl(®->out_endp[ep_num].doepctl);
130 writel(the_controller->dma_addr[ep_index(ep)+1],
131 ®->out_endp[ep_num].doepdma);
132 writel(DOEPT_SIZ_PKT_CNT(pktcnt) | DOEPT_SIZ_XFER_SIZE(length),
133 ®->out_endp[ep_num].doeptsiz);
134 writel(DEPCTL_EPENA|DEPCTL_CNAK|ctrl, ®->out_endp[ep_num].doepctl);
136 debug_cond(DEBUG_OUT_EP != 0,
137 "%s: EP%d RX DMA start : DOEPDMA = 0x%x,"
138 "DOEPTSIZ = 0x%x, DOEPCTL = 0x%x\n"
139 "\tbuf = 0x%p, pktcnt = %d, xfersize = %d\n",
141 readl(®->out_endp[ep_num].doepdma),
142 readl(®->out_endp[ep_num].doeptsiz),
143 readl(®->out_endp[ep_num].doepctl),
144 buf, pktcnt, length);
149 int setdma_tx(struct s3c_ep *ep, struct s3c_request *req)
153 u32 ep_num = ep_index(ep);
154 u32 *p = the_controller->dma_buf[ep_index(ep)+1];
156 buf = req->req.buf + req->req.actual;
157 length = req->req.length - req->req.actual;
159 if (ep_num == EP0_CON)
160 length = min(length, (u32)ep_maxpacket(ep));
164 memcpy(p, ep->dma_buf, length);
166 flush_dcache_range((unsigned long) p ,
167 (unsigned long) p + DMA_BUFFER_SIZE);
172 pktcnt = (length - 1)/(ep->ep.maxpacket) + 1;
174 /* Flush the endpoint's Tx FIFO */
175 writel(TX_FIFO_NUMBER(ep->fifo_num), ®->grstctl);
176 writel(TX_FIFO_NUMBER(ep->fifo_num) | TX_FIFO_FLUSH, ®->grstctl);
177 while (readl(®->grstctl) & TX_FIFO_FLUSH)
180 writel(the_controller->dma_addr[ep_index(ep)+1],
181 ®->in_endp[ep_num].diepdma);
182 writel(DIEPT_SIZ_PKT_CNT(pktcnt) | DIEPT_SIZ_XFER_SIZE(length),
183 ®->in_endp[ep_num].dieptsiz);
185 ctrl = readl(®->in_endp[ep_num].diepctl);
187 /* Write the FIFO number to be used for this endpoint */
188 ctrl &= DIEPCTL_TX_FIFO_NUM_MASK;
189 ctrl |= DIEPCTL_TX_FIFO_NUM(ep->fifo_num);
191 /* Clear reserved (Next EP) bits */
192 ctrl = (ctrl&~(EP_MASK<<DEPCTL_NEXT_EP_BIT));
194 writel(DEPCTL_EPENA|DEPCTL_CNAK|ctrl, ®->in_endp[ep_num].diepctl);
196 debug_cond(DEBUG_IN_EP,
197 "%s:EP%d TX DMA start : DIEPDMA0 = 0x%x,"
198 "DIEPTSIZ0 = 0x%x, DIEPCTL0 = 0x%x\n"
199 "\tbuf = 0x%p, pktcnt = %d, xfersize = %d\n",
201 readl(®->in_endp[ep_num].diepdma),
202 readl(®->in_endp[ep_num].dieptsiz),
203 readl(®->in_endp[ep_num].diepctl),
204 buf, pktcnt, length);
209 static void complete_rx(struct s3c_udc *dev, u8 ep_num)
211 struct s3c_ep *ep = &dev->ep[ep_num];
212 struct s3c_request *req = NULL;
213 u32 ep_tsr = 0, xfer_size = 0, is_short = 0;
214 u32 *p = the_controller->dma_buf[ep_index(ep)+1];
216 if (list_empty(&ep->queue)) {
217 debug_cond(DEBUG_OUT_EP != 0,
218 "%s: RX DMA done : NULL REQ on OUT EP-%d\n",
224 req = list_entry(ep->queue.next, struct s3c_request, queue);
225 ep_tsr = readl(®->out_endp[ep_num].doeptsiz);
227 if (ep_num == EP0_CON)
228 xfer_size = (ep_tsr & DOEPT_SIZ_XFER_SIZE_MAX_EP0);
230 xfer_size = (ep_tsr & DOEPT_SIZ_XFER_SIZE_MAX_EP);
232 xfer_size = ep->len - xfer_size;
234 invalidate_dcache_range((unsigned long) p,
235 (unsigned long) p + DMA_BUFFER_SIZE);
237 memcpy(ep->dma_buf, p, ep->len);
239 req->req.actual += min(xfer_size, req->req.length - req->req.actual);
240 is_short = (xfer_size < ep->ep.maxpacket);
242 debug_cond(DEBUG_OUT_EP != 0,
243 "%s: RX DMA done : ep = %d, rx bytes = %d/%d, "
244 "is_short = %d, DOEPTSIZ = 0x%x, remained bytes = %d\n",
245 __func__, ep_num, req->req.actual, req->req.length,
246 is_short, ep_tsr, xfer_size);
248 if (is_short || req->req.actual == req->req.length) {
249 if (ep_num == EP0_CON && dev->ep0state == DATA_STATE_RECV) {
250 debug_cond(DEBUG_OUT_EP != 0, " => Send ZLP\n");
251 s3c_udc_ep0_zlp(dev);
252 /* packet will be completed in complete_tx() */
253 dev->ep0state = WAIT_FOR_IN_COMPLETE;
257 if (!list_empty(&ep->queue)) {
258 req = list_entry(ep->queue.next,
259 struct s3c_request, queue);
260 debug_cond(DEBUG_OUT_EP != 0,
261 "%s: Next Rx request start...\n",
270 static void complete_tx(struct s3c_udc *dev, u8 ep_num)
272 struct s3c_ep *ep = &dev->ep[ep_num];
273 struct s3c_request *req;
274 u32 ep_tsr = 0, xfer_size = 0, is_short = 0;
277 if (dev->ep0state == WAIT_FOR_NULL_COMPLETE) {
278 dev->ep0state = WAIT_FOR_OUT_COMPLETE;
279 s3c_ep0_complete_out();
283 if (list_empty(&ep->queue)) {
284 debug_cond(DEBUG_IN_EP,
285 "%s: TX DMA done : NULL REQ on IN EP-%d\n",
291 req = list_entry(ep->queue.next, struct s3c_request, queue);
293 ep_tsr = readl(®->in_endp[ep_num].dieptsiz);
296 is_short = (xfer_size < ep->ep.maxpacket);
297 req->req.actual += min(xfer_size, req->req.length - req->req.actual);
299 debug_cond(DEBUG_IN_EP,
300 "%s: TX DMA done : ep = %d, tx bytes = %d/%d, "
301 "is_short = %d, DIEPTSIZ = 0x%x, remained bytes = %d\n",
302 __func__, ep_num, req->req.actual, req->req.length,
303 is_short, ep_tsr, xfer_size);
306 if (dev->ep0state == DATA_STATE_XMIT) {
307 debug_cond(DEBUG_IN_EP,
308 "%s: ep_num = %d, ep0stat =="
311 last = write_fifo_ep0(ep, req);
313 dev->ep0state = WAIT_FOR_COMPLETE;
314 } else if (dev->ep0state == WAIT_FOR_IN_COMPLETE) {
315 debug_cond(DEBUG_IN_EP,
316 "%s: ep_num = %d, completing request\n",
319 dev->ep0state = WAIT_FOR_SETUP;
320 } else if (dev->ep0state == WAIT_FOR_COMPLETE) {
321 debug_cond(DEBUG_IN_EP,
322 "%s: ep_num = %d, completing request\n",
325 dev->ep0state = WAIT_FOR_OUT_COMPLETE;
326 s3c_ep0_complete_out();
328 debug_cond(DEBUG_IN_EP,
329 "%s: ep_num = %d, invalid ep state\n",
335 if (req->req.actual == req->req.length)
338 if (!list_empty(&ep->queue)) {
339 req = list_entry(ep->queue.next, struct s3c_request, queue);
340 debug_cond(DEBUG_IN_EP,
341 "%s: Next Tx request start...\n", __func__);
346 static inline void s3c_udc_check_tx_queue(struct s3c_udc *dev, u8 ep_num)
348 struct s3c_ep *ep = &dev->ep[ep_num];
349 struct s3c_request *req;
351 debug_cond(DEBUG_IN_EP,
352 "%s: Check queue, ep_num = %d\n", __func__, ep_num);
354 if (!list_empty(&ep->queue)) {
355 req = list_entry(ep->queue.next, struct s3c_request, queue);
356 debug_cond(DEBUG_IN_EP,
357 "%s: Next Tx request(0x%p) start...\n",
365 debug_cond(DEBUG_IN_EP,
366 "%s: NULL REQ on IN EP-%d\n", __func__, ep_num);
373 static void process_ep_in_intr(struct s3c_udc *dev)
375 u32 ep_intr, ep_intr_status;
378 ep_intr = readl(®->daint);
379 debug_cond(DEBUG_IN_EP,
380 "*** %s: EP In interrupt : DAINT = 0x%x\n", __func__, ep_intr);
382 ep_intr &= DAINT_MASK;
385 if (ep_intr & DAINT_IN_EP_INT(1)) {
386 ep_intr_status = readl(®->in_endp[ep_num].diepint);
387 debug_cond(DEBUG_IN_EP,
388 "\tEP%d-IN : DIEPINT = 0x%x\n",
389 ep_num, ep_intr_status);
391 /* Interrupt Clear */
392 writel(ep_intr_status, ®->in_endp[ep_num].diepint);
394 if (ep_intr_status & TRANSFER_DONE) {
395 complete_tx(dev, ep_num);
399 WAIT_FOR_IN_COMPLETE)
400 dev->ep0state = WAIT_FOR_SETUP;
402 if (dev->ep0state == WAIT_FOR_SETUP)
405 /* continue transfer after
406 set_clear_halt for DMA mode */
407 if (clear_feature_flag == 1) {
408 s3c_udc_check_tx_queue(dev,
410 clear_feature_flag = 0;
420 static void process_ep_out_intr(struct s3c_udc *dev)
422 u32 ep_intr, ep_intr_status;
425 ep_intr = readl(®->daint);
426 debug_cond(DEBUG_OUT_EP != 0,
427 "*** %s: EP OUT interrupt : DAINT = 0x%x\n",
430 ep_intr = (ep_intr >> DAINT_OUT_BIT) & DAINT_MASK;
434 ep_intr_status = readl(®->out_endp[ep_num].doepint);
435 debug_cond(DEBUG_OUT_EP != 0,
436 "\tEP%d-OUT : DOEPINT = 0x%x\n",
437 ep_num, ep_intr_status);
439 /* Interrupt Clear */
440 writel(ep_intr_status, ®->out_endp[ep_num].doepint);
443 if (ep_intr_status & TRANSFER_DONE) {
445 WAIT_FOR_OUT_COMPLETE)
446 complete_rx(dev, ep_num);
448 dev->ep0state = WAIT_FOR_SETUP;
454 CTRL_OUT_EP_SETUP_PHASE_DONE) {
455 debug_cond(DEBUG_OUT_EP != 0,
456 "SETUP packet arrived\n");
460 if (ep_intr_status & TRANSFER_DONE)
461 complete_rx(dev, ep_num);
470 * usb client interrupt handler.
472 static int s3c_udc_irq(int irq, void *_dev)
474 struct s3c_udc *dev = _dev;
476 u32 usb_status, gintmsk;
479 spin_lock_irqsave(&dev->lock, flags);
481 intr_status = readl(®->gintsts);
482 gintmsk = readl(®->gintmsk);
484 debug_cond(DEBUG_ISR,
485 "\n*** %s : GINTSTS=0x%x(on state %s), GINTMSK : 0x%x,"
486 "DAINT : 0x%x, DAINTMSK : 0x%x\n",
487 __func__, intr_status, state_names[dev->ep0state], gintmsk,
488 readl(®->daint), readl(®->daintmsk));
491 spin_unlock_irqrestore(&dev->lock, flags);
495 if (intr_status & INT_ENUMDONE) {
496 debug_cond(DEBUG_ISR, "\tSpeed Detection interrupt\n");
498 writel(INT_ENUMDONE, ®->gintsts);
499 usb_status = (readl(®->dsts) & 0x6);
501 if (usb_status & (USB_FULL_30_60MHZ | USB_FULL_48MHZ)) {
502 debug_cond(DEBUG_ISR,
503 "\t\tFull Speed Detection\n");
504 set_max_pktsize(dev, USB_SPEED_FULL);
507 debug_cond(DEBUG_ISR,
508 "\t\tHigh Speed Detection : 0x%x\n",
510 set_max_pktsize(dev, USB_SPEED_HIGH);
514 if (intr_status & INT_EARLY_SUSPEND) {
515 debug_cond(DEBUG_ISR, "\tEarly suspend interrupt\n");
516 writel(INT_EARLY_SUSPEND, ®->gintsts);
519 if (intr_status & INT_SUSPEND) {
520 usb_status = readl(®->dsts);
521 debug_cond(DEBUG_ISR,
522 "\tSuspend interrupt :(DSTS):0x%x\n", usb_status);
523 writel(INT_SUSPEND, ®->gintsts);
525 if (dev->gadget.speed != USB_SPEED_UNKNOWN
527 if (dev->driver->suspend)
528 dev->driver->suspend(&dev->gadget);
530 /* HACK to let gadget detect disconnected state */
531 if (dev->driver->disconnect) {
532 spin_unlock_irqrestore(&dev->lock, flags);
533 dev->driver->disconnect(&dev->gadget);
534 spin_lock_irqsave(&dev->lock, flags);
539 if (intr_status & INT_RESUME) {
540 debug_cond(DEBUG_ISR, "\tResume interrupt\n");
541 writel(INT_RESUME, ®->gintsts);
543 if (dev->gadget.speed != USB_SPEED_UNKNOWN
545 && dev->driver->resume) {
547 dev->driver->resume(&dev->gadget);
551 if (intr_status & INT_RESET) {
552 usb_status = readl(®->gotgctl);
553 debug_cond(DEBUG_ISR,
554 "\tReset interrupt - (GOTGCTL):0x%x\n", usb_status);
555 writel(INT_RESET, ®->gintsts);
557 if ((usb_status & 0xc0000) == (0x3 << 18)) {
558 if (reset_available) {
559 debug_cond(DEBUG_ISR,
560 "\t\tOTG core got reset (%d)!!\n",
563 dev->ep0state = WAIT_FOR_SETUP;
571 debug_cond(DEBUG_ISR,
572 "\t\tRESET handling skipped\n");
576 if (intr_status & INT_IN_EP)
577 process_ep_in_intr(dev);
579 if (intr_status & INT_OUT_EP)
580 process_ep_out_intr(dev);
582 spin_unlock_irqrestore(&dev->lock, flags);
587 /** Queue one request
588 * Kickstart transfer if needed
590 static int s3c_queue(struct usb_ep *_ep, struct usb_request *_req,
593 struct s3c_request *req;
599 req = container_of(_req, struct s3c_request, req);
600 if (unlikely(!_req || !_req->complete || !_req->buf
601 || !list_empty(&req->queue))) {
603 debug("%s: bad params\n", __func__);
607 ep = container_of(_ep, struct s3c_ep, ep);
609 if (unlikely(!_ep || (!ep->desc && ep->ep.name != ep0name))) {
611 debug("%s: bad ep: %s, %d, %p\n", __func__,
612 ep->ep.name, !ep->desc, _ep);
616 ep_num = ep_index(ep);
618 if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
620 debug("%s: bogus device state %p\n", __func__, dev->driver);
624 spin_lock_irqsave(&dev->lock, flags);
626 _req->status = -EINPROGRESS;
629 /* kickstart this i/o queue? */
630 debug("\n*** %s: %s-%s req = %p, len = %d, buf = %p"
631 "Q empty = %d, stopped = %d\n",
632 __func__, _ep->name, ep_is_in(ep) ? "in" : "out",
633 _req, _req->length, _req->buf,
634 list_empty(&ep->queue), ep->stopped);
638 int i, len = _req->length;
643 for (i = 0; i < len; i++) {
644 printf("%02x", ((u8 *)_req->buf)[i]);
652 if (list_empty(&ep->queue) && !ep->stopped) {
656 list_add_tail(&req->queue, &ep->queue);
657 s3c_ep0_kick(dev, ep);
660 } else if (ep_is_in(ep)) {
661 gintsts = readl(®->gintsts);
662 debug_cond(DEBUG_IN_EP,
663 "%s: ep_is_in, S3C_UDC_OTG_GINTSTS=0x%x\n",
668 gintsts = readl(®->gintsts);
669 debug_cond(DEBUG_OUT_EP != 0,
670 "%s:ep_is_out, S3C_UDC_OTG_GINTSTS=0x%x\n",
677 /* pio or dma irq handler advances the queue. */
678 if (likely(req != 0))
679 list_add_tail(&req->queue, &ep->queue);
681 spin_unlock_irqrestore(&dev->lock, flags);
686 /****************************************************************/
687 /* End Point 0 related functions */
688 /****************************************************************/
690 /* return: 0 = still running, 1 = completed, negative = errno */
691 static int write_fifo_ep0(struct s3c_ep *ep, struct s3c_request *req)
697 max = ep_maxpacket(ep);
699 debug_cond(DEBUG_EP0 != 0, "%s: max = %d\n", __func__, max);
701 count = setdma_tx(ep, req);
703 /* last packet is usually short (or a zlp) */
704 if (likely(count != max))
707 if (likely(req->req.length != req->req.actual + count)
714 debug_cond(DEBUG_EP0 != 0,
715 "%s: wrote %s %d bytes%s %d left %p\n", __func__,
718 req->req.length - req->req.actual - count, req);
720 /* requests complete when all IN data is in the FIFO */
722 ep->dev->ep0state = WAIT_FOR_SETUP;
729 int s3c_fifo_read(struct s3c_ep *ep, u32 *cp, int max)
733 bytes = sizeof(struct usb_ctrlrequest);
735 invalidate_dcache_range((unsigned long) ep->dev->dma_buf[ep_index(ep)],
736 (unsigned long) ep->dev->dma_buf[ep_index(ep)]
739 debug_cond(DEBUG_EP0 != 0,
740 "%s: bytes=%d, ep_index=%d %p\n", __func__,
741 bytes, ep_index(ep), ep->dev->dma_buf[ep_index(ep)]);
747 * udc_set_address - set the USB address for this device
750 * Called from control endpoint function
751 * after it decodes a set address setup packet.
753 static void udc_set_address(struct s3c_udc *dev, unsigned char address)
755 u32 ctrl = readl(®->dcfg);
756 writel(DEVICE_ADDRESS(address) | ctrl, ®->dcfg);
758 s3c_udc_ep0_zlp(dev);
760 debug_cond(DEBUG_EP0 != 0,
761 "%s: USB OTG 2.0 Device address=%d, DCFG=0x%x\n",
762 __func__, address, readl(®->dcfg));
764 dev->usb_address = address;
767 static inline void s3c_udc_ep0_set_stall(struct s3c_ep *ep)
773 ep_ctrl = readl(®->in_endp[EP0_CON].diepctl);
775 /* set the disable and stall bits */
776 if (ep_ctrl & DEPCTL_EPENA)
777 ep_ctrl |= DEPCTL_EPDIS;
779 ep_ctrl |= DEPCTL_STALL;
781 writel(ep_ctrl, ®->in_endp[EP0_CON].diepctl);
783 debug_cond(DEBUG_EP0 != 0,
784 "%s: set ep%d stall, DIEPCTL0 = 0x%p\n",
785 __func__, ep_index(ep), ®->in_endp[EP0_CON].diepctl);
787 * The application can only set this bit, and the core clears it,
788 * when a SETUP token is received for this endpoint
790 dev->ep0state = WAIT_FOR_SETUP;
795 static void s3c_ep0_read(struct s3c_udc *dev)
797 struct s3c_request *req;
798 struct s3c_ep *ep = &dev->ep[0];
800 if (!list_empty(&ep->queue)) {
801 req = list_entry(ep->queue.next, struct s3c_request, queue);
804 debug("%s: ---> BUG\n", __func__);
809 debug_cond(DEBUG_EP0 != 0,
810 "%s: req = %p, req.length = 0x%x, req.actual = 0x%x\n",
811 __func__, req, req->req.length, req->req.actual);
813 if (req->req.length == 0) {
814 /* zlp for Set_configuration, Set_interface,
815 * or Bulk-Only mass storge reset */
818 s3c_udc_ep0_zlp(dev);
820 debug_cond(DEBUG_EP0 != 0,
821 "%s: req.length = 0, bRequest = %d\n",
822 __func__, usb_ctrl->bRequest);
832 static int s3c_ep0_write(struct s3c_udc *dev)
834 struct s3c_request *req;
835 struct s3c_ep *ep = &dev->ep[0];
836 int ret, need_zlp = 0;
838 if (list_empty(&ep->queue))
841 req = list_entry(ep->queue.next, struct s3c_request, queue);
844 debug_cond(DEBUG_EP0 != 0, "%s: NULL REQ\n", __func__);
848 debug_cond(DEBUG_EP0 != 0,
849 "%s: req = %p, req.length = 0x%x, req.actual = 0x%x\n",
850 __func__, req, req->req.length, req->req.actual);
852 if (req->req.length - req->req.actual == ep0_fifo_size) {
853 /* Next write will end with the packet size, */
854 /* so we need Zero-length-packet */
858 ret = write_fifo_ep0(ep, req);
860 if ((ret == 1) && !need_zlp) {
862 dev->ep0state = WAIT_FOR_COMPLETE;
863 debug_cond(DEBUG_EP0 != 0,
864 "%s: finished, waiting for status\n", __func__);
867 dev->ep0state = DATA_STATE_XMIT;
868 debug_cond(DEBUG_EP0 != 0,
869 "%s: not finished\n", __func__);
877 int s3c_udc_get_status(struct s3c_udc *dev,
878 struct usb_ctrlrequest *crq)
880 u8 ep_num = crq->wIndex & 0x7F;
882 u32 *p = the_controller->dma_buf[1];
884 debug_cond(DEBUG_SETUP != 0,
885 "%s: *** USB_REQ_GET_STATUS\n", __func__);
886 printf("crq->brequest:0x%x\n", crq->bRequestType & USB_RECIP_MASK);
887 switch (crq->bRequestType & USB_RECIP_MASK) {
888 case USB_RECIP_INTERFACE:
890 debug_cond(DEBUG_SETUP != 0,
891 "\tGET_STATUS:USB_RECIP_INTERFACE, g_stauts = %d\n",
895 case USB_RECIP_DEVICE:
896 g_status = 0x1; /* Self powered */
897 debug_cond(DEBUG_SETUP != 0,
898 "\tGET_STATUS: USB_RECIP_DEVICE, g_stauts = %d\n",
902 case USB_RECIP_ENDPOINT:
903 if (crq->wLength > 2) {
904 debug_cond(DEBUG_SETUP != 0,
905 "\tGET_STATUS:Not support EP or wLength\n");
909 g_status = dev->ep[ep_num].stopped;
910 debug_cond(DEBUG_SETUP != 0,
911 "\tGET_STATUS: USB_RECIP_ENDPOINT, g_stauts = %d\n",
920 memcpy(p, &g_status, sizeof(g_status));
922 flush_dcache_range((unsigned long) p,
923 (unsigned long) p + DMA_BUFFER_SIZE);
925 writel(the_controller->dma_addr[1], ®->in_endp[EP0_CON].diepdma);
926 writel(DIEPT_SIZ_PKT_CNT(1) | DIEPT_SIZ_XFER_SIZE(2),
927 ®->in_endp[EP0_CON].dieptsiz);
929 ep_ctrl = readl(®->in_endp[EP0_CON].diepctl);
930 writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK,
931 ®->in_endp[EP0_CON].diepctl);
932 dev->ep0state = WAIT_FOR_NULL_COMPLETE;
937 static void s3c_udc_set_nak(struct s3c_ep *ep)
942 ep_num = ep_index(ep);
943 debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type);
946 ep_ctrl = readl(®->in_endp[ep_num].diepctl);
947 ep_ctrl |= DEPCTL_SNAK;
948 writel(ep_ctrl, ®->in_endp[ep_num].diepctl);
949 debug("%s: set NAK, DIEPCTL%d = 0x%x\n",
950 __func__, ep_num, readl(®->in_endp[ep_num].diepctl));
952 ep_ctrl = readl(®->out_endp[ep_num].doepctl);
953 ep_ctrl |= DEPCTL_SNAK;
954 writel(ep_ctrl, ®->out_endp[ep_num].doepctl);
955 debug("%s: set NAK, DOEPCTL%d = 0x%x\n",
956 __func__, ep_num, readl(®->out_endp[ep_num].doepctl));
963 void s3c_udc_ep_set_stall(struct s3c_ep *ep)
968 ep_num = ep_index(ep);
969 debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type);
972 ep_ctrl = readl(®->in_endp[ep_num].diepctl);
974 /* set the disable and stall bits */
975 if (ep_ctrl & DEPCTL_EPENA)
976 ep_ctrl |= DEPCTL_EPDIS;
978 ep_ctrl |= DEPCTL_STALL;
980 writel(ep_ctrl, ®->in_endp[ep_num].diepctl);
981 debug("%s: set stall, DIEPCTL%d = 0x%x\n",
982 __func__, ep_num, readl(®->in_endp[ep_num].diepctl));
985 ep_ctrl = readl(®->out_endp[ep_num].doepctl);
987 /* set the stall bit */
988 ep_ctrl |= DEPCTL_STALL;
990 writel(ep_ctrl, ®->out_endp[ep_num].doepctl);
991 debug("%s: set stall, DOEPCTL%d = 0x%x\n",
992 __func__, ep_num, readl(®->out_endp[ep_num].doepctl));
998 void s3c_udc_ep_clear_stall(struct s3c_ep *ep)
1003 ep_num = ep_index(ep);
1004 debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type);
1007 ep_ctrl = readl(®->in_endp[ep_num].diepctl);
1009 /* clear stall bit */
1010 ep_ctrl &= ~DEPCTL_STALL;
1013 * USB Spec 9.4.5: For endpoints using data toggle, regardless
1014 * of whether an endpoint has the Halt feature set, a
1015 * ClearFeature(ENDPOINT_HALT) request always results in the
1016 * data toggle being reinitialized to DATA0.
1018 if (ep->bmAttributes == USB_ENDPOINT_XFER_INT
1019 || ep->bmAttributes == USB_ENDPOINT_XFER_BULK) {
1020 ep_ctrl |= DEPCTL_SETD0PID; /* DATA0 */
1023 writel(ep_ctrl, ®->in_endp[ep_num].diepctl);
1024 debug("%s: cleared stall, DIEPCTL%d = 0x%x\n",
1025 __func__, ep_num, readl(®->in_endp[ep_num].diepctl));
1028 ep_ctrl = readl(®->out_endp[ep_num].doepctl);
1030 /* clear stall bit */
1031 ep_ctrl &= ~DEPCTL_STALL;
1033 if (ep->bmAttributes == USB_ENDPOINT_XFER_INT
1034 || ep->bmAttributes == USB_ENDPOINT_XFER_BULK) {
1035 ep_ctrl |= DEPCTL_SETD0PID; /* DATA0 */
1038 writel(ep_ctrl, ®->out_endp[ep_num].doepctl);
1039 debug("%s: cleared stall, DOEPCTL%d = 0x%x\n",
1040 __func__, ep_num, readl(®->out_endp[ep_num].doepctl));
1046 static int s3c_udc_set_halt(struct usb_ep *_ep, int value)
1049 struct s3c_udc *dev;
1050 unsigned long flags;
1053 ep = container_of(_ep, struct s3c_ep, ep);
1054 ep_num = ep_index(ep);
1056 if (unlikely(!_ep || !ep->desc || ep_num == EP0_CON ||
1057 ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC)) {
1058 debug("%s: %s bad ep or descriptor\n", __func__, ep->ep.name);
1062 /* Attempt to halt IN ep will fail if any transfer requests
1063 * are still queue */
1064 if (value && ep_is_in(ep) && !list_empty(&ep->queue)) {
1065 debug("%s: %s queue not empty, req = %p\n",
1066 __func__, ep->ep.name,
1067 list_entry(ep->queue.next, struct s3c_request, queue));
1073 debug("%s: ep_num = %d, value = %d\n", __func__, ep_num, value);
1075 spin_lock_irqsave(&dev->lock, flags);
1079 s3c_udc_ep_clear_stall(ep);
1082 dev->ep0state = WAIT_FOR_SETUP;
1085 s3c_udc_ep_set_stall(ep);
1088 spin_unlock_irqrestore(&dev->lock, flags);
1093 void s3c_udc_ep_activate(struct s3c_ep *ep)
1096 u32 ep_ctrl = 0, daintmsk = 0;
1098 ep_num = ep_index(ep);
1100 /* Read DEPCTLn register */
1102 ep_ctrl = readl(®->in_endp[ep_num].diepctl);
1103 daintmsk = 1 << ep_num;
1105 ep_ctrl = readl(®->out_endp[ep_num].doepctl);
1106 daintmsk = (1 << ep_num) << DAINT_OUT_BIT;
1109 debug("%s: EPCTRL%d = 0x%x, ep_is_in = %d\n",
1110 __func__, ep_num, ep_ctrl, ep_is_in(ep));
1112 /* If the EP is already active don't change the EP Control
1114 if (!(ep_ctrl & DEPCTL_USBACTEP)) {
1115 ep_ctrl = (ep_ctrl & ~DEPCTL_TYPE_MASK) |
1116 (ep->bmAttributes << DEPCTL_TYPE_BIT);
1117 ep_ctrl = (ep_ctrl & ~DEPCTL_MPS_MASK) |
1118 (ep->ep.maxpacket << DEPCTL_MPS_BIT);
1119 ep_ctrl |= (DEPCTL_SETD0PID | DEPCTL_USBACTEP | DEPCTL_SNAK);
1122 writel(ep_ctrl, ®->in_endp[ep_num].diepctl);
1123 debug("%s: USB Ative EP%d, DIEPCTRL%d = 0x%x\n",
1124 __func__, ep_num, ep_num,
1125 readl(®->in_endp[ep_num].diepctl));
1127 writel(ep_ctrl, ®->out_endp[ep_num].doepctl);
1128 debug("%s: USB Ative EP%d, DOEPCTRL%d = 0x%x\n",
1129 __func__, ep_num, ep_num,
1130 readl(®->out_endp[ep_num].doepctl));
1134 /* Unmask EP Interrtupt */
1135 writel(readl(®->daintmsk)|daintmsk, ®->daintmsk);
1136 debug("%s: DAINTMSK = 0x%x\n", __func__, readl(®->daintmsk));
1140 static int s3c_udc_clear_feature(struct usb_ep *_ep)
1142 struct s3c_udc *dev;
1146 ep = container_of(_ep, struct s3c_ep, ep);
1147 ep_num = ep_index(ep);
1150 debug_cond(DEBUG_SETUP != 0,
1151 "%s: ep_num = %d, is_in = %d, clear_feature_flag = %d\n",
1152 __func__, ep_num, ep_is_in(ep), clear_feature_flag);
1154 if (usb_ctrl->wLength != 0) {
1155 debug_cond(DEBUG_SETUP != 0,
1156 "\tCLEAR_FEATURE: wLength is not zero.....\n");
1160 switch (usb_ctrl->bRequestType & USB_RECIP_MASK) {
1161 case USB_RECIP_DEVICE:
1162 switch (usb_ctrl->wValue) {
1163 case USB_DEVICE_REMOTE_WAKEUP:
1164 debug_cond(DEBUG_SETUP != 0,
1165 "\tOFF:USB_DEVICE_REMOTE_WAKEUP\n");
1168 case USB_DEVICE_TEST_MODE:
1169 debug_cond(DEBUG_SETUP != 0,
1170 "\tCLEAR_FEATURE: USB_DEVICE_TEST_MODE\n");
1171 /** @todo Add CLEAR_FEATURE for TEST modes. */
1175 s3c_udc_ep0_zlp(dev);
1178 case USB_RECIP_ENDPOINT:
1179 debug_cond(DEBUG_SETUP != 0,
1180 "\tCLEAR_FEATURE:USB_RECIP_ENDPOINT, wValue = %d\n",
1183 if (usb_ctrl->wValue == USB_ENDPOINT_HALT) {
1185 s3c_udc_ep0_set_stall(ep);
1189 s3c_udc_ep0_zlp(dev);
1191 s3c_udc_ep_clear_stall(ep);
1192 s3c_udc_ep_activate(ep);
1195 clear_feature_num = ep_num;
1196 clear_feature_flag = 1;
1204 static int s3c_udc_set_feature(struct usb_ep *_ep)
1206 struct s3c_udc *dev;
1210 ep = container_of(_ep, struct s3c_ep, ep);
1211 ep_num = ep_index(ep);
1214 debug_cond(DEBUG_SETUP != 0,
1215 "%s: *** USB_REQ_SET_FEATURE , ep_num = %d\n",
1218 if (usb_ctrl->wLength != 0) {
1219 debug_cond(DEBUG_SETUP != 0,
1220 "\tSET_FEATURE: wLength is not zero.....\n");
1224 switch (usb_ctrl->bRequestType & USB_RECIP_MASK) {
1225 case USB_RECIP_DEVICE:
1226 switch (usb_ctrl->wValue) {
1227 case USB_DEVICE_REMOTE_WAKEUP:
1228 debug_cond(DEBUG_SETUP != 0,
1229 "\tSET_FEATURE:USB_DEVICE_REMOTE_WAKEUP\n");
1231 case USB_DEVICE_B_HNP_ENABLE:
1232 debug_cond(DEBUG_SETUP != 0,
1233 "\tSET_FEATURE: USB_DEVICE_B_HNP_ENABLE\n");
1236 case USB_DEVICE_A_HNP_SUPPORT:
1237 /* RH port supports HNP */
1238 debug_cond(DEBUG_SETUP != 0,
1239 "\tSET_FEATURE:USB_DEVICE_A_HNP_SUPPORT\n");
1242 case USB_DEVICE_A_ALT_HNP_SUPPORT:
1243 /* other RH port does */
1244 debug_cond(DEBUG_SETUP != 0,
1245 "\tSET: USB_DEVICE_A_ALT_HNP_SUPPORT\n");
1249 s3c_udc_ep0_zlp(dev);
1252 case USB_RECIP_INTERFACE:
1253 debug_cond(DEBUG_SETUP != 0,
1254 "\tSET_FEATURE: USB_RECIP_INTERFACE\n");
1257 case USB_RECIP_ENDPOINT:
1258 debug_cond(DEBUG_SETUP != 0,
1259 "\tSET_FEATURE: USB_RECIP_ENDPOINT\n");
1260 if (usb_ctrl->wValue == USB_ENDPOINT_HALT) {
1262 s3c_udc_ep0_set_stall(ep);
1266 s3c_udc_ep_set_stall(ep);
1269 s3c_udc_ep0_zlp(dev);
1277 * WAIT_FOR_SETUP (OUT_PKT_RDY)
1279 void s3c_ep0_setup(struct s3c_udc *dev)
1281 struct s3c_ep *ep = &dev->ep[0];
1285 /* Nuke all previous transfers */
1288 /* read control req from fifo (8 bytes) */
1289 s3c_fifo_read(ep, (u32 *)usb_ctrl, 8);
1291 debug_cond(DEBUG_SETUP != 0,
1292 "%s: bRequestType = 0x%x(%s), bRequest = 0x%x"
1293 "\twLength = 0x%x, wValue = 0x%x, wIndex= 0x%x\n",
1294 __func__, usb_ctrl->bRequestType,
1295 (usb_ctrl->bRequestType & USB_DIR_IN) ? "IN" : "OUT",
1297 usb_ctrl->wLength, usb_ctrl->wValue, usb_ctrl->wIndex);
1301 int i, len = sizeof(*usb_ctrl);
1302 char *p = (char *)usb_ctrl;
1305 for (i = 0; i < len; i++) {
1306 printf("%02x", ((u8 *)p)[i]);
1314 if (usb_ctrl->bRequest == GET_MAX_LUN_REQUEST &&
1315 usb_ctrl->wLength != 1) {
1316 debug_cond(DEBUG_SETUP != 0,
1317 "\t%s:GET_MAX_LUN_REQUEST:invalid",
1319 debug_cond(DEBUG_SETUP != 0,
1320 "wLength = %d, setup returned\n",
1323 s3c_udc_ep0_set_stall(ep);
1324 dev->ep0state = WAIT_FOR_SETUP;
1327 } else if (usb_ctrl->bRequest == BOT_RESET_REQUEST &&
1328 usb_ctrl->wLength != 0) {
1329 /* Bulk-Only *mass storge reset of class-specific request */
1330 debug_cond(DEBUG_SETUP != 0,
1331 "%s:BOT Rest:invalid wLength =%d, setup returned\n",
1332 __func__, usb_ctrl->wLength);
1334 s3c_udc_ep0_set_stall(ep);
1335 dev->ep0state = WAIT_FOR_SETUP;
1340 /* Set direction of EP0 */
1341 if (likely(usb_ctrl->bRequestType & USB_DIR_IN)) {
1342 ep->bEndpointAddress |= USB_DIR_IN;
1344 ep->bEndpointAddress &= ~USB_DIR_IN;
1346 /* cope with automagic for some standard requests. */
1347 dev->req_std = (usb_ctrl->bRequestType & USB_TYPE_MASK)
1348 == USB_TYPE_STANDARD;
1350 dev->req_pending = 1;
1352 /* Handle some SETUP packets ourselves */
1354 switch (usb_ctrl->bRequest) {
1355 case USB_REQ_SET_ADDRESS:
1356 debug_cond(DEBUG_SETUP != 0,
1357 "%s: *** USB_REQ_SET_ADDRESS (%d)\n",
1358 __func__, usb_ctrl->wValue);
1359 if (usb_ctrl->bRequestType
1360 != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1363 udc_set_address(dev, usb_ctrl->wValue);
1366 case USB_REQ_SET_CONFIGURATION:
1367 debug_cond(DEBUG_SETUP != 0,
1368 "=====================================\n");
1369 debug_cond(DEBUG_SETUP != 0,
1370 "%s: USB_REQ_SET_CONFIGURATION (%d)\n",
1371 __func__, usb_ctrl->wValue);
1373 if (usb_ctrl->bRequestType == USB_RECIP_DEVICE)
1374 reset_available = 1;
1378 case USB_REQ_GET_DESCRIPTOR:
1379 debug_cond(DEBUG_SETUP != 0,
1380 "%s: *** USB_REQ_GET_DESCRIPTOR\n",
1384 case USB_REQ_SET_INTERFACE:
1385 debug_cond(DEBUG_SETUP != 0,
1386 "%s: *** USB_REQ_SET_INTERFACE (%d)\n",
1387 __func__, usb_ctrl->wValue);
1389 if (usb_ctrl->bRequestType == USB_RECIP_INTERFACE)
1390 reset_available = 1;
1394 case USB_REQ_GET_CONFIGURATION:
1395 debug_cond(DEBUG_SETUP != 0,
1396 "%s: *** USB_REQ_GET_CONFIGURATION\n",
1400 case USB_REQ_GET_STATUS:
1401 if (!s3c_udc_get_status(dev, usb_ctrl))
1406 case USB_REQ_CLEAR_FEATURE:
1407 ep_num = usb_ctrl->wIndex & 0x7f;
1409 if (!s3c_udc_clear_feature(&dev->ep[ep_num].ep))
1414 case USB_REQ_SET_FEATURE:
1415 ep_num = usb_ctrl->wIndex & 0x7f;
1417 if (!s3c_udc_set_feature(&dev->ep[ep_num].ep))
1423 debug_cond(DEBUG_SETUP != 0,
1424 "%s: *** Default of usb_ctrl->bRequest=0x%x"
1425 "happened.\n", __func__, usb_ctrl->bRequest);
1431 if (likely(dev->driver)) {
1432 /* device-2-host (IN) or no data setup command,
1433 * process immediately */
1434 debug_cond(DEBUG_SETUP != 0,
1435 "%s:usb_ctrlreq will be passed to fsg_setup()\n",
1438 spin_unlock(&dev->lock);
1439 i = dev->driver->setup(&dev->gadget, usb_ctrl);
1440 spin_lock(&dev->lock);
1443 /* setup processing failed, force stall */
1444 s3c_udc_ep0_set_stall(ep);
1445 dev->ep0state = WAIT_FOR_SETUP;
1447 debug_cond(DEBUG_SETUP != 0,
1448 "\tdev->driver->setup failed (%d),"
1450 i, usb_ctrl->bRequest);
1453 } else if (dev->req_pending) {
1454 dev->req_pending = 0;
1455 debug_cond(DEBUG_SETUP != 0,
1456 "\tdev->req_pending...\n");
1459 debug_cond(DEBUG_SETUP != 0,
1460 "\tep0state = %s\n", state_names[dev->ep0state]);
1466 * handle ep0 interrupt
1468 static void s3c_handle_ep0(struct s3c_udc *dev)
1470 if (dev->ep0state == WAIT_FOR_SETUP) {
1471 debug_cond(DEBUG_OUT_EP != 0,
1472 "%s: WAIT_FOR_SETUP\n", __func__);
1476 debug_cond(DEBUG_OUT_EP != 0,
1477 "%s: strange state!!(state = %s)\n",
1478 __func__, state_names[dev->ep0state]);
1482 static void s3c_ep0_kick(struct s3c_udc *dev, struct s3c_ep *ep)
1484 debug_cond(DEBUG_EP0 != 0,
1485 "%s: ep_is_in = %d\n", __func__, ep_is_in(ep));
1487 dev->ep0state = DATA_STATE_XMIT;
1491 dev->ep0state = DATA_STATE_RECV;