2 * drivers/usb/gadget/s3c_udc_otg_xfer_dma.c
3 * Samsung S3C on-chip full/high speed USB OTG 2.0 device controllers
5 * Copyright (C) 2009 for Samsung Electronics
7 * BSP Support for Samsung's UDC driver
9 * git://git.kernel.org/pub/scm/linux/kernel/git/kki_ap/linux-2.6-samsung.git
11 * State machine bugfixes:
12 * Marek Szyprowski <m.szyprowski@samsung.com>
15 * Marek Szyprowski <m.szyprowski@samsung.com>
16 * Lukasz Majewski <l.majewski@samsumg.com>
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 2 of the License, or
21 * (at your option) any later version.
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
34 static u8 clear_feature_num;
35 int clear_feature_flag;
37 /* Bulk-Only Mass Storage Reset (class-specific request) */
38 #define GET_MAX_LUN_REQUEST 0xFE
39 #define BOT_RESET_REQUEST 0xFF
41 static inline void s3c_udc_ep0_zlp(struct s3c_udc *dev)
45 flush_dcache_range((unsigned long) usb_ctrl_dma_addr,
46 (unsigned long) usb_ctrl_dma_addr
49 writel(usb_ctrl_dma_addr, ®->in_endp[EP0_CON].diepdma);
50 writel(DIEPT_SIZ_PKT_CNT(1), ®->in_endp[EP0_CON].dieptsiz);
52 ep_ctrl = readl(®->in_endp[EP0_CON].diepctl);
53 writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK,
54 ®->in_endp[EP0_CON].diepctl);
56 DEBUG_EP0("%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
57 __func__, readl(®->in_endp[EP0_CON].diepctl));
58 dev->ep0state = WAIT_FOR_IN_COMPLETE;
61 void s3c_udc_pre_setup(void)
65 debug_cond(DEBUG_IN_EP, "%s : Prepare Setup packets.\n", __func__);
67 invalidate_dcache_range((unsigned long) usb_ctrl_dma_addr,
68 (unsigned long) usb_ctrl_dma_addr
71 writel(DOEPT_SIZ_PKT_CNT(1) | sizeof(struct usb_ctrlrequest),
72 ®->out_endp[EP0_CON].doeptsiz);
73 writel(usb_ctrl_dma_addr, ®->out_endp[EP0_CON].doepdma);
75 ep_ctrl = readl(®->out_endp[EP0_CON].doepctl);
76 writel(ep_ctrl|DEPCTL_EPENA, ®->out_endp[EP0_CON].doepctl);
78 DEBUG_EP0("%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
79 __func__, readl(®->in_endp[EP0_CON].diepctl));
80 DEBUG_EP0("%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
81 __func__, readl(®->out_endp[EP0_CON].doepctl));
85 static inline void s3c_ep0_complete_out(void)
89 DEBUG_EP0("%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
90 __func__, readl(®->in_endp[EP0_CON].diepctl));
91 DEBUG_EP0("%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
92 __func__, readl(®->out_endp[EP0_CON].doepctl));
94 debug_cond(DEBUG_IN_EP,
95 "%s : Prepare Complete Out packet.\n", __func__);
97 invalidate_dcache_range((unsigned long) usb_ctrl_dma_addr,
98 (unsigned long) usb_ctrl_dma_addr
101 writel(DOEPT_SIZ_PKT_CNT(1) | sizeof(struct usb_ctrlrequest),
102 ®->out_endp[EP0_CON].doeptsiz);
103 writel(usb_ctrl_dma_addr, ®->out_endp[EP0_CON].doepdma);
105 ep_ctrl = readl(®->out_endp[EP0_CON].doepctl);
106 writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK,
107 ®->out_endp[EP0_CON].doepctl);
109 DEBUG_EP0("%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
110 __func__, readl(®->in_endp[EP0_CON].diepctl));
111 DEBUG_EP0("%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
112 __func__, readl(®->out_endp[EP0_CON].doepctl));
117 static int setdma_rx(struct s3c_ep *ep, struct s3c_request *req)
121 u32 ep_num = ep_index(ep);
123 buf = req->req.buf + req->req.actual;
125 length = min(req->req.length - req->req.actual, (int)ep->ep.maxpacket);
130 invalidate_dcache_range((unsigned long) ep->dev->dma_buf[ep_num],
131 (unsigned long) ep->dev->dma_buf[ep_num]
137 pktcnt = (length - 1)/(ep->ep.maxpacket) + 1;
140 ctrl = readl(®->out_endp[ep_num].doepctl);
142 writel(the_controller->dma_addr[ep_index(ep)+1],
143 ®->out_endp[ep_num].doepdma);
144 writel(DOEPT_SIZ_PKT_CNT(pktcnt) | DOEPT_SIZ_XFER_SIZE(length),
145 ®->out_endp[ep_num].doeptsiz);
146 writel(DEPCTL_EPENA|DEPCTL_CNAK|ctrl, ®->out_endp[ep_num].doepctl);
148 DEBUG_OUT_EP("%s: EP%d RX DMA start : DOEPDMA = 0x%x,"
149 "DOEPTSIZ = 0x%x, DOEPCTL = 0x%x\n"
150 "\tbuf = 0x%p, pktcnt = %d, xfersize = %d\n",
152 readl(®->out_endp[ep_num].doepdma),
153 readl(®->out_endp[ep_num].doeptsiz),
154 readl(®->out_endp[ep_num].doepctl),
155 buf, pktcnt, length);
160 int setdma_tx(struct s3c_ep *ep, struct s3c_request *req)
164 u32 ep_num = ep_index(ep);
165 u32 *p = the_controller->dma_buf[ep_index(ep)+1];
167 buf = req->req.buf + req->req.actual;
168 length = req->req.length - req->req.actual;
170 if (ep_num == EP0_CON)
171 length = min_t(length, (u32)ep_maxpacket(ep));
175 memcpy(p, ep->dma_buf, length);
177 flush_dcache_range((unsigned long) p ,
178 (unsigned long) p + DMA_BUFFER_SIZE);
183 pktcnt = (length - 1)/(ep->ep.maxpacket) + 1;
185 /* Flush the endpoint's Tx FIFO */
186 writel(TX_FIFO_NUMBER(ep->fifo_num), ®->grstctl);
187 writel(TX_FIFO_NUMBER(ep->fifo_num) | TX_FIFO_FLUSH, ®->grstctl);
188 while (readl(®->grstctl) & TX_FIFO_FLUSH)
191 writel(the_controller->dma_addr[ep_index(ep)+1],
192 ®->in_endp[ep_num].diepdma);
193 writel(DIEPT_SIZ_PKT_CNT(pktcnt) | DIEPT_SIZ_XFER_SIZE(length),
194 ®->in_endp[ep_num].dieptsiz);
196 ctrl = readl(®->in_endp[ep_num].diepctl);
198 /* Write the FIFO number to be used for this endpoint */
199 ctrl &= DIEPCTL_TX_FIFO_NUM_MASK;
200 ctrl |= DIEPCTL_TX_FIFO_NUM(ep->fifo_num);
202 /* Clear reserved (Next EP) bits */
203 ctrl = (ctrl&~(EP_MASK<<DEPCTL_NEXT_EP_BIT));
205 writel(DEPCTL_EPENA|DEPCTL_CNAK|ctrl, ®->in_endp[ep_num].diepctl);
207 debug_cond(DEBUG_IN_EP,
208 "%s:EP%d TX DMA start : DIEPDMA0 = 0x%x,"
209 "DIEPTSIZ0 = 0x%x, DIEPCTL0 = 0x%x\n"
210 "\tbuf = 0x%p, pktcnt = %d, xfersize = %d\n",
212 readl(®->in_endp[ep_num].diepdma),
213 readl(®->in_endp[ep_num].dieptsiz),
214 readl(®->in_endp[ep_num].diepctl),
215 buf, pktcnt, length);
220 static void complete_rx(struct s3c_udc *dev, u8 ep_num)
222 struct s3c_ep *ep = &dev->ep[ep_num];
223 struct s3c_request *req = NULL;
224 u32 ep_tsr = 0, xfer_size = 0, is_short = 0;
225 u32 *p = the_controller->dma_buf[ep_index(ep)+1];
227 if (list_empty(&ep->queue)) {
228 DEBUG_OUT_EP("%s: RX DMA done : NULL REQ on OUT EP-%d\n",
234 req = list_entry(ep->queue.next, struct s3c_request, queue);
235 ep_tsr = readl(®->out_endp[ep_num].doeptsiz);
237 if (ep_num == EP0_CON)
238 xfer_size = (ep_tsr & DOEPT_SIZ_XFER_SIZE_MAX_EP0);
240 xfer_size = (ep_tsr & DOEPT_SIZ_XFER_SIZE_MAX_EP);
242 xfer_size = ep->len - xfer_size;
244 invalidate_dcache_range((unsigned long) p,
245 (unsigned long) p + DMA_BUFFER_SIZE);
247 memcpy(ep->dma_buf, p, ep->len);
249 req->req.actual += min(xfer_size, req->req.length - req->req.actual);
250 is_short = (xfer_size < ep->ep.maxpacket);
252 DEBUG_OUT_EP("%s: RX DMA done : ep = %d, rx bytes = %d/%d, "
253 "is_short = %d, DOEPTSIZ = 0x%x, remained bytes = %d\n",
254 __func__, ep_num, req->req.actual, req->req.length,
255 is_short, ep_tsr, xfer_size);
257 if (is_short || req->req.actual == req->req.length) {
258 if (ep_num == EP0_CON && dev->ep0state == DATA_STATE_RECV) {
259 DEBUG_OUT_EP(" => Send ZLP\n");
260 s3c_udc_ep0_zlp(dev);
261 /* packet will be completed in complete_tx() */
262 dev->ep0state = WAIT_FOR_IN_COMPLETE;
266 if (!list_empty(&ep->queue)) {
267 req = list_entry(ep->queue.next,
268 struct s3c_request, queue);
269 DEBUG_OUT_EP("%s: Next Rx request start...\n",
278 static void complete_tx(struct s3c_udc *dev, u8 ep_num)
280 struct s3c_ep *ep = &dev->ep[ep_num];
281 struct s3c_request *req;
282 u32 ep_tsr = 0, xfer_size = 0, is_short = 0;
285 if (dev->ep0state == WAIT_FOR_NULL_COMPLETE) {
286 dev->ep0state = WAIT_FOR_OUT_COMPLETE;
287 s3c_ep0_complete_out();
291 if (list_empty(&ep->queue)) {
292 debug_cond(DEBUG_IN_EP,
293 "%s: TX DMA done : NULL REQ on IN EP-%d\n",
299 req = list_entry(ep->queue.next, struct s3c_request, queue);
301 ep_tsr = readl(®->in_endp[ep_num].dieptsiz);
304 is_short = (xfer_size < ep->ep.maxpacket);
305 req->req.actual += min(xfer_size, req->req.length - req->req.actual);
307 debug_cond(DEBUG_IN_EP,
308 "%s: TX DMA done : ep = %d, tx bytes = %d/%d, "
309 "is_short = %d, DIEPTSIZ = 0x%x, remained bytes = %d\n",
310 __func__, ep_num, req->req.actual, req->req.length,
311 is_short, ep_tsr, xfer_size);
314 if (dev->ep0state == DATA_STATE_XMIT) {
315 debug_cond(DEBUG_IN_EP,
316 "%s: ep_num = %d, ep0stat =="
319 last = write_fifo_ep0(ep, req);
321 dev->ep0state = WAIT_FOR_COMPLETE;
322 } else if (dev->ep0state == WAIT_FOR_IN_COMPLETE) {
323 debug_cond(DEBUG_IN_EP,
324 "%s: ep_num = %d, completing request\n",
327 dev->ep0state = WAIT_FOR_SETUP;
328 } else if (dev->ep0state == WAIT_FOR_COMPLETE) {
329 debug_cond(DEBUG_IN_EP,
330 "%s: ep_num = %d, completing request\n",
333 dev->ep0state = WAIT_FOR_OUT_COMPLETE;
334 s3c_ep0_complete_out();
336 debug_cond(DEBUG_IN_EP,
337 "%s: ep_num = %d, invalid ep state\n",
343 if (req->req.actual == req->req.length)
346 if (!list_empty(&ep->queue)) {
347 req = list_entry(ep->queue.next, struct s3c_request, queue);
348 debug_cond(DEBUG_IN_EP,
349 "%s: Next Tx request start...\n", __func__);
354 static inline void s3c_udc_check_tx_queue(struct s3c_udc *dev, u8 ep_num)
356 struct s3c_ep *ep = &dev->ep[ep_num];
357 struct s3c_request *req;
359 debug_cond(DEBUG_IN_EP,
360 "%s: Check queue, ep_num = %d\n", __func__, ep_num);
362 if (!list_empty(&ep->queue)) {
363 req = list_entry(ep->queue.next, struct s3c_request, queue);
364 debug_cond(DEBUG_IN_EP,
365 "%s: Next Tx request(0x%p) start...\n",
373 debug_cond(DEBUG_IN_EP,
374 "%s: NULL REQ on IN EP-%d\n", __func__, ep_num);
381 static void process_ep_in_intr(struct s3c_udc *dev)
383 u32 ep_intr, ep_intr_status;
386 ep_intr = readl(®->daint);
387 debug_cond(DEBUG_IN_EP,
388 "*** %s: EP In interrupt : DAINT = 0x%x\n", __func__, ep_intr);
390 ep_intr &= DAINT_MASK;
393 if (ep_intr & DAINT_IN_EP_INT(1)) {
394 ep_intr_status = readl(®->in_endp[ep_num].diepint);
395 debug_cond(DEBUG_IN_EP, "\tEP%d-IN : DIEPINT = 0x%x\n",
396 ep_num, ep_intr_status);
398 /* Interrupt Clear */
399 writel(ep_intr_status, ®->in_endp[ep_num].diepint);
401 if (ep_intr_status & TRANSFER_DONE) {
402 complete_tx(dev, ep_num);
406 WAIT_FOR_IN_COMPLETE)
407 dev->ep0state = WAIT_FOR_SETUP;
409 if (dev->ep0state == WAIT_FOR_SETUP)
412 /* continue transfer after
413 set_clear_halt for DMA mode */
414 if (clear_feature_flag == 1) {
415 s3c_udc_check_tx_queue(dev,
417 clear_feature_flag = 0;
427 static void process_ep_out_intr(struct s3c_udc *dev)
429 u32 ep_intr, ep_intr_status;
432 ep_intr = readl(®->daint);
433 DEBUG_OUT_EP("*** %s: EP OUT interrupt : DAINT = 0x%x\n",
436 ep_intr = (ep_intr >> DAINT_OUT_BIT) & DAINT_MASK;
440 ep_intr_status = readl(®->out_endp[ep_num].doepint);
441 DEBUG_OUT_EP("\tEP%d-OUT : DOEPINT = 0x%x\n",
442 ep_num, ep_intr_status);
444 /* Interrupt Clear */
445 writel(ep_intr_status, ®->out_endp[ep_num].doepint);
448 if (ep_intr_status & TRANSFER_DONE) {
450 WAIT_FOR_OUT_COMPLETE)
451 complete_rx(dev, ep_num);
453 dev->ep0state = WAIT_FOR_SETUP;
459 CTRL_OUT_EP_SETUP_PHASE_DONE) {
460 DEBUG_OUT_EP("SETUP packet arrived\n");
464 if (ep_intr_status & TRANSFER_DONE)
465 complete_rx(dev, ep_num);
474 * usb client interrupt handler.
476 static int s3c_udc_irq(int irq, void *_dev)
478 struct s3c_udc *dev = _dev;
480 u32 usb_status, gintmsk;
483 spin_lock_irqsave(&dev->lock, flags);
485 intr_status = readl(®->gintsts);
486 gintmsk = readl(®->gintmsk);
488 debug_cond(DEBUG_ISR,
489 "\n*** %s : GINTSTS=0x%x(on state %s), GINTMSK : 0x%x,"
490 "DAINT : 0x%x, DAINTMSK : 0x%x\n",
491 __func__, intr_status, state_names[dev->ep0state], gintmsk,
492 readl(®->daint), readl(®->daintmsk));
495 spin_unlock_irqrestore(&dev->lock, flags);
499 if (intr_status & INT_ENUMDONE) {
500 debug_cond(DEBUG_ISR, "\tSpeed Detection interrupt\n");
502 writel(INT_ENUMDONE, ®->gintsts);
503 usb_status = (readl(®->dsts) & 0x6);
505 if (usb_status & (USB_FULL_30_60MHZ | USB_FULL_48MHZ)) {
506 debug_cond(DEBUG_ISR, "\t\tFull Speed Detection\n");
507 set_max_pktsize(dev, USB_SPEED_FULL);
510 debug_cond(DEBUG_ISR,
511 "\t\tHigh Speed Detection : 0x%x\n",
513 set_max_pktsize(dev, USB_SPEED_HIGH);
517 if (intr_status & INT_EARLY_SUSPEND) {
518 debug_cond(DEBUG_ISR, "\tEarly suspend interrupt\n");
519 writel(INT_EARLY_SUSPEND, ®->gintsts);
522 if (intr_status & INT_SUSPEND) {
523 usb_status = readl(®->dsts);
524 debug_cond(DEBUG_ISR,
525 "\tSuspend interrupt :(DSTS):0x%x\n", usb_status);
526 writel(INT_SUSPEND, ®->gintsts);
528 if (dev->gadget.speed != USB_SPEED_UNKNOWN
530 if (dev->driver->suspend)
531 dev->driver->suspend(&dev->gadget);
533 /* HACK to let gadget detect disconnected state */
534 if (dev->driver->disconnect) {
535 spin_unlock_irqrestore(&dev->lock, flags);
536 dev->driver->disconnect(&dev->gadget);
537 spin_lock_irqsave(&dev->lock, flags);
542 if (intr_status & INT_RESUME) {
543 debug_cond(DEBUG_ISR, "\tResume interrupt\n");
544 writel(INT_RESUME, ®->gintsts);
546 if (dev->gadget.speed != USB_SPEED_UNKNOWN
548 && dev->driver->resume) {
550 dev->driver->resume(&dev->gadget);
554 if (intr_status & INT_RESET) {
555 usb_status = readl(®->gotgctl);
556 debug_cond(DEBUG_ISR,
557 "\tReset interrupt - (GOTGCTL):0x%x\n", usb_status);
558 writel(INT_RESET, ®->gintsts);
560 if ((usb_status & 0xc0000) == (0x3 << 18)) {
561 if (reset_available) {
562 debug_cond(DEBUG_ISR,
563 "\t\tOTG core got reset (%d)!!\n",
566 dev->ep0state = WAIT_FOR_SETUP;
574 debug_cond(DEBUG_ISR, "\t\tRESET handling skipped\n");
578 if (intr_status & INT_IN_EP)
579 process_ep_in_intr(dev);
581 if (intr_status & INT_OUT_EP)
582 process_ep_out_intr(dev);
584 spin_unlock_irqrestore(&dev->lock, flags);
589 /** Queue one request
590 * Kickstart transfer if needed
592 static int s3c_queue(struct usb_ep *_ep, struct usb_request *_req,
595 struct s3c_request *req;
601 req = container_of(_req, struct s3c_request, req);
602 if (unlikely(!_req || !_req->complete || !_req->buf
603 || !list_empty(&req->queue))) {
605 debug("%s: bad params\n", __func__);
609 ep = container_of(_ep, struct s3c_ep, ep);
611 if (unlikely(!_ep || (!ep->desc && ep->ep.name != ep0name))) {
613 debug("%s: bad ep: %s, %d, %p\n", __func__,
614 ep->ep.name, !ep->desc, _ep);
618 ep_num = ep_index(ep);
620 if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
622 debug("%s: bogus device state %p\n", __func__, dev->driver);
626 spin_lock_irqsave(&dev->lock, flags);
628 _req->status = -EINPROGRESS;
631 /* kickstart this i/o queue? */
632 debug("\n*** %s: %s-%s req = %p, len = %d, buf = %p"
633 "Q empty = %d, stopped = %d\n",
634 __func__, _ep->name, ep_is_in(ep) ? "in" : "out",
635 _req, _req->length, _req->buf,
636 list_empty(&ep->queue), ep->stopped);
640 int i, len = _req->length;
645 for (i = 0; i < len; i++) {
646 printf("%02x", ((u8 *)_req->buf)[i]);
654 if (list_empty(&ep->queue) && !ep->stopped) {
658 list_add_tail(&req->queue, &ep->queue);
659 s3c_ep0_kick(dev, ep);
662 } else if (ep_is_in(ep)) {
663 gintsts = readl(®->gintsts);
664 debug_cond(DEBUG_IN_EP,
665 "%s: ep_is_in, S3C_UDC_OTG_GINTSTS=0x%x\n",
670 gintsts = readl(®->gintsts);
671 DEBUG_OUT_EP("%s:ep_is_out, S3C_UDC_OTG_GINTSTS=0x%x\n",
678 /* pio or dma irq handler advances the queue. */
679 if (likely(req != 0))
680 list_add_tail(&req->queue, &ep->queue);
682 spin_unlock_irqrestore(&dev->lock, flags);
687 /****************************************************************/
688 /* End Point 0 related functions */
689 /****************************************************************/
691 /* return: 0 = still running, 1 = completed, negative = errno */
692 static int write_fifo_ep0(struct s3c_ep *ep, struct s3c_request *req)
698 max = ep_maxpacket(ep);
700 DEBUG_EP0("%s: max = %d\n", __func__, max);
702 count = setdma_tx(ep, req);
704 /* last packet is usually short (or a zlp) */
705 if (likely(count != max))
708 if (likely(req->req.length != req->req.actual + count)
715 DEBUG_EP0("%s: wrote %s %d bytes%s %d left %p\n", __func__,
718 req->req.length - req->req.actual - count, req);
720 /* requests complete when all IN data is in the FIFO */
722 ep->dev->ep0state = WAIT_FOR_SETUP;
729 int s3c_fifo_read(struct s3c_ep *ep, u32 *cp, int max)
733 bytes = sizeof(struct usb_ctrlrequest);
735 invalidate_dcache_range((unsigned long) ep->dev->dma_buf[ep_index(ep)],
736 (unsigned long) ep->dev->dma_buf[ep_index(ep)]
739 DEBUG_EP0("%s: bytes=%d, ep_index=%d %p\n", __func__,
740 bytes, ep_index(ep), ep->dev->dma_buf[ep_index(ep)]);
746 * udc_set_address - set the USB address for this device
749 * Called from control endpoint function
750 * after it decodes a set address setup packet.
752 static void udc_set_address(struct s3c_udc *dev, unsigned char address)
754 u32 ctrl = readl(®->dcfg);
755 writel(DEVICE_ADDRESS(address) | ctrl, ®->dcfg);
757 s3c_udc_ep0_zlp(dev);
759 DEBUG_EP0("%s: USB OTG 2.0 Device address=%d, DCFG=0x%x\n",
760 __func__, address, readl(®->dcfg));
762 dev->usb_address = address;
765 static inline void s3c_udc_ep0_set_stall(struct s3c_ep *ep)
771 ep_ctrl = readl(®->in_endp[EP0_CON].diepctl);
773 /* set the disable and stall bits */
774 if (ep_ctrl & DEPCTL_EPENA)
775 ep_ctrl |= DEPCTL_EPDIS;
777 ep_ctrl |= DEPCTL_STALL;
779 writel(ep_ctrl, ®->in_endp[EP0_CON].diepctl);
781 DEBUG_EP0("%s: set ep%d stall, DIEPCTL0 = 0x%x\n",
782 __func__, ep_index(ep), ®->in_endp[EP0_CON].diepctl);
784 * The application can only set this bit, and the core clears it,
785 * when a SETUP token is received for this endpoint
787 dev->ep0state = WAIT_FOR_SETUP;
792 static void s3c_ep0_read(struct s3c_udc *dev)
794 struct s3c_request *req;
795 struct s3c_ep *ep = &dev->ep[0];
797 if (!list_empty(&ep->queue)) {
798 req = list_entry(ep->queue.next, struct s3c_request, queue);
801 debug("%s: ---> BUG\n", __func__);
806 DEBUG_EP0("%s: req = %p, req.length = 0x%x, req.actual = 0x%x\n",
807 __func__, req, req->req.length, req->req.actual);
809 if (req->req.length == 0) {
810 /* zlp for Set_configuration, Set_interface,
811 * or Bulk-Only mass storge reset */
814 s3c_udc_ep0_zlp(dev);
816 DEBUG_EP0("%s: req.length = 0, bRequest = %d\n",
817 __func__, usb_ctrl->bRequest);
827 static int s3c_ep0_write(struct s3c_udc *dev)
829 struct s3c_request *req;
830 struct s3c_ep *ep = &dev->ep[0];
831 int ret, need_zlp = 0;
833 if (list_empty(&ep->queue))
836 req = list_entry(ep->queue.next, struct s3c_request, queue);
839 DEBUG_EP0("%s: NULL REQ\n", __func__);
843 DEBUG_EP0("%s: req = %p, req.length = 0x%x, req.actual = 0x%x\n",
844 __func__, req, req->req.length, req->req.actual);
846 if (req->req.length - req->req.actual == ep0_fifo_size) {
847 /* Next write will end with the packet size, */
848 /* so we need Zero-length-packet */
852 ret = write_fifo_ep0(ep, req);
854 if ((ret == 1) && !need_zlp) {
856 dev->ep0state = WAIT_FOR_COMPLETE;
857 DEBUG_EP0("%s: finished, waiting for status\n", __func__);
860 dev->ep0state = DATA_STATE_XMIT;
861 DEBUG_EP0("%s: not finished\n", __func__);
869 int s3c_udc_get_status(struct s3c_udc *dev,
870 struct usb_ctrlrequest *crq)
872 u8 ep_num = crq->wIndex & 0x7F;
874 u32 *p = the_controller->dma_buf[1];
876 DEBUG_SETUP("%s: *** USB_REQ_GET_STATUS\n", __func__);
877 printf("crq->brequest:0x%x\n", crq->bRequestType & USB_RECIP_MASK);
878 switch (crq->bRequestType & USB_RECIP_MASK) {
879 case USB_RECIP_INTERFACE:
881 DEBUG_SETUP("\tGET_STATUS:USB_RECIP_INTERFACE, g_stauts = %d\n",
885 case USB_RECIP_DEVICE:
886 g_status = 0x1; /* Self powered */
887 DEBUG_SETUP("\tGET_STATUS: USB_RECIP_DEVICE, g_stauts = %d\n",
891 case USB_RECIP_ENDPOINT:
892 if (crq->wLength > 2) {
893 DEBUG_SETUP("\tGET_STATUS:Not support EP or wLength\n");
897 g_status = dev->ep[ep_num].stopped;
898 DEBUG_SETUP("\tGET_STATUS: USB_RECIP_ENDPOINT, g_stauts = %d\n",
907 memcpy(p, &g_status, sizeof(g_status));
909 flush_dcache_range((unsigned long) p,
910 (unsigned long) p + DMA_BUFFER_SIZE);
912 writel(the_controller->dma_addr[1], ®->in_endp[EP0_CON].diepdma);
913 writel(DIEPT_SIZ_PKT_CNT(1) | DIEPT_SIZ_XFER_SIZE(2),
914 ®->in_endp[EP0_CON].dieptsiz);
916 ep_ctrl = readl(®->in_endp[EP0_CON].diepctl);
917 writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK,
918 ®->in_endp[EP0_CON].diepctl);
919 dev->ep0state = WAIT_FOR_NULL_COMPLETE;
924 static void s3c_udc_set_nak(struct s3c_ep *ep)
929 ep_num = ep_index(ep);
930 debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type);
933 ep_ctrl = readl(®->in_endp[ep_num].diepctl);
934 ep_ctrl |= DEPCTL_SNAK;
935 writel(ep_ctrl, ®->in_endp[ep_num].diepctl);
936 debug("%s: set NAK, DIEPCTL%d = 0x%x\n",
937 __func__, ep_num, readl(®->in_endp[ep_num].diepctl));
939 ep_ctrl = readl(®->out_endp[ep_num].doepctl);
940 ep_ctrl |= DEPCTL_SNAK;
941 writel(ep_ctrl, ®->out_endp[ep_num].doepctl);
942 debug("%s: set NAK, DOEPCTL%d = 0x%x\n",
943 __func__, ep_num, readl(®->out_endp[ep_num].doepctl));
950 void s3c_udc_ep_set_stall(struct s3c_ep *ep)
955 ep_num = ep_index(ep);
956 debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type);
959 ep_ctrl = readl(®->in_endp[ep_num].diepctl);
961 /* set the disable and stall bits */
962 if (ep_ctrl & DEPCTL_EPENA)
963 ep_ctrl |= DEPCTL_EPDIS;
965 ep_ctrl |= DEPCTL_STALL;
967 writel(ep_ctrl, ®->in_endp[ep_num].diepctl);
968 debug("%s: set stall, DIEPCTL%d = 0x%x\n",
969 __func__, ep_num, readl(®->in_endp[ep_num].diepctl));
972 ep_ctrl = readl(®->out_endp[ep_num].doepctl);
974 /* set the stall bit */
975 ep_ctrl |= DEPCTL_STALL;
977 writel(ep_ctrl, ®->out_endp[ep_num].doepctl);
978 debug("%s: set stall, DOEPCTL%d = 0x%x\n",
979 __func__, ep_num, readl(®->out_endp[ep_num].doepctl));
985 void s3c_udc_ep_clear_stall(struct s3c_ep *ep)
990 ep_num = ep_index(ep);
991 debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type);
994 ep_ctrl = readl(®->in_endp[ep_num].diepctl);
996 /* clear stall bit */
997 ep_ctrl &= ~DEPCTL_STALL;
1000 * USB Spec 9.4.5: For endpoints using data toggle, regardless
1001 * of whether an endpoint has the Halt feature set, a
1002 * ClearFeature(ENDPOINT_HALT) request always results in the
1003 * data toggle being reinitialized to DATA0.
1005 if (ep->bmAttributes == USB_ENDPOINT_XFER_INT
1006 || ep->bmAttributes == USB_ENDPOINT_XFER_BULK) {
1007 ep_ctrl |= DEPCTL_SETD0PID; /* DATA0 */
1010 writel(ep_ctrl, ®->in_endp[ep_num].diepctl);
1011 debug("%s: cleared stall, DIEPCTL%d = 0x%x\n",
1012 __func__, ep_num, readl(®->in_endp[ep_num].diepctl));
1015 ep_ctrl = readl(®->out_endp[ep_num].doepctl);
1017 /* clear stall bit */
1018 ep_ctrl &= ~DEPCTL_STALL;
1020 if (ep->bmAttributes == USB_ENDPOINT_XFER_INT
1021 || ep->bmAttributes == USB_ENDPOINT_XFER_BULK) {
1022 ep_ctrl |= DEPCTL_SETD0PID; /* DATA0 */
1025 writel(ep_ctrl, ®->out_endp[ep_num].doepctl);
1026 debug("%s: cleared stall, DOEPCTL%d = 0x%x\n",
1027 __func__, ep_num, readl(®->out_endp[ep_num].doepctl));
1033 static int s3c_udc_set_halt(struct usb_ep *_ep, int value)
1036 struct s3c_udc *dev;
1037 unsigned long flags;
1040 ep = container_of(_ep, struct s3c_ep, ep);
1041 ep_num = ep_index(ep);
1043 if (unlikely(!_ep || !ep->desc || ep_num == EP0_CON ||
1044 ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC)) {
1045 debug("%s: %s bad ep or descriptor\n", __func__, ep->ep.name);
1049 /* Attempt to halt IN ep will fail if any transfer requests
1050 * are still queue */
1051 if (value && ep_is_in(ep) && !list_empty(&ep->queue)) {
1052 debug("%s: %s queue not empty, req = %p\n",
1053 __func__, ep->ep.name,
1054 list_entry(ep->queue.next, struct s3c_request, queue));
1060 debug("%s: ep_num = %d, value = %d\n", __func__, ep_num, value);
1062 spin_lock_irqsave(&dev->lock, flags);
1066 s3c_udc_ep_clear_stall(ep);
1069 dev->ep0state = WAIT_FOR_SETUP;
1072 s3c_udc_ep_set_stall(ep);
1075 spin_unlock_irqrestore(&dev->lock, flags);
1080 void s3c_udc_ep_activate(struct s3c_ep *ep)
1083 u32 ep_ctrl = 0, daintmsk = 0;
1085 ep_num = ep_index(ep);
1087 /* Read DEPCTLn register */
1089 ep_ctrl = readl(®->in_endp[ep_num].diepctl);
1090 daintmsk = 1 << ep_num;
1092 ep_ctrl = readl(®->out_endp[ep_num].doepctl);
1093 daintmsk = (1 << ep_num) << DAINT_OUT_BIT;
1096 debug("%s: EPCTRL%d = 0x%x, ep_is_in = %d\n",
1097 __func__, ep_num, ep_ctrl, ep_is_in(ep));
1099 /* If the EP is already active don't change the EP Control
1101 if (!(ep_ctrl & DEPCTL_USBACTEP)) {
1102 ep_ctrl = (ep_ctrl & ~DEPCTL_TYPE_MASK) |
1103 (ep->bmAttributes << DEPCTL_TYPE_BIT);
1104 ep_ctrl = (ep_ctrl & ~DEPCTL_MPS_MASK) |
1105 (ep->ep.maxpacket << DEPCTL_MPS_BIT);
1106 ep_ctrl |= (DEPCTL_SETD0PID | DEPCTL_USBACTEP | DEPCTL_SNAK);
1109 writel(ep_ctrl, ®->in_endp[ep_num].diepctl);
1110 debug("%s: USB Ative EP%d, DIEPCTRL%d = 0x%x\n",
1111 __func__, ep_num, ep_num,
1112 readl(®->in_endp[ep_num].diepctl));
1114 writel(ep_ctrl, ®->out_endp[ep_num].doepctl);
1115 debug("%s: USB Ative EP%d, DOEPCTRL%d = 0x%x\n",
1116 __func__, ep_num, ep_num,
1117 readl(®->out_endp[ep_num].doepctl));
1121 /* Unmask EP Interrtupt */
1122 writel(readl(®->daintmsk)|daintmsk, ®->daintmsk);
1123 debug("%s: DAINTMSK = 0x%x\n", __func__, readl(®->daintmsk));
1127 static int s3c_udc_clear_feature(struct usb_ep *_ep)
1129 struct s3c_udc *dev;
1133 ep = container_of(_ep, struct s3c_ep, ep);
1134 ep_num = ep_index(ep);
1137 DEBUG_SETUP("%s: ep_num = %d, is_in = %d, clear_feature_flag = %d\n",
1138 __func__, ep_num, ep_is_in(ep), clear_feature_flag);
1140 if (usb_ctrl->wLength != 0) {
1141 DEBUG_SETUP("\tCLEAR_FEATURE: wLength is not zero.....\n");
1145 switch (usb_ctrl->bRequestType & USB_RECIP_MASK) {
1146 case USB_RECIP_DEVICE:
1147 switch (usb_ctrl->wValue) {
1148 case USB_DEVICE_REMOTE_WAKEUP:
1149 DEBUG_SETUP("\tOFF:USB_DEVICE_REMOTE_WAKEUP\n");
1152 case USB_DEVICE_TEST_MODE:
1153 DEBUG_SETUP("\tCLEAR_FEATURE: USB_DEVICE_TEST_MODE\n");
1154 /** @todo Add CLEAR_FEATURE for TEST modes. */
1158 s3c_udc_ep0_zlp(dev);
1161 case USB_RECIP_ENDPOINT:
1162 DEBUG_SETUP("\tCLEAR_FEATURE:USB_RECIP_ENDPOINT, wValue = %d\n",
1165 if (usb_ctrl->wValue == USB_ENDPOINT_HALT) {
1167 s3c_udc_ep0_set_stall(ep);
1171 s3c_udc_ep0_zlp(dev);
1173 s3c_udc_ep_clear_stall(ep);
1174 s3c_udc_ep_activate(ep);
1177 clear_feature_num = ep_num;
1178 clear_feature_flag = 1;
1186 static int s3c_udc_set_feature(struct usb_ep *_ep)
1188 struct s3c_udc *dev;
1192 ep = container_of(_ep, struct s3c_ep, ep);
1193 ep_num = ep_index(ep);
1196 DEBUG_SETUP("%s: *** USB_REQ_SET_FEATURE , ep_num = %d\n",
1199 if (usb_ctrl->wLength != 0) {
1200 DEBUG_SETUP("\tSET_FEATURE: wLength is not zero.....\n");
1204 switch (usb_ctrl->bRequestType & USB_RECIP_MASK) {
1205 case USB_RECIP_DEVICE:
1206 switch (usb_ctrl->wValue) {
1207 case USB_DEVICE_REMOTE_WAKEUP:
1208 DEBUG_SETUP("\tSET_FEATURE:USB_DEVICE_REMOTE_WAKEUP\n");
1210 case USB_DEVICE_B_HNP_ENABLE:
1211 DEBUG_SETUP("\tSET_FEATURE: USB_DEVICE_B_HNP_ENABLE\n");
1214 case USB_DEVICE_A_HNP_SUPPORT:
1215 /* RH port supports HNP */
1216 DEBUG_SETUP("\tSET_FEATURE:USB_DEVICE_A_HNP_SUPPORT\n");
1219 case USB_DEVICE_A_ALT_HNP_SUPPORT:
1220 /* other RH port does */
1221 DEBUG_SETUP("\tSET: USB_DEVICE_A_ALT_HNP_SUPPORT\n");
1225 s3c_udc_ep0_zlp(dev);
1228 case USB_RECIP_INTERFACE:
1229 DEBUG_SETUP("\tSET_FEATURE: USB_RECIP_INTERFACE\n");
1232 case USB_RECIP_ENDPOINT:
1233 DEBUG_SETUP("\tSET_FEATURE: USB_RECIP_ENDPOINT\n");
1234 if (usb_ctrl->wValue == USB_ENDPOINT_HALT) {
1236 s3c_udc_ep0_set_stall(ep);
1240 s3c_udc_ep_set_stall(ep);
1243 s3c_udc_ep0_zlp(dev);
1251 * WAIT_FOR_SETUP (OUT_PKT_RDY)
1253 void s3c_ep0_setup(struct s3c_udc *dev)
1255 struct s3c_ep *ep = &dev->ep[0];
1259 /* Nuke all previous transfers */
1262 /* read control req from fifo (8 bytes) */
1263 s3c_fifo_read(ep, (u32 *)usb_ctrl, 8);
1265 DEBUG_SETUP("%s: bRequestType = 0x%x(%s), bRequest = 0x%x"
1266 "\twLength = 0x%x, wValue = 0x%x, wIndex= 0x%x\n",
1267 __func__, usb_ctrl->bRequestType,
1268 (usb_ctrl->bRequestType & USB_DIR_IN) ? "IN" : "OUT",
1270 usb_ctrl->wLength, usb_ctrl->wValue, usb_ctrl->wIndex);
1272 #ifdef DEBUG_S3C_UDC
1274 int i, len = sizeof(*usb_ctrl);
1275 char *p = (char *)usb_ctrl;
1278 for (i = 0; i < len; i++) {
1279 printf("%02x", ((u8 *)p)[i]);
1287 if (usb_ctrl->bRequest == GET_MAX_LUN_REQUEST &&
1288 usb_ctrl->wLength != 1) {
1289 DEBUG_SETUP("\t%s:GET_MAX_LUN_REQUEST:invalid",
1291 DEBUG_SETUP("wLength = %d, setup returned\n",
1294 s3c_udc_ep0_set_stall(ep);
1295 dev->ep0state = WAIT_FOR_SETUP;
1298 } else if (usb_ctrl->bRequest == BOT_RESET_REQUEST &&
1299 usb_ctrl->wLength != 0) {
1300 /* Bulk-Only *mass storge reset of class-specific request */
1301 DEBUG_SETUP("%s:BOT Rest:invalid wLength =%d, setup returned\n",
1302 __func__, usb_ctrl->wLength);
1304 s3c_udc_ep0_set_stall(ep);
1305 dev->ep0state = WAIT_FOR_SETUP;
1310 /* Set direction of EP0 */
1311 if (likely(usb_ctrl->bRequestType & USB_DIR_IN)) {
1312 ep->bEndpointAddress |= USB_DIR_IN;
1314 ep->bEndpointAddress &= ~USB_DIR_IN;
1316 /* cope with automagic for some standard requests. */
1317 dev->req_std = (usb_ctrl->bRequestType & USB_TYPE_MASK)
1318 == USB_TYPE_STANDARD;
1319 dev->req_config = 0;
1320 dev->req_pending = 1;
1322 /* Handle some SETUP packets ourselves */
1324 switch (usb_ctrl->bRequest) {
1325 case USB_REQ_SET_ADDRESS:
1326 DEBUG_SETUP("%s: *** USB_REQ_SET_ADDRESS (%d)\n",
1327 __func__, usb_ctrl->wValue);
1328 if (usb_ctrl->bRequestType
1329 != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1332 udc_set_address(dev, usb_ctrl->wValue);
1335 case USB_REQ_SET_CONFIGURATION:
1336 DEBUG_SETUP("=====================================\n");
1337 DEBUG_SETUP("%s: USB_REQ_SET_CONFIGURATION (%d)\n",
1338 __func__, usb_ctrl->wValue);
1340 if (usb_ctrl->bRequestType == USB_RECIP_DEVICE) {
1341 reset_available = 1;
1342 dev->req_config = 1;
1346 case USB_REQ_GET_DESCRIPTOR:
1347 DEBUG_SETUP("%s: *** USB_REQ_GET_DESCRIPTOR\n",
1351 case USB_REQ_SET_INTERFACE:
1352 DEBUG_SETUP("%s: *** USB_REQ_SET_INTERFACE (%d)\n",
1353 __func__, usb_ctrl->wValue);
1355 if (usb_ctrl->bRequestType == USB_RECIP_INTERFACE) {
1356 reset_available = 1;
1357 dev->req_config = 1;
1361 case USB_REQ_GET_CONFIGURATION:
1362 DEBUG_SETUP("%s: *** USB_REQ_GET_CONFIGURATION\n",
1366 case USB_REQ_GET_STATUS:
1367 if (!s3c_udc_get_status(dev, usb_ctrl))
1372 case USB_REQ_CLEAR_FEATURE:
1373 ep_num = usb_ctrl->wIndex & 0x7f;
1375 if (!s3c_udc_clear_feature(&dev->ep[ep_num].ep))
1380 case USB_REQ_SET_FEATURE:
1381 ep_num = usb_ctrl->wIndex & 0x7f;
1383 if (!s3c_udc_set_feature(&dev->ep[ep_num].ep))
1389 DEBUG_SETUP("%s: *** Default of usb_ctrl->bRequest=0x%x"
1390 "happened.\n", __func__, usb_ctrl->bRequest);
1396 if (likely(dev->driver)) {
1397 /* device-2-host (IN) or no data setup command,
1398 * process immediately */
1399 DEBUG_SETUP("%s:usb_ctrlreq will be passed to fsg_setup()\n",
1402 spin_unlock(&dev->lock);
1403 i = dev->driver->setup(&dev->gadget, usb_ctrl);
1404 spin_lock(&dev->lock);
1407 if (dev->req_config) {
1408 DEBUG_SETUP("\tconfig change 0x%02x fail %d?\n",
1409 (u32)usb_ctrl->bRequest, i);
1413 /* setup processing failed, force stall */
1414 s3c_udc_ep0_set_stall(ep);
1415 dev->ep0state = WAIT_FOR_SETUP;
1417 DEBUG_SETUP("\tdev->driver->setup failed (%d),"
1419 i, usb_ctrl->bRequest);
1422 } else if (dev->req_pending) {
1423 dev->req_pending = 0;
1424 DEBUG_SETUP("\tdev->req_pending...\n");
1427 DEBUG_SETUP("\tep0state = %s\n", state_names[dev->ep0state]);
1433 * handle ep0 interrupt
1435 static void s3c_handle_ep0(struct s3c_udc *dev)
1437 if (dev->ep0state == WAIT_FOR_SETUP) {
1438 DEBUG_OUT_EP("%s: WAIT_FOR_SETUP\n", __func__);
1442 DEBUG_OUT_EP("%s: strange state!!(state = %s)\n",
1443 __func__, state_names[dev->ep0state]);
1447 static void s3c_ep0_kick(struct s3c_udc *dev, struct s3c_ep *ep)
1449 DEBUG_EP0("%s: ep_is_in = %d\n", __func__, ep_is_in(ep));
1451 dev->ep0state = DATA_STATE_XMIT;
1455 dev->ep0state = DATA_STATE_RECV;