2 * Copyright (C) 2011 Marvell International Ltd. All rights reserved.
3 * Author: Chao Xie <chao.xie@marvell.com>
4 * Neil Zhang <zhangwm@marvell.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
12 #include <linux/module.h>
13 #include <linux/pci.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/dmapool.h>
16 #include <linux/kernel.h>
17 #include <linux/delay.h>
18 #include <linux/ioport.h>
19 #include <linux/sched.h>
20 #include <linux/slab.h>
21 #include <linux/errno.h>
22 #include <linux/err.h>
23 #include <linux/timer.h>
24 #include <linux/list.h>
25 #include <linux/interrupt.h>
26 #include <linux/moduleparam.h>
27 #include <linux/device.h>
28 #include <linux/usb/ch9.h>
29 #include <linux/usb/gadget.h>
30 #include <linux/usb/otg.h>
33 #include <linux/irq.h>
34 #include <linux/platform_device.h>
35 #include <linux/clk.h>
36 #include <linux/platform_data/mv_usb.h>
37 #include <asm/unaligned.h>
41 #define DRIVER_DESC "Marvell PXA USB Device Controller driver"
42 #define DRIVER_VERSION "8 Nov 2010"
44 #define ep_dir(ep) (((ep)->ep_num == 0) ? \
45 ((ep)->udc->ep0_dir) : ((ep)->direction))
47 /* timeout value -- usec */
48 #define RESET_TIMEOUT 10000
49 #define FLUSH_TIMEOUT 10000
50 #define EPSTATUS_TIMEOUT 10000
51 #define PRIME_TIMEOUT 10000
52 #define READSAFE_TIMEOUT 1000
54 #define LOOPS_USEC_SHIFT 1
55 #define LOOPS_USEC (1 << LOOPS_USEC_SHIFT)
56 #define LOOPS(timeout) ((timeout) >> LOOPS_USEC_SHIFT)
58 static DECLARE_COMPLETION(release_done);
60 static const char driver_name[] = "mv_udc";
61 static const char driver_desc[] = DRIVER_DESC;
63 static void nuke(struct mv_ep *ep, int status);
64 static void stop_activity(struct mv_udc *udc, struct usb_gadget_driver *driver);
66 /* for endpoint 0 operations */
67 static const struct usb_endpoint_descriptor mv_ep0_desc = {
68 .bLength = USB_DT_ENDPOINT_SIZE,
69 .bDescriptorType = USB_DT_ENDPOINT,
70 .bEndpointAddress = 0,
71 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
72 .wMaxPacketSize = EP0_MAX_PKT_SIZE,
75 static void ep0_reset(struct mv_udc *udc)
82 for (i = 0; i < 2; i++) {
87 ep->dqh = &udc->ep_dqh[i];
89 /* configure ep0 endpoint capabilities in dQH */
90 ep->dqh->max_packet_length =
91 (EP0_MAX_PKT_SIZE << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
94 ep->dqh->next_dtd_ptr = EP_QUEUE_HEAD_NEXT_TERMINATE;
96 epctrlx = readl(&udc->op_regs->epctrlx[0]);
98 epctrlx |= EPCTRL_TX_ENABLE
99 | (USB_ENDPOINT_XFER_CONTROL
100 << EPCTRL_TX_EP_TYPE_SHIFT);
103 epctrlx |= EPCTRL_RX_ENABLE
104 | (USB_ENDPOINT_XFER_CONTROL
105 << EPCTRL_RX_EP_TYPE_SHIFT);
108 writel(epctrlx, &udc->op_regs->epctrlx[0]);
112 /* protocol ep0 stall, will automatically be cleared on new transaction */
113 static void ep0_stall(struct mv_udc *udc)
117 /* set TX and RX to stall */
118 epctrlx = readl(&udc->op_regs->epctrlx[0]);
119 epctrlx |= EPCTRL_RX_EP_STALL | EPCTRL_TX_EP_STALL;
120 writel(epctrlx, &udc->op_regs->epctrlx[0]);
122 /* update ep0 state */
123 udc->ep0_state = WAIT_FOR_SETUP;
124 udc->ep0_dir = EP_DIR_OUT;
127 static int process_ep_req(struct mv_udc *udc, int index,
128 struct mv_req *curr_req)
130 struct mv_dtd *curr_dtd;
131 struct mv_dqh *curr_dqh;
132 int td_complete, actual, remaining_length;
138 curr_dqh = &udc->ep_dqh[index];
139 direction = index % 2;
141 curr_dtd = curr_req->head;
143 actual = curr_req->req.length;
145 for (i = 0; i < curr_req->dtd_count; i++) {
146 if (curr_dtd->size_ioc_sts & DTD_STATUS_ACTIVE) {
147 dev_dbg(&udc->dev->dev, "%s, dTD not completed\n",
148 udc->eps[index].name);
152 errors = curr_dtd->size_ioc_sts & DTD_ERROR_MASK;
155 (curr_dtd->size_ioc_sts & DTD_PACKET_SIZE)
156 >> DTD_LENGTH_BIT_POS;
157 actual -= remaining_length;
159 if (remaining_length) {
161 dev_dbg(&udc->dev->dev,
162 "TX dTD remains data\n");
169 dev_info(&udc->dev->dev,
170 "complete_tr error: ep=%d %s: error = 0x%x\n",
171 index >> 1, direction ? "SEND" : "RECV",
173 if (errors & DTD_STATUS_HALTED) {
174 /* Clear the errors and Halt condition */
175 curr_dqh->size_ioc_int_sts &= ~errors;
177 } else if (errors & DTD_STATUS_DATA_BUFF_ERR) {
179 } else if (errors & DTD_STATUS_TRANSACTION_ERR) {
183 if (i != curr_req->dtd_count - 1)
184 curr_dtd = (struct mv_dtd *)curr_dtd->next_dtd_virt;
189 if (direction == EP_DIR_OUT)
190 bit_pos = 1 << curr_req->ep->ep_num;
192 bit_pos = 1 << (16 + curr_req->ep->ep_num);
194 while ((curr_dqh->curr_dtd_ptr == curr_dtd->td_dma)) {
195 if (curr_dtd->dtd_next == EP_QUEUE_HEAD_NEXT_TERMINATE) {
196 while (readl(&udc->op_regs->epstatus) & bit_pos)
203 curr_req->req.actual = actual;
209 * done() - retire a request; caller blocked irqs
210 * @status : request status to be set, only works when
211 * request is still in progress.
213 static void done(struct mv_ep *ep, struct mv_req *req, int status)
214 __releases(&ep->udc->lock)
215 __acquires(&ep->udc->lock)
217 struct mv_udc *udc = NULL;
218 unsigned char stopped = ep->stopped;
219 struct mv_dtd *curr_td, *next_td;
222 udc = (struct mv_udc *)ep->udc;
223 /* Removed the req from fsl_ep->queue */
224 list_del_init(&req->queue);
226 /* req.status should be set as -EINPROGRESS in ep_queue() */
227 if (req->req.status == -EINPROGRESS)
228 req->req.status = status;
230 status = req->req.status;
232 /* Free dtd for the request */
234 for (j = 0; j < req->dtd_count; j++) {
236 if (j != req->dtd_count - 1)
237 next_td = curr_td->next_dtd_virt;
238 dma_pool_free(udc->dtd_pool, curr_td, curr_td->td_dma);
241 usb_gadget_unmap_request(&udc->gadget, &req->req, ep_dir(ep));
243 if (status && (status != -ESHUTDOWN))
244 dev_info(&udc->dev->dev, "complete %s req %p stat %d len %u/%u",
245 ep->ep.name, &req->req, status,
246 req->req.actual, req->req.length);
250 spin_unlock(&ep->udc->lock);
252 usb_gadget_giveback_request(&ep->ep, &req->req);
254 spin_lock(&ep->udc->lock);
255 ep->stopped = stopped;
258 static int queue_dtd(struct mv_ep *ep, struct mv_req *req)
262 u32 bit_pos, direction;
263 u32 usbcmd, epstatus;
268 direction = ep_dir(ep);
269 dqh = &(udc->ep_dqh[ep->ep_num * 2 + direction]);
270 bit_pos = 1 << (((direction == EP_DIR_OUT) ? 0 : 16) + ep->ep_num);
272 /* check if the pipe is empty */
273 if (!(list_empty(&ep->queue))) {
274 struct mv_req *lastreq;
275 lastreq = list_entry(ep->queue.prev, struct mv_req, queue);
276 lastreq->tail->dtd_next =
277 req->head->td_dma & EP_QUEUE_HEAD_NEXT_POINTER_MASK;
281 if (readl(&udc->op_regs->epprime) & bit_pos)
284 loops = LOOPS(READSAFE_TIMEOUT);
286 /* start with setting the semaphores */
287 usbcmd = readl(&udc->op_regs->usbcmd);
288 usbcmd |= USBCMD_ATDTW_TRIPWIRE_SET;
289 writel(usbcmd, &udc->op_regs->usbcmd);
291 /* read the endpoint status */
292 epstatus = readl(&udc->op_regs->epstatus) & bit_pos;
295 * Reread the ATDTW semaphore bit to check if it is
296 * cleared. When hardware see a hazard, it will clear
297 * the bit or else we remain set to 1 and we can
298 * proceed with priming of endpoint if not already
301 if (readl(&udc->op_regs->usbcmd)
302 & USBCMD_ATDTW_TRIPWIRE_SET)
307 dev_err(&udc->dev->dev,
308 "Timeout for ATDTW_TRIPWIRE...\n");
315 /* Clear the semaphore */
316 usbcmd = readl(&udc->op_regs->usbcmd);
317 usbcmd &= USBCMD_ATDTW_TRIPWIRE_CLEAR;
318 writel(usbcmd, &udc->op_regs->usbcmd);
324 /* Write dQH next pointer and terminate bit to 0 */
325 dqh->next_dtd_ptr = req->head->td_dma
326 & EP_QUEUE_HEAD_NEXT_POINTER_MASK;
328 /* clear active and halt bit, in case set from a previous error */
329 dqh->size_ioc_int_sts &= ~(DTD_STATUS_ACTIVE | DTD_STATUS_HALTED);
331 /* Ensure that updates to the QH will occur before priming. */
334 /* Prime the Endpoint */
335 writel(bit_pos, &udc->op_regs->epprime);
341 static struct mv_dtd *build_dtd(struct mv_req *req, unsigned *length,
342 dma_addr_t *dma, int *is_last)
349 /* how big will this transfer be? */
350 if (usb_endpoint_xfer_isoc(req->ep->ep.desc)) {
352 mult = (dqh->max_packet_length >> EP_QUEUE_HEAD_MULT_POS)
354 *length = min(req->req.length - req->req.actual,
355 (unsigned)(mult * req->ep->ep.maxpacket));
357 *length = min(req->req.length - req->req.actual,
358 (unsigned)EP_MAX_LENGTH_TRANSFER);
363 * Be careful that no _GFP_HIGHMEM is set,
364 * or we can not use dma_to_virt
366 dtd = dma_pool_alloc(udc->dtd_pool, GFP_ATOMIC, dma);
371 /* initialize buffer page pointers */
372 temp = (u32)(req->req.dma + req->req.actual);
373 dtd->buff_ptr0 = cpu_to_le32(temp);
375 dtd->buff_ptr1 = cpu_to_le32(temp + 0x1000);
376 dtd->buff_ptr2 = cpu_to_le32(temp + 0x2000);
377 dtd->buff_ptr3 = cpu_to_le32(temp + 0x3000);
378 dtd->buff_ptr4 = cpu_to_le32(temp + 0x4000);
380 req->req.actual += *length;
382 /* zlp is needed if req->req.zero is set */
384 if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
388 } else if (req->req.length == req->req.actual)
393 /* Fill in the transfer size; set active bit */
394 temp = ((*length << DTD_LENGTH_BIT_POS) | DTD_STATUS_ACTIVE);
396 /* Enable interrupt for the last dtd of a request */
397 if (*is_last && !req->req.no_interrupt)
402 dtd->size_ioc_sts = temp;
409 /* generate dTD linked list for a request */
410 static int req_to_dtd(struct mv_req *req)
413 int is_last, is_first = 1;
414 struct mv_dtd *dtd, *last_dtd = NULL;
421 dtd = build_dtd(req, &count, &dma, &is_last);
429 last_dtd->dtd_next = dma;
430 last_dtd->next_dtd_virt = dtd;
436 /* set terminate bit to 1 for the last dTD */
437 dtd->dtd_next = DTD_NEXT_TERMINATE;
444 static int mv_ep_enable(struct usb_ep *_ep,
445 const struct usb_endpoint_descriptor *desc)
451 u32 bit_pos, epctrlx, direction;
452 unsigned char zlt = 0, ios = 0, mult = 0;
455 ep = container_of(_ep, struct mv_ep, ep);
459 || desc->bDescriptorType != USB_DT_ENDPOINT)
462 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
465 direction = ep_dir(ep);
466 max = usb_endpoint_maxp(desc);
469 * disable HW zero length termination select
470 * driver handles zero length packet through req->req.zero
474 bit_pos = 1 << ((direction == EP_DIR_OUT ? 0 : 16) + ep->ep_num);
476 /* Check if the Endpoint is Primed */
477 if ((readl(&udc->op_regs->epprime) & bit_pos)
478 || (readl(&udc->op_regs->epstatus) & bit_pos)) {
479 dev_info(&udc->dev->dev,
480 "ep=%d %s: Init ERROR: ENDPTPRIME=0x%x,"
481 " ENDPTSTATUS=0x%x, bit_pos=0x%x\n",
482 (unsigned)ep->ep_num, direction ? "SEND" : "RECV",
483 (unsigned)readl(&udc->op_regs->epprime),
484 (unsigned)readl(&udc->op_regs->epstatus),
488 /* Set the max packet length, interrupt on Setup and Mult fields */
489 switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
490 case USB_ENDPOINT_XFER_BULK:
494 case USB_ENDPOINT_XFER_CONTROL:
496 case USB_ENDPOINT_XFER_INT:
499 case USB_ENDPOINT_XFER_ISOC:
500 /* Calculate transactions needed for high bandwidth iso */
501 mult = (unsigned char)(1 + ((max >> 11) & 0x03));
502 max = max & 0x7ff; /* bit 0~10 */
503 /* 3 transactions at most */
511 spin_lock_irqsave(&udc->lock, flags);
512 /* Get the endpoint queue head address */
514 dqh->max_packet_length = (max << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
515 | (mult << EP_QUEUE_HEAD_MULT_POS)
516 | (zlt ? EP_QUEUE_HEAD_ZLT_SEL : 0)
517 | (ios ? EP_QUEUE_HEAD_IOS : 0);
518 dqh->next_dtd_ptr = 1;
519 dqh->size_ioc_int_sts = 0;
521 ep->ep.maxpacket = max;
525 /* Enable the endpoint for Rx or Tx and set the endpoint type */
526 epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
527 if (direction == EP_DIR_IN) {
528 epctrlx &= ~EPCTRL_TX_ALL_MASK;
529 epctrlx |= EPCTRL_TX_ENABLE | EPCTRL_TX_DATA_TOGGLE_RST
530 | ((desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK)
531 << EPCTRL_TX_EP_TYPE_SHIFT);
533 epctrlx &= ~EPCTRL_RX_ALL_MASK;
534 epctrlx |= EPCTRL_RX_ENABLE | EPCTRL_RX_DATA_TOGGLE_RST
535 | ((desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK)
536 << EPCTRL_RX_EP_TYPE_SHIFT);
538 writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
541 * Implement Guideline (GL# USB-7) The unused endpoint type must
542 * be programmed to bulk.
544 epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
545 if ((epctrlx & EPCTRL_RX_ENABLE) == 0) {
546 epctrlx |= (USB_ENDPOINT_XFER_BULK
547 << EPCTRL_RX_EP_TYPE_SHIFT);
548 writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
551 epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
552 if ((epctrlx & EPCTRL_TX_ENABLE) == 0) {
553 epctrlx |= (USB_ENDPOINT_XFER_BULK
554 << EPCTRL_TX_EP_TYPE_SHIFT);
555 writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
558 spin_unlock_irqrestore(&udc->lock, flags);
565 static int mv_ep_disable(struct usb_ep *_ep)
570 u32 bit_pos, epctrlx, direction;
573 ep = container_of(_ep, struct mv_ep, ep);
574 if ((_ep == NULL) || !ep->ep.desc)
579 /* Get the endpoint queue head address */
582 spin_lock_irqsave(&udc->lock, flags);
584 direction = ep_dir(ep);
585 bit_pos = 1 << ((direction == EP_DIR_OUT ? 0 : 16) + ep->ep_num);
587 /* Reset the max packet length and the interrupt on Setup */
588 dqh->max_packet_length = 0;
590 /* Disable the endpoint for Rx or Tx and reset the endpoint type */
591 epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
592 epctrlx &= ~((direction == EP_DIR_IN)
593 ? (EPCTRL_TX_ENABLE | EPCTRL_TX_TYPE)
594 : (EPCTRL_RX_ENABLE | EPCTRL_RX_TYPE));
595 writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
597 /* nuke all pending requests (does flush) */
598 nuke(ep, -ESHUTDOWN);
603 spin_unlock_irqrestore(&udc->lock, flags);
608 static struct usb_request *
609 mv_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
611 struct mv_req *req = NULL;
613 req = kzalloc(sizeof *req, gfp_flags);
617 req->req.dma = DMA_ADDR_INVALID;
618 INIT_LIST_HEAD(&req->queue);
623 static void mv_free_request(struct usb_ep *_ep, struct usb_request *_req)
625 struct mv_req *req = NULL;
627 req = container_of(_req, struct mv_req, req);
633 static void mv_ep_fifo_flush(struct usb_ep *_ep)
636 u32 bit_pos, direction;
643 ep = container_of(_ep, struct mv_ep, ep);
648 direction = ep_dir(ep);
651 bit_pos = (1 << 16) | 1;
652 else if (direction == EP_DIR_OUT)
653 bit_pos = 1 << ep->ep_num;
655 bit_pos = 1 << (16 + ep->ep_num);
657 loops = LOOPS(EPSTATUS_TIMEOUT);
659 unsigned int inter_loops;
662 dev_err(&udc->dev->dev,
663 "TIMEOUT for ENDPTSTATUS=0x%x, bit_pos=0x%x\n",
664 (unsigned)readl(&udc->op_regs->epstatus),
668 /* Write 1 to the Flush register */
669 writel(bit_pos, &udc->op_regs->epflush);
671 /* Wait until flushing completed */
672 inter_loops = LOOPS(FLUSH_TIMEOUT);
673 while (readl(&udc->op_regs->epflush)) {
675 * ENDPTFLUSH bit should be cleared to indicate this
676 * operation is complete
678 if (inter_loops == 0) {
679 dev_err(&udc->dev->dev,
680 "TIMEOUT for ENDPTFLUSH=0x%x,"
682 (unsigned)readl(&udc->op_regs->epflush),
690 } while (readl(&udc->op_regs->epstatus) & bit_pos);
693 /* queues (submits) an I/O request to an endpoint */
695 mv_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
697 struct mv_ep *ep = container_of(_ep, struct mv_ep, ep);
698 struct mv_req *req = container_of(_req, struct mv_req, req);
699 struct mv_udc *udc = ep->udc;
703 /* catch various bogus parameters */
704 if (!_req || !req->req.complete || !req->req.buf
705 || !list_empty(&req->queue)) {
706 dev_err(&udc->dev->dev, "%s, bad params", __func__);
709 if (unlikely(!_ep || !ep->ep.desc)) {
710 dev_err(&udc->dev->dev, "%s, bad ep", __func__);
715 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
720 /* map virtual address to hardware */
721 retval = usb_gadget_map_request(&udc->gadget, _req, ep_dir(ep));
725 req->req.status = -EINPROGRESS;
729 spin_lock_irqsave(&udc->lock, flags);
731 /* build dtds and push them to device queue */
732 if (!req_to_dtd(req)) {
733 retval = queue_dtd(ep, req);
735 spin_unlock_irqrestore(&udc->lock, flags);
736 dev_err(&udc->dev->dev, "Failed to queue dtd\n");
740 spin_unlock_irqrestore(&udc->lock, flags);
741 dev_err(&udc->dev->dev, "Failed to dma_pool_alloc\n");
746 /* Update ep0 state */
748 udc->ep0_state = DATA_STATE_XMIT;
750 /* irq handler advances the queue */
751 list_add_tail(&req->queue, &ep->queue);
752 spin_unlock_irqrestore(&udc->lock, flags);
757 usb_gadget_unmap_request(&udc->gadget, _req, ep_dir(ep));
762 static void mv_prime_ep(struct mv_ep *ep, struct mv_req *req)
764 struct mv_dqh *dqh = ep->dqh;
767 /* Write dQH next pointer and terminate bit to 0 */
768 dqh->next_dtd_ptr = req->head->td_dma
769 & EP_QUEUE_HEAD_NEXT_POINTER_MASK;
771 /* clear active and halt bit, in case set from a previous error */
772 dqh->size_ioc_int_sts &= ~(DTD_STATUS_ACTIVE | DTD_STATUS_HALTED);
774 /* Ensure that updates to the QH will occure before priming. */
777 bit_pos = 1 << (((ep_dir(ep) == EP_DIR_OUT) ? 0 : 16) + ep->ep_num);
779 /* Prime the Endpoint */
780 writel(bit_pos, &ep->udc->op_regs->epprime);
783 /* dequeues (cancels, unlinks) an I/O request from an endpoint */
784 static int mv_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
786 struct mv_ep *ep = container_of(_ep, struct mv_ep, ep);
788 struct mv_udc *udc = ep->udc;
790 int stopped, ret = 0;
796 spin_lock_irqsave(&ep->udc->lock, flags);
797 stopped = ep->stopped;
799 /* Stop the ep before we deal with the queue */
801 epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
802 if (ep_dir(ep) == EP_DIR_IN)
803 epctrlx &= ~EPCTRL_TX_ENABLE;
805 epctrlx &= ~EPCTRL_RX_ENABLE;
806 writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
808 /* make sure it's actually queued on this endpoint */
809 list_for_each_entry(req, &ep->queue, queue) {
810 if (&req->req == _req)
813 if (&req->req != _req) {
818 /* The request is in progress, or completed but not dequeued */
819 if (ep->queue.next == &req->queue) {
820 _req->status = -ECONNRESET;
821 mv_ep_fifo_flush(_ep); /* flush current transfer */
823 /* The request isn't the last request in this ep queue */
824 if (req->queue.next != &ep->queue) {
825 struct mv_req *next_req;
827 next_req = list_entry(req->queue.next,
828 struct mv_req, queue);
830 /* Point the QH to the first TD of next request */
831 mv_prime_ep(ep, next_req);
836 qh->next_dtd_ptr = 1;
837 qh->size_ioc_int_sts = 0;
840 /* The request hasn't been processed, patch up the TD chain */
842 struct mv_req *prev_req;
844 prev_req = list_entry(req->queue.prev, struct mv_req, queue);
845 writel(readl(&req->tail->dtd_next),
846 &prev_req->tail->dtd_next);
850 done(ep, req, -ECONNRESET);
854 epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
855 if (ep_dir(ep) == EP_DIR_IN)
856 epctrlx |= EPCTRL_TX_ENABLE;
858 epctrlx |= EPCTRL_RX_ENABLE;
859 writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
860 ep->stopped = stopped;
862 spin_unlock_irqrestore(&ep->udc->lock, flags);
866 static void ep_set_stall(struct mv_udc *udc, u8 ep_num, u8 direction, int stall)
870 epctrlx = readl(&udc->op_regs->epctrlx[ep_num]);
873 if (direction == EP_DIR_IN)
874 epctrlx |= EPCTRL_TX_EP_STALL;
876 epctrlx |= EPCTRL_RX_EP_STALL;
878 if (direction == EP_DIR_IN) {
879 epctrlx &= ~EPCTRL_TX_EP_STALL;
880 epctrlx |= EPCTRL_TX_DATA_TOGGLE_RST;
882 epctrlx &= ~EPCTRL_RX_EP_STALL;
883 epctrlx |= EPCTRL_RX_DATA_TOGGLE_RST;
886 writel(epctrlx, &udc->op_regs->epctrlx[ep_num]);
889 static int ep_is_stall(struct mv_udc *udc, u8 ep_num, u8 direction)
893 epctrlx = readl(&udc->op_regs->epctrlx[ep_num]);
895 if (direction == EP_DIR_OUT)
896 return (epctrlx & EPCTRL_RX_EP_STALL) ? 1 : 0;
898 return (epctrlx & EPCTRL_TX_EP_STALL) ? 1 : 0;
901 static int mv_ep_set_halt_wedge(struct usb_ep *_ep, int halt, int wedge)
904 unsigned long flags = 0;
908 ep = container_of(_ep, struct mv_ep, ep);
910 if (!_ep || !ep->ep.desc) {
915 if (ep->ep.desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
916 status = -EOPNOTSUPP;
921 * Attempt to halt IN ep will fail if any transfer requests
924 if (halt && (ep_dir(ep) == EP_DIR_IN) && !list_empty(&ep->queue)) {
929 spin_lock_irqsave(&ep->udc->lock, flags);
930 ep_set_stall(udc, ep->ep_num, ep_dir(ep), halt);
935 spin_unlock_irqrestore(&ep->udc->lock, flags);
937 if (ep->ep_num == 0) {
938 udc->ep0_state = WAIT_FOR_SETUP;
939 udc->ep0_dir = EP_DIR_OUT;
945 static int mv_ep_set_halt(struct usb_ep *_ep, int halt)
947 return mv_ep_set_halt_wedge(_ep, halt, 0);
950 static int mv_ep_set_wedge(struct usb_ep *_ep)
952 return mv_ep_set_halt_wedge(_ep, 1, 1);
955 static struct usb_ep_ops mv_ep_ops = {
956 .enable = mv_ep_enable,
957 .disable = mv_ep_disable,
959 .alloc_request = mv_alloc_request,
960 .free_request = mv_free_request,
962 .queue = mv_ep_queue,
963 .dequeue = mv_ep_dequeue,
965 .set_wedge = mv_ep_set_wedge,
966 .set_halt = mv_ep_set_halt,
967 .fifo_flush = mv_ep_fifo_flush, /* flush fifo */
970 static void udc_clock_enable(struct mv_udc *udc)
972 clk_prepare_enable(udc->clk);
975 static void udc_clock_disable(struct mv_udc *udc)
977 clk_disable_unprepare(udc->clk);
980 static void udc_stop(struct mv_udc *udc)
984 /* Disable interrupts */
985 tmp = readl(&udc->op_regs->usbintr);
986 tmp &= ~(USBINTR_INT_EN | USBINTR_ERR_INT_EN |
987 USBINTR_PORT_CHANGE_DETECT_EN | USBINTR_RESET_EN);
988 writel(tmp, &udc->op_regs->usbintr);
992 /* Reset the Run the bit in the command register to stop VUSB */
993 tmp = readl(&udc->op_regs->usbcmd);
994 tmp &= ~USBCMD_RUN_STOP;
995 writel(tmp, &udc->op_regs->usbcmd);
998 static void udc_start(struct mv_udc *udc)
1002 usbintr = USBINTR_INT_EN | USBINTR_ERR_INT_EN
1003 | USBINTR_PORT_CHANGE_DETECT_EN
1004 | USBINTR_RESET_EN | USBINTR_DEVICE_SUSPEND;
1005 /* Enable interrupts */
1006 writel(usbintr, &udc->op_regs->usbintr);
1010 /* Set the Run bit in the command register */
1011 writel(USBCMD_RUN_STOP, &udc->op_regs->usbcmd);
1014 static int udc_reset(struct mv_udc *udc)
1019 /* Stop the controller */
1020 tmp = readl(&udc->op_regs->usbcmd);
1021 tmp &= ~USBCMD_RUN_STOP;
1022 writel(tmp, &udc->op_regs->usbcmd);
1024 /* Reset the controller to get default values */
1025 writel(USBCMD_CTRL_RESET, &udc->op_regs->usbcmd);
1027 /* wait for reset to complete */
1028 loops = LOOPS(RESET_TIMEOUT);
1029 while (readl(&udc->op_regs->usbcmd) & USBCMD_CTRL_RESET) {
1031 dev_err(&udc->dev->dev,
1032 "Wait for RESET completed TIMEOUT\n");
1039 /* set controller to device mode */
1040 tmp = readl(&udc->op_regs->usbmode);
1041 tmp |= USBMODE_CTRL_MODE_DEVICE;
1043 /* turn setup lockout off, require setup tripwire in usbcmd */
1044 tmp |= USBMODE_SETUP_LOCK_OFF;
1046 writel(tmp, &udc->op_regs->usbmode);
1048 writel(0x0, &udc->op_regs->epsetupstat);
1050 /* Configure the Endpoint List Address */
1051 writel(udc->ep_dqh_dma & USB_EP_LIST_ADDRESS_MASK,
1052 &udc->op_regs->eplistaddr);
1054 portsc = readl(&udc->op_regs->portsc[0]);
1055 if (readl(&udc->cap_regs->hcsparams) & HCSPARAMS_PPC)
1056 portsc &= (~PORTSCX_W1C_BITS | ~PORTSCX_PORT_POWER);
1059 portsc |= PORTSCX_FORCE_FULL_SPEED_CONNECT;
1061 portsc &= (~PORTSCX_FORCE_FULL_SPEED_CONNECT);
1063 writel(portsc, &udc->op_regs->portsc[0]);
1065 tmp = readl(&udc->op_regs->epctrlx[0]);
1066 tmp &= ~(EPCTRL_TX_EP_STALL | EPCTRL_RX_EP_STALL);
1067 writel(tmp, &udc->op_regs->epctrlx[0]);
1072 static int mv_udc_enable_internal(struct mv_udc *udc)
1079 dev_dbg(&udc->dev->dev, "enable udc\n");
1080 udc_clock_enable(udc);
1081 if (udc->pdata->phy_init) {
1082 retval = udc->pdata->phy_init(udc->phy_regs);
1084 dev_err(&udc->dev->dev,
1085 "init phy error %d\n", retval);
1086 udc_clock_disable(udc);
1095 static int mv_udc_enable(struct mv_udc *udc)
1097 if (udc->clock_gating)
1098 return mv_udc_enable_internal(udc);
1103 static void mv_udc_disable_internal(struct mv_udc *udc)
1106 dev_dbg(&udc->dev->dev, "disable udc\n");
1107 if (udc->pdata->phy_deinit)
1108 udc->pdata->phy_deinit(udc->phy_regs);
1109 udc_clock_disable(udc);
1114 static void mv_udc_disable(struct mv_udc *udc)
1116 if (udc->clock_gating)
1117 mv_udc_disable_internal(udc);
1120 static int mv_udc_get_frame(struct usb_gadget *gadget)
1128 udc = container_of(gadget, struct mv_udc, gadget);
1130 retval = readl(&udc->op_regs->frindex) & USB_FRINDEX_MASKS;
1135 /* Tries to wake up the host connected to this gadget */
1136 static int mv_udc_wakeup(struct usb_gadget *gadget)
1138 struct mv_udc *udc = container_of(gadget, struct mv_udc, gadget);
1141 /* Remote wakeup feature not enabled by host */
1142 if (!udc->remote_wakeup)
1145 portsc = readl(&udc->op_regs->portsc);
1146 /* not suspended? */
1147 if (!(portsc & PORTSCX_PORT_SUSPEND))
1149 /* trigger force resume */
1150 portsc |= PORTSCX_PORT_FORCE_RESUME;
1151 writel(portsc, &udc->op_regs->portsc[0]);
1155 static int mv_udc_vbus_session(struct usb_gadget *gadget, int is_active)
1158 unsigned long flags;
1161 udc = container_of(gadget, struct mv_udc, gadget);
1162 spin_lock_irqsave(&udc->lock, flags);
1164 udc->vbus_active = (is_active != 0);
1166 dev_dbg(&udc->dev->dev, "%s: softconnect %d, vbus_active %d\n",
1167 __func__, udc->softconnect, udc->vbus_active);
1169 if (udc->driver && udc->softconnect && udc->vbus_active) {
1170 retval = mv_udc_enable(udc);
1172 /* Clock is disabled, need re-init registers */
1177 } else if (udc->driver && udc->softconnect) {
1181 /* stop all the transfer in queue*/
1182 stop_activity(udc, udc->driver);
1184 mv_udc_disable(udc);
1188 spin_unlock_irqrestore(&udc->lock, flags);
1192 static int mv_udc_pullup(struct usb_gadget *gadget, int is_on)
1195 unsigned long flags;
1198 udc = container_of(gadget, struct mv_udc, gadget);
1199 spin_lock_irqsave(&udc->lock, flags);
1201 udc->softconnect = (is_on != 0);
1203 dev_dbg(&udc->dev->dev, "%s: softconnect %d, vbus_active %d\n",
1204 __func__, udc->softconnect, udc->vbus_active);
1206 if (udc->driver && udc->softconnect && udc->vbus_active) {
1207 retval = mv_udc_enable(udc);
1209 /* Clock is disabled, need re-init registers */
1214 } else if (udc->driver && udc->vbus_active) {
1215 /* stop all the transfer in queue*/
1216 stop_activity(udc, udc->driver);
1218 mv_udc_disable(udc);
1221 spin_unlock_irqrestore(&udc->lock, flags);
1225 static int mv_udc_start(struct usb_gadget *, struct usb_gadget_driver *);
1226 static int mv_udc_stop(struct usb_gadget *);
1227 /* device controller usb_gadget_ops structure */
1228 static const struct usb_gadget_ops mv_ops = {
1230 /* returns the current frame number */
1231 .get_frame = mv_udc_get_frame,
1233 /* tries to wake up the host connected to this gadget */
1234 .wakeup = mv_udc_wakeup,
1236 /* notify controller that VBUS is powered or not */
1237 .vbus_session = mv_udc_vbus_session,
1239 /* D+ pullup, software-controlled connect/disconnect to USB host */
1240 .pullup = mv_udc_pullup,
1241 .udc_start = mv_udc_start,
1242 .udc_stop = mv_udc_stop,
1245 static int eps_init(struct mv_udc *udc)
1251 /* initialize ep0 */
1254 strncpy(ep->name, "ep0", sizeof(ep->name));
1255 ep->ep.name = ep->name;
1256 ep->ep.ops = &mv_ep_ops;
1259 usb_ep_set_maxpacket_limit(&ep->ep, EP0_MAX_PKT_SIZE);
1260 ep->ep.caps.type_control = true;
1261 ep->ep.caps.dir_in = true;
1262 ep->ep.caps.dir_out = true;
1264 ep->ep.desc = &mv_ep0_desc;
1265 INIT_LIST_HEAD(&ep->queue);
1267 ep->ep_type = USB_ENDPOINT_XFER_CONTROL;
1269 /* initialize other endpoints */
1270 for (i = 2; i < udc->max_eps * 2; i++) {
1273 snprintf(name, sizeof(name), "ep%din", i / 2);
1274 ep->direction = EP_DIR_IN;
1275 ep->ep.caps.dir_in = true;
1277 snprintf(name, sizeof(name), "ep%dout", i / 2);
1278 ep->direction = EP_DIR_OUT;
1279 ep->ep.caps.dir_out = true;
1282 strncpy(ep->name, name, sizeof(ep->name));
1283 ep->ep.name = ep->name;
1285 ep->ep.caps.type_iso = true;
1286 ep->ep.caps.type_bulk = true;
1287 ep->ep.caps.type_int = true;
1289 ep->ep.ops = &mv_ep_ops;
1291 usb_ep_set_maxpacket_limit(&ep->ep, (unsigned short) ~0);
1294 INIT_LIST_HEAD(&ep->queue);
1295 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
1297 ep->dqh = &udc->ep_dqh[i];
1303 /* delete all endpoint requests, called with spinlock held */
1304 static void nuke(struct mv_ep *ep, int status)
1306 /* called with spinlock held */
1309 /* endpoint fifo flush */
1310 mv_ep_fifo_flush(&ep->ep);
1312 while (!list_empty(&ep->queue)) {
1313 struct mv_req *req = NULL;
1314 req = list_entry(ep->queue.next, struct mv_req, queue);
1315 done(ep, req, status);
1319 static void gadget_reset(struct mv_udc *udc, struct usb_gadget_driver *driver)
1323 nuke(&udc->eps[0], -ESHUTDOWN);
1325 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
1326 nuke(ep, -ESHUTDOWN);
1329 /* report reset; the driver is already quiesced */
1331 spin_unlock(&udc->lock);
1332 usb_gadget_udc_reset(&udc->gadget, driver);
1333 spin_lock(&udc->lock);
1336 /* stop all USB activities */
1337 static void stop_activity(struct mv_udc *udc, struct usb_gadget_driver *driver)
1341 nuke(&udc->eps[0], -ESHUTDOWN);
1343 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
1344 nuke(ep, -ESHUTDOWN);
1347 /* report disconnect; the driver is already quiesced */
1349 spin_unlock(&udc->lock);
1350 driver->disconnect(&udc->gadget);
1351 spin_lock(&udc->lock);
1355 static int mv_udc_start(struct usb_gadget *gadget,
1356 struct usb_gadget_driver *driver)
1360 unsigned long flags;
1362 udc = container_of(gadget, struct mv_udc, gadget);
1367 spin_lock_irqsave(&udc->lock, flags);
1369 /* hook up the driver ... */
1370 driver->driver.bus = NULL;
1371 udc->driver = driver;
1373 udc->usb_state = USB_STATE_ATTACHED;
1374 udc->ep0_state = WAIT_FOR_SETUP;
1375 udc->ep0_dir = EP_DIR_OUT;
1377 spin_unlock_irqrestore(&udc->lock, flags);
1379 if (udc->transceiver) {
1380 retval = otg_set_peripheral(udc->transceiver->otg,
1383 dev_err(&udc->dev->dev,
1384 "unable to register peripheral to otg\n");
1390 /* When boot with cable attached, there will be no vbus irq occurred */
1392 queue_work(udc->qwork, &udc->vbus_work);
1397 static int mv_udc_stop(struct usb_gadget *gadget)
1400 unsigned long flags;
1402 udc = container_of(gadget, struct mv_udc, gadget);
1404 spin_lock_irqsave(&udc->lock, flags);
1409 /* stop all usb activities */
1410 udc->gadget.speed = USB_SPEED_UNKNOWN;
1411 stop_activity(udc, NULL);
1412 mv_udc_disable(udc);
1414 spin_unlock_irqrestore(&udc->lock, flags);
1416 /* unbind gadget driver */
1422 static void mv_set_ptc(struct mv_udc *udc, u32 mode)
1426 portsc = readl(&udc->op_regs->portsc[0]);
1427 portsc |= mode << 16;
1428 writel(portsc, &udc->op_regs->portsc[0]);
1431 static void prime_status_complete(struct usb_ep *ep, struct usb_request *_req)
1433 struct mv_ep *mvep = container_of(ep, struct mv_ep, ep);
1434 struct mv_req *req = container_of(_req, struct mv_req, req);
1436 unsigned long flags;
1440 dev_info(&udc->dev->dev, "switch to test mode %d\n", req->test_mode);
1442 spin_lock_irqsave(&udc->lock, flags);
1443 if (req->test_mode) {
1444 mv_set_ptc(udc, req->test_mode);
1447 spin_unlock_irqrestore(&udc->lock, flags);
1451 udc_prime_status(struct mv_udc *udc, u8 direction, u16 status, bool empty)
1458 udc->ep0_dir = direction;
1459 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1461 req = udc->status_req;
1463 /* fill in the reqest structure */
1464 if (empty == false) {
1465 *((u16 *) req->req.buf) = cpu_to_le16(status);
1466 req->req.length = 2;
1468 req->req.length = 0;
1471 req->req.status = -EINPROGRESS;
1472 req->req.actual = 0;
1473 if (udc->test_mode) {
1474 req->req.complete = prime_status_complete;
1475 req->test_mode = udc->test_mode;
1478 req->req.complete = NULL;
1481 if (req->req.dma == DMA_ADDR_INVALID) {
1482 req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
1483 req->req.buf, req->req.length,
1484 ep_dir(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1488 /* prime the data phase */
1489 if (!req_to_dtd(req)) {
1490 retval = queue_dtd(ep, req);
1492 dev_err(&udc->dev->dev,
1493 "Failed to queue dtd when prime status\n");
1496 } else{ /* no mem */
1498 dev_err(&udc->dev->dev,
1499 "Failed to dma_pool_alloc when prime status\n");
1503 list_add_tail(&req->queue, &ep->queue);
1507 usb_gadget_unmap_request(&udc->gadget, &req->req, ep_dir(ep));
1512 static void mv_udc_testmode(struct mv_udc *udc, u16 index)
1514 if (index <= TEST_FORCE_EN) {
1515 udc->test_mode = index;
1516 if (udc_prime_status(udc, EP_DIR_IN, 0, true))
1519 dev_err(&udc->dev->dev,
1520 "This test mode(%d) is not supported\n", index);
1523 static void ch9setaddress(struct mv_udc *udc, struct usb_ctrlrequest *setup)
1525 udc->dev_addr = (u8)setup->wValue;
1527 /* update usb state */
1528 udc->usb_state = USB_STATE_ADDRESS;
1530 if (udc_prime_status(udc, EP_DIR_IN, 0, true))
1534 static void ch9getstatus(struct mv_udc *udc, u8 ep_num,
1535 struct usb_ctrlrequest *setup)
1540 if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK))
1541 != (USB_DIR_IN | USB_TYPE_STANDARD))
1544 if ((setup->bRequestType & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
1545 status = 1 << USB_DEVICE_SELF_POWERED;
1546 status |= udc->remote_wakeup << USB_DEVICE_REMOTE_WAKEUP;
1547 } else if ((setup->bRequestType & USB_RECIP_MASK)
1548 == USB_RECIP_INTERFACE) {
1549 /* get interface status */
1551 } else if ((setup->bRequestType & USB_RECIP_MASK)
1552 == USB_RECIP_ENDPOINT) {
1553 u8 ep_num, direction;
1555 ep_num = setup->wIndex & USB_ENDPOINT_NUMBER_MASK;
1556 direction = (setup->wIndex & USB_ENDPOINT_DIR_MASK)
1557 ? EP_DIR_IN : EP_DIR_OUT;
1558 status = ep_is_stall(udc, ep_num, direction)
1559 << USB_ENDPOINT_HALT;
1562 retval = udc_prime_status(udc, EP_DIR_IN, status, false);
1566 udc->ep0_state = DATA_STATE_XMIT;
1569 static void ch9clearfeature(struct mv_udc *udc, struct usb_ctrlrequest *setup)
1575 if ((setup->bRequestType & (USB_TYPE_MASK | USB_RECIP_MASK))
1576 == ((USB_TYPE_STANDARD | USB_RECIP_DEVICE))) {
1577 switch (setup->wValue) {
1578 case USB_DEVICE_REMOTE_WAKEUP:
1579 udc->remote_wakeup = 0;
1584 } else if ((setup->bRequestType & (USB_TYPE_MASK | USB_RECIP_MASK))
1585 == ((USB_TYPE_STANDARD | USB_RECIP_ENDPOINT))) {
1586 switch (setup->wValue) {
1587 case USB_ENDPOINT_HALT:
1588 ep_num = setup->wIndex & USB_ENDPOINT_NUMBER_MASK;
1589 direction = (setup->wIndex & USB_ENDPOINT_DIR_MASK)
1590 ? EP_DIR_IN : EP_DIR_OUT;
1591 if (setup->wValue != 0 || setup->wLength != 0
1592 || ep_num > udc->max_eps)
1594 ep = &udc->eps[ep_num * 2 + direction];
1597 spin_unlock(&udc->lock);
1598 ep_set_stall(udc, ep_num, direction, 0);
1599 spin_lock(&udc->lock);
1607 if (udc_prime_status(udc, EP_DIR_IN, 0, true))
1613 static void ch9setfeature(struct mv_udc *udc, struct usb_ctrlrequest *setup)
1618 if ((setup->bRequestType & (USB_TYPE_MASK | USB_RECIP_MASK))
1619 == ((USB_TYPE_STANDARD | USB_RECIP_DEVICE))) {
1620 switch (setup->wValue) {
1621 case USB_DEVICE_REMOTE_WAKEUP:
1622 udc->remote_wakeup = 1;
1624 case USB_DEVICE_TEST_MODE:
1625 if (setup->wIndex & 0xFF
1626 || udc->gadget.speed != USB_SPEED_HIGH)
1629 if (udc->usb_state != USB_STATE_CONFIGURED
1630 && udc->usb_state != USB_STATE_ADDRESS
1631 && udc->usb_state != USB_STATE_DEFAULT)
1634 mv_udc_testmode(udc, (setup->wIndex >> 8));
1639 } else if ((setup->bRequestType & (USB_TYPE_MASK | USB_RECIP_MASK))
1640 == ((USB_TYPE_STANDARD | USB_RECIP_ENDPOINT))) {
1641 switch (setup->wValue) {
1642 case USB_ENDPOINT_HALT:
1643 ep_num = setup->wIndex & USB_ENDPOINT_NUMBER_MASK;
1644 direction = (setup->wIndex & USB_ENDPOINT_DIR_MASK)
1645 ? EP_DIR_IN : EP_DIR_OUT;
1646 if (setup->wValue != 0 || setup->wLength != 0
1647 || ep_num > udc->max_eps)
1649 spin_unlock(&udc->lock);
1650 ep_set_stall(udc, ep_num, direction, 1);
1651 spin_lock(&udc->lock);
1659 if (udc_prime_status(udc, EP_DIR_IN, 0, true))
1665 static void handle_setup_packet(struct mv_udc *udc, u8 ep_num,
1666 struct usb_ctrlrequest *setup)
1667 __releases(&ep->udc->lock)
1668 __acquires(&ep->udc->lock)
1670 bool delegate = false;
1672 nuke(&udc->eps[ep_num * 2 + EP_DIR_OUT], -ESHUTDOWN);
1674 dev_dbg(&udc->dev->dev, "SETUP %02x.%02x v%04x i%04x l%04x\n",
1675 setup->bRequestType, setup->bRequest,
1676 setup->wValue, setup->wIndex, setup->wLength);
1677 /* We process some standard setup requests here */
1678 if ((setup->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1679 switch (setup->bRequest) {
1680 case USB_REQ_GET_STATUS:
1681 ch9getstatus(udc, ep_num, setup);
1684 case USB_REQ_SET_ADDRESS:
1685 ch9setaddress(udc, setup);
1688 case USB_REQ_CLEAR_FEATURE:
1689 ch9clearfeature(udc, setup);
1692 case USB_REQ_SET_FEATURE:
1693 ch9setfeature(udc, setup);
1702 /* delegate USB standard requests to the gadget driver */
1703 if (delegate == true) {
1704 /* USB requests handled by gadget */
1705 if (setup->wLength) {
1706 /* DATA phase from gadget, STATUS phase from udc */
1707 udc->ep0_dir = (setup->bRequestType & USB_DIR_IN)
1708 ? EP_DIR_IN : EP_DIR_OUT;
1709 spin_unlock(&udc->lock);
1710 if (udc->driver->setup(&udc->gadget,
1711 &udc->local_setup_buff) < 0)
1713 spin_lock(&udc->lock);
1714 udc->ep0_state = (setup->bRequestType & USB_DIR_IN)
1715 ? DATA_STATE_XMIT : DATA_STATE_RECV;
1717 /* no DATA phase, IN STATUS phase from gadget */
1718 udc->ep0_dir = EP_DIR_IN;
1719 spin_unlock(&udc->lock);
1720 if (udc->driver->setup(&udc->gadget,
1721 &udc->local_setup_buff) < 0)
1723 spin_lock(&udc->lock);
1724 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1729 /* complete DATA or STATUS phase of ep0 prime status phase if needed */
1730 static void ep0_req_complete(struct mv_udc *udc,
1731 struct mv_ep *ep0, struct mv_req *req)
1735 if (udc->usb_state == USB_STATE_ADDRESS) {
1736 /* set the new address */
1737 new_addr = (u32)udc->dev_addr;
1738 writel(new_addr << USB_DEVICE_ADDRESS_BIT_SHIFT,
1739 &udc->op_regs->deviceaddr);
1744 switch (udc->ep0_state) {
1745 case DATA_STATE_XMIT:
1746 /* receive status phase */
1747 if (udc_prime_status(udc, EP_DIR_OUT, 0, true))
1750 case DATA_STATE_RECV:
1751 /* send status phase */
1752 if (udc_prime_status(udc, EP_DIR_IN, 0 , true))
1755 case WAIT_FOR_OUT_STATUS:
1756 udc->ep0_state = WAIT_FOR_SETUP;
1758 case WAIT_FOR_SETUP:
1759 dev_err(&udc->dev->dev, "unexpect ep0 packets\n");
1767 static void get_setup_data(struct mv_udc *udc, u8 ep_num, u8 *buffer_ptr)
1772 dqh = &udc->ep_dqh[ep_num * 2 + EP_DIR_OUT];
1774 /* Clear bit in ENDPTSETUPSTAT */
1775 writel((1 << ep_num), &udc->op_regs->epsetupstat);
1777 /* while a hazard exists when setup package arrives */
1779 /* Set Setup Tripwire */
1780 temp = readl(&udc->op_regs->usbcmd);
1781 writel(temp | USBCMD_SETUP_TRIPWIRE_SET, &udc->op_regs->usbcmd);
1783 /* Copy the setup packet to local buffer */
1784 memcpy(buffer_ptr, (u8 *) dqh->setup_buffer, 8);
1785 } while (!(readl(&udc->op_regs->usbcmd) & USBCMD_SETUP_TRIPWIRE_SET));
1787 /* Clear Setup Tripwire */
1788 temp = readl(&udc->op_regs->usbcmd);
1789 writel(temp & ~USBCMD_SETUP_TRIPWIRE_SET, &udc->op_regs->usbcmd);
1792 static void irq_process_tr_complete(struct mv_udc *udc)
1795 int i, ep_num = 0, direction = 0;
1796 struct mv_ep *curr_ep;
1797 struct mv_req *curr_req, *temp_req;
1801 * We use separate loops for ENDPTSETUPSTAT and ENDPTCOMPLETE
1802 * because the setup packets are to be read ASAP
1805 /* Process all Setup packet received interrupts */
1806 tmp = readl(&udc->op_regs->epsetupstat);
1809 for (i = 0; i < udc->max_eps; i++) {
1810 if (tmp & (1 << i)) {
1811 get_setup_data(udc, i,
1812 (u8 *)(&udc->local_setup_buff));
1813 handle_setup_packet(udc, i,
1814 &udc->local_setup_buff);
1819 /* Don't clear the endpoint setup status register here.
1820 * It is cleared as a setup packet is read out of the buffer
1823 /* Process non-setup transaction complete interrupts */
1824 tmp = readl(&udc->op_regs->epcomplete);
1829 writel(tmp, &udc->op_regs->epcomplete);
1831 for (i = 0; i < udc->max_eps * 2; i++) {
1835 bit_pos = 1 << (ep_num + 16 * direction);
1837 if (!(bit_pos & tmp))
1841 curr_ep = &udc->eps[0];
1843 curr_ep = &udc->eps[i];
1844 /* process the req queue until an uncomplete request */
1845 list_for_each_entry_safe(curr_req, temp_req,
1846 &curr_ep->queue, queue) {
1847 status = process_ep_req(udc, i, curr_req);
1851 /* write back status to req */
1852 curr_req->req.status = status;
1854 /* ep0 request completion */
1856 ep0_req_complete(udc, curr_ep, curr_req);
1859 done(curr_ep, curr_req, status);
1865 static void irq_process_reset(struct mv_udc *udc)
1870 udc->ep0_dir = EP_DIR_OUT;
1871 udc->ep0_state = WAIT_FOR_SETUP;
1872 udc->remote_wakeup = 0; /* default to 0 on reset */
1874 /* The address bits are past bit 25-31. Set the address */
1875 tmp = readl(&udc->op_regs->deviceaddr);
1876 tmp &= ~(USB_DEVICE_ADDRESS_MASK);
1877 writel(tmp, &udc->op_regs->deviceaddr);
1879 /* Clear all the setup token semaphores */
1880 tmp = readl(&udc->op_regs->epsetupstat);
1881 writel(tmp, &udc->op_regs->epsetupstat);
1883 /* Clear all the endpoint complete status bits */
1884 tmp = readl(&udc->op_regs->epcomplete);
1885 writel(tmp, &udc->op_regs->epcomplete);
1887 /* wait until all endptprime bits cleared */
1888 loops = LOOPS(PRIME_TIMEOUT);
1889 while (readl(&udc->op_regs->epprime) & 0xFFFFFFFF) {
1891 dev_err(&udc->dev->dev,
1892 "Timeout for ENDPTPRIME = 0x%x\n",
1893 readl(&udc->op_regs->epprime));
1900 /* Write 1s to the Flush register */
1901 writel((u32)~0, &udc->op_regs->epflush);
1903 if (readl(&udc->op_regs->portsc[0]) & PORTSCX_PORT_RESET) {
1904 dev_info(&udc->dev->dev, "usb bus reset\n");
1905 udc->usb_state = USB_STATE_DEFAULT;
1906 /* reset all the queues, stop all USB activities */
1907 gadget_reset(udc, udc->driver);
1909 dev_info(&udc->dev->dev, "USB reset portsc 0x%x\n",
1910 readl(&udc->op_regs->portsc));
1918 /* reset all the queues, stop all USB activities */
1919 stop_activity(udc, udc->driver);
1921 /* reset ep0 dQH and endptctrl */
1924 /* enable interrupt and set controller to run state */
1927 udc->usb_state = USB_STATE_ATTACHED;
1931 static void handle_bus_resume(struct mv_udc *udc)
1933 udc->usb_state = udc->resume_state;
1934 udc->resume_state = 0;
1936 /* report resume to the driver */
1938 if (udc->driver->resume) {
1939 spin_unlock(&udc->lock);
1940 udc->driver->resume(&udc->gadget);
1941 spin_lock(&udc->lock);
1946 static void irq_process_suspend(struct mv_udc *udc)
1948 udc->resume_state = udc->usb_state;
1949 udc->usb_state = USB_STATE_SUSPENDED;
1951 if (udc->driver->suspend) {
1952 spin_unlock(&udc->lock);
1953 udc->driver->suspend(&udc->gadget);
1954 spin_lock(&udc->lock);
1958 static void irq_process_port_change(struct mv_udc *udc)
1962 portsc = readl(&udc->op_regs->portsc[0]);
1963 if (!(portsc & PORTSCX_PORT_RESET)) {
1965 u32 speed = portsc & PORTSCX_PORT_SPEED_MASK;
1967 case PORTSCX_PORT_SPEED_HIGH:
1968 udc->gadget.speed = USB_SPEED_HIGH;
1970 case PORTSCX_PORT_SPEED_FULL:
1971 udc->gadget.speed = USB_SPEED_FULL;
1973 case PORTSCX_PORT_SPEED_LOW:
1974 udc->gadget.speed = USB_SPEED_LOW;
1977 udc->gadget.speed = USB_SPEED_UNKNOWN;
1982 if (portsc & PORTSCX_PORT_SUSPEND) {
1983 udc->resume_state = udc->usb_state;
1984 udc->usb_state = USB_STATE_SUSPENDED;
1985 if (udc->driver->suspend) {
1986 spin_unlock(&udc->lock);
1987 udc->driver->suspend(&udc->gadget);
1988 spin_lock(&udc->lock);
1992 if (!(portsc & PORTSCX_PORT_SUSPEND)
1993 && udc->usb_state == USB_STATE_SUSPENDED) {
1994 handle_bus_resume(udc);
1997 if (!udc->resume_state)
1998 udc->usb_state = USB_STATE_DEFAULT;
2001 static void irq_process_error(struct mv_udc *udc)
2003 /* Increment the error count */
2007 static irqreturn_t mv_udc_irq(int irq, void *dev)
2009 struct mv_udc *udc = (struct mv_udc *)dev;
2012 /* Disable ISR when stopped bit is set */
2016 spin_lock(&udc->lock);
2018 status = readl(&udc->op_regs->usbsts);
2019 intr = readl(&udc->op_regs->usbintr);
2023 spin_unlock(&udc->lock);
2027 /* Clear all the interrupts occurred */
2028 writel(status, &udc->op_regs->usbsts);
2030 if (status & USBSTS_ERR)
2031 irq_process_error(udc);
2033 if (status & USBSTS_RESET)
2034 irq_process_reset(udc);
2036 if (status & USBSTS_PORT_CHANGE)
2037 irq_process_port_change(udc);
2039 if (status & USBSTS_INT)
2040 irq_process_tr_complete(udc);
2042 if (status & USBSTS_SUSPEND)
2043 irq_process_suspend(udc);
2045 spin_unlock(&udc->lock);
2050 static irqreturn_t mv_udc_vbus_irq(int irq, void *dev)
2052 struct mv_udc *udc = (struct mv_udc *)dev;
2054 /* polling VBUS and init phy may cause too much time*/
2056 queue_work(udc->qwork, &udc->vbus_work);
2061 static void mv_udc_vbus_work(struct work_struct *work)
2066 udc = container_of(work, struct mv_udc, vbus_work);
2067 if (!udc->pdata->vbus)
2070 vbus = udc->pdata->vbus->poll();
2071 dev_info(&udc->dev->dev, "vbus is %d\n", vbus);
2073 if (vbus == VBUS_HIGH)
2074 mv_udc_vbus_session(&udc->gadget, 1);
2075 else if (vbus == VBUS_LOW)
2076 mv_udc_vbus_session(&udc->gadget, 0);
2079 /* release device structure */
2080 static void gadget_release(struct device *_dev)
2084 udc = dev_get_drvdata(_dev);
2086 complete(udc->done);
2089 static int mv_udc_remove(struct platform_device *pdev)
2093 udc = platform_get_drvdata(pdev);
2095 usb_del_gadget_udc(&udc->gadget);
2098 flush_workqueue(udc->qwork);
2099 destroy_workqueue(udc->qwork);
2102 /* free memory allocated in probe */
2103 dma_pool_destroy(udc->dtd_pool);
2106 dma_free_coherent(&pdev->dev, udc->ep_dqh_size,
2107 udc->ep_dqh, udc->ep_dqh_dma);
2109 mv_udc_disable(udc);
2111 /* free dev, wait for the release() finished */
2112 wait_for_completion(udc->done);
2117 static int mv_udc_probe(struct platform_device *pdev)
2119 struct mv_usb_platform_data *pdata = dev_get_platdata(&pdev->dev);
2125 if (pdata == NULL) {
2126 dev_err(&pdev->dev, "missing platform_data\n");
2130 udc = devm_kzalloc(&pdev->dev, sizeof(*udc), GFP_KERNEL);
2134 udc->done = &release_done;
2135 udc->pdata = dev_get_platdata(&pdev->dev);
2136 spin_lock_init(&udc->lock);
2140 if (pdata->mode == MV_USB_MODE_OTG) {
2141 udc->transceiver = devm_usb_get_phy(&pdev->dev,
2143 if (IS_ERR(udc->transceiver)) {
2144 retval = PTR_ERR(udc->transceiver);
2146 if (retval == -ENXIO)
2149 udc->transceiver = NULL;
2150 return -EPROBE_DEFER;
2154 /* udc only have one sysclk. */
2155 udc->clk = devm_clk_get(&pdev->dev, NULL);
2156 if (IS_ERR(udc->clk))
2157 return PTR_ERR(udc->clk);
2159 r = platform_get_resource_byname(udc->dev, IORESOURCE_MEM, "capregs");
2161 dev_err(&pdev->dev, "no I/O memory resource defined\n");
2165 udc->cap_regs = (struct mv_cap_regs __iomem *)
2166 devm_ioremap(&pdev->dev, r->start, resource_size(r));
2167 if (udc->cap_regs == NULL) {
2168 dev_err(&pdev->dev, "failed to map I/O memory\n");
2172 r = platform_get_resource_byname(udc->dev, IORESOURCE_MEM, "phyregs");
2174 dev_err(&pdev->dev, "no phy I/O memory resource defined\n");
2178 udc->phy_regs = devm_ioremap(&pdev->dev, r->start, resource_size(r));
2179 if (udc->phy_regs == NULL) {
2180 dev_err(&pdev->dev, "failed to map phy I/O memory\n");
2184 /* we will acces controller register, so enable the clk */
2185 retval = mv_udc_enable_internal(udc);
2190 (struct mv_op_regs __iomem *)((unsigned long)udc->cap_regs
2191 + (readl(&udc->cap_regs->caplength_hciversion)
2193 udc->max_eps = readl(&udc->cap_regs->dccparams) & DCCPARAMS_DEN_MASK;
2196 * some platform will use usb to download image, it may not disconnect
2197 * usb gadget before loading kernel. So first stop udc here.
2200 writel(0xFFFFFFFF, &udc->op_regs->usbsts);
2202 size = udc->max_eps * sizeof(struct mv_dqh) *2;
2203 size = (size + DQH_ALIGNMENT - 1) & ~(DQH_ALIGNMENT - 1);
2204 udc->ep_dqh = dma_alloc_coherent(&pdev->dev, size,
2205 &udc->ep_dqh_dma, GFP_KERNEL);
2207 if (udc->ep_dqh == NULL) {
2208 dev_err(&pdev->dev, "allocate dQH memory failed\n");
2210 goto err_disable_clock;
2212 udc->ep_dqh_size = size;
2214 /* create dTD dma_pool resource */
2215 udc->dtd_pool = dma_pool_create("mv_dtd",
2217 sizeof(struct mv_dtd),
2221 if (!udc->dtd_pool) {
2226 size = udc->max_eps * sizeof(struct mv_ep) *2;
2227 udc->eps = devm_kzalloc(&pdev->dev, size, GFP_KERNEL);
2228 if (udc->eps == NULL) {
2230 goto err_destroy_dma;
2233 /* initialize ep0 status request structure */
2234 udc->status_req = devm_kzalloc(&pdev->dev, sizeof(struct mv_req),
2236 if (!udc->status_req) {
2238 goto err_destroy_dma;
2240 INIT_LIST_HEAD(&udc->status_req->queue);
2242 /* allocate a small amount of memory to get valid address */
2243 udc->status_req->req.buf = kzalloc(8, GFP_KERNEL);
2244 udc->status_req->req.dma = DMA_ADDR_INVALID;
2246 udc->resume_state = USB_STATE_NOTATTACHED;
2247 udc->usb_state = USB_STATE_POWERED;
2248 udc->ep0_dir = EP_DIR_OUT;
2249 udc->remote_wakeup = 0;
2251 r = platform_get_resource(udc->dev, IORESOURCE_IRQ, 0);
2253 dev_err(&pdev->dev, "no IRQ resource defined\n");
2255 goto err_destroy_dma;
2257 udc->irq = r->start;
2258 if (devm_request_irq(&pdev->dev, udc->irq, mv_udc_irq,
2259 IRQF_SHARED, driver_name, udc)) {
2260 dev_err(&pdev->dev, "Request irq %d for UDC failed\n",
2263 goto err_destroy_dma;
2266 /* initialize gadget structure */
2267 udc->gadget.ops = &mv_ops; /* usb_gadget_ops */
2268 udc->gadget.ep0 = &udc->eps[0].ep; /* gadget ep0 */
2269 INIT_LIST_HEAD(&udc->gadget.ep_list); /* ep_list */
2270 udc->gadget.speed = USB_SPEED_UNKNOWN; /* speed */
2271 udc->gadget.max_speed = USB_SPEED_HIGH; /* support dual speed */
2273 /* the "gadget" abstracts/virtualizes the controller */
2274 udc->gadget.name = driver_name; /* gadget name */
2278 /* VBUS detect: we can disable/enable clock on demand.*/
2279 if (udc->transceiver)
2280 udc->clock_gating = 1;
2281 else if (pdata->vbus) {
2282 udc->clock_gating = 1;
2283 retval = devm_request_threaded_irq(&pdev->dev,
2284 pdata->vbus->irq, NULL,
2285 mv_udc_vbus_irq, IRQF_ONESHOT, "vbus", udc);
2287 dev_info(&pdev->dev,
2288 "Can not request irq for VBUS, "
2289 "disable clock gating\n");
2290 udc->clock_gating = 0;
2293 udc->qwork = create_singlethread_workqueue("mv_udc_queue");
2295 dev_err(&pdev->dev, "cannot create workqueue\n");
2297 goto err_destroy_dma;
2300 INIT_WORK(&udc->vbus_work, mv_udc_vbus_work);
2304 * When clock gating is supported, we can disable clk and phy.
2305 * If not, it means that VBUS detection is not supported, we
2306 * have to enable vbus active all the time to let controller work.
2308 if (udc->clock_gating)
2309 mv_udc_disable_internal(udc);
2311 udc->vbus_active = 1;
2313 retval = usb_add_gadget_udc_release(&pdev->dev, &udc->gadget,
2316 goto err_create_workqueue;
2318 platform_set_drvdata(pdev, udc);
2319 dev_info(&pdev->dev, "successful probe UDC device %s clock gating.\n",
2320 udc->clock_gating ? "with" : "without");
2324 err_create_workqueue:
2325 destroy_workqueue(udc->qwork);
2327 dma_pool_destroy(udc->dtd_pool);
2329 dma_free_coherent(&pdev->dev, udc->ep_dqh_size,
2330 udc->ep_dqh, udc->ep_dqh_dma);
2332 mv_udc_disable_internal(udc);
2338 static int mv_udc_suspend(struct device *dev)
2342 udc = dev_get_drvdata(dev);
2344 /* if OTG is enabled, the following will be done in OTG driver*/
2345 if (udc->transceiver)
2348 if (udc->pdata->vbus && udc->pdata->vbus->poll)
2349 if (udc->pdata->vbus->poll() == VBUS_HIGH) {
2350 dev_info(&udc->dev->dev, "USB cable is connected!\n");
2355 * only cable is unplugged, udc can suspend.
2356 * So do not care about clock_gating == 1.
2358 if (!udc->clock_gating) {
2361 spin_lock_irq(&udc->lock);
2362 /* stop all usb activities */
2363 stop_activity(udc, udc->driver);
2364 spin_unlock_irq(&udc->lock);
2366 mv_udc_disable_internal(udc);
2372 static int mv_udc_resume(struct device *dev)
2377 udc = dev_get_drvdata(dev);
2379 /* if OTG is enabled, the following will be done in OTG driver*/
2380 if (udc->transceiver)
2383 if (!udc->clock_gating) {
2384 retval = mv_udc_enable_internal(udc);
2388 if (udc->driver && udc->softconnect) {
2398 static const struct dev_pm_ops mv_udc_pm_ops = {
2399 .suspend = mv_udc_suspend,
2400 .resume = mv_udc_resume,
2404 static void mv_udc_shutdown(struct platform_device *pdev)
2409 udc = platform_get_drvdata(pdev);
2410 /* reset controller mode to IDLE */
2412 mode = readl(&udc->op_regs->usbmode);
2414 writel(mode, &udc->op_regs->usbmode);
2415 mv_udc_disable(udc);
2418 static struct platform_driver udc_driver = {
2419 .probe = mv_udc_probe,
2420 .remove = mv_udc_remove,
2421 .shutdown = mv_udc_shutdown,
2425 .pm = &mv_udc_pm_ops,
2430 module_platform_driver(udc_driver);
2431 MODULE_ALIAS("platform:mv-udc");
2432 MODULE_DESCRIPTION(DRIVER_DESC);
2433 MODULE_AUTHOR("Chao Xie <chao.xie@marvell.com>");
2434 MODULE_VERSION(DRIVER_VERSION);
2435 MODULE_LICENSE("GPL");