2 * Copyright (c) 2007-2008, Juniper Networks, Inc.
3 * Copyright (c) 2008, Excito Elektronik i Skåne AB
4 * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation version 2 of
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <asm/byteorder.h>
33 struct ehci_hccr *hccr; /* R/O registers, not need for volatile */
34 volatile struct ehci_hcor *hcor;
36 static uint16_t portreset;
37 DEFINE_ALIGN_BUFFER(struct QH, qh_list, 1, USB_DMA_MINALIGN);
39 #define ALIGN_END_ADDR(type, ptr, size) \
40 ((uint32_t)(ptr) + roundup((size) * sizeof(type), USB_DMA_MINALIGN))
42 static struct descriptor {
43 struct usb_hub_descriptor hub;
44 struct usb_device_descriptor device;
45 struct usb_linux_config_descriptor config;
46 struct usb_linux_interface_descriptor interface;
47 struct usb_endpoint_descriptor endpoint;
48 } __attribute__ ((packed)) descriptor = {
50 0x8, /* bDescLength */
51 0x29, /* bDescriptorType: hub descriptor */
52 2, /* bNrPorts -- runtime modified */
53 0, /* wHubCharacteristics */
54 10, /* bPwrOn2PwrGood */
55 0, /* bHubCntrCurrent */
56 {}, /* Device removable */
57 {} /* at most 7 ports! XXX */
61 1, /* bDescriptorType: UDESC_DEVICE */
62 cpu_to_le16(0x0200), /* bcdUSB: v2.0 */
63 9, /* bDeviceClass: UDCLASS_HUB */
64 0, /* bDeviceSubClass: UDSUBCLASS_HUB */
65 1, /* bDeviceProtocol: UDPROTO_HSHUBSTT */
66 64, /* bMaxPacketSize: 64 bytes */
67 0x0000, /* idVendor */
68 0x0000, /* idProduct */
69 cpu_to_le16(0x0100), /* bcdDevice */
70 1, /* iManufacturer */
72 0, /* iSerialNumber */
73 1 /* bNumConfigurations: 1 */
77 2, /* bDescriptorType: UDESC_CONFIG */
79 1, /* bNumInterface */
80 1, /* bConfigurationValue */
81 0, /* iConfiguration */
82 0x40, /* bmAttributes: UC_SELF_POWER */
87 4, /* bDescriptorType: UDESC_INTERFACE */
88 0, /* bInterfaceNumber */
89 0, /* bAlternateSetting */
90 1, /* bNumEndpoints */
91 9, /* bInterfaceClass: UICLASS_HUB */
92 0, /* bInterfaceSubClass: UISUBCLASS_HUB */
93 0, /* bInterfaceProtocol: UIPROTO_HSHUBSTT */
98 5, /* bDescriptorType: UDESC_ENDPOINT */
99 0x81, /* bEndpointAddress:
100 * UE_DIR_IN | EHCI_INTR_ENDPT
102 3, /* bmAttributes: UE_INTERRUPT */
103 8, /* wMaxPacketSize */
108 #if defined(CONFIG_EHCI_IS_TDI)
109 #define ehci_is_TDI() (1)
111 #define ehci_is_TDI() (0)
114 void __ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg)
119 void ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg)
120 __attribute__((weak, alias("__ehci_powerup_fixup")));
122 static int handshake(uint32_t *ptr, uint32_t mask, uint32_t done, int usec)
126 result = ehci_readl(ptr);
128 if (result == ~(uint32_t)0)
138 static int ehci_reset(void)
145 cmd = ehci_readl(&hcor->or_usbcmd);
146 cmd = (cmd & ~CMD_RUN) | CMD_RESET;
147 ehci_writel(&hcor->or_usbcmd, cmd);
148 ret = handshake((uint32_t *)&hcor->or_usbcmd, CMD_RESET, 0, 250 * 1000);
150 printf("EHCI fail to reset\n");
155 reg_ptr = (uint32_t *)((u8 *)hcor + USBMODE);
156 tmp = ehci_readl(reg_ptr);
157 tmp |= USBMODE_CM_HC;
158 #if defined(CONFIG_EHCI_MMIO_BIG_ENDIAN)
161 ehci_writel(reg_ptr, tmp);
164 #ifdef CONFIG_USB_EHCI_TXFIFO_THRESH
165 cmd = ehci_readl(&hcor->or_txfilltuning);
166 cmd &= ~TXFIFO_THRESH_MASK;
167 cmd |= TXFIFO_THRESH(CONFIG_USB_EHCI_TXFIFO_THRESH);
168 ehci_writel(&hcor->or_txfilltuning, cmd);
174 static int ehci_td_buffer(struct qTD *td, void *buf, size_t sz)
176 uint32_t delta, next;
177 uint32_t addr = (uint32_t)buf;
180 if (addr != ALIGN(addr, ARCH_DMA_MINALIGN))
181 debug("EHCI-HCD: Misaligned buffer address (%p)\n", buf);
183 flush_dcache_range(addr, ALIGN(addr + sz, ARCH_DMA_MINALIGN));
186 while (idx < QT_BUFFER_CNT) {
187 td->qt_buffer[idx] = cpu_to_hc32(addr);
188 td->qt_buffer_hi[idx] = 0;
189 next = (addr + EHCI_PAGE_SIZE) & ~(EHCI_PAGE_SIZE - 1);
198 if (idx == QT_BUFFER_CNT) {
199 printf("out of buffer pointers (%u bytes left)\n", sz);
207 ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
208 int length, struct devrequest *req)
210 ALLOC_ALIGN_BUFFER(struct QH, qh, 1, USB_DMA_MINALIGN);
215 volatile struct qTD *vtd;
218 uint32_t endpt, token, usbsts;
224 debug("dev=%p, pipe=%lx, buffer=%p, length=%d, req=%p\n", dev, pipe,
225 buffer, length, req);
227 debug("req=%u (%#x), type=%u (%#x), value=%u (%#x), index=%u\n",
228 req->request, req->request,
229 req->requesttype, req->requesttype,
230 le16_to_cpu(req->value), le16_to_cpu(req->value),
231 le16_to_cpu(req->index));
234 * The USB transfer is split into qTD transfers. Eeach qTD transfer is
235 * described by a transfer descriptor (the qTD). The qTDs form a linked
236 * list with a queue head (QH).
238 * Each qTD transfer starts with a new USB packet, i.e. a packet cannot
239 * have its beginning in a qTD transfer and its end in the following
240 * one, so the qTD transfer lengths have to be chosen accordingly.
242 * Each qTD transfer uses up to QT_BUFFER_CNT data buffers, mapped to
243 * single pages. The first data buffer can start at any offset within a
244 * page (not considering the cache-line alignment issues), while the
245 * following buffers must be page-aligned. There is no alignment
246 * constraint on the size of a qTD transfer.
249 /* 1 qTD will be needed for SETUP, and 1 for ACK. */
251 if (length > 0 || req == NULL) {
253 * Determine the qTD transfer size that will be used for the
254 * data payload (not considering the final qTD transfer, which
257 * In order to keep each packet within a qTD transfer, the qTD
258 * transfer size is aligned to EHCI_PAGE_SIZE, which is a
259 * multiple of wMaxPacketSize (except in some cases for
260 * interrupt transfers, see comment in submit_int_msg()).
262 * By default, i.e. if the input buffer is page-aligned,
263 * QT_BUFFER_CNT full pages will be used.
265 int xfr_sz = QT_BUFFER_CNT;
267 * However, if the input buffer is not page-aligned, the qTD
268 * transfer size will be one page shorter, and the first qTD
269 * data buffer of each transfer will be page-unaligned.
271 if ((uint32_t)buffer & (EHCI_PAGE_SIZE - 1))
273 /* Convert the qTD transfer size to bytes. */
274 xfr_sz *= EHCI_PAGE_SIZE;
276 * Determine the number of qTDs that will be required for the
277 * data payload. This value has to be rounded up since the final
278 * qTD transfer may be shorter than the regular qTD transfer
279 * size that has just been computed.
281 qtd_count += DIV_ROUND_UP(length, xfr_sz);
282 /* ZLPs also need a qTD. */
287 * Threshold value based on the worst-case total size of the qTDs to allocate
288 * for a mass-storage transfer of 65535 blocks of 512 bytes.
290 #if CONFIG_SYS_MALLOC_LEN <= 128 * 1024
291 #warning CONFIG_SYS_MALLOC_LEN may be too small for EHCI
293 qtd = memalign(USB_DMA_MINALIGN, qtd_count * sizeof(struct qTD));
295 printf("unable to allocate TDs\n");
299 memset(qh, 0, sizeof(struct QH));
300 memset(qtd, 0, qtd_count * sizeof(*qtd));
302 toggle = usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe));
305 * Setup QH (3.6 in ehci-r10.pdf)
307 * qh_link ................. 03-00 H
308 * qh_endpt1 ............... 07-04 H
309 * qh_endpt2 ............... 0B-08 H
311 * qh_overlay.qt_next ...... 13-10 H
312 * - qh_overlay.qt_altnext
314 qh->qh_link = cpu_to_hc32((uint32_t)qh_list | QH_LINK_TYPE_QH);
315 c = usb_pipespeed(pipe) != USB_SPEED_HIGH && !usb_pipeendpoint(pipe);
316 endpt = QH_ENDPT1_RL(8) | QH_ENDPT1_C(c) |
317 QH_ENDPT1_MAXPKTLEN(usb_maxpacket(dev, pipe)) | QH_ENDPT1_H(0) |
318 QH_ENDPT1_DTC(QH_ENDPT1_DTC_DT_FROM_QTD) |
319 QH_ENDPT1_EPS(usb_pipespeed(pipe)) |
320 QH_ENDPT1_ENDPT(usb_pipeendpoint(pipe)) | QH_ENDPT1_I(0) |
321 QH_ENDPT1_DEVADDR(usb_pipedevice(pipe));
322 qh->qh_endpt1 = cpu_to_hc32(endpt);
323 endpt = QH_ENDPT2_MULT(1) | QH_ENDPT2_PORTNUM(dev->portnr) |
324 QH_ENDPT2_HUBADDR(dev->parent->devnum) |
325 QH_ENDPT2_UFCMASK(0) | QH_ENDPT2_UFSMASK(0);
326 qh->qh_endpt2 = cpu_to_hc32(endpt);
327 qh->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
329 tdp = &qh->qh_overlay.qt_next;
333 * Setup request qTD (3.5 in ehci-r10.pdf)
335 * qt_next ................ 03-00 H
336 * qt_altnext ............. 07-04 H
337 * qt_token ............... 0B-08 H
339 * [ buffer, buffer_hi ] loaded with "req".
341 qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
342 qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
343 token = QT_TOKEN_DT(0) | QT_TOKEN_TOTALBYTES(sizeof(*req)) |
344 QT_TOKEN_IOC(0) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) |
345 QT_TOKEN_PID(QT_TOKEN_PID_SETUP) |
346 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
347 qtd[qtd_counter].qt_token = cpu_to_hc32(token);
348 if (ehci_td_buffer(&qtd[qtd_counter], req, sizeof(*req))) {
349 printf("unable to construct SETUP TD\n");
352 /* Update previous qTD! */
353 *tdp = cpu_to_hc32((uint32_t)&qtd[qtd_counter]);
354 tdp = &qtd[qtd_counter++].qt_next;
358 if (length > 0 || req == NULL) {
359 uint8_t *buf_ptr = buffer;
360 int left_length = length;
364 * Determine the size of this qTD transfer. By default,
365 * QT_BUFFER_CNT full pages can be used.
367 int xfr_bytes = QT_BUFFER_CNT * EHCI_PAGE_SIZE;
369 * However, if the input buffer is not page-aligned, the
370 * portion of the first page before the buffer start
371 * offset within that page is unusable.
373 xfr_bytes -= (uint32_t)buf_ptr & (EHCI_PAGE_SIZE - 1);
375 * In order to keep each packet within a qTD transfer,
376 * align the qTD transfer size to EHCI_PAGE_SIZE.
378 xfr_bytes &= ~(EHCI_PAGE_SIZE - 1);
380 * This transfer may be shorter than the available qTD
381 * transfer size that has just been computed.
383 xfr_bytes = min(xfr_bytes, left_length);
386 * Setup request qTD (3.5 in ehci-r10.pdf)
388 * qt_next ................ 03-00 H
389 * qt_altnext ............. 07-04 H
390 * qt_token ............... 0B-08 H
392 * [ buffer, buffer_hi ] loaded with "buffer".
394 qtd[qtd_counter].qt_next =
395 cpu_to_hc32(QT_NEXT_TERMINATE);
396 qtd[qtd_counter].qt_altnext =
397 cpu_to_hc32(QT_NEXT_TERMINATE);
398 token = QT_TOKEN_DT(toggle) |
399 QT_TOKEN_TOTALBYTES(xfr_bytes) |
400 QT_TOKEN_IOC(req == NULL) | QT_TOKEN_CPAGE(0) |
402 QT_TOKEN_PID(usb_pipein(pipe) ?
403 QT_TOKEN_PID_IN : QT_TOKEN_PID_OUT) |
404 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
405 qtd[qtd_counter].qt_token = cpu_to_hc32(token);
406 if (ehci_td_buffer(&qtd[qtd_counter], buf_ptr,
408 printf("unable to construct DATA TD\n");
411 /* Update previous qTD! */
412 *tdp = cpu_to_hc32((uint32_t)&qtd[qtd_counter]);
413 tdp = &qtd[qtd_counter++].qt_next;
414 buf_ptr += xfr_bytes;
415 left_length -= xfr_bytes;
416 } while (left_length > 0);
421 * Setup request qTD (3.5 in ehci-r10.pdf)
423 * qt_next ................ 03-00 H
424 * qt_altnext ............. 07-04 H
425 * qt_token ............... 0B-08 H
427 qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
428 qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
429 token = QT_TOKEN_DT(toggle) | QT_TOKEN_TOTALBYTES(0) |
430 QT_TOKEN_IOC(1) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) |
431 QT_TOKEN_PID(usb_pipein(pipe) ?
432 QT_TOKEN_PID_OUT : QT_TOKEN_PID_IN) |
433 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
434 qtd[qtd_counter].qt_token = cpu_to_hc32(token);
435 /* Update previous qTD! */
436 *tdp = cpu_to_hc32((uint32_t)&qtd[qtd_counter]);
437 tdp = &qtd[qtd_counter++].qt_next;
440 qh_list->qh_link = cpu_to_hc32((uint32_t)qh | QH_LINK_TYPE_QH);
443 flush_dcache_range((uint32_t)qh_list,
444 ALIGN_END_ADDR(struct QH, qh_list, 1));
445 flush_dcache_range((uint32_t)qh, ALIGN_END_ADDR(struct QH, qh, 1));
446 flush_dcache_range((uint32_t)qtd,
447 ALIGN_END_ADDR(struct qTD, qtd, qtd_count));
449 /* Set async. queue head pointer. */
450 ehci_writel(&hcor->or_asynclistaddr, (uint32_t)qh_list);
452 usbsts = ehci_readl(&hcor->or_usbsts);
453 ehci_writel(&hcor->or_usbsts, (usbsts & 0x3f));
455 /* Enable async. schedule. */
456 cmd = ehci_readl(&hcor->or_usbcmd);
458 ehci_writel(&hcor->or_usbcmd, cmd);
460 ret = handshake((uint32_t *)&hcor->or_usbsts, STS_ASS, STS_ASS,
463 printf("EHCI fail timeout STS_ASS set\n");
467 /* Wait for TDs to be processed. */
469 vtd = &qtd[qtd_counter - 1];
470 timeout = USB_TIMEOUT_MS(pipe);
472 /* Invalidate dcache */
473 invalidate_dcache_range((uint32_t)qh_list,
474 ALIGN_END_ADDR(struct QH, qh_list, 1));
475 invalidate_dcache_range((uint32_t)qh,
476 ALIGN_END_ADDR(struct QH, qh, 1));
477 invalidate_dcache_range((uint32_t)qtd,
478 ALIGN_END_ADDR(struct qTD, qtd, qtd_count));
480 token = hc32_to_cpu(vtd->qt_token);
481 if (!(QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE))
484 } while (get_timer(ts) < timeout);
487 * Invalidate the memory area occupied by buffer
488 * Don't try to fix the buffer alignment, if it isn't properly
489 * aligned it's upper layer's fault so let invalidate_dcache_range()
490 * vow about it. But we have to fix the length as it's actual
491 * transfer length and can be unaligned. This is potentially
492 * dangerous operation, it's responsibility of the calling
493 * code to make sure enough space is reserved.
495 invalidate_dcache_range((uint32_t)buffer,
496 ALIGN((uint32_t)buffer + length, ARCH_DMA_MINALIGN));
498 /* Check that the TD processing happened */
499 if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE)
500 printf("EHCI timed out on TD - token=%#x\n", token);
502 /* Disable async schedule. */
503 cmd = ehci_readl(&hcor->or_usbcmd);
505 ehci_writel(&hcor->or_usbcmd, cmd);
507 ret = handshake((uint32_t *)&hcor->or_usbsts, STS_ASS, 0,
510 printf("EHCI fail timeout STS_ASS reset\n");
514 token = hc32_to_cpu(qh->qh_overlay.qt_token);
515 if (!(QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE)) {
516 debug("TOKEN=%#x\n", token);
517 switch (QT_TOKEN_GET_STATUS(token) &
518 ~(QT_TOKEN_STATUS_SPLITXSTATE | QT_TOKEN_STATUS_PERR)) {
520 toggle = QT_TOKEN_GET_DT(token);
521 usb_settoggle(dev, usb_pipeendpoint(pipe),
522 usb_pipeout(pipe), toggle);
525 case QT_TOKEN_STATUS_HALTED:
526 dev->status = USB_ST_STALLED;
528 case QT_TOKEN_STATUS_ACTIVE | QT_TOKEN_STATUS_DATBUFERR:
529 case QT_TOKEN_STATUS_DATBUFERR:
530 dev->status = USB_ST_BUF_ERR;
532 case QT_TOKEN_STATUS_HALTED | QT_TOKEN_STATUS_BABBLEDET:
533 case QT_TOKEN_STATUS_BABBLEDET:
534 dev->status = USB_ST_BABBLE_DET;
537 dev->status = USB_ST_CRC_ERR;
538 if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_HALTED)
539 dev->status |= USB_ST_STALLED;
542 dev->act_len = length - QT_TOKEN_GET_TOTALBYTES(token);
545 debug("dev=%u, usbsts=%#x, p[1]=%#x, p[2]=%#x\n",
546 dev->devnum, ehci_readl(&hcor->or_usbsts),
547 ehci_readl(&hcor->or_portsc[0]),
548 ehci_readl(&hcor->or_portsc[1]));
552 return (dev->status != USB_ST_NOT_PROC) ? 0 : -1;
559 static inline int min3(int a, int b, int c)
570 ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer,
571 int length, struct devrequest *req)
578 uint32_t *status_reg;
580 if (le16_to_cpu(req->index) > CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS) {
581 printf("The request port(%d) is not configured\n",
582 le16_to_cpu(req->index) - 1);
585 status_reg = (uint32_t *)&hcor->or_portsc[
586 le16_to_cpu(req->index) - 1];
589 debug("req=%u (%#x), type=%u (%#x), value=%u, index=%u\n",
590 req->request, req->request,
591 req->requesttype, req->requesttype,
592 le16_to_cpu(req->value), le16_to_cpu(req->index));
594 typeReq = req->request | req->requesttype << 8;
597 case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
598 switch (le16_to_cpu(req->value) >> 8) {
600 debug("USB_DT_DEVICE request\n");
601 srcptr = &descriptor.device;
602 srclen = descriptor.device.bLength;
605 debug("USB_DT_CONFIG config\n");
606 srcptr = &descriptor.config;
607 srclen = descriptor.config.bLength +
608 descriptor.interface.bLength +
609 descriptor.endpoint.bLength;
612 debug("USB_DT_STRING config\n");
613 switch (le16_to_cpu(req->value) & 0xff) {
614 case 0: /* Language */
619 srcptr = "\16\3u\0-\0b\0o\0o\0t\0";
622 case 2: /* Product */
623 srcptr = "\52\3E\0H\0C\0I\0 "
625 "\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0";
629 debug("unknown value DT_STRING %x\n",
630 le16_to_cpu(req->value));
635 debug("unknown value %x\n", le16_to_cpu(req->value));
639 case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8):
640 switch (le16_to_cpu(req->value) >> 8) {
642 debug("USB_DT_HUB config\n");
643 srcptr = &descriptor.hub;
644 srclen = descriptor.hub.bLength;
647 debug("unknown value %x\n", le16_to_cpu(req->value));
651 case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8):
652 debug("USB_REQ_SET_ADDRESS\n");
653 rootdev = le16_to_cpu(req->value);
655 case DeviceOutRequest | USB_REQ_SET_CONFIGURATION:
656 debug("USB_REQ_SET_CONFIGURATION\n");
659 case USB_REQ_GET_STATUS | ((USB_DIR_IN | USB_RT_HUB) << 8):
660 tmpbuf[0] = 1; /* USB_STATUS_SELFPOWERED */
665 case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
666 memset(tmpbuf, 0, 4);
667 reg = ehci_readl(status_reg);
668 if (reg & EHCI_PS_CS)
669 tmpbuf[0] |= USB_PORT_STAT_CONNECTION;
670 if (reg & EHCI_PS_PE)
671 tmpbuf[0] |= USB_PORT_STAT_ENABLE;
672 if (reg & EHCI_PS_SUSP)
673 tmpbuf[0] |= USB_PORT_STAT_SUSPEND;
674 if (reg & EHCI_PS_OCA)
675 tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT;
676 if (reg & EHCI_PS_PR)
677 tmpbuf[0] |= USB_PORT_STAT_RESET;
678 if (reg & EHCI_PS_PP)
679 tmpbuf[1] |= USB_PORT_STAT_POWER >> 8;
682 switch (PORTSC_PSPD(reg)) {
686 tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8;
690 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
694 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
697 if (reg & EHCI_PS_CSC)
698 tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION;
699 if (reg & EHCI_PS_PEC)
700 tmpbuf[2] |= USB_PORT_STAT_C_ENABLE;
701 if (reg & EHCI_PS_OCC)
702 tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT;
703 if (portreset & (1 << le16_to_cpu(req->index)))
704 tmpbuf[2] |= USB_PORT_STAT_C_RESET;
709 case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
710 reg = ehci_readl(status_reg);
711 reg &= ~EHCI_PS_CLEAR;
712 switch (le16_to_cpu(req->value)) {
713 case USB_PORT_FEAT_ENABLE:
715 ehci_writel(status_reg, reg);
717 case USB_PORT_FEAT_POWER:
718 if (HCS_PPC(ehci_readl(&hccr->cr_hcsparams))) {
720 ehci_writel(status_reg, reg);
723 case USB_PORT_FEAT_RESET:
724 if ((reg & (EHCI_PS_PE | EHCI_PS_CS)) == EHCI_PS_CS &&
726 EHCI_PS_IS_LOWSPEED(reg)) {
727 /* Low speed device, give up ownership. */
728 debug("port %d low speed --> companion\n",
731 ehci_writel(status_reg, reg);
738 ehci_writel(status_reg, reg);
740 * caller must wait, then call GetPortStatus
741 * usb 2.0 specification say 50 ms resets on
744 ehci_powerup_fixup(status_reg, ®);
746 ehci_writel(status_reg, reg & ~EHCI_PS_PR);
748 * A host controller must terminate the reset
749 * and stabilize the state of the port within
752 ret = handshake(status_reg, EHCI_PS_PR, 0,
756 1 << le16_to_cpu(req->index);
758 printf("port(%d) reset error\n",
759 le16_to_cpu(req->index) - 1);
763 debug("unknown feature %x\n", le16_to_cpu(req->value));
766 /* unblock posted writes */
767 (void) ehci_readl(&hcor->or_usbcmd);
769 case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
770 reg = ehci_readl(status_reg);
771 switch (le16_to_cpu(req->value)) {
772 case USB_PORT_FEAT_ENABLE:
775 case USB_PORT_FEAT_C_ENABLE:
776 reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_PE;
778 case USB_PORT_FEAT_POWER:
779 if (HCS_PPC(ehci_readl(&hccr->cr_hcsparams)))
780 reg = reg & ~(EHCI_PS_CLEAR | EHCI_PS_PP);
781 case USB_PORT_FEAT_C_CONNECTION:
782 reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_CSC;
784 case USB_PORT_FEAT_OVER_CURRENT:
785 reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_OCC;
787 case USB_PORT_FEAT_C_RESET:
788 portreset &= ~(1 << le16_to_cpu(req->index));
791 debug("unknown feature %x\n", le16_to_cpu(req->value));
794 ehci_writel(status_reg, reg);
795 /* unblock posted write */
796 (void) ehci_readl(&hcor->or_usbcmd);
799 debug("Unknown request\n");
804 len = min3(srclen, le16_to_cpu(req->length), length);
805 if (srcptr != NULL && len > 0)
806 memcpy(buffer, srcptr, len);
815 debug("requesttype=%x, request=%x, value=%x, index=%x, length=%x\n",
816 req->requesttype, req->request, le16_to_cpu(req->value),
817 le16_to_cpu(req->index), le16_to_cpu(req->length));
820 dev->status = USB_ST_STALLED;
824 int usb_lowlevel_stop(void)
826 return ehci_hcd_stop();
829 int usb_lowlevel_init(void)
837 /* EHCI spec section 4.1 */
841 #if defined(CONFIG_EHCI_HCD_INIT_AFTER_RESET)
846 /* Set head of reclaim list */
847 memset(qh_list, 0, sizeof(*qh_list));
848 qh_list->qh_link = cpu_to_hc32((uint32_t)qh_list | QH_LINK_TYPE_QH);
849 qh_list->qh_endpt1 = cpu_to_hc32(QH_ENDPT1_H(1) |
850 QH_ENDPT1_EPS(USB_SPEED_HIGH));
851 qh_list->qh_curtd = cpu_to_hc32(QT_NEXT_TERMINATE);
852 qh_list->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
853 qh_list->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
854 qh_list->qh_overlay.qt_token =
855 cpu_to_hc32(QT_TOKEN_STATUS(QT_TOKEN_STATUS_HALTED));
857 reg = ehci_readl(&hccr->cr_hcsparams);
858 descriptor.hub.bNbrPorts = HCS_N_PORTS(reg);
859 printf("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts);
860 /* Port Indicators */
861 if (HCS_INDICATOR(reg))
862 descriptor.hub.wHubCharacteristics |= 0x80;
863 /* Port Power Control */
865 descriptor.hub.wHubCharacteristics |= 0x01;
867 /* Start the host controller. */
868 cmd = ehci_readl(&hcor->or_usbcmd);
870 * Philips, Intel, and maybe others need CMD_RUN before the
871 * root hub will detect new devices (why?); NEC doesn't
873 cmd &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
875 ehci_writel(&hcor->or_usbcmd, cmd);
877 /* take control over the ports */
878 cmd = ehci_readl(&hcor->or_configflag);
880 ehci_writel(&hcor->or_configflag, cmd);
881 /* unblock posted write */
882 cmd = ehci_readl(&hcor->or_usbcmd);
884 reg = HC_VERSION(ehci_readl(&hccr->cr_capbase));
885 printf("USB EHCI %x.%02x\n", reg >> 8, reg & 0xff);
893 submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
897 if (usb_pipetype(pipe) != PIPE_BULK) {
898 debug("non-bulk pipe (type=%lu)", usb_pipetype(pipe));
901 return ehci_submit_async(dev, pipe, buffer, length, NULL);
905 submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
906 int length, struct devrequest *setup)
909 if (usb_pipetype(pipe) != PIPE_CONTROL) {
910 debug("non-control pipe (type=%lu)", usb_pipetype(pipe));
914 if (usb_pipedevice(pipe) == rootdev) {
916 dev->speed = USB_SPEED_HIGH;
917 return ehci_submit_root(dev, pipe, buffer, length, setup);
919 return ehci_submit_async(dev, pipe, buffer, length, setup);
923 submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
924 int length, int interval)
926 debug("dev=%p, pipe=%lu, buffer=%p, length=%d, interval=%d",
927 dev, pipe, buffer, length, interval);
930 * Interrupt transfers requiring several transactions are not supported
931 * because bInterval is ignored.
933 * Also, ehci_submit_async() relies on wMaxPacketSize being a power of 2
934 * if several qTDs are required, while the USB specification does not
935 * constrain this for interrupt transfers. That means that
936 * ehci_submit_async() would support interrupt transfers requiring
937 * several transactions only as long as the transfer size does not
938 * require more than a single qTD.
940 if (length > usb_maxpacket(dev, pipe)) {
941 printf("%s: Interrupt transfers requiring several transactions "
942 "are not supported.\n", __func__);
945 return ehci_submit_async(dev, pipe, buffer, length, NULL);