2 * Copyright (c) 2001 by David Brownell
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software Foundation,
16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 /* this file is part of ehci-hcd.c */
21 /*-------------------------------------------------------------------------*/
24 * There's basically three types of memory:
25 * - data used only by the HCD ... kmalloc is fine
26 * - async and periodic schedules, shared by HC and HCD ... these
27 * need to use dma_pool or dma_alloc_coherent
28 * - driver buffers, read/written by HC ... single shot DMA mapped
30 * There's also "register" data (e.g. PCI or SOC), which is memory mapped.
31 * No memory seen by this driver is pageable.
34 /*-------------------------------------------------------------------------*/
36 /* Allocate the key transfer structures from the previously allocated pool */
38 static inline void ehci_qtd_init(struct ehci_hcd *ehci, struct ehci_qtd *qtd,
41 memset (qtd, 0, sizeof *qtd);
43 qtd->hw_token = cpu_to_le32 (QTD_STS_HALT);
44 qtd->hw_next = EHCI_LIST_END(ehci);
45 qtd->hw_alt_next = EHCI_LIST_END(ehci);
46 INIT_LIST_HEAD (&qtd->qtd_list);
49 static struct ehci_qtd *ehci_qtd_alloc (struct ehci_hcd *ehci, gfp_t flags)
54 qtd = dma_pool_alloc (ehci->qtd_pool, flags, &dma);
56 ehci_qtd_init(ehci, qtd, dma);
61 static inline void ehci_qtd_free (struct ehci_hcd *ehci, struct ehci_qtd *qtd)
63 dma_pool_free (ehci->qtd_pool, qtd, qtd->qtd_dma);
67 static void qh_destroy(struct ehci_qh *qh)
69 struct ehci_hcd *ehci = qh->ehci;
71 /* clean qtds first, and know this is not linked */
72 if (!list_empty (&qh->qtd_list) || qh->qh_next.ptr) {
73 ehci_dbg (ehci, "unused qh not empty!\n");
77 ehci_qtd_free (ehci, qh->dummy);
78 dma_pool_free(ehci->qh_pool, qh->hw, qh->qh_dma);
82 static struct ehci_qh *ehci_qh_alloc (struct ehci_hcd *ehci, gfp_t flags)
87 qh = kzalloc(sizeof *qh, GFP_ATOMIC);
90 qh->hw = (struct ehci_qh_hw *)
91 dma_pool_alloc(ehci->qh_pool, flags, &dma);
94 memset(qh->hw, 0, sizeof *qh->hw);
98 // INIT_LIST_HEAD (&qh->qh_list);
99 INIT_LIST_HEAD (&qh->qtd_list);
101 /* dummy td enables safe urb queuing */
102 qh->dummy = ehci_qtd_alloc (ehci, flags);
103 if (qh->dummy == NULL) {
104 ehci_dbg (ehci, "no dummy td\n");
110 dma_pool_free(ehci->qh_pool, qh->hw, qh->qh_dma);
116 /* to share a qh (cpu threads, or hc) */
117 static inline struct ehci_qh *qh_get (struct ehci_qh *qh)
119 WARN_ON(!qh->refcount);
124 static inline void qh_put (struct ehci_qh *qh)
130 /*-------------------------------------------------------------------------*/
132 /* The queue heads and transfer descriptors are managed from pools tied
133 * to each of the "per device" structures.
134 * This is the initialisation and cleanup code.
137 static void ehci_mem_cleanup (struct ehci_hcd *ehci)
139 free_cached_lists(ehci);
141 qh_put (ehci->async);
144 /* DMA consistent memory and pools */
146 dma_pool_destroy (ehci->qtd_pool);
147 ehci->qtd_pool = NULL;
150 dma_pool_destroy (ehci->qh_pool);
151 ehci->qh_pool = NULL;
155 dma_pool_destroy (ehci->itd_pool);
156 ehci->itd_pool = NULL;
159 dma_pool_destroy (ehci->sitd_pool);
160 ehci->sitd_pool = NULL;
163 dma_free_coherent (ehci_to_hcd(ehci)->self.controller,
164 ehci->periodic_size * sizeof (u32),
165 ehci->periodic, ehci->periodic_dma);
166 ehci->periodic = NULL;
168 /* shadow periodic table */
169 kfree(ehci->pshadow);
170 ehci->pshadow = NULL;
173 /* remember to add cleanup code (above) if you add anything here */
174 static int ehci_mem_init (struct ehci_hcd *ehci, gfp_t flags)
178 /* QTDs for control/bulk/intr transfers */
179 ehci->qtd_pool = dma_pool_create ("ehci_qtd",
180 ehci_to_hcd(ehci)->self.controller,
181 sizeof (struct ehci_qtd),
182 32 /* byte alignment (for hw parts) */,
183 4096 /* can't cross 4K */);
184 if (!ehci->qtd_pool) {
188 /* QHs for control/bulk/intr transfers */
189 ehci->qh_pool = dma_pool_create ("ehci_qh",
190 ehci_to_hcd(ehci)->self.controller,
191 sizeof(struct ehci_qh_hw),
192 32 /* byte alignment (for hw parts) */,
193 4096 /* can't cross 4K */);
194 if (!ehci->qh_pool) {
197 ehci->async = ehci_qh_alloc (ehci, flags);
202 /* ITD for high speed ISO transfers */
203 ehci->itd_pool = dma_pool_create ("ehci_itd",
204 ehci_to_hcd(ehci)->self.controller,
205 sizeof (struct ehci_itd),
206 32 /* byte alignment (for hw parts) */,
207 4096 /* can't cross 4K */);
208 if (!ehci->itd_pool) {
212 /* SITD for full/low speed split ISO transfers */
213 ehci->sitd_pool = dma_pool_create ("ehci_sitd",
214 ehci_to_hcd(ehci)->self.controller,
215 sizeof (struct ehci_sitd),
216 32 /* byte alignment (for hw parts) */,
217 4096 /* can't cross 4K */);
218 if (!ehci->sitd_pool) {
222 /* Hardware periodic table */
223 ehci->periodic = (__le32 *)
224 dma_alloc_coherent (ehci_to_hcd(ehci)->self.controller,
225 ehci->periodic_size * sizeof(__le32),
226 &ehci->periodic_dma, 0);
227 if (ehci->periodic == NULL) {
230 for (i = 0; i < ehci->periodic_size; i++)
231 ehci->periodic [i] = EHCI_LIST_END(ehci);
233 /* software shadow of hardware table */
234 ehci->pshadow = kcalloc(ehci->periodic_size, sizeof(void *), flags);
235 if (ehci->pshadow != NULL)
239 ehci_dbg (ehci, "couldn't init memory\n");
240 ehci_mem_cleanup (ehci);