2 * ehci-omap.c - driver for USBHOST on OMAP 34xx processor
4 * Bus Glue for OMAP34xx USBHOST 3 port EHCI controller
5 * Tested on OMAP3430 ES2.0 SDP
7 * Copyright (C) 2007-2008 Texas Instruments, Inc.
8 * Author: Vikram Pandita <vikram.pandita@ti.com>
10 * Copyright (C) 2009 Nokia Corporation
11 * Contact: Felipe Balbi <felipe.balbi@nokia.com>
13 * Based on "ehci-fsl.c" and "ehci-au1xxx.c" ehci glue layers
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
29 * TODO (last updated Feb 23rd, 2009):
32 * - move DPLL5 programming to clock fw
33 * - add suspend/resume
34 * - move workarounds to board-files
37 #include <linux/platform_device.h>
38 #include <linux/clk.h>
39 #include <linux/gpio.h>
43 * OMAP USBHOST Register addresses: VIRTUAL ADDRESSES
44 * Use ehci_omap_readl()/ehci_omap_writel() functions
47 /* TLL Register Set */
48 #define OMAP_USBTLL_REVISION (0x00)
49 #define OMAP_USBTLL_SYSCONFIG (0x10)
50 #define OMAP_USBTLL_SYSCONFIG_CACTIVITY (1 << 8)
51 #define OMAP_USBTLL_SYSCONFIG_SIDLEMODE (1 << 3)
52 #define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP (1 << 2)
53 #define OMAP_USBTLL_SYSCONFIG_SOFTRESET (1 << 1)
54 #define OMAP_USBTLL_SYSCONFIG_AUTOIDLE (1 << 0)
56 #define OMAP_USBTLL_SYSSTATUS (0x14)
57 #define OMAP_USBTLL_SYSSTATUS_RESETDONE (1 << 0)
59 #define OMAP_USBTLL_IRQSTATUS (0x18)
60 #define OMAP_USBTLL_IRQENABLE (0x1C)
62 #define OMAP_TLL_SHARED_CONF (0x30)
63 #define OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN (1 << 6)
64 #define OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN (1 << 5)
65 #define OMAP_TLL_SHARED_CONF_USB_DIVRATION (1 << 2)
66 #define OMAP_TLL_SHARED_CONF_FCLK_REQ (1 << 1)
67 #define OMAP_TLL_SHARED_CONF_FCLK_IS_ON (1 << 0)
69 #define OMAP_TLL_CHANNEL_CONF(num) (0x040 + 0x004 * num)
70 #define OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF (1 << 11)
71 #define OMAP_TLL_CHANNEL_CONF_ULPI_ULPIAUTOIDLE (1 << 10)
72 #define OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE (1 << 9)
73 #define OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE (1 << 8)
74 #define OMAP_TLL_CHANNEL_CONF_CHANEN (1 << 0)
76 #define OMAP_TLL_ULPI_FUNCTION_CTRL(num) (0x804 + 0x100 * num)
77 #define OMAP_TLL_ULPI_INTERFACE_CTRL(num) (0x807 + 0x100 * num)
78 #define OMAP_TLL_ULPI_OTG_CTRL(num) (0x80A + 0x100 * num)
79 #define OMAP_TLL_ULPI_INT_EN_RISE(num) (0x80D + 0x100 * num)
80 #define OMAP_TLL_ULPI_INT_EN_FALL(num) (0x810 + 0x100 * num)
81 #define OMAP_TLL_ULPI_INT_STATUS(num) (0x813 + 0x100 * num)
82 #define OMAP_TLL_ULPI_INT_LATCH(num) (0x814 + 0x100 * num)
83 #define OMAP_TLL_ULPI_DEBUG(num) (0x815 + 0x100 * num)
84 #define OMAP_TLL_ULPI_SCRATCH_REGISTER(num) (0x816 + 0x100 * num)
86 #define OMAP_TLL_CHANNEL_COUNT 3
87 #define OMAP_TLL_CHANNEL_1_EN_MASK (1 << 1)
88 #define OMAP_TLL_CHANNEL_2_EN_MASK (1 << 2)
89 #define OMAP_TLL_CHANNEL_3_EN_MASK (1 << 4)
91 /* UHH Register Set */
92 #define OMAP_UHH_REVISION (0x00)
93 #define OMAP_UHH_SYSCONFIG (0x10)
94 #define OMAP_UHH_SYSCONFIG_MIDLEMODE (1 << 12)
95 #define OMAP_UHH_SYSCONFIG_CACTIVITY (1 << 8)
96 #define OMAP_UHH_SYSCONFIG_SIDLEMODE (1 << 3)
97 #define OMAP_UHH_SYSCONFIG_ENAWAKEUP (1 << 2)
98 #define OMAP_UHH_SYSCONFIG_SOFTRESET (1 << 1)
99 #define OMAP_UHH_SYSCONFIG_AUTOIDLE (1 << 0)
101 #define OMAP_UHH_SYSSTATUS (0x14)
102 #define OMAP_UHH_HOSTCONFIG (0x40)
103 #define OMAP_UHH_HOSTCONFIG_ULPI_BYPASS (1 << 0)
104 #define OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS (1 << 0)
105 #define OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS (1 << 11)
106 #define OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS (1 << 12)
107 #define OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN (1 << 2)
108 #define OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN (1 << 3)
109 #define OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN (1 << 4)
110 #define OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN (1 << 5)
111 #define OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS (1 << 8)
112 #define OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS (1 << 9)
113 #define OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS (1 << 10)
115 #define OMAP_UHH_DEBUG_CSR (0x44)
117 /* EHCI Register Set */
118 #define EHCI_INSNREG05_ULPI (0xA4)
119 #define EHCI_INSNREG05_ULPI_CONTROL_SHIFT 31
120 #define EHCI_INSNREG05_ULPI_PORTSEL_SHIFT 24
121 #define EHCI_INSNREG05_ULPI_OPSEL_SHIFT 22
122 #define EHCI_INSNREG05_ULPI_REGADD_SHIFT 16
123 #define EHCI_INSNREG05_ULPI_EXTREGADD_SHIFT 8
124 #define EHCI_INSNREG05_ULPI_WRDATA_SHIFT 0
126 /*-------------------------------------------------------------------------*/
128 static inline void ehci_omap_writel(void __iomem *base, u32 reg, u32 val)
130 __raw_writel(val, base + reg);
133 static inline u32 ehci_omap_readl(void __iomem *base, u32 reg)
135 return __raw_readl(base + reg);
138 static inline void ehci_omap_writeb(void __iomem *base, u8 reg, u8 val)
140 __raw_writeb(val, base + reg);
143 static inline u8 ehci_omap_readb(void __iomem *base, u8 reg)
145 return __raw_readb(base + reg);
148 /*-------------------------------------------------------------------------*/
150 struct ehci_hcd_omap {
151 struct ehci_hcd *ehci;
154 struct clk *usbhost_ick;
155 struct clk *usbhost2_120m_fck;
156 struct clk *usbhost1_48m_fck;
157 struct clk *usbtll_fck;
158 struct clk *usbtll_ick;
160 /* FIXME the following two workarounds are
161 * board specific not silicon-specific so these
162 * should be moved to board-file instead.
164 * Maybe someone from TI will know better which
165 * board is affected and needs the workarounds
169 /* gpio for resetting phy */
170 int reset_gpio_port[OMAP3_HS_USB_PORTS];
172 /* phy reset workaround */
175 /* desired phy_mode: TLL, PHY */
176 enum ehci_hcd_omap_mode port_mode[OMAP3_HS_USB_PORTS];
178 void __iomem *uhh_base;
179 void __iomem *tll_base;
180 void __iomem *ehci_base;
183 /*-------------------------------------------------------------------------*/
185 static void omap_usb_utmi_init(struct ehci_hcd_omap *omap, u8 tll_channel_mask)
190 /* Program the 3 TLL channels upfront */
191 for (i = 0; i < OMAP_TLL_CHANNEL_COUNT; i++) {
192 reg = ehci_omap_readl(omap->tll_base, OMAP_TLL_CHANNEL_CONF(i));
194 /* Disable AutoIdle, BitStuffing and use SDR Mode */
195 reg &= ~(OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE
196 | OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF
197 | OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE);
198 ehci_omap_writel(omap->tll_base, OMAP_TLL_CHANNEL_CONF(i), reg);
201 /* Program Common TLL register */
202 reg = ehci_omap_readl(omap->tll_base, OMAP_TLL_SHARED_CONF);
203 reg |= (OMAP_TLL_SHARED_CONF_FCLK_IS_ON
204 | OMAP_TLL_SHARED_CONF_USB_DIVRATION
205 | OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN);
206 reg &= ~OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN;
208 ehci_omap_writel(omap->tll_base, OMAP_TLL_SHARED_CONF, reg);
210 /* Enable channels now */
211 for (i = 0; i < OMAP_TLL_CHANNEL_COUNT; i++) {
212 reg = ehci_omap_readl(omap->tll_base, OMAP_TLL_CHANNEL_CONF(i));
214 /* Enable only the reg that is needed */
215 if (!(tll_channel_mask & 1<<i))
218 reg |= OMAP_TLL_CHANNEL_CONF_CHANEN;
219 ehci_omap_writel(omap->tll_base, OMAP_TLL_CHANNEL_CONF(i), reg);
221 ehci_omap_writeb(omap->tll_base,
222 OMAP_TLL_ULPI_SCRATCH_REGISTER(i), 0xbe);
223 dev_dbg(omap->dev, "ULPI_SCRATCH_REG[ch=%d]= 0x%02x\n",
224 i+1, ehci_omap_readb(omap->tll_base,
225 OMAP_TLL_ULPI_SCRATCH_REGISTER(i)));
229 /*-------------------------------------------------------------------------*/
232 * - Start the TI USBHOST controller
234 static int omap_start_ehc(struct ehci_hcd_omap *omap, struct usb_hcd *hcd)
236 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
241 dev_dbg(omap->dev, "starting TI EHCI USB Controller\n");
243 /* Enable Clocks for USBHOST */
244 omap->usbhost_ick = clk_get(omap->dev, "usbhost_ick");
245 if (IS_ERR(omap->usbhost_ick)) {
246 ret = PTR_ERR(omap->usbhost_ick);
249 clk_enable(omap->usbhost_ick);
251 omap->usbhost2_120m_fck = clk_get(omap->dev, "usbhost_120m_fck");
252 if (IS_ERR(omap->usbhost2_120m_fck)) {
253 ret = PTR_ERR(omap->usbhost2_120m_fck);
254 goto err_host_120m_fck;
256 clk_enable(omap->usbhost2_120m_fck);
258 omap->usbhost1_48m_fck = clk_get(omap->dev, "usbhost_48m_fck");
259 if (IS_ERR(omap->usbhost1_48m_fck)) {
260 ret = PTR_ERR(omap->usbhost1_48m_fck);
261 goto err_host_48m_fck;
263 clk_enable(omap->usbhost1_48m_fck);
265 if (omap->phy_reset) {
267 if (gpio_is_valid(omap->reset_gpio_port[0])) {
268 gpio_request(omap->reset_gpio_port[0],
270 gpio_direction_output(omap->reset_gpio_port[0], 0);
273 if (gpio_is_valid(omap->reset_gpio_port[1])) {
274 gpio_request(omap->reset_gpio_port[1],
276 gpio_direction_output(omap->reset_gpio_port[1], 0);
279 /* Hold the PHY in RESET for enough time till DIR is high */
283 /* Configure TLL for 60Mhz clk for ULPI */
284 omap->usbtll_fck = clk_get(omap->dev, "usbtll_fck");
285 if (IS_ERR(omap->usbtll_fck)) {
286 ret = PTR_ERR(omap->usbtll_fck);
289 clk_enable(omap->usbtll_fck);
291 omap->usbtll_ick = clk_get(omap->dev, "usbtll_ick");
292 if (IS_ERR(omap->usbtll_ick)) {
293 ret = PTR_ERR(omap->usbtll_ick);
296 clk_enable(omap->usbtll_ick);
298 /* perform TLL soft reset, and wait until reset is complete */
299 ehci_omap_writel(omap->tll_base, OMAP_USBTLL_SYSCONFIG,
300 OMAP_USBTLL_SYSCONFIG_SOFTRESET);
302 /* Wait for TLL reset to complete */
303 while (!(ehci_omap_readl(omap->tll_base, OMAP_USBTLL_SYSSTATUS)
304 & OMAP_USBTLL_SYSSTATUS_RESETDONE)) {
307 if (time_after(jiffies, timeout)) {
308 dev_dbg(omap->dev, "operation timed out\n");
314 dev_dbg(omap->dev, "TLL RESET DONE\n");
316 /* (1<<3) = no idle mode only for initial debugging */
317 ehci_omap_writel(omap->tll_base, OMAP_USBTLL_SYSCONFIG,
318 OMAP_USBTLL_SYSCONFIG_ENAWAKEUP |
319 OMAP_USBTLL_SYSCONFIG_SIDLEMODE |
320 OMAP_USBTLL_SYSCONFIG_CACTIVITY);
323 /* Put UHH in NoIdle/NoStandby mode */
324 reg = ehci_omap_readl(omap->uhh_base, OMAP_UHH_SYSCONFIG);
325 reg |= (OMAP_UHH_SYSCONFIG_ENAWAKEUP
326 | OMAP_UHH_SYSCONFIG_SIDLEMODE
327 | OMAP_UHH_SYSCONFIG_CACTIVITY
328 | OMAP_UHH_SYSCONFIG_MIDLEMODE);
329 reg &= ~OMAP_UHH_SYSCONFIG_AUTOIDLE;
331 ehci_omap_writel(omap->uhh_base, OMAP_UHH_SYSCONFIG, reg);
333 reg = ehci_omap_readl(omap->uhh_base, OMAP_UHH_HOSTCONFIG);
335 /* setup ULPI bypass and burst configurations */
336 reg |= (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN
337 | OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN
338 | OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN);
339 reg &= ~OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN;
341 if (omap->port_mode[0] == EHCI_HCD_OMAP_MODE_UNKNOWN)
342 reg &= ~OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS;
343 if (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_UNKNOWN)
344 reg &= ~OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS;
345 if (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_UNKNOWN)
346 reg &= ~OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS;
348 /* Bypass the TLL module for PHY mode operation */
349 if (omap_rev() <= OMAP3430_REV_ES2_1) {
350 dev_dbg(omap->dev, "OMAP3 ES version <= ES2.1 \n");
351 if ((omap->port_mode[0] == EHCI_HCD_OMAP_MODE_PHY) ||
352 (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_PHY) ||
353 (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_PHY))
354 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
356 reg |= OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
358 dev_dbg(omap->dev, "OMAP3 ES version > ES2.1\n");
359 if (omap->port_mode[0] == EHCI_HCD_OMAP_MODE_PHY)
360 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
361 else if (omap->port_mode[0] == EHCI_HCD_OMAP_MODE_TLL)
362 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
364 if (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_PHY)
365 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS;
366 else if (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_TLL)
367 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS;
369 if (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_PHY)
370 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS;
371 else if (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_TLL)
372 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS;
375 ehci_omap_writel(omap->uhh_base, OMAP_UHH_HOSTCONFIG, reg);
376 dev_dbg(omap->dev, "UHH setup done, uhh_hostconfig=%x\n", reg);
379 if ((omap->port_mode[0] == EHCI_HCD_OMAP_MODE_TLL) ||
380 (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_TLL) ||
381 (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_TLL)) {
383 if (omap->port_mode[0] == EHCI_HCD_OMAP_MODE_TLL)
384 tll_ch_mask |= OMAP_TLL_CHANNEL_1_EN_MASK;
385 if (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_TLL)
386 tll_ch_mask |= OMAP_TLL_CHANNEL_2_EN_MASK;
387 if (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_TLL)
388 tll_ch_mask |= OMAP_TLL_CHANNEL_3_EN_MASK;
390 /* Enable UTMI mode for required TLL channels */
391 omap_usb_utmi_init(omap, tll_ch_mask);
394 if (omap->phy_reset) {
396 * Hold the PHY in RESET for enough time till
397 * PHY is settled and ready
401 if (gpio_is_valid(omap->reset_gpio_port[0]))
402 gpio_set_value(omap->reset_gpio_port[0], 1);
404 if (gpio_is_valid(omap->reset_gpio_port[1]))
405 gpio_set_value(omap->reset_gpio_port[1], 1);
411 clk_disable(omap->usbtll_ick);
412 clk_put(omap->usbtll_ick);
415 clk_disable(omap->usbtll_fck);
416 clk_put(omap->usbtll_fck);
419 clk_disable(omap->usbhost1_48m_fck);
420 clk_put(omap->usbhost1_48m_fck);
422 if (omap->phy_reset) {
423 if (gpio_is_valid(omap->reset_gpio_port[0]))
424 gpio_free(omap->reset_gpio_port[0]);
426 if (gpio_is_valid(omap->reset_gpio_port[1]))
427 gpio_free(omap->reset_gpio_port[1]);
431 clk_disable(omap->usbhost2_120m_fck);
432 clk_put(omap->usbhost2_120m_fck);
435 clk_disable(omap->usbhost_ick);
436 clk_put(omap->usbhost_ick);
442 static void omap_stop_ehc(struct ehci_hcd_omap *omap, struct usb_hcd *hcd)
444 unsigned long timeout = jiffies + msecs_to_jiffies(100);
446 dev_dbg(omap->dev, "stopping TI EHCI USB Controller\n");
448 /* Reset OMAP modules for insmod/rmmod to work */
449 ehci_omap_writel(omap->uhh_base, OMAP_UHH_SYSCONFIG,
450 OMAP_UHH_SYSCONFIG_SOFTRESET);
451 while (!(ehci_omap_readl(omap->uhh_base, OMAP_UHH_SYSSTATUS)
455 if (time_after(jiffies, timeout))
456 dev_dbg(omap->dev, "operation timed out\n");
459 while (!(ehci_omap_readl(omap->uhh_base, OMAP_UHH_SYSSTATUS)
463 if (time_after(jiffies, timeout))
464 dev_dbg(omap->dev, "operation timed out\n");
467 while (!(ehci_omap_readl(omap->uhh_base, OMAP_UHH_SYSSTATUS)
471 if (time_after(jiffies, timeout))
472 dev_dbg(omap->dev, "operation timed out\n");
475 ehci_omap_writel(omap->tll_base, OMAP_USBTLL_SYSCONFIG, (1 << 1));
477 while (!(ehci_omap_readl(omap->tll_base, OMAP_USBTLL_SYSSTATUS)
481 if (time_after(jiffies, timeout))
482 dev_dbg(omap->dev, "operation timed out\n");
485 if (omap->usbtll_fck != NULL) {
486 clk_disable(omap->usbtll_fck);
487 clk_put(omap->usbtll_fck);
488 omap->usbtll_fck = NULL;
491 if (omap->usbhost_ick != NULL) {
492 clk_disable(omap->usbhost_ick);
493 clk_put(omap->usbhost_ick);
494 omap->usbhost_ick = NULL;
497 if (omap->usbhost1_48m_fck != NULL) {
498 clk_disable(omap->usbhost1_48m_fck);
499 clk_put(omap->usbhost1_48m_fck);
500 omap->usbhost1_48m_fck = NULL;
503 if (omap->usbhost2_120m_fck != NULL) {
504 clk_disable(omap->usbhost2_120m_fck);
505 clk_put(omap->usbhost2_120m_fck);
506 omap->usbhost2_120m_fck = NULL;
509 if (omap->usbtll_ick != NULL) {
510 clk_disable(omap->usbtll_ick);
511 clk_put(omap->usbtll_ick);
512 omap->usbtll_ick = NULL;
515 if (omap->phy_reset) {
516 if (gpio_is_valid(omap->reset_gpio_port[0]))
517 gpio_free(omap->reset_gpio_port[0]);
519 if (gpio_is_valid(omap->reset_gpio_port[1]))
520 gpio_free(omap->reset_gpio_port[1]);
523 dev_dbg(omap->dev, "Clock to USB host has been disabled\n");
526 /*-------------------------------------------------------------------------*/
528 static const struct hc_driver ehci_omap_hc_driver;
530 /* configure so an HC device and id are always provided */
531 /* always called with process context; sleeping is OK */
534 * ehci_hcd_omap_probe - initialize TI-based HCDs
536 * Allocates basic resources for this USB host controller, and
537 * then invokes the start() method for the HCD associated with it
538 * through the hotplug entry's driver_data.
540 static int ehci_hcd_omap_probe(struct platform_device *pdev)
542 struct ehci_hcd_omap_platform_data *pdata = pdev->dev.platform_data;
543 struct ehci_hcd_omap *omap;
544 struct resource *res;
547 int irq = platform_get_irq(pdev, 0);
551 dev_dbg(&pdev->dev, "missing platform_data\n");
558 omap = kzalloc(sizeof(*omap), GFP_KERNEL);
564 hcd = usb_create_hcd(&ehci_omap_hc_driver, &pdev->dev,
565 dev_name(&pdev->dev));
567 dev_dbg(&pdev->dev, "failed to create hcd with err %d\n", ret);
572 platform_set_drvdata(pdev, omap);
573 omap->dev = &pdev->dev;
574 omap->phy_reset = pdata->phy_reset;
575 omap->reset_gpio_port[0] = pdata->reset_gpio_port[0];
576 omap->reset_gpio_port[1] = pdata->reset_gpio_port[1];
577 omap->reset_gpio_port[2] = pdata->reset_gpio_port[2];
578 omap->port_mode[0] = pdata->port_mode[0];
579 omap->port_mode[1] = pdata->port_mode[1];
580 omap->port_mode[2] = pdata->port_mode[2];
581 omap->ehci = hcd_to_ehci(hcd);
582 omap->ehci->sbrn = 0x20;
584 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
586 hcd->rsrc_start = res->start;
587 hcd->rsrc_len = resource_size(res);
589 hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
591 dev_err(&pdev->dev, "EHCI ioremap failed\n");
596 /* we know this is the memory we want, no need to ioremap again */
597 omap->ehci->caps = hcd->regs;
598 omap->ehci_base = hcd->regs;
600 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
601 omap->uhh_base = ioremap(res->start, resource_size(res));
602 if (!omap->uhh_base) {
603 dev_err(&pdev->dev, "UHH ioremap failed\n");
605 goto err_uhh_ioremap;
608 res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
609 omap->tll_base = ioremap(res->start, resource_size(res));
610 if (!omap->tll_base) {
611 dev_err(&pdev->dev, "TLL ioremap failed\n");
613 goto err_tll_ioremap;
616 ret = omap_start_ehc(omap, hcd);
618 dev_dbg(&pdev->dev, "failed to start ehci\n");
622 omap->ehci->regs = hcd->regs
623 + HC_LENGTH(readl(&omap->ehci->caps->hc_capbase));
625 /* cache this readonly data; minimize chip reads */
626 omap->ehci->hcs_params = readl(&omap->ehci->caps->hcs_params);
628 /* SET 1 micro-frame Interrupt interval */
629 writel(readl(&omap->ehci->regs->command) | (1 << 16),
630 &omap->ehci->regs->command);
632 ret = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED);
634 dev_dbg(&pdev->dev, "failed to add hcd with err %d\n", ret);
641 omap_stop_ehc(omap, hcd);
644 iounmap(omap->tll_base);
647 iounmap(omap->uhh_base);
662 /* may be called without controller electrically present */
663 /* may be called with controller, bus, and devices active */
666 * ehci_hcd_omap_remove - shutdown processing for EHCI HCDs
667 * @pdev: USB Host Controller being removed
669 * Reverses the effect of usb_ehci_hcd_omap_probe(), first invoking
670 * the HCD's stop() method. It is always called from a thread
671 * context, normally "rmmod", "apmd", or something similar.
673 static int ehci_hcd_omap_remove(struct platform_device *pdev)
675 struct ehci_hcd_omap *omap = platform_get_drvdata(pdev);
676 struct usb_hcd *hcd = ehci_to_hcd(omap->ehci);
679 omap_stop_ehc(omap, hcd);
681 iounmap(omap->tll_base);
682 iounmap(omap->uhh_base);
688 static void ehci_hcd_omap_shutdown(struct platform_device *pdev)
690 struct ehci_hcd_omap *omap = platform_get_drvdata(pdev);
691 struct usb_hcd *hcd = ehci_to_hcd(omap->ehci);
693 if (hcd->driver->shutdown)
694 hcd->driver->shutdown(hcd);
697 static struct platform_driver ehci_hcd_omap_driver = {
698 .probe = ehci_hcd_omap_probe,
699 .remove = ehci_hcd_omap_remove,
700 .shutdown = ehci_hcd_omap_shutdown,
701 /*.suspend = ehci_hcd_omap_suspend, */
702 /*.resume = ehci_hcd_omap_resume, */
708 /*-------------------------------------------------------------------------*/
710 static const struct hc_driver ehci_omap_hc_driver = {
711 .description = hcd_name,
712 .product_desc = "OMAP-EHCI Host Controller",
713 .hcd_priv_size = sizeof(struct ehci_hcd),
716 * generic hardware linkage
719 .flags = HCD_MEMORY | HCD_USB2,
722 * basic lifecycle operations
727 .shutdown = ehci_shutdown,
730 * managing i/o requests and associated device resources
732 .urb_enqueue = ehci_urb_enqueue,
733 .urb_dequeue = ehci_urb_dequeue,
734 .endpoint_disable = ehci_endpoint_disable,
735 .endpoint_reset = ehci_endpoint_reset,
740 .get_frame_number = ehci_get_frame,
745 .hub_status_data = ehci_hub_status_data,
746 .hub_control = ehci_hub_control,
747 .bus_suspend = ehci_bus_suspend,
748 .bus_resume = ehci_bus_resume,
750 .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
753 MODULE_ALIAS("platform:omap-ehci");
754 MODULE_AUTHOR("Texas Instruments, Inc.");
755 MODULE_AUTHOR("Felipe Balbi <felipe.balbi@nokia.com>");