2 * EHCI HCD (Host Controller Driver) PCI Bus Glue.
4 * Copyright (c) 2000-2004 by David Brownell
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 #error "This file is PCI bus glue. CONFIG_PCI must be defined."
25 /*-------------------------------------------------------------------------*/
27 /* called after powerup, by probe or system-pm "wakeup" */
28 static int ehci_pci_reinit(struct ehci_hcd *ehci, struct pci_dev *pdev)
32 /* we expect static quirk code to handle the "extended capabilities"
33 * (currently just BIOS handoff) allowed starting with EHCI 0.96
36 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
37 retval = pci_set_mwi(pdev);
39 ehci_dbg(ehci, "MWI active\n");
44 /* called during probe() after chip reset completes */
45 static int ehci_pci_setup(struct usb_hcd *hcd)
47 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
48 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
49 struct pci_dev *p_smbus;
54 switch (pdev->vendor) {
55 case PCI_VENDOR_ID_TOSHIBA_2:
56 /* celleb's companion chip */
57 if (pdev->device == 0x01b5) {
58 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
59 ehci->big_endian_mmio = 1;
62 "unsupported big endian Toshiba quirk\n");
68 ehci->caps = hcd->regs;
69 ehci->regs = hcd->regs +
70 HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
72 dbg_hcs_params(ehci, "reset");
73 dbg_hcc_params(ehci, "reset");
75 /* ehci_init() causes memory for DMA transfers to be
76 * allocated. Thus, any vendor-specific workarounds based on
77 * limiting the type of memory used for DMA transfers must
78 * happen before ehci_init() is called. */
79 switch (pdev->vendor) {
80 case PCI_VENDOR_ID_NVIDIA:
81 /* NVidia reports that certain chips don't handle
82 * QH, ITD, or SITD addresses above 2GB. (But TD,
83 * data buffer, and periodic schedule are normal.)
85 switch (pdev->device) {
86 case 0x003c: /* MCP04 */
87 case 0x005b: /* CK804 */
88 case 0x00d8: /* CK8 */
89 case 0x00e8: /* CK8S */
90 if (pci_set_consistent_dma_mask(pdev,
91 DMA_BIT_MASK(31)) < 0)
92 ehci_warn(ehci, "can't enable NVidia "
93 "workaround for >2GB RAM\n");
99 /* cache this readonly data; minimize chip reads */
100 ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
102 retval = ehci_halt(ehci);
106 /* data structure init */
107 retval = ehci_init(hcd);
111 switch (pdev->vendor) {
112 case PCI_VENDOR_ID_NEC:
113 ehci->need_io_watchdog = 0;
115 case PCI_VENDOR_ID_INTEL:
116 ehci->need_io_watchdog = 0;
117 ehci->fs_i_thresh = 1;
118 if (pdev->device == 0x27cc) {
119 ehci->broken_periodic = 1;
120 ehci_info(ehci, "using broken periodic workaround\n");
123 case PCI_VENDOR_ID_TDI:
124 if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) {
129 case PCI_VENDOR_ID_AMD:
130 /* AMD8111 EHCI doesn't work, according to AMD errata */
131 if (pdev->device == 0x7463) {
132 ehci_info(ehci, "ignoring AMD8111 (errata)\n");
137 case PCI_VENDOR_ID_NVIDIA:
138 switch (pdev->device) {
139 /* Some NForce2 chips have problems with selective suspend;
140 * fixed in newer silicon.
143 if (pdev->revision < 0xa4)
144 ehci->no_selective_suspend = 1;
148 case PCI_VENDOR_ID_VIA:
149 if (pdev->device == 0x3104 && (pdev->revision & 0xf0) == 0x60) {
152 /* The VT6212 defaults to a 1 usec EHCI sleep time which
153 * hogs the PCI bus *badly*. Setting bit 5 of 0x4B makes
154 * that sleep time use the conventional 10 usec.
156 pci_read_config_byte(pdev, 0x4b, &tmp);
159 pci_write_config_byte(pdev, 0x4b, tmp | 0x20);
162 case PCI_VENDOR_ID_ATI:
163 /* SB600 and old version of SB700 have a bug in EHCI controller,
164 * which causes usb devices lose response in some cases.
166 if ((pdev->device == 0x4386) || (pdev->device == 0x4396)) {
167 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
168 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
172 rev = p_smbus->revision;
173 if ((pdev->device == 0x4386) || (rev == 0x3a)
176 ehci_info(ehci, "applying AMD SB600/SB700 USB "
177 "freeze workaround\n");
178 pci_read_config_byte(pdev, 0x53, &tmp);
179 pci_write_config_byte(pdev, 0x53, tmp | (1<<3));
181 pci_dev_put(p_smbus);
186 /* optional debug port, normally in the first BAR */
187 temp = pci_find_capability(pdev, 0x0a);
189 pci_read_config_dword(pdev, temp, &temp);
191 if ((temp & (3 << 13)) == (1 << 13)) {
193 ehci->debug = ehci_to_hcd(ehci)->regs + temp;
194 temp = ehci_readl(ehci, &ehci->debug->control);
195 ehci_info(ehci, "debug port %d%s\n",
196 HCS_DEBUG_PORT(ehci->hcs_params),
197 (temp & DBGP_ENABLED)
200 if (!(temp & DBGP_ENABLED))
207 /* at least the Genesys GL880S needs fixup here */
208 temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params);
210 if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) {
211 ehci_dbg(ehci, "bogus port configuration: "
212 "cc=%d x pcc=%d < ports=%d\n",
213 HCS_N_CC(ehci->hcs_params),
214 HCS_N_PCC(ehci->hcs_params),
215 HCS_N_PORTS(ehci->hcs_params));
217 switch (pdev->vendor) {
218 case 0x17a0: /* GENESYS */
219 /* GL880S: should be PORTS=2 */
220 temp |= (ehci->hcs_params & ~0xf);
221 ehci->hcs_params = temp;
223 case PCI_VENDOR_ID_NVIDIA:
224 /* NF4: should be PCC=10 */
229 /* Serial Bus Release Number is at PCI 0x60 offset */
230 pci_read_config_byte(pdev, 0x60, &ehci->sbrn);
232 /* Keep this around for a while just in case some EHCI
233 * implementation uses legacy PCI PM support. This test
234 * can be removed on 17 Dec 2009 if the dev_warn() hasn't
235 * been triggered by then.
237 if (!device_can_wakeup(&pdev->dev)) {
240 pci_read_config_word(pdev, 0x62, &port_wake);
241 if (port_wake & 0x0001) {
242 dev_warn(&pdev->dev, "Enabling legacy PCI PM\n");
243 device_set_wakeup_capable(&pdev->dev, 1);
247 #ifdef CONFIG_USB_SUSPEND
248 /* REVISIT: the controller works fine for wakeup iff the root hub
249 * itself is "globally" suspended, but usbcore currently doesn't
250 * understand such things.
252 * System suspend currently expects to be able to suspend the entire
253 * device tree, device-at-a-time. If we failed selective suspend
254 * reports, system suspend would fail; so the root hub code must claim
255 * success. That's lying to usbcore, and it matters for runtime
256 * PM scenarios with selective suspend and remote wakeup...
258 if (ehci->no_selective_suspend && device_can_wakeup(&pdev->dev))
259 ehci_warn(ehci, "selective suspend/wakeup unavailable\n");
262 ehci_port_power(ehci, 1);
263 retval = ehci_pci_reinit(ehci, pdev);
268 /*-------------------------------------------------------------------------*/
272 /* suspend/resume, section 4.3 */
274 /* These routines rely on the PCI bus glue
275 * to handle powerdown and wakeup, and currently also on
276 * transceivers that don't need any software attention to set up
277 * the right sort of wakeup.
278 * Also they depend on separate root hub suspend/resume.
281 static int ehci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
283 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
287 if (time_before(jiffies, ehci->next_statechange))
290 /* Root hub was already suspended. Disable irq emission and
291 * mark HW unaccessible. The PM and USB cores make sure that
292 * the root hub is either suspended or stopped.
294 spin_lock_irqsave (&ehci->lock, flags);
295 ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup);
296 ehci_writel(ehci, 0, &ehci->regs->intr_enable);
297 (void)ehci_readl(ehci, &ehci->regs->intr_enable);
299 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
300 spin_unlock_irqrestore (&ehci->lock, flags);
302 // could save FLADJ in case of Vaux power loss
303 // ... we'd only use it to handle clock skew
308 static int ehci_pci_resume(struct usb_hcd *hcd, bool hibernated)
310 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
311 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
313 // maybe restore FLADJ
315 if (time_before(jiffies, ehci->next_statechange))
318 /* Mark hardware accessible again as we are out of D3 state by now */
319 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
321 /* If CF is still set and we aren't resuming from hibernation
322 * then we maintained PCI Vaux power.
323 * Just undo the effect of ehci_pci_suspend().
325 if (ehci_readl(ehci, &ehci->regs->configured_flag) == FLAG_CF &&
327 int mask = INTR_MASK;
329 ehci_prepare_ports_for_controller_resume(ehci);
330 if (!hcd->self.root_hub->do_remote_wakeup)
332 ehci_writel(ehci, mask, &ehci->regs->intr_enable);
333 ehci_readl(ehci, &ehci->regs->intr_enable);
337 usb_root_hub_lost_power(hcd->self.root_hub);
339 /* Else reset, to cope with power loss or flush-to-storage
340 * style "resume" having let BIOS kick in during reboot.
342 (void) ehci_halt(ehci);
343 (void) ehci_reset(ehci);
344 (void) ehci_pci_reinit(ehci, pdev);
346 /* emptying the schedule aborts any urbs */
347 spin_lock_irq(&ehci->lock);
349 end_unlink_async(ehci);
351 spin_unlock_irq(&ehci->lock);
353 ehci_writel(ehci, ehci->command, &ehci->regs->command);
354 ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
355 ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
357 /* here we "know" root ports should always stay powered */
358 ehci_port_power(ehci, 1);
360 hcd->state = HC_STATE_SUSPENDED;
365 static int ehci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
367 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
370 if (!udev->parent) /* udev is root hub itself, impossible */
372 /* we only support lpm device connected to root hub yet */
373 if (ehci->has_lpm && !udev->parent->parent) {
374 rc = ehci_lpm_set_da(ehci, udev->devnum, udev->portnum);
376 rc = ehci_lpm_check(ehci, udev->portnum);
381 static const struct hc_driver ehci_pci_hc_driver = {
382 .description = hcd_name,
383 .product_desc = "EHCI Host Controller",
384 .hcd_priv_size = sizeof(struct ehci_hcd),
387 * generic hardware linkage
390 .flags = HCD_MEMORY | HCD_USB2,
393 * basic lifecycle operations
395 .reset = ehci_pci_setup,
398 .pci_suspend = ehci_pci_suspend,
399 .pci_resume = ehci_pci_resume,
402 .shutdown = ehci_shutdown,
405 * managing i/o requests and associated device resources
407 .urb_enqueue = ehci_urb_enqueue,
408 .urb_dequeue = ehci_urb_dequeue,
409 .endpoint_disable = ehci_endpoint_disable,
410 .endpoint_reset = ehci_endpoint_reset,
415 .get_frame_number = ehci_get_frame,
420 .hub_status_data = ehci_hub_status_data,
421 .hub_control = ehci_hub_control,
422 .bus_suspend = ehci_bus_suspend,
423 .bus_resume = ehci_bus_resume,
424 .relinquish_port = ehci_relinquish_port,
425 .port_handed_over = ehci_port_handed_over,
428 * call back when device connected and addressed
430 .update_device = ehci_update_device,
432 .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
435 /*-------------------------------------------------------------------------*/
437 /* PCI driver selection metadata; PCI hotplugging uses this */
438 static const struct pci_device_id pci_ids [] = { {
439 /* handle any USB 2.0 EHCI controller */
440 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_EHCI, ~0),
441 .driver_data = (unsigned long) &ehci_pci_hc_driver,
443 { /* end: all zeroes */ }
445 MODULE_DEVICE_TABLE(pci, pci_ids);
447 /* pci driver glue; this is a "new style" PCI driver module */
448 static struct pci_driver ehci_pci_driver = {
449 .name = (char *) hcd_name,
452 .probe = usb_hcd_pci_probe,
453 .remove = usb_hcd_pci_remove,
454 .shutdown = usb_hcd_pci_shutdown,
456 #ifdef CONFIG_PM_SLEEP
458 .pm = &usb_hcd_pci_pm_ops