2 * EHCI HCD (Host Controller Driver) for USB.
4 * Copyright (C) 2013,2014 Renesas Electronics Corporation
5 * Copyright (C) 2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
7 * SPDX-License-Identifier: GPL-2.0
12 #include <asm/arch/ehci-rmobile.h>
15 #if defined(CONFIG_R8A7740)
16 static u32 usb_base_address[CONFIG_USB_MAX_CONTROLLER_COUNT] = {
19 #elif defined(CONFIG_R8A7790)
20 static u32 usb_base_address[CONFIG_USB_MAX_CONTROLLER_COUNT] = {
21 0xEE080000, /* USB0 (EHCI) */
22 0xEE0A0000, /* USB1 */
23 0xEE0C0000, /* USB2 */
25 #elif defined(CONFIG_R8A7791)
26 static u32 usb_base_address[CONFIG_USB_MAX_CONTROLLER_COUNT] = {
27 0xEE080000, /* USB0 (EHCI) */
28 0xEE0C0000, /* USB1 */
30 #elif defined(CONFIG_R8A7793)
31 static u32 usb_base_address[CONFIG_USB_MAX_CONTROLLER_COUNT] = {
32 0xEE080000, /* USB0 (EHCI) */
33 0xEE0C0000, /* USB1 */
35 #elif defined(CONFIG_R8A7794)
36 static u32 usb_base_address[CONFIG_USB_MAX_CONTROLLER_COUNT] = {
37 0xEE080000, /* USB0 (EHCI) */
38 0xEE0C0000, /* USB1 */
41 #error rmobile EHCI USB driver not supported on this platform
44 int ehci_hcd_stop(int index)
48 struct ahbcom_pci_bridge *ahbcom_pci;
50 base = usb_base_address[index];
51 ahbcom_pci = (struct ahbcom_pci_bridge *)(base + AHBPCI_OFFSET);
52 writel(0, &ahbcom_pci->ahb_bus_ctr);
55 setbits_le32(base + EHCI_USBCMD, CMD_RESET);
56 for (i = 100; i > 0; i--) {
57 if (!(readl(base + EHCI_USBCMD) & CMD_RESET))
63 printf("error : ehci(%d) reset failed.\n", index);
65 if (index == (CONFIG_USB_MAX_CONTROLLER_COUNT - 1))
66 setbits_le32(SMSTPCR7, SMSTPCR703);
71 int ehci_hcd_init(int index, enum usb_init_type init,
72 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
76 struct rmobile_ehci_reg *rehci;
77 struct ahbcom_pci_bridge *ahbcom_pci;
78 struct ahbconf_pci_bridge *ahbconf_pci;
79 struct ahb_pciconf *ahb_pciconf_ohci;
80 struct ahb_pciconf *ahb_pciconf_ehci;
83 base = usb_base_address[index];
86 clrbits_le32(SMSTPCR7, SMSTPCR703);
88 rehci = (struct rmobile_ehci_reg *)(base + EHCI_OFFSET);
89 ahbcom_pci = (struct ahbcom_pci_bridge *)(base + AHBPCI_OFFSET);
91 (struct ahbconf_pci_bridge *)(base + PCI_CONF_AHBPCI_OFFSET);
92 ahb_pciconf_ohci = (struct ahb_pciconf *)(base + PCI_CONF_OHCI_OFFSET);
93 ahb_pciconf_ehci = (struct ahb_pciconf *)(base + PCI_CONF_EHCI_OFFSET);
95 /* Clock & Reset & Direct Power Down */
96 clrsetbits_le32(&ahbcom_pci->usbctr,
97 (DIRPD | PCICLK_MASK | USBH_RST), USBCTR_WIN_SIZE_1GB);
98 clrbits_le32(&ahbcom_pci->usbctr, PLL_RST);
100 /* AHB-PCI Bridge Communication Registers */
101 writel(AHB_BUS_CTR_INIT, &ahbcom_pci->ahb_bus_ctr);
102 writel((CONFIG_SYS_SDRAM_BASE & 0xf0000000) | PCIAHB_WIN_PREFETCH,
103 &ahbcom_pci->pciahb_win1_ctr);
104 writel(0xf0000000 | PCIAHB_WIN_PREFETCH,
105 &ahbcom_pci->pciahb_win2_ctr);
106 writel(phys_base | PCIWIN2_PCICMD, &ahbcom_pci->ahbpci_win2_ctr);
108 setbits_le32(&ahbcom_pci->pci_arbiter_ctr,
109 PCIBP_MODE | PCIREQ1 | PCIREQ0);
111 /* PCI Configuration Registers for AHBPCI */
112 writel(PCIWIN1_PCICMD | AHB_CFG_AHBPCI,
113 &ahbcom_pci->ahbpci_win1_ctr);
114 writel(phys_base + AHBPCI_OFFSET, &ahbconf_pci->basead);
115 writel(CONFIG_SYS_SDRAM_BASE & 0xf0000000, &ahbconf_pci->win1_basead);
116 writel(0xf0000000, &ahbconf_pci->win2_basead);
117 writel(SERREN | PERREN | MASTEREN | MEMEN,
118 &ahbconf_pci->cmnd_sts);
120 /* PCI Configuration Registers for EHCI */
121 writel(PCIWIN1_PCICMD | AHB_CFG_HOST, &ahbcom_pci->ahbpci_win1_ctr);
122 writel(phys_base + OHCI_OFFSET, &ahb_pciconf_ohci->basead);
123 writel(phys_base + EHCI_OFFSET, &ahb_pciconf_ehci->basead);
124 writel(SERREN | PERREN | MASTEREN | MEMEN,
125 &ahb_pciconf_ohci->cmnd_sts);
126 writel(SERREN | PERREN | MASTEREN | MEMEN,
127 &ahb_pciconf_ehci->cmnd_sts);
129 /* Enable PCI interrupt */
130 setbits_le32(&ahbcom_pci->pci_int_enable,
131 USBH_PMEEN | USBH_INTBEN | USBH_INTAEN);
133 *hccr = (struct ehci_hccr *)((uint32_t)&rehci->hciversion);
134 cap_base = ehci_readl(&(*hccr)->cr_capbase);
135 *hcor = (struct ehci_hcor *)((uint32_t)*hccr + HC_LENGTH(cap_base));