2 * Copyright (c) 2001-2004 by David Brownell
3 * Copyright (c) 2003 Michal Sojka, for high-speed iso transfers
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software Foundation,
17 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 /* this file is part of ehci-hcd.c */
22 /*-------------------------------------------------------------------------*/
25 * EHCI scheduled transaction support: interrupt, iso, split iso
26 * These are called "periodic" transactions in the EHCI spec.
28 * Note that for interrupt transfers, the QH/QTD manipulation is shared
29 * with the "asynchronous" transaction support (control/bulk transfers).
30 * The only real difference is in how interrupt transfers are scheduled.
32 * For ISO, we make an "iso_stream" head to serve the same role as a QH.
33 * It keeps track of every ITD (or SITD) that's linked, and holds enough
34 * pre-calculated schedule data to make appending to the queue be quick.
37 static int ehci_get_frame (struct usb_hcd *hcd);
39 /*-------------------------------------------------------------------------*/
42 * periodic_next_shadow - return "next" pointer on shadow list
43 * @periodic: host pointer to qh/itd/sitd
44 * @tag: hardware tag for type of this record
46 static union ehci_shadow *
47 periodic_next_shadow(struct ehci_hcd *ehci, union ehci_shadow *periodic,
50 switch (hc32_to_cpu(ehci, tag)) {
52 return &periodic->qh->qh_next;
54 return &periodic->fstn->fstn_next;
56 return &periodic->itd->itd_next;
59 return &periodic->sitd->sitd_next;
64 shadow_next_periodic(struct ehci_hcd *ehci, union ehci_shadow *periodic,
67 switch (hc32_to_cpu(ehci, tag)) {
68 /* our ehci_shadow.qh is actually software part */
70 return &periodic->qh->hw->hw_next;
71 /* others are hw parts */
73 return periodic->hw_next;
77 /* caller must hold ehci->lock */
78 static void periodic_unlink (struct ehci_hcd *ehci, unsigned frame, void *ptr)
80 union ehci_shadow *prev_p = &ehci->pshadow[frame];
81 __hc32 *hw_p = &ehci->periodic[frame];
82 union ehci_shadow here = *prev_p;
84 /* find predecessor of "ptr"; hw and shadow lists are in sync */
85 while (here.ptr && here.ptr != ptr) {
86 prev_p = periodic_next_shadow(ehci, prev_p,
87 Q_NEXT_TYPE(ehci, *hw_p));
88 hw_p = shadow_next_periodic(ehci, &here,
89 Q_NEXT_TYPE(ehci, *hw_p));
92 /* an interrupt entry (at list end) could have been shared */
96 /* update shadow and hardware lists ... the old "next" pointers
97 * from ptr may still be in use, the caller updates them.
99 *prev_p = *periodic_next_shadow(ehci, &here,
100 Q_NEXT_TYPE(ehci, *hw_p));
101 *hw_p = *shadow_next_periodic(ehci, &here, Q_NEXT_TYPE(ehci, *hw_p));
104 /* how many of the uframe's 125 usecs are allocated? */
105 static unsigned short
106 periodic_usecs (struct ehci_hcd *ehci, unsigned frame, unsigned uframe)
108 __hc32 *hw_p = &ehci->periodic [frame];
109 union ehci_shadow *q = &ehci->pshadow [frame];
111 struct ehci_qh_hw *hw;
114 switch (hc32_to_cpu(ehci, Q_NEXT_TYPE(ehci, *hw_p))) {
117 /* is it in the S-mask? */
118 if (hw->hw_info2 & cpu_to_hc32(ehci, 1 << uframe))
119 usecs += q->qh->usecs;
121 if (hw->hw_info2 & cpu_to_hc32(ehci,
123 usecs += q->qh->c_usecs;
129 /* for "save place" FSTNs, count the relevant INTR
130 * bandwidth from the previous frame
132 if (q->fstn->hw_prev != EHCI_LIST_END(ehci)) {
133 ehci_dbg (ehci, "ignoring FSTN cost ...\n");
135 hw_p = &q->fstn->hw_next;
136 q = &q->fstn->fstn_next;
139 if (q->itd->hw_transaction[uframe])
140 usecs += q->itd->stream->usecs;
141 hw_p = &q->itd->hw_next;
142 q = &q->itd->itd_next;
145 /* is it in the S-mask? (count SPLIT, DATA) */
146 if (q->sitd->hw_uframe & cpu_to_hc32(ehci,
148 if (q->sitd->hw_fullspeed_ep &
149 cpu_to_hc32(ehci, 1<<31))
150 usecs += q->sitd->stream->usecs;
151 else /* worst case for OUT start-split */
152 usecs += HS_USECS_ISO (188);
155 /* ... C-mask? (count CSPLIT, DATA) */
156 if (q->sitd->hw_uframe &
157 cpu_to_hc32(ehci, 1 << (8 + uframe))) {
158 /* worst case for IN complete-split */
159 usecs += q->sitd->stream->c_usecs;
162 hw_p = &q->sitd->hw_next;
163 q = &q->sitd->sitd_next;
169 ehci_err (ehci, "uframe %d sched overrun: %d usecs\n",
170 frame * 8 + uframe, usecs);
175 /*-------------------------------------------------------------------------*/
177 static int same_tt (struct usb_device *dev1, struct usb_device *dev2)
179 if (!dev1->tt || !dev2->tt)
181 if (dev1->tt != dev2->tt)
184 return dev1->ttport == dev2->ttport;
189 #ifdef CONFIG_USB_EHCI_TT_NEWSCHED
191 /* Which uframe does the low/fullspeed transfer start in?
193 * The parameter is the mask of ssplits in "H-frame" terms
194 * and this returns the transfer start uframe in "B-frame" terms,
195 * which allows both to match, e.g. a ssplit in "H-frame" uframe 0
196 * will cause a transfer in "B-frame" uframe 0. "B-frames" lag
197 * "H-frames" by 1 uframe. See the EHCI spec sec 4.5 and figure 4.7.
199 static inline unsigned char tt_start_uframe(struct ehci_hcd *ehci, __hc32 mask)
201 unsigned char smask = QH_SMASK & hc32_to_cpu(ehci, mask);
203 ehci_err(ehci, "invalid empty smask!\n");
204 /* uframe 7 can't have bw so this will indicate failure */
207 return ffs(smask) - 1;
210 static const unsigned char
211 max_tt_usecs[] = { 125, 125, 125, 125, 125, 125, 30, 0 };
213 /* carryover low/fullspeed bandwidth that crosses uframe boundries */
214 static inline void carryover_tt_bandwidth(unsigned short tt_usecs[8])
217 for (i=0; i<7; i++) {
218 if (max_tt_usecs[i] < tt_usecs[i]) {
219 tt_usecs[i+1] += tt_usecs[i] - max_tt_usecs[i];
220 tt_usecs[i] = max_tt_usecs[i];
225 /* How many of the tt's periodic downstream 1000 usecs are allocated?
227 * While this measures the bandwidth in terms of usecs/uframe,
228 * the low/fullspeed bus has no notion of uframes, so any particular
229 * low/fullspeed transfer can "carry over" from one uframe to the next,
230 * since the TT just performs downstream transfers in sequence.
232 * For example two separate 100 usec transfers can start in the same uframe,
233 * and the second one would "carry over" 75 usecs into the next uframe.
237 struct ehci_hcd *ehci,
238 struct usb_device *dev,
240 unsigned short tt_usecs[8]
243 __hc32 *hw_p = &ehci->periodic [frame];
244 union ehci_shadow *q = &ehci->pshadow [frame];
247 memset(tt_usecs, 0, 16);
250 switch (hc32_to_cpu(ehci, Q_NEXT_TYPE(ehci, *hw_p))) {
252 hw_p = &q->itd->hw_next;
253 q = &q->itd->itd_next;
256 if (same_tt(dev, q->qh->dev)) {
257 uf = tt_start_uframe(ehci, q->qh->hw->hw_info2);
258 tt_usecs[uf] += q->qh->tt_usecs;
260 hw_p = &q->qh->hw->hw_next;
264 if (same_tt(dev, q->sitd->urb->dev)) {
265 uf = tt_start_uframe(ehci, q->sitd->hw_uframe);
266 tt_usecs[uf] += q->sitd->stream->tt_usecs;
268 hw_p = &q->sitd->hw_next;
269 q = &q->sitd->sitd_next;
273 ehci_dbg(ehci, "ignoring periodic frame %d FSTN\n",
275 hw_p = &q->fstn->hw_next;
276 q = &q->fstn->fstn_next;
280 carryover_tt_bandwidth(tt_usecs);
282 if (max_tt_usecs[7] < tt_usecs[7])
283 ehci_err(ehci, "frame %d tt sched overrun: %d usecs\n",
284 frame, tt_usecs[7] - max_tt_usecs[7]);
288 * Return true if the device's tt's downstream bus is available for a
289 * periodic transfer of the specified length (usecs), starting at the
290 * specified frame/uframe. Note that (as summarized in section 11.19
291 * of the usb 2.0 spec) TTs can buffer multiple transactions for each
294 * The uframe parameter is when the fullspeed/lowspeed transfer
295 * should be executed in "B-frame" terms, which is the same as the
296 * highspeed ssplit's uframe (which is in "H-frame" terms). For example
297 * a ssplit in "H-frame" 0 causes a transfer in "B-frame" 0.
298 * See the EHCI spec sec 4.5 and fig 4.7.
300 * This checks if the full/lowspeed bus, at the specified starting uframe,
301 * has the specified bandwidth available, according to rules listed
302 * in USB 2.0 spec section 11.18.1 fig 11-60.
304 * This does not check if the transfer would exceed the max ssplit
305 * limit of 16, specified in USB 2.0 spec section 11.18.4 requirement #4,
306 * since proper scheduling limits ssplits to less than 16 per uframe.
308 static int tt_available (
309 struct ehci_hcd *ehci,
311 struct usb_device *dev,
317 if ((period == 0) || (uframe >= 7)) /* error */
320 for (; frame < ehci->periodic_size; frame += period) {
321 unsigned short tt_usecs[8];
323 periodic_tt_usecs (ehci, dev, frame, tt_usecs);
325 ehci_vdbg(ehci, "tt frame %d check %d usecs start uframe %d in"
326 " schedule %d/%d/%d/%d/%d/%d/%d/%d\n",
327 frame, usecs, uframe,
328 tt_usecs[0], tt_usecs[1], tt_usecs[2], tt_usecs[3],
329 tt_usecs[4], tt_usecs[5], tt_usecs[6], tt_usecs[7]);
331 if (max_tt_usecs[uframe] <= tt_usecs[uframe]) {
332 ehci_vdbg(ehci, "frame %d uframe %d fully scheduled\n",
337 /* special case for isoc transfers larger than 125us:
338 * the first and each subsequent fully used uframe
339 * must be empty, so as to not illegally delay
340 * already scheduled transactions
343 int ufs = (usecs / 125);
345 for (i = uframe; i < (uframe + ufs) && i < 8; i++)
346 if (0 < tt_usecs[i]) {
348 "multi-uframe xfer can't fit "
349 "in frame %d uframe %d\n",
355 tt_usecs[uframe] += usecs;
357 carryover_tt_bandwidth(tt_usecs);
359 /* fail if the carryover pushed bw past the last uframe's limit */
360 if (max_tt_usecs[7] < tt_usecs[7]) {
362 "tt unavailable usecs %d frame %d uframe %d\n",
363 usecs, frame, uframe);
373 /* return true iff the device's transaction translator is available
374 * for a periodic transfer starting at the specified frame, using
375 * all the uframes in the mask.
377 static int tt_no_collision (
378 struct ehci_hcd *ehci,
380 struct usb_device *dev,
385 if (period == 0) /* error */
388 /* note bandwidth wastage: split never follows csplit
389 * (different dev or endpoint) until the next uframe.
390 * calling convention doesn't make that distinction.
392 for (; frame < ehci->periodic_size; frame += period) {
393 union ehci_shadow here;
395 struct ehci_qh_hw *hw;
397 here = ehci->pshadow [frame];
398 type = Q_NEXT_TYPE(ehci, ehci->periodic [frame]);
400 switch (hc32_to_cpu(ehci, type)) {
402 type = Q_NEXT_TYPE(ehci, here.itd->hw_next);
403 here = here.itd->itd_next;
407 if (same_tt (dev, here.qh->dev)) {
410 mask = hc32_to_cpu(ehci,
412 /* "knows" no gap is needed */
417 type = Q_NEXT_TYPE(ehci, hw->hw_next);
418 here = here.qh->qh_next;
421 if (same_tt (dev, here.sitd->urb->dev)) {
424 mask = hc32_to_cpu(ehci, here.sitd
426 /* FIXME assumes no gap for IN! */
431 type = Q_NEXT_TYPE(ehci, here.sitd->hw_next);
432 here = here.sitd->sitd_next;
437 "periodic frame %d bogus type %d\n",
441 /* collision or error */
450 #endif /* CONFIG_USB_EHCI_TT_NEWSCHED */
452 /*-------------------------------------------------------------------------*/
454 static int enable_periodic (struct ehci_hcd *ehci)
459 if (ehci->periodic_sched++)
462 /* did clearing PSE did take effect yet?
463 * takes effect only at frame boundaries...
465 status = handshake_on_error_set_halt(ehci, &ehci->regs->status,
466 STS_PSS, 0, 9 * 125);
470 cmd = ehci_readl(ehci, &ehci->regs->command) | CMD_PSE;
471 ehci_writel(ehci, cmd, &ehci->regs->command);
472 /* posted write ... PSS happens later */
473 ehci_to_hcd(ehci)->state = HC_STATE_RUNNING;
475 /* make sure ehci_work scans these */
476 ehci->next_uframe = ehci_readl(ehci, &ehci->regs->frame_index)
477 % (ehci->periodic_size << 3);
478 if (unlikely(ehci->broken_periodic))
479 ehci->last_periodic_enable = ktime_get_real();
483 static int disable_periodic (struct ehci_hcd *ehci)
488 if (--ehci->periodic_sched)
491 if (unlikely(ehci->broken_periodic)) {
492 /* delay experimentally determined */
493 ktime_t safe = ktime_add_us(ehci->last_periodic_enable, 1000);
494 ktime_t now = ktime_get_real();
495 s64 delay = ktime_us_delta(safe, now);
497 if (unlikely(delay > 0))
501 /* did setting PSE not take effect yet?
502 * takes effect only at frame boundaries...
504 status = handshake_on_error_set_halt(ehci, &ehci->regs->status,
505 STS_PSS, STS_PSS, 9 * 125);
509 cmd = ehci_readl(ehci, &ehci->regs->command) & ~CMD_PSE;
510 ehci_writel(ehci, cmd, &ehci->regs->command);
511 /* posted write ... */
513 ehci->next_uframe = -1;
517 /*-------------------------------------------------------------------------*/
519 /* periodic schedule slots have iso tds (normal or split) first, then a
520 * sparse tree for active interrupt transfers.
522 * this just links in a qh; caller guarantees uframe masks are set right.
523 * no FSTN support (yet; ehci 0.96+)
525 static int qh_link_periodic (struct ehci_hcd *ehci, struct ehci_qh *qh)
528 unsigned period = qh->period;
530 dev_dbg (&qh->dev->dev,
531 "link qh%d-%04x/%p start %d [%d/%d us]\n",
532 period, hc32_to_cpup(ehci, &qh->hw->hw_info2)
533 & (QH_CMASK | QH_SMASK),
534 qh, qh->start, qh->usecs, qh->c_usecs);
536 /* high bandwidth, or otherwise every microframe */
540 for (i = qh->start; i < ehci->periodic_size; i += period) {
541 union ehci_shadow *prev = &ehci->pshadow[i];
542 __hc32 *hw_p = &ehci->periodic[i];
543 union ehci_shadow here = *prev;
546 /* skip the iso nodes at list head */
548 type = Q_NEXT_TYPE(ehci, *hw_p);
549 if (type == cpu_to_hc32(ehci, Q_TYPE_QH))
551 prev = periodic_next_shadow(ehci, prev, type);
552 hw_p = shadow_next_periodic(ehci, &here, type);
556 /* sorting each branch by period (slow-->fast)
557 * enables sharing interior tree nodes
559 while (here.ptr && qh != here.qh) {
560 if (qh->period > here.qh->period)
562 prev = &here.qh->qh_next;
563 hw_p = &here.qh->hw->hw_next;
566 /* link in this qh, unless some earlier pass did that */
570 qh->hw->hw_next = *hw_p;
573 *hw_p = QH_NEXT (ehci, qh->qh_dma);
576 qh->qh_state = QH_STATE_LINKED;
580 /* update per-qh bandwidth for usbfs */
581 ehci_to_hcd(ehci)->self.bandwidth_allocated += qh->period
582 ? ((qh->usecs + qh->c_usecs) / qh->period)
585 /* maybe enable periodic schedule processing */
586 return enable_periodic(ehci);
589 static int qh_unlink_periodic(struct ehci_hcd *ehci, struct ehci_qh *qh)
595 // IF this isn't high speed
596 // and this qh is active in the current uframe
597 // (and overlay token SplitXstate is false?)
599 // qh->hw_info1 |= cpu_to_hc32(1 << 7 /* "ignore" */);
601 /* high bandwidth, or otherwise part of every microframe */
602 if ((period = qh->period) == 0)
605 for (i = qh->start; i < ehci->periodic_size; i += period)
606 periodic_unlink (ehci, i, qh);
608 /* update per-qh bandwidth for usbfs */
609 ehci_to_hcd(ehci)->self.bandwidth_allocated -= qh->period
610 ? ((qh->usecs + qh->c_usecs) / qh->period)
613 dev_dbg (&qh->dev->dev,
614 "unlink qh%d-%04x/%p start %d [%d/%d us]\n",
616 hc32_to_cpup(ehci, &qh->hw->hw_info2) & (QH_CMASK | QH_SMASK),
617 qh, qh->start, qh->usecs, qh->c_usecs);
619 /* qh->qh_next still "live" to HC */
620 qh->qh_state = QH_STATE_UNLINK;
621 qh->qh_next.ptr = NULL;
624 /* maybe turn off periodic schedule */
625 return disable_periodic(ehci);
628 static void intr_deschedule (struct ehci_hcd *ehci, struct ehci_qh *qh)
631 struct ehci_qh_hw *hw = qh->hw;
634 /* If the QH isn't linked then there's nothing we can do
635 * unless we were called during a giveback, in which case
636 * qh_completions() has to deal with it.
638 if (qh->qh_state != QH_STATE_LINKED) {
639 if (qh->qh_state == QH_STATE_COMPLETING)
640 qh->needs_rescan = 1;
644 qh_unlink_periodic (ehci, qh);
646 /* simple/paranoid: always delay, expecting the HC needs to read
647 * qh->hw_next or finish a writeback after SPLIT/CSPLIT ... and
648 * expect khubd to clean up after any CSPLITs we won't issue.
649 * active high speed queues may need bigger delays...
651 if (list_empty (&qh->qtd_list)
652 || (cpu_to_hc32(ehci, QH_CMASK)
653 & hw->hw_info2) != 0)
656 wait = 55; /* worst case: 3 * 1024 */
659 qh->qh_state = QH_STATE_IDLE;
660 hw->hw_next = EHCI_LIST_END(ehci);
663 qh_completions(ehci, qh);
665 /* reschedule QH iff another request is queued */
666 if (!list_empty(&qh->qtd_list) &&
667 HC_IS_RUNNING(ehci_to_hcd(ehci)->state)) {
668 rc = qh_schedule(ehci, qh);
670 /* An error here likely indicates handshake failure
671 * or no space left in the schedule. Neither fault
672 * should happen often ...
674 * FIXME kill the now-dysfunctional queued urbs
677 ehci_err(ehci, "can't reschedule qh %p, err %d\n",
682 /*-------------------------------------------------------------------------*/
684 static int check_period (
685 struct ehci_hcd *ehci,
693 /* complete split running into next frame?
694 * given FSTN support, we could sometimes check...
700 * 80% periodic == 100 usec/uframe available
701 * convert "usecs we need" to "max already claimed"
705 /* we "know" 2 and 4 uframe intervals were rejected; so
706 * for period 0, check _every_ microframe in the schedule.
708 if (unlikely (period == 0)) {
710 for (uframe = 0; uframe < 7; uframe++) {
711 claimed = periodic_usecs (ehci, frame, uframe);
715 } while ((frame += 1) < ehci->periodic_size);
717 /* just check the specified uframe, at that period */
720 claimed = periodic_usecs (ehci, frame, uframe);
723 } while ((frame += period) < ehci->periodic_size);
730 static int check_intr_schedule (
731 struct ehci_hcd *ehci,
734 const struct ehci_qh *qh,
738 int retval = -ENOSPC;
741 if (qh->c_usecs && uframe >= 6) /* FSTN territory? */
744 if (!check_period (ehci, frame, uframe, qh->period, qh->usecs))
752 #ifdef CONFIG_USB_EHCI_TT_NEWSCHED
753 if (tt_available (ehci, qh->period, qh->dev, frame, uframe,
757 /* TODO : this may need FSTN for SSPLIT in uframe 5. */
758 for (i=uframe+1; i<8 && i<uframe+4; i++)
759 if (!check_period (ehci, frame, i,
760 qh->period, qh->c_usecs))
767 *c_maskp = cpu_to_hc32(ehci, mask << 8);
770 /* Make sure this tt's buffer is also available for CSPLITs.
771 * We pessimize a bit; probably the typical full speed case
772 * doesn't need the second CSPLIT.
774 * NOTE: both SPLIT and CSPLIT could be checked in just
777 mask = 0x03 << (uframe + qh->gap_uf);
778 *c_maskp = cpu_to_hc32(ehci, mask << 8);
781 if (tt_no_collision (ehci, qh->period, qh->dev, frame, mask)) {
782 if (!check_period (ehci, frame, uframe + qh->gap_uf + 1,
783 qh->period, qh->c_usecs))
785 if (!check_period (ehci, frame, uframe + qh->gap_uf,
786 qh->period, qh->c_usecs))
795 /* "first fit" scheduling policy used the first time through,
796 * or when the previous schedule slot can't be re-used.
798 static int qh_schedule(struct ehci_hcd *ehci, struct ehci_qh *qh)
803 unsigned frame; /* 0..(qh->period - 1), or NO_FRAME */
804 struct ehci_qh_hw *hw = qh->hw;
806 qh_refresh(ehci, qh);
807 hw->hw_next = EHCI_LIST_END(ehci);
810 /* reuse the previous schedule slots, if we can */
811 if (frame < qh->period) {
812 uframe = ffs(hc32_to_cpup(ehci, &hw->hw_info2) & QH_SMASK);
813 status = check_intr_schedule (ehci, frame, --uframe,
821 /* else scan the schedule to find a group of slots such that all
822 * uframes have enough periodic bandwidth available.
825 /* "normal" case, uframing flexible except with splits */
829 for (i = qh->period; status && i > 0; --i) {
830 frame = ++ehci->random_frame % qh->period;
831 for (uframe = 0; uframe < 8; uframe++) {
832 status = check_intr_schedule (ehci,
840 /* qh->period == 0 means every uframe */
843 status = check_intr_schedule (ehci, 0, 0, qh, &c_mask);
849 /* reset S-frame and (maybe) C-frame masks */
850 hw->hw_info2 &= cpu_to_hc32(ehci, ~(QH_CMASK | QH_SMASK));
851 hw->hw_info2 |= qh->period
852 ? cpu_to_hc32(ehci, 1 << uframe)
853 : cpu_to_hc32(ehci, QH_SMASK);
854 hw->hw_info2 |= c_mask;
856 ehci_dbg (ehci, "reused qh %p schedule\n", qh);
858 /* stuff into the periodic schedule */
859 status = qh_link_periodic (ehci, qh);
864 static int intr_submit (
865 struct ehci_hcd *ehci,
867 struct list_head *qtd_list,
874 struct list_head empty;
876 /* get endpoint and transfer/schedule data */
877 epnum = urb->ep->desc.bEndpointAddress;
879 spin_lock_irqsave (&ehci->lock, flags);
881 if (unlikely(!test_bit(HCD_FLAG_HW_ACCESSIBLE,
882 &ehci_to_hcd(ehci)->flags))) {
884 goto done_not_linked;
886 status = usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci), urb);
887 if (unlikely(status))
888 goto done_not_linked;
890 /* get qh and force any scheduling errors */
891 INIT_LIST_HEAD (&empty);
892 qh = qh_append_tds(ehci, urb, &empty, epnum, &urb->ep->hcpriv);
897 if (qh->qh_state == QH_STATE_IDLE) {
898 if ((status = qh_schedule (ehci, qh)) != 0)
902 /* then queue the urb's tds to the qh */
903 qh = qh_append_tds(ehci, urb, qtd_list, epnum, &urb->ep->hcpriv);
906 /* ... update usbfs periodic stats */
907 ehci_to_hcd(ehci)->self.bandwidth_int_reqs++;
910 if (unlikely(status))
911 usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb);
913 spin_unlock_irqrestore (&ehci->lock, flags);
915 qtd_list_free (ehci, urb, qtd_list);
920 /*-------------------------------------------------------------------------*/
922 /* ehci_iso_stream ops work with both ITD and SITD */
924 static struct ehci_iso_stream *
925 iso_stream_alloc (gfp_t mem_flags)
927 struct ehci_iso_stream *stream;
929 stream = kzalloc(sizeof *stream, mem_flags);
930 if (likely (stream != NULL)) {
931 INIT_LIST_HEAD(&stream->td_list);
932 INIT_LIST_HEAD(&stream->free_list);
933 stream->next_uframe = -1;
934 stream->refcount = 1;
941 struct ehci_hcd *ehci,
942 struct ehci_iso_stream *stream,
943 struct usb_device *dev,
948 static const u8 smask_out [] = { 0x01, 0x03, 0x07, 0x0f, 0x1f, 0x3f };
951 unsigned epnum, maxp;
956 * this might be a "high bandwidth" highspeed endpoint,
957 * as encoded in the ep descriptor's wMaxPacket field
959 epnum = usb_pipeendpoint (pipe);
960 is_input = usb_pipein (pipe) ? USB_DIR_IN : 0;
961 maxp = usb_maxpacket(dev, pipe, !is_input);
968 /* knows about ITD vs SITD */
969 if (dev->speed == USB_SPEED_HIGH) {
970 unsigned multi = hb_mult(maxp);
972 stream->highspeed = 1;
974 maxp = max_packet(maxp);
978 stream->buf0 = cpu_to_hc32(ehci, (epnum << 8) | dev->devnum);
979 stream->buf1 = cpu_to_hc32(ehci, buf1);
980 stream->buf2 = cpu_to_hc32(ehci, multi);
982 /* usbfs wants to report the average usecs per frame tied up
983 * when transfers on this endpoint are scheduled ...
985 stream->usecs = HS_USECS_ISO (maxp);
986 bandwidth = stream->usecs * 8;
987 bandwidth /= interval;
994 addr = dev->ttport << 24;
995 if (!ehci_is_TDI(ehci)
997 ehci_to_hcd(ehci)->self.root_hub))
998 addr |= dev->tt->hub->devnum << 16;
1000 addr |= dev->devnum;
1001 stream->usecs = HS_USECS_ISO (maxp);
1002 think_time = dev->tt ? dev->tt->think_time : 0;
1003 stream->tt_usecs = NS_TO_US (think_time + usb_calc_bus_time (
1004 dev->speed, is_input, 1, maxp));
1005 hs_transfers = max (1u, (maxp + 187) / 188);
1010 stream->c_usecs = stream->usecs;
1011 stream->usecs = HS_USECS_ISO (1);
1012 stream->raw_mask = 1;
1014 /* c-mask as specified in USB 2.0 11.18.4 3.c */
1015 tmp = (1 << (hs_transfers + 2)) - 1;
1016 stream->raw_mask |= tmp << (8 + 2);
1018 stream->raw_mask = smask_out [hs_transfers - 1];
1019 bandwidth = stream->usecs + stream->c_usecs;
1020 bandwidth /= interval << 3;
1022 /* stream->splits gets created from raw_mask later */
1023 stream->address = cpu_to_hc32(ehci, addr);
1025 stream->bandwidth = bandwidth;
1029 stream->bEndpointAddress = is_input | epnum;
1030 stream->interval = interval;
1031 stream->maxp = maxp;
1035 iso_stream_put(struct ehci_hcd *ehci, struct ehci_iso_stream *stream)
1039 /* free whenever just a dev->ep reference remains.
1040 * not like a QH -- no persistent state (toggle, halt)
1042 if (stream->refcount == 1) {
1045 // BUG_ON (!list_empty(&stream->td_list));
1047 while (!list_empty (&stream->free_list)) {
1048 struct list_head *entry;
1050 entry = stream->free_list.next;
1053 /* knows about ITD vs SITD */
1054 if (stream->highspeed) {
1055 struct ehci_itd *itd;
1057 itd = list_entry (entry, struct ehci_itd,
1059 dma_pool_free (ehci->itd_pool, itd,
1062 struct ehci_sitd *sitd;
1064 sitd = list_entry (entry, struct ehci_sitd,
1066 dma_pool_free (ehci->sitd_pool, sitd,
1071 is_in = (stream->bEndpointAddress & USB_DIR_IN) ? 0x10 : 0;
1072 stream->bEndpointAddress &= 0x0f;
1074 stream->ep->hcpriv = NULL;
1076 if (stream->rescheduled) {
1077 ehci_info (ehci, "ep%d%s-iso rescheduled "
1078 "%lu times in %lu seconds\n",
1079 stream->bEndpointAddress, is_in ? "in" : "out",
1080 stream->rescheduled,
1081 ((jiffies - stream->start)/HZ)
1089 static inline struct ehci_iso_stream *
1090 iso_stream_get (struct ehci_iso_stream *stream)
1092 if (likely (stream != NULL))
1097 static struct ehci_iso_stream *
1098 iso_stream_find (struct ehci_hcd *ehci, struct urb *urb)
1101 struct ehci_iso_stream *stream;
1102 struct usb_host_endpoint *ep;
1103 unsigned long flags;
1105 epnum = usb_pipeendpoint (urb->pipe);
1106 if (usb_pipein(urb->pipe))
1107 ep = urb->dev->ep_in[epnum];
1109 ep = urb->dev->ep_out[epnum];
1111 spin_lock_irqsave (&ehci->lock, flags);
1112 stream = ep->hcpriv;
1114 if (unlikely (stream == NULL)) {
1115 stream = iso_stream_alloc(GFP_ATOMIC);
1116 if (likely (stream != NULL)) {
1117 /* dev->ep owns the initial refcount */
1118 ep->hcpriv = stream;
1120 iso_stream_init(ehci, stream, urb->dev, urb->pipe,
1124 /* if dev->ep [epnum] is a QH, info1.maxpacket is nonzero */
1125 } else if (unlikely (stream->hw_info1 != 0)) {
1126 ehci_dbg (ehci, "dev %s ep%d%s, not iso??\n",
1127 urb->dev->devpath, epnum,
1128 usb_pipein(urb->pipe) ? "in" : "out");
1132 /* caller guarantees an eventual matching iso_stream_put */
1133 stream = iso_stream_get (stream);
1135 spin_unlock_irqrestore (&ehci->lock, flags);
1139 /*-------------------------------------------------------------------------*/
1141 /* ehci_iso_sched ops can be ITD-only or SITD-only */
1143 static struct ehci_iso_sched *
1144 iso_sched_alloc (unsigned packets, gfp_t mem_flags)
1146 struct ehci_iso_sched *iso_sched;
1147 int size = sizeof *iso_sched;
1149 size += packets * sizeof (struct ehci_iso_packet);
1150 iso_sched = kzalloc(size, mem_flags);
1151 if (likely (iso_sched != NULL)) {
1152 INIT_LIST_HEAD (&iso_sched->td_list);
1159 struct ehci_hcd *ehci,
1160 struct ehci_iso_sched *iso_sched,
1161 struct ehci_iso_stream *stream,
1166 dma_addr_t dma = urb->transfer_dma;
1168 /* how many uframes are needed for these transfers */
1169 iso_sched->span = urb->number_of_packets * stream->interval;
1171 /* figure out per-uframe itd fields that we'll need later
1172 * when we fit new itds into the schedule.
1174 for (i = 0; i < urb->number_of_packets; i++) {
1175 struct ehci_iso_packet *uframe = &iso_sched->packet [i];
1180 length = urb->iso_frame_desc [i].length;
1181 buf = dma + urb->iso_frame_desc [i].offset;
1183 trans = EHCI_ISOC_ACTIVE;
1184 trans |= buf & 0x0fff;
1185 if (unlikely (((i + 1) == urb->number_of_packets))
1186 && !(urb->transfer_flags & URB_NO_INTERRUPT))
1187 trans |= EHCI_ITD_IOC;
1188 trans |= length << 16;
1189 uframe->transaction = cpu_to_hc32(ehci, trans);
1191 /* might need to cross a buffer page within a uframe */
1192 uframe->bufp = (buf & ~(u64)0x0fff);
1194 if (unlikely ((uframe->bufp != (buf & ~(u64)0x0fff))))
1201 struct ehci_iso_stream *stream,
1202 struct ehci_iso_sched *iso_sched
1207 // caller must hold ehci->lock!
1208 list_splice (&iso_sched->td_list, &stream->free_list);
1213 itd_urb_transaction (
1214 struct ehci_iso_stream *stream,
1215 struct ehci_hcd *ehci,
1220 struct ehci_itd *itd;
1224 struct ehci_iso_sched *sched;
1225 unsigned long flags;
1227 sched = iso_sched_alloc (urb->number_of_packets, mem_flags);
1228 if (unlikely (sched == NULL))
1231 itd_sched_init(ehci, sched, stream, urb);
1233 if (urb->interval < 8)
1234 num_itds = 1 + (sched->span + 7) / 8;
1236 num_itds = urb->number_of_packets;
1238 /* allocate/init ITDs */
1239 spin_lock_irqsave (&ehci->lock, flags);
1240 for (i = 0; i < num_itds; i++) {
1242 /* free_list.next might be cache-hot ... but maybe
1243 * the HC caches it too. avoid that issue for now.
1246 /* prefer previously-allocated itds */
1247 if (likely (!list_empty(&stream->free_list))) {
1248 itd = list_entry (stream->free_list.prev,
1249 struct ehci_itd, itd_list);
1250 list_del (&itd->itd_list);
1251 itd_dma = itd->itd_dma;
1253 spin_unlock_irqrestore (&ehci->lock, flags);
1254 itd = dma_pool_alloc (ehci->itd_pool, mem_flags,
1256 spin_lock_irqsave (&ehci->lock, flags);
1258 iso_sched_free(stream, sched);
1259 spin_unlock_irqrestore(&ehci->lock, flags);
1264 memset (itd, 0, sizeof *itd);
1265 itd->itd_dma = itd_dma;
1266 list_add (&itd->itd_list, &sched->td_list);
1268 spin_unlock_irqrestore (&ehci->lock, flags);
1270 /* temporarily store schedule info in hcpriv */
1271 urb->hcpriv = sched;
1272 urb->error_count = 0;
1276 /*-------------------------------------------------------------------------*/
1280 struct ehci_hcd *ehci,
1289 /* can't commit more than 80% periodic == 100 usec */
1290 if (periodic_usecs (ehci, uframe >> 3, uframe & 0x7)
1294 /* we know urb->interval is 2^N uframes */
1296 } while (uframe < mod);
1302 struct ehci_hcd *ehci,
1304 struct ehci_iso_stream *stream,
1306 struct ehci_iso_sched *sched,
1313 mask = stream->raw_mask << (uframe & 7);
1315 /* for IN, don't wrap CSPLIT into the next frame */
1319 /* this multi-pass logic is simple, but performance may
1320 * suffer when the schedule data isn't cached.
1323 /* check bandwidth */
1324 uframe %= period_uframes;
1328 frame = uframe >> 3;
1331 #ifdef CONFIG_USB_EHCI_TT_NEWSCHED
1332 /* The tt's fullspeed bus bandwidth must be available.
1333 * tt_available scheduling guarantees 10+% for control/bulk.
1335 if (!tt_available (ehci, period_uframes << 3,
1336 stream->udev, frame, uf, stream->tt_usecs))
1339 /* tt must be idle for start(s), any gap, and csplit.
1340 * assume scheduling slop leaves 10+% for control/bulk.
1342 if (!tt_no_collision (ehci, period_uframes << 3,
1343 stream->udev, frame, mask))
1347 /* check starts (OUT uses more than one) */
1348 max_used = 100 - stream->usecs;
1349 for (tmp = stream->raw_mask & 0xff; tmp; tmp >>= 1, uf++) {
1350 if (periodic_usecs (ehci, frame, uf) > max_used)
1354 /* for IN, check CSPLIT */
1355 if (stream->c_usecs) {
1357 max_used = 100 - stream->c_usecs;
1361 if ((stream->raw_mask & tmp) == 0)
1363 if (periodic_usecs (ehci, frame, uf)
1369 /* we know urb->interval is 2^N uframes */
1370 uframe += period_uframes;
1371 } while (uframe < mod);
1373 stream->splits = cpu_to_hc32(ehci, stream->raw_mask << (uframe & 7));
1378 * This scheduler plans almost as far into the future as it has actual
1379 * periodic schedule slots. (Affected by TUNE_FLS, which defaults to
1380 * "as small as possible" to be cache-friendlier.) That limits the size
1381 * transfers you can stream reliably; avoid more than 64 msec per urb.
1382 * Also avoid queue depths of less than ehci's worst irq latency (affected
1383 * by the per-urb URB_NO_INTERRUPT hint, the log2_irq_thresh module parameter,
1384 * and other factors); or more than about 230 msec total (for portability,
1385 * given EHCI_TUNE_FLS and the slop). Or, write a smarter scheduler!
1388 #define SCHEDULE_SLOP 80 /* microframes */
1391 iso_stream_schedule (
1392 struct ehci_hcd *ehci,
1394 struct ehci_iso_stream *stream
1397 u32 now, next, start, period;
1399 unsigned mod = ehci->periodic_size << 3;
1400 struct ehci_iso_sched *sched = urb->hcpriv;
1401 struct pci_dev *pdev;
1403 if (sched->span > (mod - SCHEDULE_SLOP)) {
1404 ehci_dbg (ehci, "iso request %p too long\n", urb);
1409 if ((stream->depth + sched->span) > mod) {
1410 ehci_dbg (ehci, "request %p would overflow (%d+%d>%d)\n",
1411 urb, stream->depth, sched->span, mod);
1416 period = urb->interval;
1417 if (!stream->highspeed)
1420 now = ehci_readl(ehci, &ehci->regs->frame_index) % mod;
1422 /* Typical case: reuse current schedule, stream is still active.
1423 * Hopefully there are no gaps from the host falling behind
1424 * (irq delays etc), but if there are we'll take the next
1425 * slot in the schedule, implicitly assuming URB_ISO_ASAP.
1427 if (likely (!list_empty (&stream->td_list))) {
1428 pdev = to_pci_dev(ehci_to_hcd(ehci)->self.controller);
1429 start = stream->next_uframe;
1431 /* For high speed devices, allow scheduling within the
1432 * isochronous scheduling threshold. For full speed devices,
1433 * don't. (Work around for Intel ICH9 bug.)
1435 if (!stream->highspeed &&
1436 pdev->vendor == PCI_VENDOR_ID_INTEL)
1437 next = now + ehci->i_thresh;
1441 /* Fell behind (by up to twice the slop amount)? */
1442 if (((start - next) & (mod - 1)) >=
1443 mod - 2 * SCHEDULE_SLOP)
1444 start += period * DIV_ROUND_UP(
1445 (next - start) & (mod - 1),
1448 /* Tried to schedule too far into the future? */
1449 if (unlikely(((start - now) & (mod - 1)) + sched->span
1450 >= mod - 2 * SCHEDULE_SLOP)) {
1454 stream->next_uframe = start;
1458 /* need to schedule; when's the next (u)frame we could start?
1459 * this is bigger than ehci->i_thresh allows; scheduling itself
1460 * isn't free, the slop should handle reasonably slow cpus. it
1461 * can also help high bandwidth if the dma and irq loads don't
1462 * jump until after the queue is primed.
1464 start = SCHEDULE_SLOP + (now & ~0x07);
1466 stream->next_uframe = start;
1468 /* NOTE: assumes URB_ISO_ASAP, to limit complexity/bugs */
1470 /* find a uframe slot with enough bandwidth */
1471 for (; start < (stream->next_uframe + period); start++) {
1474 /* check schedule: enough space? */
1475 if (stream->highspeed)
1476 enough_space = itd_slot_ok (ehci, mod, start,
1477 stream->usecs, period);
1479 if ((start % 8) >= 6)
1481 enough_space = sitd_slot_ok (ehci, mod, stream,
1482 start, sched, period);
1485 /* schedule it here if there's enough bandwidth */
1487 stream->next_uframe = start % mod;
1492 /* no room in the schedule */
1493 ehci_dbg (ehci, "iso %ssched full %p (now %d max %d)\n",
1494 list_empty (&stream->td_list) ? "" : "re",
1495 urb, now, now + mod);
1499 iso_sched_free (stream, sched);
1504 /* report high speed start in uframes; full speed, in frames */
1505 urb->start_frame = stream->next_uframe;
1506 if (!stream->highspeed)
1507 urb->start_frame >>= 3;
1511 /*-------------------------------------------------------------------------*/
1514 itd_init(struct ehci_hcd *ehci, struct ehci_iso_stream *stream,
1515 struct ehci_itd *itd)
1519 /* it's been recently zeroed */
1520 itd->hw_next = EHCI_LIST_END(ehci);
1521 itd->hw_bufp [0] = stream->buf0;
1522 itd->hw_bufp [1] = stream->buf1;
1523 itd->hw_bufp [2] = stream->buf2;
1525 for (i = 0; i < 8; i++)
1528 /* All other fields are filled when scheduling */
1533 struct ehci_hcd *ehci,
1534 struct ehci_itd *itd,
1535 struct ehci_iso_sched *iso_sched,
1540 struct ehci_iso_packet *uf = &iso_sched->packet [index];
1541 unsigned pg = itd->pg;
1543 // BUG_ON (pg == 6 && uf->cross);
1546 itd->index [uframe] = index;
1548 itd->hw_transaction[uframe] = uf->transaction;
1549 itd->hw_transaction[uframe] |= cpu_to_hc32(ehci, pg << 12);
1550 itd->hw_bufp[pg] |= cpu_to_hc32(ehci, uf->bufp & ~(u32)0);
1551 itd->hw_bufp_hi[pg] |= cpu_to_hc32(ehci, (u32)(uf->bufp >> 32));
1553 /* iso_frame_desc[].offset must be strictly increasing */
1554 if (unlikely (uf->cross)) {
1555 u64 bufp = uf->bufp + 4096;
1558 itd->hw_bufp[pg] |= cpu_to_hc32(ehci, bufp & ~(u32)0);
1559 itd->hw_bufp_hi[pg] |= cpu_to_hc32(ehci, (u32)(bufp >> 32));
1564 itd_link (struct ehci_hcd *ehci, unsigned frame, struct ehci_itd *itd)
1566 /* always prepend ITD/SITD ... only QH tree is order-sensitive */
1567 itd->itd_next = ehci->pshadow [frame];
1568 itd->hw_next = ehci->periodic [frame];
1569 ehci->pshadow [frame].itd = itd;
1572 ehci->periodic[frame] = cpu_to_hc32(ehci, itd->itd_dma | Q_TYPE_ITD);
1575 /* fit urb's itds into the selected schedule slot; activate as needed */
1578 struct ehci_hcd *ehci,
1581 struct ehci_iso_stream *stream
1585 unsigned next_uframe, uframe, frame;
1586 struct ehci_iso_sched *iso_sched = urb->hcpriv;
1587 struct ehci_itd *itd;
1589 next_uframe = stream->next_uframe % mod;
1591 if (unlikely (list_empty(&stream->td_list))) {
1592 ehci_to_hcd(ehci)->self.bandwidth_allocated
1593 += stream->bandwidth;
1595 "schedule devp %s ep%d%s-iso period %d start %d.%d\n",
1596 urb->dev->devpath, stream->bEndpointAddress & 0x0f,
1597 (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out",
1599 next_uframe >> 3, next_uframe & 0x7);
1600 stream->start = jiffies;
1602 ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs++;
1604 /* fill iTDs uframe by uframe */
1605 for (packet = 0, itd = NULL; packet < urb->number_of_packets; ) {
1607 /* ASSERT: we have all necessary itds */
1608 // BUG_ON (list_empty (&iso_sched->td_list));
1610 /* ASSERT: no itds for this endpoint in this uframe */
1612 itd = list_entry (iso_sched->td_list.next,
1613 struct ehci_itd, itd_list);
1614 list_move_tail (&itd->itd_list, &stream->td_list);
1615 itd->stream = iso_stream_get (stream);
1617 itd_init (ehci, stream, itd);
1620 uframe = next_uframe & 0x07;
1621 frame = next_uframe >> 3;
1623 itd_patch(ehci, itd, iso_sched, packet, uframe);
1625 next_uframe += stream->interval;
1626 stream->depth += stream->interval;
1630 /* link completed itds into the schedule */
1631 if (((next_uframe >> 3) != frame)
1632 || packet == urb->number_of_packets) {
1633 itd_link (ehci, frame % ehci->periodic_size, itd);
1637 stream->next_uframe = next_uframe;
1639 /* don't need that schedule data any more */
1640 iso_sched_free (stream, iso_sched);
1643 timer_action (ehci, TIMER_IO_WATCHDOG);
1644 return enable_periodic(ehci);
1647 #define ISO_ERRS (EHCI_ISOC_BUF_ERR | EHCI_ISOC_BABBLE | EHCI_ISOC_XACTERR)
1649 /* Process and recycle a completed ITD. Return true iff its urb completed,
1650 * and hence its completion callback probably added things to the hardware
1653 * Note that we carefully avoid recycling this descriptor until after any
1654 * completion callback runs, so that it won't be reused quickly. That is,
1655 * assuming (a) no more than two urbs per frame on this endpoint, and also
1656 * (b) only this endpoint's completions submit URBs. It seems some silicon
1657 * corrupts things if you reuse completed descriptors very quickly...
1661 struct ehci_hcd *ehci,
1662 struct ehci_itd *itd
1664 struct urb *urb = itd->urb;
1665 struct usb_iso_packet_descriptor *desc;
1669 struct ehci_iso_stream *stream = itd->stream;
1670 struct usb_device *dev;
1671 unsigned retval = false;
1673 /* for each uframe with a packet */
1674 for (uframe = 0; uframe < 8; uframe++) {
1675 if (likely (itd->index[uframe] == -1))
1677 urb_index = itd->index[uframe];
1678 desc = &urb->iso_frame_desc [urb_index];
1680 t = hc32_to_cpup(ehci, &itd->hw_transaction [uframe]);
1681 itd->hw_transaction [uframe] = 0;
1682 stream->depth -= stream->interval;
1684 /* report transfer status */
1685 if (unlikely (t & ISO_ERRS)) {
1687 if (t & EHCI_ISOC_BUF_ERR)
1688 desc->status = usb_pipein (urb->pipe)
1689 ? -ENOSR /* hc couldn't read */
1690 : -ECOMM; /* hc couldn't write */
1691 else if (t & EHCI_ISOC_BABBLE)
1692 desc->status = -EOVERFLOW;
1693 else /* (t & EHCI_ISOC_XACTERR) */
1694 desc->status = -EPROTO;
1696 /* HC need not update length with this error */
1697 if (!(t & EHCI_ISOC_BABBLE)) {
1698 desc->actual_length = EHCI_ITD_LENGTH(t);
1699 urb->actual_length += desc->actual_length;
1701 } else if (likely ((t & EHCI_ISOC_ACTIVE) == 0)) {
1703 desc->actual_length = EHCI_ITD_LENGTH(t);
1704 urb->actual_length += desc->actual_length;
1706 /* URB was too late */
1707 desc->status = -EXDEV;
1711 /* handle completion now? */
1712 if (likely ((urb_index + 1) != urb->number_of_packets))
1715 /* ASSERT: it's really the last itd for this urb
1716 list_for_each_entry (itd, &stream->td_list, itd_list)
1717 BUG_ON (itd->urb == urb);
1720 /* give urb back to the driver; completion often (re)submits */
1722 ehci_urb_done(ehci, urb, 0);
1725 (void) disable_periodic(ehci);
1726 ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs--;
1728 if (unlikely(list_is_singular(&stream->td_list))) {
1729 ehci_to_hcd(ehci)->self.bandwidth_allocated
1730 -= stream->bandwidth;
1732 "deschedule devp %s ep%d%s-iso\n",
1733 dev->devpath, stream->bEndpointAddress & 0x0f,
1734 (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out");
1736 iso_stream_put (ehci, stream);
1740 if (ehci->clock_frame != itd->frame || itd->index[7] != -1) {
1741 /* OK to recycle this ITD now. */
1743 list_move(&itd->itd_list, &stream->free_list);
1744 iso_stream_put(ehci, stream);
1746 /* HW might remember this ITD, so we can't recycle it yet.
1747 * Move it to a safe place until a new frame starts.
1749 list_move(&itd->itd_list, &ehci->cached_itd_list);
1750 if (stream->refcount == 2) {
1751 /* If iso_stream_put() were called here, stream
1752 * would be freed. Instead, just prevent reuse.
1754 stream->ep->hcpriv = NULL;
1761 /*-------------------------------------------------------------------------*/
1763 static int itd_submit (struct ehci_hcd *ehci, struct urb *urb,
1766 int status = -EINVAL;
1767 unsigned long flags;
1768 struct ehci_iso_stream *stream;
1770 /* Get iso_stream head */
1771 stream = iso_stream_find (ehci, urb);
1772 if (unlikely (stream == NULL)) {
1773 ehci_dbg (ehci, "can't get iso stream\n");
1776 if (unlikely (urb->interval != stream->interval)) {
1777 ehci_dbg (ehci, "can't change iso interval %d --> %d\n",
1778 stream->interval, urb->interval);
1782 #ifdef EHCI_URB_TRACE
1784 "%s %s urb %p ep%d%s len %d, %d pkts %d uframes [%p]\n",
1785 __func__, urb->dev->devpath, urb,
1786 usb_pipeendpoint (urb->pipe),
1787 usb_pipein (urb->pipe) ? "in" : "out",
1788 urb->transfer_buffer_length,
1789 urb->number_of_packets, urb->interval,
1793 /* allocate ITDs w/o locking anything */
1794 status = itd_urb_transaction (stream, ehci, urb, mem_flags);
1795 if (unlikely (status < 0)) {
1796 ehci_dbg (ehci, "can't init itds\n");
1800 /* schedule ... need to lock */
1801 spin_lock_irqsave (&ehci->lock, flags);
1802 if (unlikely(!test_bit(HCD_FLAG_HW_ACCESSIBLE,
1803 &ehci_to_hcd(ehci)->flags))) {
1804 status = -ESHUTDOWN;
1805 goto done_not_linked;
1807 status = usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci), urb);
1808 if (unlikely(status))
1809 goto done_not_linked;
1810 status = iso_stream_schedule(ehci, urb, stream);
1811 if (likely (status == 0))
1812 itd_link_urb (ehci, urb, ehci->periodic_size << 3, stream);
1814 usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb);
1816 spin_unlock_irqrestore (&ehci->lock, flags);
1819 if (unlikely (status < 0))
1820 iso_stream_put (ehci, stream);
1824 /*-------------------------------------------------------------------------*/
1827 * "Split ISO TDs" ... used for USB 1.1 devices going through the
1828 * TTs in USB 2.0 hubs. These need microframe scheduling.
1833 struct ehci_hcd *ehci,
1834 struct ehci_iso_sched *iso_sched,
1835 struct ehci_iso_stream *stream,
1840 dma_addr_t dma = urb->transfer_dma;
1842 /* how many frames are needed for these transfers */
1843 iso_sched->span = urb->number_of_packets * stream->interval;
1845 /* figure out per-frame sitd fields that we'll need later
1846 * when we fit new sitds into the schedule.
1848 for (i = 0; i < urb->number_of_packets; i++) {
1849 struct ehci_iso_packet *packet = &iso_sched->packet [i];
1854 length = urb->iso_frame_desc [i].length & 0x03ff;
1855 buf = dma + urb->iso_frame_desc [i].offset;
1857 trans = SITD_STS_ACTIVE;
1858 if (((i + 1) == urb->number_of_packets)
1859 && !(urb->transfer_flags & URB_NO_INTERRUPT))
1861 trans |= length << 16;
1862 packet->transaction = cpu_to_hc32(ehci, trans);
1864 /* might need to cross a buffer page within a td */
1866 packet->buf1 = (buf + length) & ~0x0fff;
1867 if (packet->buf1 != (buf & ~(u64)0x0fff))
1870 /* OUT uses multiple start-splits */
1871 if (stream->bEndpointAddress & USB_DIR_IN)
1873 length = (length + 187) / 188;
1874 if (length > 1) /* BEGIN vs ALL */
1876 packet->buf1 |= length;
1881 sitd_urb_transaction (
1882 struct ehci_iso_stream *stream,
1883 struct ehci_hcd *ehci,
1888 struct ehci_sitd *sitd;
1889 dma_addr_t sitd_dma;
1891 struct ehci_iso_sched *iso_sched;
1892 unsigned long flags;
1894 iso_sched = iso_sched_alloc (urb->number_of_packets, mem_flags);
1895 if (iso_sched == NULL)
1898 sitd_sched_init(ehci, iso_sched, stream, urb);
1900 /* allocate/init sITDs */
1901 spin_lock_irqsave (&ehci->lock, flags);
1902 for (i = 0; i < urb->number_of_packets; i++) {
1904 /* NOTE: for now, we don't try to handle wraparound cases
1905 * for IN (using sitd->hw_backpointer, like a FSTN), which
1906 * means we never need two sitds for full speed packets.
1909 /* free_list.next might be cache-hot ... but maybe
1910 * the HC caches it too. avoid that issue for now.
1913 /* prefer previously-allocated sitds */
1914 if (!list_empty(&stream->free_list)) {
1915 sitd = list_entry (stream->free_list.prev,
1916 struct ehci_sitd, sitd_list);
1917 list_del (&sitd->sitd_list);
1918 sitd_dma = sitd->sitd_dma;
1920 spin_unlock_irqrestore (&ehci->lock, flags);
1921 sitd = dma_pool_alloc (ehci->sitd_pool, mem_flags,
1923 spin_lock_irqsave (&ehci->lock, flags);
1925 iso_sched_free(stream, iso_sched);
1926 spin_unlock_irqrestore(&ehci->lock, flags);
1931 memset (sitd, 0, sizeof *sitd);
1932 sitd->sitd_dma = sitd_dma;
1933 list_add (&sitd->sitd_list, &iso_sched->td_list);
1936 /* temporarily store schedule info in hcpriv */
1937 urb->hcpriv = iso_sched;
1938 urb->error_count = 0;
1940 spin_unlock_irqrestore (&ehci->lock, flags);
1944 /*-------------------------------------------------------------------------*/
1948 struct ehci_hcd *ehci,
1949 struct ehci_iso_stream *stream,
1950 struct ehci_sitd *sitd,
1951 struct ehci_iso_sched *iso_sched,
1955 struct ehci_iso_packet *uf = &iso_sched->packet [index];
1956 u64 bufp = uf->bufp;
1958 sitd->hw_next = EHCI_LIST_END(ehci);
1959 sitd->hw_fullspeed_ep = stream->address;
1960 sitd->hw_uframe = stream->splits;
1961 sitd->hw_results = uf->transaction;
1962 sitd->hw_backpointer = EHCI_LIST_END(ehci);
1965 sitd->hw_buf[0] = cpu_to_hc32(ehci, bufp);
1966 sitd->hw_buf_hi[0] = cpu_to_hc32(ehci, bufp >> 32);
1968 sitd->hw_buf[1] = cpu_to_hc32(ehci, uf->buf1);
1971 sitd->hw_buf_hi[1] = cpu_to_hc32(ehci, bufp >> 32);
1972 sitd->index = index;
1976 sitd_link (struct ehci_hcd *ehci, unsigned frame, struct ehci_sitd *sitd)
1978 /* note: sitd ordering could matter (CSPLIT then SSPLIT) */
1979 sitd->sitd_next = ehci->pshadow [frame];
1980 sitd->hw_next = ehci->periodic [frame];
1981 ehci->pshadow [frame].sitd = sitd;
1982 sitd->frame = frame;
1984 ehci->periodic[frame] = cpu_to_hc32(ehci, sitd->sitd_dma | Q_TYPE_SITD);
1987 /* fit urb's sitds into the selected schedule slot; activate as needed */
1990 struct ehci_hcd *ehci,
1993 struct ehci_iso_stream *stream
1997 unsigned next_uframe;
1998 struct ehci_iso_sched *sched = urb->hcpriv;
1999 struct ehci_sitd *sitd;
2001 next_uframe = stream->next_uframe;
2003 if (list_empty(&stream->td_list)) {
2004 /* usbfs ignores TT bandwidth */
2005 ehci_to_hcd(ehci)->self.bandwidth_allocated
2006 += stream->bandwidth;
2008 "sched devp %s ep%d%s-iso [%d] %dms/%04x\n",
2009 urb->dev->devpath, stream->bEndpointAddress & 0x0f,
2010 (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out",
2011 (next_uframe >> 3) % ehci->periodic_size,
2012 stream->interval, hc32_to_cpu(ehci, stream->splits));
2013 stream->start = jiffies;
2015 ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs++;
2017 /* fill sITDs frame by frame */
2018 for (packet = 0, sitd = NULL;
2019 packet < urb->number_of_packets;
2022 /* ASSERT: we have all necessary sitds */
2023 BUG_ON (list_empty (&sched->td_list));
2025 /* ASSERT: no itds for this endpoint in this frame */
2027 sitd = list_entry (sched->td_list.next,
2028 struct ehci_sitd, sitd_list);
2029 list_move_tail (&sitd->sitd_list, &stream->td_list);
2030 sitd->stream = iso_stream_get (stream);
2033 sitd_patch(ehci, stream, sitd, sched, packet);
2034 sitd_link (ehci, (next_uframe >> 3) % ehci->periodic_size,
2037 next_uframe += stream->interval << 3;
2038 stream->depth += stream->interval << 3;
2040 stream->next_uframe = next_uframe % mod;
2042 /* don't need that schedule data any more */
2043 iso_sched_free (stream, sched);
2046 timer_action (ehci, TIMER_IO_WATCHDOG);
2047 return enable_periodic(ehci);
2050 /*-------------------------------------------------------------------------*/
2052 #define SITD_ERRS (SITD_STS_ERR | SITD_STS_DBE | SITD_STS_BABBLE \
2053 | SITD_STS_XACT | SITD_STS_MMF)
2055 /* Process and recycle a completed SITD. Return true iff its urb completed,
2056 * and hence its completion callback probably added things to the hardware
2059 * Note that we carefully avoid recycling this descriptor until after any
2060 * completion callback runs, so that it won't be reused quickly. That is,
2061 * assuming (a) no more than two urbs per frame on this endpoint, and also
2062 * (b) only this endpoint's completions submit URBs. It seems some silicon
2063 * corrupts things if you reuse completed descriptors very quickly...
2067 struct ehci_hcd *ehci,
2068 struct ehci_sitd *sitd
2070 struct urb *urb = sitd->urb;
2071 struct usb_iso_packet_descriptor *desc;
2074 struct ehci_iso_stream *stream = sitd->stream;
2075 struct usb_device *dev;
2076 unsigned retval = false;
2078 urb_index = sitd->index;
2079 desc = &urb->iso_frame_desc [urb_index];
2080 t = hc32_to_cpup(ehci, &sitd->hw_results);
2082 /* report transfer status */
2083 if (t & SITD_ERRS) {
2085 if (t & SITD_STS_DBE)
2086 desc->status = usb_pipein (urb->pipe)
2087 ? -ENOSR /* hc couldn't read */
2088 : -ECOMM; /* hc couldn't write */
2089 else if (t & SITD_STS_BABBLE)
2090 desc->status = -EOVERFLOW;
2091 else /* XACT, MMF, etc */
2092 desc->status = -EPROTO;
2095 desc->actual_length = desc->length - SITD_LENGTH(t);
2096 urb->actual_length += desc->actual_length;
2098 stream->depth -= stream->interval << 3;
2100 /* handle completion now? */
2101 if ((urb_index + 1) != urb->number_of_packets)
2104 /* ASSERT: it's really the last sitd for this urb
2105 list_for_each_entry (sitd, &stream->td_list, sitd_list)
2106 BUG_ON (sitd->urb == urb);
2109 /* give urb back to the driver; completion often (re)submits */
2111 ehci_urb_done(ehci, urb, 0);
2114 (void) disable_periodic(ehci);
2115 ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs--;
2117 if (list_is_singular(&stream->td_list)) {
2118 ehci_to_hcd(ehci)->self.bandwidth_allocated
2119 -= stream->bandwidth;
2121 "deschedule devp %s ep%d%s-iso\n",
2122 dev->devpath, stream->bEndpointAddress & 0x0f,
2123 (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out");
2125 iso_stream_put (ehci, stream);
2126 /* OK to recycle this SITD now that its completion callback ran. */
2129 sitd->stream = NULL;
2130 list_move(&sitd->sitd_list, &stream->free_list);
2131 iso_stream_put(ehci, stream);
2137 static int sitd_submit (struct ehci_hcd *ehci, struct urb *urb,
2140 int status = -EINVAL;
2141 unsigned long flags;
2142 struct ehci_iso_stream *stream;
2144 /* Get iso_stream head */
2145 stream = iso_stream_find (ehci, urb);
2146 if (stream == NULL) {
2147 ehci_dbg (ehci, "can't get iso stream\n");
2150 if (urb->interval != stream->interval) {
2151 ehci_dbg (ehci, "can't change iso interval %d --> %d\n",
2152 stream->interval, urb->interval);
2156 #ifdef EHCI_URB_TRACE
2158 "submit %p dev%s ep%d%s-iso len %d\n",
2159 urb, urb->dev->devpath,
2160 usb_pipeendpoint (urb->pipe),
2161 usb_pipein (urb->pipe) ? "in" : "out",
2162 urb->transfer_buffer_length);
2165 /* allocate SITDs */
2166 status = sitd_urb_transaction (stream, ehci, urb, mem_flags);
2168 ehci_dbg (ehci, "can't init sitds\n");
2172 /* schedule ... need to lock */
2173 spin_lock_irqsave (&ehci->lock, flags);
2174 if (unlikely(!test_bit(HCD_FLAG_HW_ACCESSIBLE,
2175 &ehci_to_hcd(ehci)->flags))) {
2176 status = -ESHUTDOWN;
2177 goto done_not_linked;
2179 status = usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci), urb);
2180 if (unlikely(status))
2181 goto done_not_linked;
2182 status = iso_stream_schedule(ehci, urb, stream);
2184 sitd_link_urb (ehci, urb, ehci->periodic_size << 3, stream);
2186 usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb);
2188 spin_unlock_irqrestore (&ehci->lock, flags);
2192 iso_stream_put (ehci, stream);
2196 /*-------------------------------------------------------------------------*/
2198 static void free_cached_itd_list(struct ehci_hcd *ehci)
2200 struct ehci_itd *itd, *n;
2202 list_for_each_entry_safe(itd, n, &ehci->cached_itd_list, itd_list) {
2203 struct ehci_iso_stream *stream = itd->stream;
2205 list_move(&itd->itd_list, &stream->free_list);
2206 iso_stream_put(ehci, stream);
2210 /*-------------------------------------------------------------------------*/
2213 scan_periodic (struct ehci_hcd *ehci)
2215 unsigned now_uframe, frame, clock, clock_frame, mod;
2218 mod = ehci->periodic_size << 3;
2221 * When running, scan from last scan point up to "now"
2222 * else clean up by scanning everything that's left.
2223 * Touches as few pages as possible: cache-friendly.
2225 now_uframe = ehci->next_uframe;
2226 if (HC_IS_RUNNING(ehci_to_hcd(ehci)->state)) {
2227 clock = ehci_readl(ehci, &ehci->regs->frame_index);
2228 clock_frame = (clock >> 3) % ehci->periodic_size;
2230 clock = now_uframe + mod - 1;
2233 if (ehci->clock_frame != clock_frame) {
2234 free_cached_itd_list(ehci);
2235 ehci->clock_frame = clock_frame;
2238 clock_frame = clock >> 3;
2241 union ehci_shadow q, *q_p;
2243 unsigned incomplete = false;
2245 frame = now_uframe >> 3;
2248 /* scan each element in frame's queue for completions */
2249 q_p = &ehci->pshadow [frame];
2250 hw_p = &ehci->periodic [frame];
2252 type = Q_NEXT_TYPE(ehci, *hw_p);
2255 while (q.ptr != NULL) {
2257 union ehci_shadow temp;
2260 live = HC_IS_RUNNING (ehci_to_hcd(ehci)->state);
2261 switch (hc32_to_cpu(ehci, type)) {
2263 /* handle any completions */
2264 temp.qh = qh_get (q.qh);
2265 type = Q_NEXT_TYPE(ehci, q.qh->hw->hw_next);
2267 modified = qh_completions (ehci, temp.qh);
2268 if (unlikely(list_empty(&temp.qh->qtd_list) ||
2269 temp.qh->needs_rescan))
2270 intr_deschedule (ehci, temp.qh);
2274 /* for "save place" FSTNs, look at QH entries
2275 * in the previous frame for completions.
2277 if (q.fstn->hw_prev != EHCI_LIST_END(ehci)) {
2278 dbg ("ignoring completions from FSTNs");
2280 type = Q_NEXT_TYPE(ehci, q.fstn->hw_next);
2281 q = q.fstn->fstn_next;
2284 /* If this ITD is still active, leave it for
2285 * later processing ... check the next entry.
2286 * No need to check for activity unless the
2289 if (frame == clock_frame && live) {
2291 for (uf = 0; uf < 8; uf++) {
2292 if (q.itd->hw_transaction[uf] &
2298 q_p = &q.itd->itd_next;
2299 hw_p = &q.itd->hw_next;
2300 type = Q_NEXT_TYPE(ehci,
2307 /* Take finished ITDs out of the schedule
2308 * and process them: recycle, maybe report
2309 * URB completion. HC won't cache the
2310 * pointer for much longer, if at all.
2312 *q_p = q.itd->itd_next;
2313 *hw_p = q.itd->hw_next;
2314 type = Q_NEXT_TYPE(ehci, q.itd->hw_next);
2316 modified = itd_complete (ehci, q.itd);
2320 /* If this SITD is still active, leave it for
2321 * later processing ... check the next entry.
2322 * No need to check for activity unless the
2325 if (frame == clock_frame && live &&
2326 (q.sitd->hw_results &
2327 SITD_ACTIVE(ehci))) {
2329 q_p = &q.sitd->sitd_next;
2330 hw_p = &q.sitd->hw_next;
2331 type = Q_NEXT_TYPE(ehci,
2337 /* Take finished SITDs out of the schedule
2338 * and process them: recycle, maybe report
2341 *q_p = q.sitd->sitd_next;
2342 *hw_p = q.sitd->hw_next;
2343 type = Q_NEXT_TYPE(ehci, q.sitd->hw_next);
2345 modified = sitd_complete (ehci, q.sitd);
2349 dbg ("corrupt type %d frame %d shadow %p",
2350 type, frame, q.ptr);
2355 /* assume completion callbacks modify the queue */
2356 if (unlikely (modified)) {
2357 if (likely(ehci->periodic_sched > 0))
2359 /* short-circuit this scan */
2365 /* If we can tell we caught up to the hardware, stop now.
2366 * We can't advance our scan without collecting the ISO
2367 * transfers that are still pending in this frame.
2369 if (incomplete && HC_IS_RUNNING(ehci_to_hcd(ehci)->state)) {
2370 ehci->next_uframe = now_uframe;
2374 // FIXME: this assumes we won't get lapped when
2375 // latencies climb; that should be rare, but...
2376 // detect it, and just go all the way around.
2377 // FLR might help detect this case, so long as latencies
2378 // don't exceed periodic_size msec (default 1.024 sec).
2380 // FIXME: likewise assumes HC doesn't halt mid-scan
2382 if (now_uframe == clock) {
2385 if (!HC_IS_RUNNING (ehci_to_hcd(ehci)->state)
2386 || ehci->periodic_sched == 0)
2388 ehci->next_uframe = now_uframe;
2389 now = ehci_readl(ehci, &ehci->regs->frame_index) % mod;
2390 if (now_uframe == now)
2393 /* rescan the rest of this frame, then ... */
2395 clock_frame = clock >> 3;
2396 if (ehci->clock_frame != clock_frame) {
2397 free_cached_itd_list(ehci);
2398 ehci->clock_frame = clock_frame;