drivers/usb/host/ehci-tegra.c

   1 /*
   2  * EHCI-compliant USB host controller driver for NVIDIA Tegra SoCs
   3  *
   4  * Copyright (C) 2010 Google, Inc.
   5  * Copyright (C) 2009 NVIDIA Corporation
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License as published by the
   9  * Free Software Foundation; either version 2 of the License, or (at your
  10  * option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  */
  18
  19 #include <linux/clk.h>
  20 #include <linux/err.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/platform_data/tegra_usb.h>
  23 #include <linux/irq.h>
  24 #include <linux/usb/otg.h>
  25 #include <linux/gpio.h>
  26 #include <linux/of.h>
  27 #include <linux/of_gpio.h>
  28 #include <linux/pm_runtime.h>
  29
  30 #include <linux/usb/tegra_usb_phy.h>
  31
  32 #define TEGRA_USB_BASE                  0xC5000000
  33 #define TEGRA_USB2_BASE                 0xC5004000
  34 #define TEGRA_USB3_BASE                 0xC5008000
  35
  36 #define TEGRA_USB_DMA_ALIGN 32
  37
  38 struct tegra_ehci_hcd {
  39         struct ehci_hcd *ehci;
  40         struct tegra_usb_phy *phy;
  41         struct clk *clk;
  42         struct clk *emc_clk;
  43         struct usb_phy *transceiver;
  44         int host_resumed;
  45         int port_resuming;
  46         enum tegra_usb_phy_port_speed port_speed;
  47 };
  48
  49 static void tegra_ehci_power_up(struct usb_hcd *hcd)
  50 {
  51         struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
  52
  53         clk_prepare_enable(tegra->emc_clk);
  54         clk_prepare_enable(tegra->clk);
  55         usb_phy_set_suspend(&tegra->phy->u_phy, 0);
  56         tegra->host_resumed = 1;
  57 }
  58
  59 static void tegra_ehci_power_down(struct usb_hcd *hcd)
  60 {
  61         struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
  62
  63         tegra->host_resumed = 0;
  64         usb_phy_set_suspend(&tegra->phy->u_phy, 1);
  65         clk_disable_unprepare(tegra->clk);
  66         clk_disable_unprepare(tegra->emc_clk);
  67 }
  68
  69 static int tegra_ehci_internal_port_reset(
  70         struct ehci_hcd *ehci,
  71         u32 __iomem     *portsc_reg
  72 )
  73 {
  74         u32             temp;
  75         unsigned long   flags;
  76         int             retval = 0;
  77         int             i, tries;
  78         u32             saved_usbintr;
  79
  80         spin_lock_irqsave(&ehci->lock, flags);
  81         saved_usbintr = ehci_readl(ehci, &ehci->regs->intr_enable);
  82         /* disable USB interrupt */
  83         ehci_writel(ehci, 0, &ehci->regs->intr_enable);
  84         spin_unlock_irqrestore(&ehci->lock, flags);
  85
  86         /*
  87          * Here we have to do Port Reset at most twice for
  88          * Port Enable bit to be set.
  89          */
  90         for (i = 0; i < 2; i++) {
  91                 temp = ehci_readl(ehci, portsc_reg);
  92                 temp |= PORT_RESET;
  93                 ehci_writel(ehci, temp, portsc_reg);
  94                 mdelay(10);
  95                 temp &= ~PORT_RESET;
  96                 ehci_writel(ehci, temp, portsc_reg);
  97                 mdelay(1);
  98                 tries = 100;
  99                 do {
 100                         mdelay(1);
 101                         /*
 102                          * Up to this point, Port Enable bit is
 103                          * expected to be set after 2 ms waiting.
 104                          * USB1 usually takes extra 45 ms, for safety,
 105                          * we take 100 ms as timeout.
 106                          */
 107                         temp = ehci_readl(ehci, portsc_reg);
 108                 } while (!(temp & PORT_PE) && tries--);
 109                 if (temp & PORT_PE)
 110                         break;
 111         }
 112         if (i == 2)
 113                 retval = -ETIMEDOUT;
 114
 115         /*
 116          * Clear Connect Status Change bit if it's set.
 117          * We can't clear PORT_PEC. It will also cause PORT_PE to be cleared.
 118          */
 119         if (temp & PORT_CSC)
 120                 ehci_writel(ehci, PORT_CSC, portsc_reg);
 121
 122         /*
 123          * Write to clear any interrupt status bits that might be set
 124          * during port reset.
 125          */
 126         temp = ehci_readl(ehci, &ehci->regs->status);
 127         ehci_writel(ehci, temp, &ehci->regs->status);
 128
 129         /* restore original interrupt enable bits */
 130         ehci_writel(ehci, saved_usbintr, &ehci->regs->intr_enable);
 131         return retval;
 132 }
 133
 134 static int tegra_ehci_hub_control(
 135         struct usb_hcd  *hcd,
 136         u16             typeReq,
 137         u16             wValue,
 138         u16             wIndex,
 139         char            *buf,
 140         u16             wLength
 141 )
 142 {
 143         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
 144         struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
 145         u32 __iomem     *status_reg;
 146         u32             temp;
 147         unsigned long   flags;
 148         int             retval = 0;
 149
 150         status_reg = &ehci->regs->port_status[(wIndex & 0xff) - 1];
 151
 152         spin_lock_irqsave(&ehci->lock, flags);
 153
 154         if (typeReq == GetPortStatus) {
 155                 temp = ehci_readl(ehci, status_reg);
 156                 if (tegra->port_resuming && !(temp & PORT_SUSPEND)) {
 157                         /* Resume completed, re-enable disconnect detection */
 158                         tegra->port_resuming = 0;
 159                         tegra_usb_phy_postresume(tegra->phy);
 160                 }
 161         }
 162
 163         else if (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_SUSPEND) {
 164                 temp = ehci_readl(ehci, status_reg);
 165                 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) != 0) {
 166                         retval = -EPIPE;
 167                         goto done;
 168                 }
 169
 170                 temp &= ~(PORT_RWC_BITS | PORT_WKCONN_E);
 171                 temp |= PORT_WKDISC_E | PORT_WKOC_E;
 172                 ehci_writel(ehci, temp | PORT_SUSPEND, status_reg);
 173
 174                 /*
 175                  * If a transaction is in progress, there may be a delay in
 176                  * suspending the port. Poll until the port is suspended.
 177                  */
 178                 if (handshake(ehci, status_reg, PORT_SUSPEND,
 179                                                 PORT_SUSPEND, 5000))
 180                         pr_err("%s: timeout waiting for SUSPEND\n", __func__);
 181
 182                 set_bit((wIndex & 0xff) - 1, &ehci->suspended_ports);
 183                 goto done;
 184         }
 185
 186         /* For USB1 port we need to issue Port Reset twice internally */
 187         if (tegra->phy->instance == 0 &&
 188            (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_RESET)) {
 189                 spin_unlock_irqrestore(&ehci->lock, flags);
 190                 return tegra_ehci_internal_port_reset(ehci, status_reg);
 191         }
 192
 193         /*
 194          * Tegra host controller will time the resume operation to clear the bit
 195          * when the port control state switches to HS or FS Idle. This behavior
 196          * is different from EHCI where the host controller driver is required
 197          * to set this bit to a zero after the resume duration is timed in the
 198          * driver.
 199          */
 200         else if (typeReq == ClearPortFeature &&
 201                                         wValue == USB_PORT_FEAT_SUSPEND) {
 202                 temp = ehci_readl(ehci, status_reg);
 203                 if ((temp & PORT_RESET) || !(temp & PORT_PE)) {
 204                         retval = -EPIPE;
 205                         goto done;
 206                 }
 207
 208                 if (!(temp & PORT_SUSPEND))
 209                         goto done;
 210
 211                 /* Disable disconnect detection during port resume */
 212                 tegra_usb_phy_preresume(tegra->phy);
 213
 214                 ehci->reset_done[wIndex-1] = jiffies + msecs_to_jiffies(25);
 215
 216                 temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
 217                 /* start resume signalling */
 218                 ehci_writel(ehci, temp | PORT_RESUME, status_reg);
 219                 set_bit(wIndex-1, &ehci->resuming_ports);
 220
 221                 spin_unlock_irqrestore(&ehci->lock, flags);
 222                 msleep(20);
 223                 spin_lock_irqsave(&ehci->lock, flags);
 224
 225                 /* Poll until the controller clears RESUME and SUSPEND */
 226                 if (handshake(ehci, status_reg, PORT_RESUME, 0, 2000))
 227                         pr_err("%s: timeout waiting for RESUME\n", __func__);
 228                 if (handshake(ehci, status_reg, PORT_SUSPEND, 0, 2000))
 229                         pr_err("%s: timeout waiting for SUSPEND\n", __func__);
 230
 231                 ehci->reset_done[wIndex-1] = 0;
 232                 clear_bit(wIndex-1, &ehci->resuming_ports);
 233
 234                 tegra->port_resuming = 1;
 235                 goto done;
 236         }
 237
 238         spin_unlock_irqrestore(&ehci->lock, flags);
 239
 240         /* Handle the hub control events here */
 241         return ehci_hub_control(hcd, typeReq, wValue, wIndex, buf, wLength);
 242 done:
 243         spin_unlock_irqrestore(&ehci->lock, flags);
 244         return retval;
 245 }
 246
 247 static void tegra_ehci_restart(struct usb_hcd *hcd)
 248 {
 249         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
 250
 251         ehci_reset(ehci);
 252
 253         /* setup the frame list and Async q heads */
 254         ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list);
 255         ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next);
 256         /* setup the command register and set the controller in RUN mode */
 257         ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
 258         ehci->command |= CMD_RUN;
 259         ehci_writel(ehci, ehci->command, &ehci->regs->command);
 260
 261         down_write(&ehci_cf_port_reset_rwsem);
 262         ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
 263         /* flush posted writes */
 264         ehci_readl(ehci, &ehci->regs->command);
 265         up_write(&ehci_cf_port_reset_rwsem);
 266 }
 267
 268 static void tegra_ehci_shutdown(struct usb_hcd *hcd)
 269 {
 270         struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
 271
 272         /* ehci_shutdown touches the USB controller registers, make sure
 273          * controller has clocks to it */
 274         if (!tegra->host_resumed)
 275                 tegra_ehci_power_up(hcd);
 276
 277         ehci_shutdown(hcd);
 278 }
 279
 280 static int tegra_ehci_setup(struct usb_hcd *hcd)
 281 {
 282         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
 283         int retval;
 284
 285         /* EHCI registers start at offset 0x100 */
 286         ehci->caps = hcd->regs + 0x100;
 287
 288         /* switch to host mode */
 289         hcd->has_tt = 1;
 290
 291         retval = ehci_setup(hcd);
 292         if (retval)
 293                 return retval;
 294
 295         ehci_port_power(ehci, 1);
 296         return retval;
 297 }
 298
 299 struct dma_aligned_buffer {
 300         void *kmalloc_ptr;
 301         void *old_xfer_buffer;
 302         u8 data[0];
 303 };
 304
 305 static void free_dma_aligned_buffer(struct urb *urb)
 306 {
 307         struct dma_aligned_buffer *temp;
 308
 309         if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER))
 310                 return;
 311
 312         temp = container_of(urb->transfer_buffer,
 313                 struct dma_aligned_buffer, data);
 314
 315         if (usb_urb_dir_in(urb))
 316                 memcpy(temp->old_xfer_buffer, temp->data,
 317                        urb->transfer_buffer_length);
 318         urb->transfer_buffer = temp->old_xfer_buffer;
 319         kfree(temp->kmalloc_ptr);
 320
 321         urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER;
 322 }
 323
 324 static int alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags)
 325 {
 326         struct dma_aligned_buffer *temp, *kmalloc_ptr;
 327         size_t kmalloc_size;
 328
 329         if (urb->num_sgs || urb->sg ||
 330             urb->transfer_buffer_length == 0 ||
 331             !((uintptr_t)urb->transfer_buffer & (TEGRA_USB_DMA_ALIGN - 1)))
 332                 return 0;
 333
 334         /* Allocate a buffer with enough padding for alignment */
 335         kmalloc_size = urb->transfer_buffer_length +
 336                 sizeof(struct dma_aligned_buffer) + TEGRA_USB_DMA_ALIGN - 1;
 337
 338         kmalloc_ptr = kmalloc(kmalloc_size, mem_flags);
 339         if (!kmalloc_ptr)
 340                 return -ENOMEM;
 341
 342         /* Position our struct dma_aligned_buffer such that data is aligned */
 343         temp = PTR_ALIGN(kmalloc_ptr + 1, TEGRA_USB_DMA_ALIGN) - 1;
 344         temp->kmalloc_ptr = kmalloc_ptr;
 345         temp->old_xfer_buffer = urb->transfer_buffer;
 346         if (usb_urb_dir_out(urb))
 347                 memcpy(temp->data, urb->transfer_buffer,
 348                        urb->transfer_buffer_length);
 349         urb->transfer_buffer = temp->data;
 350
 351         urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER;
 352
 353         return 0;
 354 }
 355
 356 static int tegra_ehci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
 357                                       gfp_t mem_flags)
 358 {
 359         int ret;
 360
 361         ret = alloc_dma_aligned_buffer(urb, mem_flags);
 362         if (ret)
 363                 return ret;
 364
 365         ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
 366         if (ret)
 367                 free_dma_aligned_buffer(urb);
 368
 369         return ret;
 370 }
 371
 372 static void tegra_ehci_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
 373 {
 374         usb_hcd_unmap_urb_for_dma(hcd, urb);
 375         free_dma_aligned_buffer(urb);
 376 }
 377
 378 static const struct hc_driver tegra_ehci_hc_driver = {
 379         .description            = hcd_name,
 380         .product_desc           = "Tegra EHCI Host Controller",
 381         .hcd_priv_size          = sizeof(struct ehci_hcd),
 382         .flags                  = HCD_USB2 | HCD_MEMORY,
 383
 384         /* standard ehci functions */
 385         .irq                    = ehci_irq,
 386         .start                  = ehci_run,
 387         .stop                   = ehci_stop,
 388         .urb_enqueue            = ehci_urb_enqueue,
 389         .urb_dequeue            = ehci_urb_dequeue,
 390         .endpoint_disable       = ehci_endpoint_disable,
 391         .endpoint_reset         = ehci_endpoint_reset,
 392         .get_frame_number       = ehci_get_frame,
 393         .hub_status_data        = ehci_hub_status_data,
 394         .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
 395         .relinquish_port        = ehci_relinquish_port,
 396         .port_handed_over       = ehci_port_handed_over,
 397
 398         /* modified ehci functions for tegra */
 399         .reset                  = tegra_ehci_setup,
 400         .shutdown               = tegra_ehci_shutdown,
 401         .map_urb_for_dma        = tegra_ehci_map_urb_for_dma,
 402         .unmap_urb_for_dma      = tegra_ehci_unmap_urb_for_dma,
 403         .hub_control            = tegra_ehci_hub_control,
 404 #ifdef CONFIG_PM
 405         .bus_suspend            = ehci_bus_suspend,
 406         .bus_resume             = ehci_bus_resume,
 407 #endif
 408 };
 409
 410 static int setup_vbus_gpio(struct platform_device *pdev,
 411                            struct tegra_ehci_platform_data *pdata)
 412 {
 413         int err = 0;
 414         int gpio;
 415
 416         gpio = pdata->vbus_gpio;
 417         if (!gpio_is_valid(gpio))
 418                 gpio = of_get_named_gpio(pdev->dev.of_node,
 419                                          "nvidia,vbus-gpio", 0);
 420         if (!gpio_is_valid(gpio))
 421                 return 0;
 422
 423         err = gpio_request(gpio, "vbus_gpio");
 424         if (err) {
 425                 dev_err(&pdev->dev, "can't request vbus gpio %d", gpio);
 426                 return err;
 427         }
 428         err = gpio_direction_output(gpio, 1);
 429         if (err) {
 430                 dev_err(&pdev->dev, "can't enable vbus\n");
 431                 return err;
 432         }
 433
 434         return err;
 435 }
 436
 437 #ifdef CONFIG_PM
 438
 439 static int controller_suspend(struct device *dev)
 440 {
 441         struct tegra_ehci_hcd *tegra =
 442                         platform_get_drvdata(to_platform_device(dev));
 443         struct ehci_hcd *ehci = tegra->ehci;
 444         struct usb_hcd *hcd = ehci_to_hcd(ehci);
 445         struct ehci_regs __iomem *hw = ehci->regs;
 446         unsigned long flags;
 447
 448         if (time_before(jiffies, ehci->next_statechange))
 449                 msleep(10);
 450
 451         ehci_halt(ehci);
 452
 453         spin_lock_irqsave(&ehci->lock, flags);
 454         tegra->port_speed = (readl(&hw->port_status[0]) >> 26) & 0x3;
 455         clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
 456         spin_unlock_irqrestore(&ehci->lock, flags);
 457
 458         tegra_ehci_power_down(hcd);
 459         return 0;
 460 }
 461
 462 static int controller_resume(struct device *dev)
 463 {
 464         struct tegra_ehci_hcd *tegra =
 465                         platform_get_drvdata(to_platform_device(dev));
 466         struct ehci_hcd *ehci = tegra->ehci;
 467         struct usb_hcd *hcd = ehci_to_hcd(ehci);
 468         struct ehci_regs __iomem *hw = ehci->regs;
 469         unsigned long val;
 470
 471         set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
 472         tegra_ehci_power_up(hcd);
 473
 474         if (tegra->port_speed > TEGRA_USB_PHY_PORT_SPEED_HIGH) {
 475                 /* Wait for the phy to detect new devices
 476                  * before we restart the controller */
 477                 msleep(10);
 478                 goto restart;
 479         }
 480
 481         /* Force the phy to keep data lines in suspend state */
 482         tegra_ehci_phy_restore_start(tegra->phy, tegra->port_speed);
 483
 484         /* Enable host mode */
 485         tdi_reset(ehci);
 486
 487         /* Enable Port Power */
 488         val = readl(&hw->port_status[0]);
 489         val |= PORT_POWER;
 490         writel(val, &hw->port_status[0]);
 491         udelay(10);
 492
 493         /* Check if the phy resume from LP0. When the phy resume from LP0
 494          * USB register will be reset. */
 495         if (!readl(&hw->async_next)) {
 496                 /* Program the field PTC based on the saved speed mode */
 497                 val = readl(&hw->port_status[0]);
 498                 val &= ~PORT_TEST(~0);
 499                 if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_HIGH)
 500                         val |= PORT_TEST_FORCE;
 501                 else if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_FULL)
 502                         val |= PORT_TEST(6);
 503                 else if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW)
 504                         val |= PORT_TEST(7);
 505                 writel(val, &hw->port_status[0]);
 506                 udelay(10);
 507
 508                 /* Disable test mode by setting PTC field to NORMAL_OP */
 509                 val = readl(&hw->port_status[0]);
 510                 val &= ~PORT_TEST(~0);
 511                 writel(val, &hw->port_status[0]);
 512                 udelay(10);
 513         }
 514
 515         /* Poll until CCS is enabled */
 516         if (handshake(ehci, &hw->port_status[0], PORT_CONNECT,
 517                                                  PORT_CONNECT, 2000)) {
 518                 pr_err("%s: timeout waiting for PORT_CONNECT\n", __func__);
 519                 goto restart;
 520         }
 521
 522         /* Poll until PE is enabled */
 523         if (handshake(ehci, &hw->port_status[0], PORT_PE,
 524                                                  PORT_PE, 2000)) {
 525                 pr_err("%s: timeout waiting for USB_PORTSC1_PE\n", __func__);
 526                 goto restart;
 527         }
 528
 529         /* Clear the PCI status, to avoid an interrupt taken upon resume */
 530         val = readl(&hw->status);
 531         val |= STS_PCD;
 532         writel(val, &hw->status);
 533
 534         /* Put controller in suspend mode by writing 1 to SUSP bit of PORTSC */
 535         val = readl(&hw->port_status[0]);
 536         if ((val & PORT_POWER) && (val & PORT_PE)) {
 537                 val |= PORT_SUSPEND;
 538                 writel(val, &hw->port_status[0]);
 539
 540                 /* Wait until port suspend completes */
 541                 if (handshake(ehci, &hw->port_status[0], PORT_SUSPEND,
 542                                                          PORT_SUSPEND, 1000)) {
 543                         pr_err("%s: timeout waiting for PORT_SUSPEND\n",
 544                                                                 __func__);
 545                         goto restart;
 546                 }
 547         }
 548
 549         tegra_ehci_phy_restore_end(tegra->phy);
 550         goto done;
 551
 552  restart:
 553         if (tegra->port_speed <= TEGRA_USB_PHY_PORT_SPEED_HIGH)
 554                 tegra_ehci_phy_restore_end(tegra->phy);
 555
 556         tegra_ehci_restart(hcd);
 557
 558  done:
 559         tegra_usb_phy_preresume(tegra->phy);
 560         tegra->port_resuming = 1;
 561         return 0;
 562 }
 563
 564 static int tegra_ehci_suspend(struct device *dev)
 565 {
 566         struct tegra_ehci_hcd *tegra =
 567                         platform_get_drvdata(to_platform_device(dev));
 568         struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci);
 569         int rc = 0;
 570
 571         /*
 572          * When system sleep is supported and USB controller wakeup is
 573          * implemented: If the controller is runtime-suspended and the
 574          * wakeup setting needs to be changed, call pm_runtime_resume().
 575          */
 576         if (HCD_HW_ACCESSIBLE(hcd))
 577                 rc = controller_suspend(dev);
 578         return rc;
 579 }
 580
 581 static int tegra_ehci_resume(struct device *dev)
 582 {
 583         int rc;
 584
 585         rc = controller_resume(dev);
 586         if (rc == 0) {
 587                 pm_runtime_disable(dev);
 588                 pm_runtime_set_active(dev);
 589                 pm_runtime_enable(dev);
 590         }
 591         return rc;
 592 }
 593
 594 static int tegra_ehci_runtime_suspend(struct device *dev)
 595 {
 596         return controller_suspend(dev);
 597 }
 598
 599 static int tegra_ehci_runtime_resume(struct device *dev)
 600 {
 601         return controller_resume(dev);
 602 }
 603
 604 static const struct dev_pm_ops tegra_ehci_pm_ops = {
 605         .suspend        = tegra_ehci_suspend,
 606         .resume         = tegra_ehci_resume,
 607         .runtime_suspend = tegra_ehci_runtime_suspend,
 608         .runtime_resume = tegra_ehci_runtime_resume,
 609 };
 610
 611 #endif
 612
 613 static u64 tegra_ehci_dma_mask = DMA_BIT_MASK(32);
 614
 615 static int tegra_ehci_probe(struct platform_device *pdev)
 616 {
 617         struct resource *res;
 618         struct usb_hcd *hcd;
 619         struct tegra_ehci_hcd *tegra;
 620         struct tegra_ehci_platform_data *pdata;
 621         int err = 0;
 622         int irq;
 623         int instance = pdev->id;
 624
 625         pdata = pdev->dev.platform_data;
 626         if (!pdata) {
 627                 dev_err(&pdev->dev, "Platform data missing\n");
 628                 return -EINVAL;
 629         }
 630
 631         /* Right now device-tree probed devices don't get dma_mask set.
 632          * Since shared usb code relies on it, set it here for now.
 633          * Once we have dma capability bindings this can go away.
 634          */
 635         if (!pdev->dev.dma_mask)
 636                 pdev->dev.dma_mask = &tegra_ehci_dma_mask;
 637
 638         setup_vbus_gpio(pdev, pdata);
 639
 640         tegra = devm_kzalloc(&pdev->dev, sizeof(struct tegra_ehci_hcd),
 641                              GFP_KERNEL);
 642         if (!tegra)
 643                 return -ENOMEM;
 644
 645         hcd = usb_create_hcd(&tegra_ehci_hc_driver, &pdev->dev,
 646                                         dev_name(&pdev->dev));
 647         if (!hcd) {
 648                 dev_err(&pdev->dev, "Unable to create HCD\n");
 649                 return -ENOMEM;
 650         }
 651
 652         platform_set_drvdata(pdev, tegra);
 653
 654         tegra->clk = devm_clk_get(&pdev->dev, NULL);
 655         if (IS_ERR(tegra->clk)) {
 656                 dev_err(&pdev->dev, "Can't get ehci clock\n");
 657                 err = PTR_ERR(tegra->clk);
 658                 goto fail_clk;
 659         }
 660
 661         err = clk_prepare_enable(tegra->clk);
 662         if (err)
 663                 goto fail_clk;
 664
 665         tegra->emc_clk = devm_clk_get(&pdev->dev, "emc");
 666         if (IS_ERR(tegra->emc_clk)) {
 667                 dev_err(&pdev->dev, "Can't get emc clock\n");
 668                 err = PTR_ERR(tegra->emc_clk);
 669                 goto fail_emc_clk;
 670         }
 671
 672         clk_prepare_enable(tegra->emc_clk);
 673         clk_set_rate(tegra->emc_clk, 400000000);
 674
 675         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 676         if (!res) {
 677                 dev_err(&pdev->dev, "Failed to get I/O memory\n");
 678                 err = -ENXIO;
 679                 goto fail_io;
 680         }
 681         hcd->rsrc_start = res->start;
 682         hcd->rsrc_len = resource_size(res);
 683         hcd->regs = devm_ioremap(&pdev->dev, res->start, resource_size(res));
 684         if (!hcd->regs) {
 685                 dev_err(&pdev->dev, "Failed to remap I/O memory\n");
 686                 err = -ENOMEM;
 687                 goto fail_io;
 688         }
 689
 690         /* This is pretty ugly and needs to be fixed when we do only
 691          * device-tree probing. Old code relies on the platform_device
 692          * numbering that we lack for device-tree-instantiated devices.
 693          */
 694         if (instance < 0) {
 695                 switch (res->start) {
 696                 case TEGRA_USB_BASE:
 697                         instance = 0;
 698                         break;
 699                 case TEGRA_USB2_BASE:
 700                         instance = 1;
 701                         break;
 702                 case TEGRA_USB3_BASE:
 703                         instance = 2;
 704                         break;
 705                 default:
 706                         err = -ENODEV;
 707                         dev_err(&pdev->dev, "unknown usb instance\n");
 708                         goto fail_io;
 709                 }
 710         }
 711
 712         tegra->phy = tegra_usb_phy_open(&pdev->dev, instance, hcd->regs,
 713                                         pdata->phy_config,
 714                                         TEGRA_USB_PHY_MODE_HOST);
 715         if (IS_ERR(tegra->phy)) {
 716                 dev_err(&pdev->dev, "Failed to open USB phy\n");
 717                 err = -ENXIO;
 718                 goto fail_io;
 719         }
 720
 721         usb_phy_init(&tegra->phy->u_phy);
 722
 723         err = usb_phy_set_suspend(&tegra->phy->u_phy, 0);
 724         if (err) {
 725                 dev_err(&pdev->dev, "Failed to power on the phy\n");
 726                 goto fail;
 727         }
 728
 729         tegra->host_resumed = 1;
 730         tegra->ehci = hcd_to_ehci(hcd);
 731
 732         irq = platform_get_irq(pdev, 0);
 733         if (!irq) {
 734                 dev_err(&pdev->dev, "Failed to get IRQ\n");
 735                 err = -ENODEV;
 736                 goto fail;
 737         }
 738
 739 #ifdef CONFIG_USB_OTG_UTILS
 740         if (pdata->operating_mode == TEGRA_USB_OTG) {
 741                 tegra->transceiver =
 742                         devm_usb_get_phy(&pdev->dev, USB_PHY_TYPE_USB2);
 743                 if (!IS_ERR_OR_NULL(tegra->transceiver))
 744                         otg_set_host(tegra->transceiver->otg, &hcd->self);
 745         }
 746 #endif
 747
 748         err = usb_add_hcd(hcd, irq, IRQF_SHARED);
 749         if (err) {
 750                 dev_err(&pdev->dev, "Failed to add USB HCD\n");
 751                 goto fail;
 752         }
 753
 754         pm_runtime_set_active(&pdev->dev);
 755         pm_runtime_get_noresume(&pdev->dev);
 756
 757         /* Don't skip the pm_runtime_forbid call if wakeup isn't working */
 758         /* if (!pdata->power_down_on_bus_suspend) */
 759                 pm_runtime_forbid(&pdev->dev);
 760         pm_runtime_enable(&pdev->dev);
 761         pm_runtime_put_sync(&pdev->dev);
 762         return err;
 763
 764 fail:
 765 #ifdef CONFIG_USB_OTG_UTILS
 766         if (!IS_ERR_OR_NULL(tegra->transceiver))
 767                 otg_set_host(tegra->transceiver->otg, NULL);
 768 #endif
 769         usb_phy_shutdown(&tegra->phy->u_phy);
 770 fail_io:
 771         clk_disable_unprepare(tegra->emc_clk);
 772 fail_emc_clk:
 773         clk_disable_unprepare(tegra->clk);
 774 fail_clk:
 775         usb_put_hcd(hcd);
 776         return err;
 777 }
 778
 779 static int tegra_ehci_remove(struct platform_device *pdev)
 780 {
 781         struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev);
 782         struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci);
 783
 784         if (tegra == NULL || hcd == NULL)
 785                 return -EINVAL;
 786
 787         pm_runtime_get_sync(&pdev->dev);
 788         pm_runtime_disable(&pdev->dev);
 789         pm_runtime_put_noidle(&pdev->dev);
 790
 791 #ifdef CONFIG_USB_OTG_UTILS
 792         if (!IS_ERR_OR_NULL(tegra->transceiver))
 793                 otg_set_host(tegra->transceiver->otg, NULL);
 794 #endif
 795
 796         usb_remove_hcd(hcd);
 797         usb_put_hcd(hcd);
 798
 799         usb_phy_shutdown(&tegra->phy->u_phy);
 800
 801         clk_disable_unprepare(tegra->clk);
 802
 803         clk_disable_unprepare(tegra->emc_clk);
 804
 805         return 0;
 806 }
 807
 808 static void tegra_ehci_hcd_shutdown(struct platform_device *pdev)
 809 {
 810         struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev);
 811         struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci);
 812
 813         if (hcd->driver->shutdown)
 814                 hcd->driver->shutdown(hcd);
 815 }
 816
 817 static struct of_device_id tegra_ehci_of_match[] __devinitdata = {
 818         { .compatible = "nvidia,tegra20-ehci", },
 819         { },
 820 };
 821
 822 static struct platform_driver tegra_ehci_driver = {
 823         .probe          = tegra_ehci_probe,
 824         .remove         = tegra_ehci_remove,
 825         .shutdown       = tegra_ehci_hcd_shutdown,
 826         .driver         = {
 827                 .name   = "tegra-ehci",
 828                 .of_match_table = tegra_ehci_of_match,
 829 #ifdef CONFIG_PM
 830                 .pm     = &tegra_ehci_pm_ops,
 831 #endif
 832         }
 833 };