2 * EHCI-compliant USB host controller driver for NVIDIA Tegra SoCs
4 * Copyright (C) 2010 Google, Inc.
5 * Copyright (C) 2009 - 2013 NVIDIA Corporation
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 #include <linux/clk.h>
20 #include <linux/clk/tegra.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/err.h>
23 #include <linux/gpio.h>
25 #include <linux/irq.h>
26 #include <linux/module.h>
28 #include <linux/of_gpio.h>
29 #include <linux/platform_device.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/slab.h>
32 #include <linux/usb/ehci_def.h>
33 #include <linux/usb/tegra_usb_phy.h>
34 #include <linux/usb.h>
35 #include <linux/usb/hcd.h>
36 #include <linux/usb/otg.h>
40 #define TEGRA_USB_BASE 0xC5000000
41 #define TEGRA_USB2_BASE 0xC5004000
42 #define TEGRA_USB3_BASE 0xC5008000
44 #define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E)
46 #define TEGRA_USB_DMA_ALIGN 32
48 #define DRIVER_DESC "Tegra EHCI driver"
49 #define DRV_NAME "tegra-ehci"
51 static struct hc_driver __read_mostly tegra_ehci_hc_driver;
53 static int (*orig_hub_control)(struct usb_hcd *hcd,
54 u16 typeReq, u16 wValue, u16 wIndex,
55 char *buf, u16 wLength);
57 struct tegra_ehci_hcd {
58 struct tegra_usb_phy *phy;
61 bool needs_double_reset;
62 enum tegra_usb_phy_port_speed port_speed;
65 static int tegra_ehci_internal_port_reset(
66 struct ehci_hcd *ehci,
67 u32 __iomem *portsc_reg
76 spin_lock_irqsave(&ehci->lock, flags);
77 saved_usbintr = ehci_readl(ehci, &ehci->regs->intr_enable);
78 /* disable USB interrupt */
79 ehci_writel(ehci, 0, &ehci->regs->intr_enable);
80 spin_unlock_irqrestore(&ehci->lock, flags);
83 * Here we have to do Port Reset at most twice for
84 * Port Enable bit to be set.
86 for (i = 0; i < 2; i++) {
87 temp = ehci_readl(ehci, portsc_reg);
89 ehci_writel(ehci, temp, portsc_reg);
92 ehci_writel(ehci, temp, portsc_reg);
98 * Up to this point, Port Enable bit is
99 * expected to be set after 2 ms waiting.
100 * USB1 usually takes extra 45 ms, for safety,
101 * we take 100 ms as timeout.
103 temp = ehci_readl(ehci, portsc_reg);
104 } while (!(temp & PORT_PE) && tries--);
112 * Clear Connect Status Change bit if it's set.
113 * We can't clear PORT_PEC. It will also cause PORT_PE to be cleared.
116 ehci_writel(ehci, PORT_CSC, portsc_reg);
119 * Write to clear any interrupt status bits that might be set
122 temp = ehci_readl(ehci, &ehci->regs->status);
123 ehci_writel(ehci, temp, &ehci->regs->status);
125 /* restore original interrupt enable bits */
126 ehci_writel(ehci, saved_usbintr, &ehci->regs->intr_enable);
130 static int tegra_ehci_hub_control(
139 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
140 struct tegra_ehci_hcd *tegra = (struct tegra_ehci_hcd *)ehci->priv;
141 u32 __iomem *status_reg;
146 status_reg = &ehci->regs->port_status[(wIndex & 0xff) - 1];
148 spin_lock_irqsave(&ehci->lock, flags);
150 if (typeReq == GetPortStatus) {
151 temp = ehci_readl(ehci, status_reg);
152 if (tegra->port_resuming && !(temp & PORT_SUSPEND)) {
153 /* Resume completed, re-enable disconnect detection */
154 tegra->port_resuming = 0;
155 tegra_usb_phy_postresume(hcd->phy);
159 else if (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_SUSPEND) {
160 temp = ehci_readl(ehci, status_reg);
161 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) != 0) {
166 temp &= ~(PORT_RWC_BITS | PORT_WKCONN_E);
167 temp |= PORT_WKDISC_E | PORT_WKOC_E;
168 ehci_writel(ehci, temp | PORT_SUSPEND, status_reg);
171 * If a transaction is in progress, there may be a delay in
172 * suspending the port. Poll until the port is suspended.
174 if (ehci_handshake(ehci, status_reg, PORT_SUSPEND,
176 pr_err("%s: timeout waiting for SUSPEND\n", __func__);
178 set_bit((wIndex & 0xff) - 1, &ehci->suspended_ports);
182 /* For USB1 port we need to issue Port Reset twice internally */
183 if (tegra->needs_double_reset &&
184 (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_RESET)) {
185 spin_unlock_irqrestore(&ehci->lock, flags);
186 return tegra_ehci_internal_port_reset(ehci, status_reg);
190 * Tegra host controller will time the resume operation to clear the bit
191 * when the port control state switches to HS or FS Idle. This behavior
192 * is different from EHCI where the host controller driver is required
193 * to set this bit to a zero after the resume duration is timed in the
196 else if (typeReq == ClearPortFeature &&
197 wValue == USB_PORT_FEAT_SUSPEND) {
198 temp = ehci_readl(ehci, status_reg);
199 if ((temp & PORT_RESET) || !(temp & PORT_PE)) {
204 if (!(temp & PORT_SUSPEND))
207 /* Disable disconnect detection during port resume */
208 tegra_usb_phy_preresume(hcd->phy);
210 ehci->reset_done[wIndex-1] = jiffies + msecs_to_jiffies(25);
212 temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
213 /* start resume signalling */
214 ehci_writel(ehci, temp | PORT_RESUME, status_reg);
215 set_bit(wIndex-1, &ehci->resuming_ports);
217 spin_unlock_irqrestore(&ehci->lock, flags);
219 spin_lock_irqsave(&ehci->lock, flags);
221 /* Poll until the controller clears RESUME and SUSPEND */
222 if (ehci_handshake(ehci, status_reg, PORT_RESUME, 0, 2000))
223 pr_err("%s: timeout waiting for RESUME\n", __func__);
224 if (ehci_handshake(ehci, status_reg, PORT_SUSPEND, 0, 2000))
225 pr_err("%s: timeout waiting for SUSPEND\n", __func__);
227 ehci->reset_done[wIndex-1] = 0;
228 clear_bit(wIndex-1, &ehci->resuming_ports);
230 tegra->port_resuming = 1;
234 spin_unlock_irqrestore(&ehci->lock, flags);
236 /* Handle the hub control events here */
237 return orig_hub_control(hcd, typeReq, wValue, wIndex, buf, wLength);
240 spin_unlock_irqrestore(&ehci->lock, flags);
244 struct dma_aligned_buffer {
246 void *old_xfer_buffer;
250 static void free_dma_aligned_buffer(struct urb *urb)
252 struct dma_aligned_buffer *temp;
254 if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER))
257 temp = container_of(urb->transfer_buffer,
258 struct dma_aligned_buffer, data);
260 if (usb_urb_dir_in(urb))
261 memcpy(temp->old_xfer_buffer, temp->data,
262 urb->transfer_buffer_length);
263 urb->transfer_buffer = temp->old_xfer_buffer;
264 kfree(temp->kmalloc_ptr);
266 urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER;
269 static int alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags)
271 struct dma_aligned_buffer *temp, *kmalloc_ptr;
274 if (urb->num_sgs || urb->sg ||
275 urb->transfer_buffer_length == 0 ||
276 !((uintptr_t)urb->transfer_buffer & (TEGRA_USB_DMA_ALIGN - 1)))
279 /* Allocate a buffer with enough padding for alignment */
280 kmalloc_size = urb->transfer_buffer_length +
281 sizeof(struct dma_aligned_buffer) + TEGRA_USB_DMA_ALIGN - 1;
283 kmalloc_ptr = kmalloc(kmalloc_size, mem_flags);
287 /* Position our struct dma_aligned_buffer such that data is aligned */
288 temp = PTR_ALIGN(kmalloc_ptr + 1, TEGRA_USB_DMA_ALIGN) - 1;
289 temp->kmalloc_ptr = kmalloc_ptr;
290 temp->old_xfer_buffer = urb->transfer_buffer;
291 if (usb_urb_dir_out(urb))
292 memcpy(temp->data, urb->transfer_buffer,
293 urb->transfer_buffer_length);
294 urb->transfer_buffer = temp->data;
296 urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER;
301 static int tegra_ehci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
306 ret = alloc_dma_aligned_buffer(urb, mem_flags);
310 ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
312 free_dma_aligned_buffer(urb);
317 static void tegra_ehci_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
319 usb_hcd_unmap_urb_for_dma(hcd, urb);
320 free_dma_aligned_buffer(urb);
323 static int tegra_ehci_probe(struct platform_device *pdev)
325 struct resource *res;
327 struct ehci_hcd *ehci;
328 struct tegra_ehci_hcd *tegra;
331 struct device_node *np_phy;
332 struct usb_phy *u_phy;
334 /* Right now device-tree probed devices don't get dma_mask set.
335 * Since shared usb code relies on it, set it here for now.
336 * Once we have dma capability bindings this can go away.
338 if (!pdev->dev.dma_mask)
339 pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
340 if (!pdev->dev.coherent_dma_mask)
341 pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
343 hcd = usb_create_hcd(&tegra_ehci_hc_driver, &pdev->dev,
344 dev_name(&pdev->dev));
346 dev_err(&pdev->dev, "Unable to create HCD\n");
349 platform_set_drvdata(pdev, hcd);
350 ehci = hcd_to_ehci(hcd);
351 tegra = (struct tegra_ehci_hcd *)ehci->priv;
355 tegra->clk = devm_clk_get(&pdev->dev, NULL);
356 if (IS_ERR(tegra->clk)) {
357 dev_err(&pdev->dev, "Can't get ehci clock\n");
358 err = PTR_ERR(tegra->clk);
359 goto cleanup_hcd_create;
362 err = clk_prepare_enable(tegra->clk);
364 goto cleanup_clk_get;
366 tegra_periph_reset_assert(tegra->clk);
368 tegra_periph_reset_deassert(tegra->clk);
370 np_phy = of_parse_phandle(pdev->dev.of_node, "nvidia,phy", 0);
376 u_phy = tegra_usb_get_phy(np_phy);
378 err = PTR_ERR(u_phy);
383 tegra->needs_double_reset = of_property_read_bool(pdev->dev.of_node,
384 "nvidia,needs-double-reset");
386 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
388 dev_err(&pdev->dev, "Failed to get I/O memory\n");
392 hcd->rsrc_start = res->start;
393 hcd->rsrc_len = resource_size(res);
394 hcd->regs = devm_ioremap(&pdev->dev, res->start, resource_size(res));
396 dev_err(&pdev->dev, "Failed to remap I/O memory\n");
400 ehci->caps = hcd->regs + 0x100;
402 err = usb_phy_init(hcd->phy);
404 dev_err(&pdev->dev, "Failed to initialize phy\n");
408 u_phy->otg = devm_kzalloc(&pdev->dev, sizeof(struct usb_otg),
411 dev_err(&pdev->dev, "Failed to alloc memory for otg\n");
415 u_phy->otg->host = hcd_to_bus(hcd);
417 err = usb_phy_set_suspend(hcd->phy, 0);
419 dev_err(&pdev->dev, "Failed to power on the phy\n");
423 irq = platform_get_irq(pdev, 0);
425 dev_err(&pdev->dev, "Failed to get IRQ\n");
430 otg_set_host(u_phy->otg, &hcd->self);
432 err = usb_add_hcd(hcd, irq, IRQF_SHARED);
434 dev_err(&pdev->dev, "Failed to add USB HCD\n");
435 goto cleanup_otg_set_host;
440 cleanup_otg_set_host:
441 otg_set_host(u_phy->otg, NULL);
443 usb_phy_shutdown(hcd->phy);
445 clk_disable_unprepare(tegra->clk);
453 static int tegra_ehci_remove(struct platform_device *pdev)
455 struct usb_hcd *hcd = platform_get_drvdata(pdev);
456 struct tegra_ehci_hcd *tegra =
457 (struct tegra_ehci_hcd *)hcd_to_ehci(hcd)->priv;
459 otg_set_host(hcd->phy->otg, NULL);
461 usb_phy_shutdown(hcd->phy);
465 clk_disable_unprepare(tegra->clk);
470 static void tegra_ehci_hcd_shutdown(struct platform_device *pdev)
472 struct usb_hcd *hcd = platform_get_drvdata(pdev);
474 if (hcd->driver->shutdown)
475 hcd->driver->shutdown(hcd);
478 static struct of_device_id tegra_ehci_of_match[] = {
479 { .compatible = "nvidia,tegra20-ehci", },
483 static struct platform_driver tegra_ehci_driver = {
484 .probe = tegra_ehci_probe,
485 .remove = tegra_ehci_remove,
486 .shutdown = tegra_ehci_hcd_shutdown,
489 .of_match_table = tegra_ehci_of_match,
493 static const struct ehci_driver_overrides tegra_overrides __initconst = {
494 .extra_priv_size = sizeof(struct tegra_ehci_hcd),
497 static int __init ehci_tegra_init(void)
502 pr_info(DRV_NAME ": " DRIVER_DESC "\n");
504 ehci_init_driver(&tegra_ehci_hc_driver, &tegra_overrides);
507 * The Tegra HW has some unusual quirks, which require Tegra-specific
508 * workarounds. We override certain hc_driver functions here to
509 * achieve that. We explicitly do not enhance ehci_driver_overrides to
510 * allow this more easily, since this is an unusual case, and we don't
511 * want to encourage others to override these functions by making it
515 orig_hub_control = tegra_ehci_hc_driver.hub_control;
517 tegra_ehci_hc_driver.map_urb_for_dma = tegra_ehci_map_urb_for_dma;
518 tegra_ehci_hc_driver.unmap_urb_for_dma = tegra_ehci_unmap_urb_for_dma;
519 tegra_ehci_hc_driver.hub_control = tegra_ehci_hub_control;
521 return platform_driver_register(&tegra_ehci_driver);
523 module_init(ehci_tegra_init);
525 static void __exit ehci_tegra_cleanup(void)
527 platform_driver_unregister(&tegra_ehci_driver);
529 module_exit(ehci_tegra_cleanup);
531 MODULE_DESCRIPTION(DRIVER_DESC);
532 MODULE_LICENSE("GPL");
533 MODULE_ALIAS("platform:" DRV_NAME);
534 MODULE_DEVICE_TABLE(of, tegra_ehci_of_match);