drivers/usb/host/isp1760-hcd.c

   1 /*
   2  * Driver for the NXP ISP1760 chip
   3  *
   4  * However, the code might contain some bugs. What doesn't work for sure is:
   5  * - ISO
   6  * - OTG
   7  e The interrupt line is configured as active low, level.
   8  *
   9  * (c) 2007 Sebastian Siewior <bigeasy@linutronix.de>
  10  *
  11  * (c) 2011 Arvid Brodin <arvid.brodin@enea.com>
  12  *
  13  */
  14 #include <linux/module.h>
  15 #include <linux/kernel.h>
  16 #include <linux/slab.h>
  17 #include <linux/list.h>
  18 #include <linux/usb.h>
  19 #include <linux/usb/hcd.h>
  20 #include <linux/debugfs.h>
  21 #include <linux/uaccess.h>
  22 #include <linux/io.h>
  23 #include <linux/mm.h>
  24 #include <asm/unaligned.h>
  25 #include <asm/cacheflush.h>
  26
  27 #include "isp1760-hcd.h"
  28
  29 static struct kmem_cache *qtd_cachep;
  30 static struct kmem_cache *qh_cachep;
  31 static struct kmem_cache *urb_listitem_cachep;
  32
  33 struct isp1760_hcd {
  34         u32 hcs_params;
  35         spinlock_t              lock;
  36         struct slotinfo         atl_slots[32];
  37         struct slotinfo         int_slots[32];
  38         struct memory_chunk memory_pool[BLOCKS];
  39         struct list_head        controlqhs, bulkqhs, interruptqhs;
  40         int active_ptds;
  41
  42         /* periodic schedule support */
  43 #define DEFAULT_I_TDPS          1024
  44         unsigned                periodic_size;
  45         unsigned                i_thresh;
  46         unsigned long           reset_done;
  47         unsigned long           next_statechange;
  48         unsigned int            devflags;
  49 };
  50
  51 static inline struct isp1760_hcd *hcd_to_priv(struct usb_hcd *hcd)
  52 {
  53         return (struct isp1760_hcd *) (hcd->hcd_priv);
  54 }
  55
  56 /* Section 2.2 Host Controller Capability Registers */
  57 #define HC_LENGTH(p)            (((p)>>00)&0x00ff)      /* bits 7:0 */
  58 #define HC_VERSION(p)           (((p)>>16)&0xffff)      /* bits 31:16 */
  59 #define HCS_INDICATOR(p)        ((p)&(1 << 16)) /* true: has port indicators */
  60 #define HCS_PPC(p)              ((p)&(1 << 4))  /* true: port power control */
  61 #define HCS_N_PORTS(p)          (((p)>>0)&0xf)  /* bits 3:0, ports on HC */
  62 #define HCC_ISOC_CACHE(p)       ((p)&(1 << 7))  /* true: can cache isoc frame */
  63 #define HCC_ISOC_THRES(p)       (((p)>>4)&0x7)  /* bits 6:4, uframes cached */
  64
  65 /* Section 2.3 Host Controller Operational Registers */
  66 #define CMD_LRESET      (1<<7)          /* partial reset (no ports, etc) */
  67 #define CMD_RESET       (1<<1)          /* reset HC not bus */
  68 #define CMD_RUN         (1<<0)          /* start/stop HC */
  69 #define STS_PCD         (1<<2)          /* port change detect */
  70 #define FLAG_CF         (1<<0)          /* true: we'll support "high speed" */
  71
  72 #define PORT_OWNER      (1<<13)         /* true: companion hc owns this port */
  73 #define PORT_POWER      (1<<12)         /* true: has power (see PPC) */
  74 #define PORT_USB11(x) (((x) & (3 << 10)) == (1 << 10))  /* USB 1.1 device */
  75 #define PORT_RESET      (1<<8)          /* reset port */
  76 #define PORT_SUSPEND    (1<<7)          /* suspend port */
  77 #define PORT_RESUME     (1<<6)          /* resume it */
  78 #define PORT_PE         (1<<2)          /* port enable */
  79 #define PORT_CSC        (1<<1)          /* connect status change */
  80 #define PORT_CONNECT    (1<<0)          /* device connected */
  81 #define PORT_RWC_BITS   (PORT_CSC)
  82
  83 struct isp1760_qtd {
  84         u8 packet_type;
  85         void *data_buffer;
  86         u32 payload_addr;
  87
  88         /* the rest is HCD-private */
  89         struct list_head qtd_list;
  90         struct urb *urb;
  91         size_t length;
  92         size_t actual_length;
  93
  94         /* QTD_ENQUEUED:        waiting for transfer (inactive) */
  95         /* QTD_PAYLOAD_ALLOC:   chip mem has been allocated for payload */
  96         /* QTD_XFER_STARTED:    valid ptd has been written to isp176x - only
  97                                 interrupt handler may touch this qtd! */
  98         /* QTD_XFER_COMPLETE:   payload has been transferred successfully */
  99         /* QTD_RETIRE:          transfer error/abort qtd */
 100 #define QTD_ENQUEUED            0
 101 #define QTD_PAYLOAD_ALLOC       1
 102 #define QTD_XFER_STARTED        2
 103 #define QTD_XFER_COMPLETE       3
 104 #define QTD_RETIRE              4
 105         u32 status;
 106 };
 107
 108 /* Queue head, one for each active endpoint */
 109 struct isp1760_qh {
 110         struct list_head qh_list;
 111         struct list_head qtd_list;
 112         u32 toggle;
 113         u32 ping;
 114         int slot;
 115 };
 116
 117 struct urb_listitem {
 118         struct list_head urb_list;
 119         struct urb *urb;
 120 };
 121
 122 /*
 123  * Access functions for isp176x registers (addresses 0..0x03FF).
 124  */
 125 static u32 reg_read32(void __iomem *base, u32 reg)
 126 {
 127         return readl(base + reg);
 128 }
 129
 130 static void reg_write32(void __iomem *base, u32 reg, u32 val)
 131 {
 132         writel(val, base + reg);
 133 }
 134
 135 /*
 136  * Access functions for isp176x memory (offset >= 0x0400).
 137  *
 138  * bank_reads8() reads memory locations prefetched by an earlier write to
 139  * HC_MEMORY_REG (see isp176x datasheet). Unless you want to do fancy multi-
 140  * bank optimizations, you should use the more generic mem_reads8() below.
 141  *
 142  * For access to ptd memory, use the specialized ptd_read() and ptd_write()
 143  * below.
 144  *
 145  * These functions copy via MMIO data to/from the device. memcpy_{to|from}io()
 146  * doesn't quite work because some people have to enforce 32-bit access
 147  */
 148 static void bank_reads8(void __iomem *src_base, u32 src_offset, u32 bank_addr,
 149                                                         __u32 *dst, u32 bytes)
 150 {
 151         __u32 __iomem *src;
 152         u32 val;
 153         __u8 *src_byteptr;
 154         __u8 *dst_byteptr;
 155
 156         src = src_base + (bank_addr | src_offset);
 157
 158         if (src_offset < PAYLOAD_OFFSET) {
 159                 while (bytes >= 4) {
 160                         *dst = le32_to_cpu(__raw_readl(src));
 161                         bytes -= 4;
 162                         src++;
 163                         dst++;
 164                 }
 165         } else {
 166                 while (bytes >= 4) {
 167                         *dst = __raw_readl(src);
 168                         bytes -= 4;
 169                         src++;
 170                         dst++;
 171                 }
 172         }
 173
 174         if (!bytes)
 175                 return;
 176
 177         /* in case we have 3, 2 or 1 by left. The dst buffer may not be fully
 178          * allocated.
 179          */
 180         if (src_offset < PAYLOAD_OFFSET)
 181                 val = le32_to_cpu(__raw_readl(src));
 182         else
 183                 val = __raw_readl(src);
 184
 185         dst_byteptr = (void *) dst;
 186         src_byteptr = (void *) &val;
 187         while (bytes > 0) {
 188                 *dst_byteptr = *src_byteptr;
 189                 dst_byteptr++;
 190                 src_byteptr++;
 191                 bytes--;
 192         }
 193 }
 194
 195 static void mem_reads8(void __iomem *src_base, u32 src_offset, void *dst,
 196                                                                 u32 bytes)
 197 {
 198         reg_write32(src_base, HC_MEMORY_REG, src_offset + ISP_BANK(0));
 199         ndelay(90);
 200         bank_reads8(src_base, src_offset, ISP_BANK(0), dst, bytes);
 201 }
 202
 203 static void mem_writes8(void __iomem *dst_base, u32 dst_offset,
 204                                                 __u32 const *src, u32 bytes)
 205 {
 206         __u32 __iomem *dst;
 207
 208         dst = dst_base + dst_offset;
 209
 210         if (dst_offset < PAYLOAD_OFFSET) {
 211                 while (bytes >= 4) {
 212                         __raw_writel(cpu_to_le32(*src), dst);
 213                         bytes -= 4;
 214                         src++;
 215                         dst++;
 216                 }
 217         } else {
 218                 while (bytes >= 4) {
 219                         __raw_writel(*src, dst);
 220                         bytes -= 4;
 221                         src++;
 222                         dst++;
 223                 }
 224         }
 225
 226         if (!bytes)
 227                 return;
 228         /* in case we have 3, 2 or 1 bytes left. The buffer is allocated and the
 229          * extra bytes should not be read by the HW.
 230          */
 231
 232         if (dst_offset < PAYLOAD_OFFSET)
 233                 __raw_writel(cpu_to_le32(*src), dst);
 234         else
 235                 __raw_writel(*src, dst);
 236 }
 237
 238 /*
 239  * Read and write ptds. 'ptd_offset' should be one of ISO_PTD_OFFSET,
 240  * INT_PTD_OFFSET, and ATL_PTD_OFFSET. 'slot' should be less than 32.
 241  */
 242 static void ptd_read(void __iomem *base, u32 ptd_offset, u32 slot,
 243                                                                 struct ptd *ptd)
 244 {
 245         reg_write32(base, HC_MEMORY_REG,
 246                                 ISP_BANK(0) + ptd_offset + slot*sizeof(*ptd));
 247         ndelay(90);
 248         bank_reads8(base, ptd_offset + slot*sizeof(*ptd), ISP_BANK(0),
 249                                                 (void *) ptd, sizeof(*ptd));
 250 }
 251
 252 static void ptd_write(void __iomem *base, u32 ptd_offset, u32 slot,
 253                                                                 struct ptd *ptd)
 254 {
 255         mem_writes8(base, ptd_offset + slot*sizeof(*ptd) + sizeof(ptd->dw0),
 256                                                 &ptd->dw1, 7*sizeof(ptd->dw1));
 257         /* Make sure dw0 gets written last (after other dw's and after payload)
 258            since it contains the enable bit */
 259         wmb();
 260         mem_writes8(base, ptd_offset + slot*sizeof(*ptd), &ptd->dw0,
 261                                                         sizeof(ptd->dw0));
 262 }
 263
 264
 265 /* memory management of the 60kb on the chip from 0x1000 to 0xffff */
 266 static void init_memory(struct isp1760_hcd *priv)
 267 {
 268         int i, curr;
 269         u32 payload_addr;
 270
 271         payload_addr = PAYLOAD_OFFSET;
 272         for (i = 0; i < BLOCK_1_NUM; i++) {
 273                 priv->memory_pool[i].start = payload_addr;
 274                 priv->memory_pool[i].size = BLOCK_1_SIZE;
 275                 priv->memory_pool[i].free = 1;
 276                 payload_addr += priv->memory_pool[i].size;
 277         }
 278
 279         curr = i;
 280         for (i = 0; i < BLOCK_2_NUM; i++) {
 281                 priv->memory_pool[curr + i].start = payload_addr;
 282                 priv->memory_pool[curr + i].size = BLOCK_2_SIZE;
 283                 priv->memory_pool[curr + i].free = 1;
 284                 payload_addr += priv->memory_pool[curr + i].size;
 285         }
 286
 287         curr = i;
 288         for (i = 0; i < BLOCK_3_NUM; i++) {
 289                 priv->memory_pool[curr + i].start = payload_addr;
 290                 priv->memory_pool[curr + i].size = BLOCK_3_SIZE;
 291                 priv->memory_pool[curr + i].free = 1;
 292                 payload_addr += priv->memory_pool[curr + i].size;
 293         }
 294
 295         WARN_ON(payload_addr - priv->memory_pool[0].start > PAYLOAD_AREA_SIZE);
 296 }
 297
 298 static void alloc_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd)
 299 {
 300         struct isp1760_hcd *priv = hcd_to_priv(hcd);
 301         int i;
 302
 303         WARN_ON(qtd->payload_addr);
 304
 305         if (!qtd->length)
 306                 return;
 307
 308         for (i = 0; i < BLOCKS; i++) {
 309                 if (priv->memory_pool[i].size >= qtd->length &&
 310                                 priv->memory_pool[i].free) {
 311                         priv->memory_pool[i].free = 0;
 312                         qtd->payload_addr = priv->memory_pool[i].start;
 313                         return;
 314                 }
 315         }
 316 }
 317
 318 static void free_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd)
 319 {
 320         struct isp1760_hcd *priv = hcd_to_priv(hcd);
 321         int i;
 322
 323         if (!qtd->payload_addr)
 324                 return;
 325
 326         for (i = 0; i < BLOCKS; i++) {
 327                 if (priv->memory_pool[i].start == qtd->payload_addr) {
 328                         WARN_ON(priv->memory_pool[i].free);
 329                         priv->memory_pool[i].free = 1;
 330                         qtd->payload_addr = 0;
 331                         return;
 332                 }
 333         }
 334
 335         dev_err(hcd->self.controller, "%s: Invalid pointer: %08x\n",
 336                                                 __func__, qtd->payload_addr);
 337         WARN_ON(1);
 338         qtd->payload_addr = 0;
 339 }
 340
 341 static int handshake(struct usb_hcd *hcd, u32 reg,
 342                       u32 mask, u32 done, int usec)
 343 {
 344         u32 result;
 345
 346         do {
 347                 result = reg_read32(hcd->regs, reg);
 348                 if (result == ~0)
 349                         return -ENODEV;
 350                 result &= mask;
 351                 if (result == done)
 352                         return 0;
 353                 udelay(1);
 354                 usec--;
 355         } while (usec > 0);
 356         return -ETIMEDOUT;
 357 }
 358
 359 /* reset a non-running (STS_HALT == 1) controller */
 360 static int ehci_reset(struct usb_hcd *hcd)
 361 {
 362         int retval;
 363         struct isp1760_hcd *priv = hcd_to_priv(hcd);
 364
 365         u32 command = reg_read32(hcd->regs, HC_USBCMD);
 366
 367         command |= CMD_RESET;
 368         reg_write32(hcd->regs, HC_USBCMD, command);
 369         hcd->state = HC_STATE_HALT;
 370         priv->next_statechange = jiffies;
 371         retval = handshake(hcd, HC_USBCMD,
 372                             CMD_RESET, 0, 250 * 1000);
 373         return retval;
 374 }
 375
 376 static struct isp1760_qh *qh_alloc(gfp_t flags)
 377 {
 378         struct isp1760_qh *qh;
 379
 380         qh = kmem_cache_zalloc(qh_cachep, flags);
 381         if (!qh)
 382                 return NULL;
 383
 384         INIT_LIST_HEAD(&qh->qh_list);
 385         INIT_LIST_HEAD(&qh->qtd_list);
 386         qh->slot = -1;
 387
 388         return qh;
 389 }
 390
 391 static void qh_free(struct isp1760_qh *qh)
 392 {
 393         WARN_ON(!list_empty(&qh->qtd_list));
 394         WARN_ON(qh->slot > -1);
 395         kmem_cache_free(qh_cachep, qh);
 396 }
 397
 398 /* one-time init, only for memory state */
 399 static int priv_init(struct usb_hcd *hcd)
 400 {
 401         struct isp1760_hcd              *priv = hcd_to_priv(hcd);
 402         u32                     hcc_params;
 403
 404         spin_lock_init(&priv->lock);
 405
 406         INIT_LIST_HEAD(&priv->interruptqhs);
 407         INIT_LIST_HEAD(&priv->controlqhs);
 408         INIT_LIST_HEAD(&priv->bulkqhs);
 409
 410         /*
 411          * hw default: 1K periodic list heads, one per frame.
 412          * periodic_size can shrink by USBCMD update if hcc_params allows.
 413          */
 414         priv->periodic_size = DEFAULT_I_TDPS;
 415
 416         /* controllers may cache some of the periodic schedule ... */
 417         hcc_params = reg_read32(hcd->regs, HC_HCCPARAMS);
 418         /* full frame cache */
 419         if (HCC_ISOC_CACHE(hcc_params))
 420                 priv->i_thresh = 8;
 421         else /* N microframes cached */
 422                 priv->i_thresh = 2 + HCC_ISOC_THRES(hcc_params);
 423
 424         return 0;
 425 }
 426
 427 static int isp1760_hc_setup(struct usb_hcd *hcd)
 428 {
 429         struct isp1760_hcd *priv = hcd_to_priv(hcd);
 430         int result;
 431         u32 scratch, hwmode;
 432
 433         /* Setup HW Mode Control: This assumes a level active-low interrupt */
 434         hwmode = HW_DATA_BUS_32BIT;
 435
 436         if (priv->devflags & ISP1760_FLAG_BUS_WIDTH_16)
 437                 hwmode &= ~HW_DATA_BUS_32BIT;
 438         if (priv->devflags & ISP1760_FLAG_ANALOG_OC)
 439                 hwmode |= HW_ANA_DIGI_OC;
 440         if (priv->devflags & ISP1760_FLAG_DACK_POL_HIGH)
 441                 hwmode |= HW_DACK_POL_HIGH;
 442         if (priv->devflags & ISP1760_FLAG_DREQ_POL_HIGH)
 443                 hwmode |= HW_DREQ_POL_HIGH;
 444         if (priv->devflags & ISP1760_FLAG_INTR_POL_HIGH)
 445                 hwmode |= HW_INTR_HIGH_ACT;
 446         if (priv->devflags & ISP1760_FLAG_INTR_EDGE_TRIG)
 447                 hwmode |= HW_INTR_EDGE_TRIG;
 448
 449         /*
 450          * We have to set this first in case we're in 16-bit mode.
 451          * Write it twice to ensure correct upper bits if switching
 452          * to 16-bit mode.
 453          */
 454         reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode);
 455         reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode);
 456
 457         reg_write32(hcd->regs, HC_SCRATCH_REG, 0xdeadbabe);
 458         /* Change bus pattern */
 459         scratch = reg_read32(hcd->regs, HC_CHIP_ID_REG);
 460         scratch = reg_read32(hcd->regs, HC_SCRATCH_REG);
 461         if (scratch != 0xdeadbabe) {
 462                 dev_err(hcd->self.controller, "Scratch test failed.\n");
 463                 return -ENODEV;
 464         }
 465
 466         /* pre reset */
 467         reg_write32(hcd->regs, HC_BUFFER_STATUS_REG, 0);
 468         reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
 469         reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
 470         reg_write32(hcd->regs, HC_ISO_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
 471
 472         /* reset */
 473         reg_write32(hcd->regs, HC_RESET_REG, SW_RESET_RESET_ALL);
 474         mdelay(100);
 475
 476         reg_write32(hcd->regs, HC_RESET_REG, SW_RESET_RESET_HC);
 477         mdelay(100);
 478
 479         result = ehci_reset(hcd);
 480         if (result)
 481                 return result;
 482
 483         /* Step 11 passed */
 484
 485         dev_info(hcd->self.controller, "bus width: %d, oc: %s\n",
 486                            (priv->devflags & ISP1760_FLAG_BUS_WIDTH_16) ?
 487                            16 : 32, (priv->devflags & ISP1760_FLAG_ANALOG_OC) ?
 488                            "analog" : "digital");
 489
 490         /* This is weird: at the first plug-in of a device there seems to be
 491            one packet queued that never gets returned? */
 492         priv->active_ptds = -1;
 493
 494         /* ATL reset */
 495         reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode | ALL_ATX_RESET);
 496         mdelay(10);
 497         reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode);
 498
 499         reg_write32(hcd->regs, HC_INTERRUPT_ENABLE, INTERRUPT_ENABLE_MASK);
 500
 501         /*
 502          * PORT 1 Control register of the ISP1760 is the OTG control
 503          * register on ISP1761. Since there is no OTG or device controller
 504          * support in this driver, we use port 1 as a "normal" USB host port on
 505          * both chips.
 506          */
 507         reg_write32(hcd->regs, HC_PORT1_CTRL, PORT1_POWER | PORT1_INIT2);
 508         mdelay(10);
 509
 510         priv->hcs_params = reg_read32(hcd->regs, HC_HCSPARAMS);
 511
 512         return priv_init(hcd);
 513 }
 514
 515 static void isp1760_init_maps(struct usb_hcd *hcd)
 516 {
 517         /*set last maps, for iso its only 1, else 32 tds bitmap*/
 518         reg_write32(hcd->regs, HC_ATL_PTD_LASTPTD_REG, 0x80000000);
 519         reg_write32(hcd->regs, HC_INT_PTD_LASTPTD_REG, 0x80000000);
 520         reg_write32(hcd->regs, HC_ISO_PTD_LASTPTD_REG, 0x00000001);
 521
 522         reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, 0);
 523         reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, 0);
 524         reg_write32(hcd->regs, HC_ISO_PTD_SKIPMAP_REG, 0);
 525
 526         reg_write32(hcd->regs, HC_BUFFER_STATUS_REG,
 527                                                 ATL_BUF_FILL | INT_BUF_FILL);
 528 }
 529
 530 static void isp1760_enable_interrupts(struct usb_hcd *hcd)
 531 {
 532         reg_write32(hcd->regs, HC_ATL_IRQ_MASK_AND_REG, 0);
 533         reg_write32(hcd->regs, HC_ATL_IRQ_MASK_OR_REG, 0xffffffff);
 534         reg_write32(hcd->regs, HC_INT_IRQ_MASK_AND_REG, 0);
 535         reg_write32(hcd->regs, HC_INT_IRQ_MASK_OR_REG, 0xffffffff);
 536         reg_write32(hcd->regs, HC_ISO_IRQ_MASK_AND_REG, 0);
 537         reg_write32(hcd->regs, HC_ISO_IRQ_MASK_OR_REG, 0xffffffff);
 538         /* step 23 passed */
 539 }
 540
 541 static int isp1760_run(struct usb_hcd *hcd)
 542 {
 543         int retval;
 544         u32 temp;
 545         u32 command;
 546         u32 chipid;
 547
 548         hcd->uses_new_polling = 1;
 549
 550         hcd->state = HC_STATE_RUNNING;
 551         isp1760_enable_interrupts(hcd);
 552         temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL);
 553         reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp | HW_GLOBAL_INTR_EN);
 554
 555         command = reg_read32(hcd->regs, HC_USBCMD);
 556         command &= ~(CMD_LRESET|CMD_RESET);
 557         command |= CMD_RUN;
 558         reg_write32(hcd->regs, HC_USBCMD, command);
 559
 560         retval = handshake(hcd, HC_USBCMD, CMD_RUN, CMD_RUN, 250 * 1000);
 561         if (retval)
 562                 return retval;
 563
 564         /*
 565          * XXX
 566          * Spec says to write FLAG_CF as last config action, priv code grabs
 567          * the semaphore while doing so.
 568          */
 569         down_write(&ehci_cf_port_reset_rwsem);
 570         reg_write32(hcd->regs, HC_CONFIGFLAG, FLAG_CF);
 571
 572         retval = handshake(hcd, HC_CONFIGFLAG, FLAG_CF, FLAG_CF, 250 * 1000);
 573         up_write(&ehci_cf_port_reset_rwsem);
 574         if (retval)
 575                 return retval;
 576
 577         chipid = reg_read32(hcd->regs, HC_CHIP_ID_REG);
 578         dev_info(hcd->self.controller, "USB ISP %04x HW rev. %d started\n",
 579                                         chipid & 0xffff, chipid >> 16);
 580
 581         /* PTD Register Init Part 2, Step 28 */
 582         /* enable INTs */
 583         isp1760_init_maps(hcd);
 584
 585         /* GRR this is run-once init(), being done every time the HC starts.
 586          * So long as they're part of class devices, we can't do it init()
 587          * since the class device isn't created that early.
 588          */
 589         return 0;
 590 }
 591
 592 static u32 base_to_chip(u32 base)
 593 {
 594         return ((base - 0x400) >> 3);
 595 }
 596
 597 static int last_qtd_of_urb(struct isp1760_qtd *qtd, struct isp1760_qh *qh)
 598 {
 599         struct urb *urb;
 600
 601         if (list_is_last(&qtd->qtd_list, &qh->qtd_list))
 602                 return 1;
 603
 604         urb = qtd->urb;
 605         qtd = list_entry(qtd->qtd_list.next, typeof(*qtd), qtd_list);
 606         return (qtd->urb != urb);
 607 }
 608
 609 /* magic numbers that can affect system performance */
 610 #define EHCI_TUNE_CERR          3       /* 0-3 qtd retries; 0 == don't stop */
 611 #define EHCI_TUNE_RL_HS         4       /* nak throttle; see 4.9 */
 612 #define EHCI_TUNE_RL_TT         0
 613 #define EHCI_TUNE_MULT_HS       1       /* 1-3 transactions/uframe; 4.10.3 */
 614 #define EHCI_TUNE_MULT_TT       1
 615 #define EHCI_TUNE_FLS           2       /* (small) 256 frame schedule */
 616
 617 static void create_ptd_atl(struct isp1760_qh *qh,
 618                         struct isp1760_qtd *qtd, struct ptd *ptd)
 619 {
 620         u32 maxpacket;
 621         u32 multi;
 622         u32 rl = RL_COUNTER;
 623         u32 nak = NAK_COUNTER;
 624
 625         memset(ptd, 0, sizeof(*ptd));
 626
 627         /* according to 3.6.2, max packet len can not be > 0x400 */
 628         maxpacket = usb_maxpacket(qtd->urb->dev, qtd->urb->pipe,
 629                                                 usb_pipeout(qtd->urb->pipe));
 630         multi =  1 + ((maxpacket >> 11) & 0x3);
 631         maxpacket &= 0x7ff;
 632
 633         /* DW0 */
 634         ptd->dw0 = DW0_VALID_BIT;
 635         ptd->dw0 |= TO_DW0_LENGTH(qtd->length);
 636         ptd->dw0 |= TO_DW0_MAXPACKET(maxpacket);
 637         ptd->dw0 |= TO_DW0_ENDPOINT(usb_pipeendpoint(qtd->urb->pipe));
 638
 639         /* DW1 */
 640         ptd->dw1 = usb_pipeendpoint(qtd->urb->pipe) >> 1;
 641         ptd->dw1 |= TO_DW1_DEVICE_ADDR(usb_pipedevice(qtd->urb->pipe));
 642         ptd->dw1 |= TO_DW1_PID_TOKEN(qtd->packet_type);
 643
 644         if (usb_pipebulk(qtd->urb->pipe))
 645                 ptd->dw1 |= DW1_TRANS_BULK;
 646         else if  (usb_pipeint(qtd->urb->pipe))
 647                 ptd->dw1 |= DW1_TRANS_INT;
 648
 649         if (qtd->urb->dev->speed != USB_SPEED_HIGH) {
 650                 /* split transaction */
 651
 652                 ptd->dw1 |= DW1_TRANS_SPLIT;
 653                 if (qtd->urb->dev->speed == USB_SPEED_LOW)
 654                         ptd->dw1 |= DW1_SE_USB_LOSPEED;
 655
 656                 ptd->dw1 |= TO_DW1_PORT_NUM(qtd->urb->dev->ttport);
 657                 ptd->dw1 |= TO_DW1_HUB_NUM(qtd->urb->dev->tt->hub->devnum);
 658
 659                 /* SE bit for Split INT transfers */
 660                 if (usb_pipeint(qtd->urb->pipe) &&
 661                                 (qtd->urb->dev->speed == USB_SPEED_LOW))
 662                         ptd->dw1 |= 2 << 16;
 663
 664                 rl = 0;
 665                 nak = 0;
 666         } else {
 667                 ptd->dw0 |= TO_DW0_MULTI(multi);
 668                 if (usb_pipecontrol(qtd->urb->pipe) ||
 669                                                 usb_pipebulk(qtd->urb->pipe))
 670                         ptd->dw3 |= TO_DW3_PING(qh->ping);
 671         }
 672         /* DW2 */
 673         ptd->dw2 = 0;
 674         ptd->dw2 |= TO_DW2_DATA_START_ADDR(base_to_chip(qtd->payload_addr));
 675         ptd->dw2 |= TO_DW2_RL(rl);
 676
 677         /* DW3 */
 678         ptd->dw3 |= TO_DW3_NAKCOUNT(nak);
 679         ptd->dw3 |= TO_DW3_DATA_TOGGLE(qh->toggle);
 680         if (usb_pipecontrol(qtd->urb->pipe)) {
 681                 if (qtd->data_buffer == qtd->urb->setup_packet)
 682                         ptd->dw3 &= ~TO_DW3_DATA_TOGGLE(1);
 683                 else if (last_qtd_of_urb(qtd, qh))
 684                         ptd->dw3 |= TO_DW3_DATA_TOGGLE(1);
 685         }
 686
 687         ptd->dw3 |= DW3_ACTIVE_BIT;
 688         /* Cerr */
 689         ptd->dw3 |= TO_DW3_CERR(ERR_COUNTER);
 690 }
 691
 692 static void transform_add_int(struct isp1760_qh *qh,
 693                         struct isp1760_qtd *qtd, struct ptd *ptd)
 694 {
 695         u32 usof;
 696         u32 period;
 697
 698         /*
 699          * Most of this is guessing. ISP1761 datasheet is quite unclear, and
 700          * the algorithm from the original Philips driver code, which was
 701          * pretty much used in this driver before as well, is quite horrendous
 702          * and, i believe, incorrect. The code below follows the datasheet and
 703          * USB2.0 spec as far as I can tell, and plug/unplug seems to be much
 704          * more reliable this way (fingers crossed...).
 705          */
 706
 707         if (qtd->urb->dev->speed == USB_SPEED_HIGH) {
 708                 /* urb->interval is in units of microframes (1/8 ms) */
 709                 period = qtd->urb->interval >> 3;
 710
 711                 if (qtd->urb->interval > 4)
 712                         usof = 0x01; /* One bit set =>
 713                                                 interval 1 ms * uFrame-match */
 714                 else if (qtd->urb->interval > 2)
 715                         usof = 0x22; /* Two bits set => interval 1/2 ms */
 716                 else if (qtd->urb->interval > 1)
 717                         usof = 0x55; /* Four bits set => interval 1/4 ms */
 718                 else
 719                         usof = 0xff; /* All bits set => interval 1/8 ms */
 720         } else {
 721                 /* urb->interval is in units of frames (1 ms) */
 722                 period = qtd->urb->interval;
 723                 usof = 0x0f;            /* Execute Start Split on any of the
 724                                            four first uFrames */
 725
 726                 /*
 727                  * First 8 bits in dw5 is uSCS and "specifies which uSOF the
 728                  * complete split needs to be sent. Valid only for IN." Also,
 729                  * "All bits can be set to one for every transfer." (p 82,
 730                  * ISP1761 data sheet.) 0x1c is from Philips driver. Where did
 731                  * that number come from? 0xff seems to work fine...
 732                  */
 733                 /* ptd->dw5 = 0x1c; */
 734                 ptd->dw5 = 0xff; /* Execute Complete Split on any uFrame */
 735         }
 736
 737         period = period >> 1;/* Ensure equal or shorter period than requested */
 738         period &= 0xf8; /* Mask off too large values and lowest unused 3 bits */
 739
 740         ptd->dw2 |= period;
 741         ptd->dw4 = usof;
 742 }
 743
 744 static void create_ptd_int(struct isp1760_qh *qh,
 745                         struct isp1760_qtd *qtd, struct ptd *ptd)
 746 {
 747         create_ptd_atl(qh, qtd, ptd);
 748         transform_add_int(qh, qtd, ptd);
 749 }
 750
 751 static void isp1760_urb_done(struct usb_hcd *hcd, struct urb *urb)
 752 __releases(priv->lock)
 753 __acquires(priv->lock)
 754 {
 755         struct isp1760_hcd *priv = hcd_to_priv(hcd);
 756
 757         if (!urb->unlinked) {
 758                 if (urb->status == -EINPROGRESS)
 759                         urb->status = 0;
 760         }
 761
 762         if (usb_pipein(urb->pipe) && usb_pipetype(urb->pipe) != PIPE_CONTROL) {
 763                 void *ptr;
 764                 for (ptr = urb->transfer_buffer;
 765                      ptr < urb->transfer_buffer + urb->transfer_buffer_length;
 766                      ptr += PAGE_SIZE)
 767                         flush_dcache_page(virt_to_page(ptr));
 768         }
 769
 770         /* complete() can reenter this HCD */
 771         usb_hcd_unlink_urb_from_ep(hcd, urb);
 772         spin_unlock(&priv->lock);
 773         usb_hcd_giveback_urb(hcd, urb, urb->status);
 774         spin_lock(&priv->lock);
 775 }
 776
 777 static struct isp1760_qtd *qtd_alloc(gfp_t flags, struct urb *urb,
 778                                                                 u8 packet_type)
 779 {
 780         struct isp1760_qtd *qtd;
 781
 782         qtd = kmem_cache_zalloc(qtd_cachep, flags);
 783         if (!qtd)
 784                 return NULL;
 785
 786         INIT_LIST_HEAD(&qtd->qtd_list);
 787         qtd->urb = urb;
 788         qtd->packet_type = packet_type;
 789         qtd->status = QTD_ENQUEUED;
 790         qtd->actual_length = 0;
 791
 792         return qtd;
 793 }
 794
 795 static void qtd_free(struct isp1760_qtd *qtd)
 796 {
 797         WARN_ON(qtd->payload_addr);
 798         kmem_cache_free(qtd_cachep, qtd);
 799 }
 800
 801 static void start_bus_transfer(struct usb_hcd *hcd, u32 ptd_offset, int slot,
 802                                 struct slotinfo *slots, struct isp1760_qtd *qtd,
 803                                 struct isp1760_qh *qh, struct ptd *ptd)
 804 {
 805         struct isp1760_hcd *priv = hcd_to_priv(hcd);
 806         WARN_ON((slot < 0) || (slot > 31));
 807         WARN_ON(qtd->length && !qtd->payload_addr);
 808         WARN_ON(slots[slot].qtd);
 809         WARN_ON(slots[slot].qh);
 810         WARN_ON(qtd->status != QTD_PAYLOAD_ALLOC);
 811
 812         slots[slot].qtd = qtd;
 813         slots[slot].qh = qh;
 814         qh->slot = slot;
 815         qtd->status = QTD_XFER_STARTED; /* Set this before writing ptd, since
 816                 interrupt routine may preempt and expects this value. */
 817         ptd_write(hcd->regs, ptd_offset, slot, ptd);
 818         priv->active_ptds++;
 819 }
 820
 821 static int is_short_bulk(struct isp1760_qtd *qtd)
 822 {
 823         return (usb_pipebulk(qtd->urb->pipe) &&
 824                                         (qtd->actual_length < qtd->length));
 825 }
 826
 827 static void collect_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh,
 828                                                 struct list_head *urb_list)
 829 {
 830         int last_qtd;
 831         struct isp1760_qtd *qtd, *qtd_next;
 832         struct urb_listitem *urb_listitem;
 833
 834         list_for_each_entry_safe(qtd, qtd_next, &qh->qtd_list, qtd_list) {
 835                 if (qtd->status < QTD_XFER_COMPLETE)
 836                         break;
 837
 838                 if (list_is_last(&qtd->qtd_list, &qh->qtd_list))
 839                         last_qtd = 1;
 840                 else
 841                         last_qtd = qtd->urb != qtd_next->urb;
 842
 843                 if ((!last_qtd) && (qtd->status == QTD_RETIRE))
 844                         qtd_next->status = QTD_RETIRE;
 845
 846                 if (qtd->status == QTD_XFER_COMPLETE) {
 847                         if (qtd->actual_length) {
 848                                 switch (qtd->packet_type) {
 849                                 case IN_PID:
 850                                         mem_reads8(hcd->regs, qtd->payload_addr,
 851                                                         qtd->data_buffer,
 852                                                         qtd->actual_length);
 853                                         /* Fall through (?) */
 854                                 case OUT_PID:
 855                                         qtd->urb->actual_length +=
 856                                                         qtd->actual_length;
 857                                         /* Fall through ... */
 858                                 case SETUP_PID:
 859                                         break;
 860                                 }
 861                         }
 862
 863                         if (is_short_bulk(qtd)) {
 864                                 if (qtd->urb->transfer_flags & URB_SHORT_NOT_OK)
 865                                         qtd->urb->status = -EREMOTEIO;
 866                                 if (!last_qtd)
 867                                         qtd_next->status = QTD_RETIRE;
 868                         }
 869                 }
 870
 871                 if (qtd->payload_addr)
 872                         free_mem(hcd, qtd);
 873
 874                 if (last_qtd) {
 875                         if ((qtd->status == QTD_RETIRE) &&
 876                                         (qtd->urb->status == -EINPROGRESS))
 877                                 qtd->urb->status = -EPIPE;
 878                         /* Defer calling of urb_done() since it releases lock */
 879                         urb_listitem = kmem_cache_zalloc(urb_listitem_cachep,
 880                                                                 GFP_ATOMIC);
 881                         if (unlikely(!urb_listitem))
 882                                 break;
 883                         urb_listitem->urb = qtd->urb;
 884                         list_add_tail(&urb_listitem->urb_list, urb_list);
 885                 }
 886
 887                 list_del(&qtd->qtd_list);
 888                 qtd_free(qtd);
 889         }
 890 }
 891
 892 #define ENQUEUE_DEPTH   2
 893 static void enqueue_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh)
 894 {
 895         struct isp1760_hcd *priv = hcd_to_priv(hcd);
 896         int ptd_offset;
 897         struct slotinfo *slots;
 898         int curr_slot, free_slot;
 899         int n;
 900         struct ptd ptd;
 901         struct isp1760_qtd *qtd;
 902
 903         if (unlikely(list_empty(&qh->qtd_list))) {
 904                 WARN_ON(1);
 905                 return;
 906         }
 907
 908         if (usb_pipeint(list_entry(qh->qtd_list.next, struct isp1760_qtd,
 909                                                         qtd_list)->urb->pipe)) {
 910                 ptd_offset = INT_PTD_OFFSET;
 911                 slots = priv->int_slots;
 912         } else {
 913                 ptd_offset = ATL_PTD_OFFSET;
 914                 slots = priv->atl_slots;
 915         }
 916
 917         free_slot = -1;
 918         for (curr_slot = 0; curr_slot < 32; curr_slot++) {
 919                 if ((free_slot == -1) && (slots[curr_slot].qtd == NULL))
 920                         free_slot = curr_slot;
 921                 if (slots[curr_slot].qh == qh)
 922                         break;
 923         }
 924
 925         n = 0;
 926         list_for_each_entry(qtd, &qh->qtd_list, qtd_list) {
 927                 if (qtd->status == QTD_ENQUEUED) {
 928                         WARN_ON(qtd->payload_addr);
 929                         alloc_mem(hcd, qtd);
 930                         if ((qtd->length) && (!qtd->payload_addr))
 931                                 break;
 932
 933                         if ((qtd->length) &&
 934                             ((qtd->packet_type == SETUP_PID) ||
 935                              (qtd->packet_type == OUT_PID))) {
 936                                 mem_writes8(hcd->regs, qtd->payload_addr,
 937                                                 qtd->data_buffer, qtd->length);
 938                         }
 939
 940                         qtd->status = QTD_PAYLOAD_ALLOC;
 941                 }
 942
 943                 if (qtd->status == QTD_PAYLOAD_ALLOC) {
 944 /*
 945                         if ((curr_slot > 31) && (free_slot == -1))
 946                                 dev_dbg(hcd->self.controller, "%s: No slot "
 947                                         "available for transfer\n", __func__);
 948 */
 949                         /* Start xfer for this endpoint if not already done */
 950                         if ((curr_slot > 31) && (free_slot > -1)) {
 951                                 if (usb_pipeint(qtd->urb->pipe))
 952                                         create_ptd_int(qh, qtd, &ptd);
 953                                 else
 954                                         create_ptd_atl(qh, qtd, &ptd);
 955
 956                                 start_bus_transfer(hcd, ptd_offset, free_slot,
 957                                                         slots, qtd, qh, &ptd);
 958                                 curr_slot = free_slot;
 959                         }
 960
 961                         n++;
 962                         if (n >= ENQUEUE_DEPTH)
 963                                 break;
 964                 }
 965         }
 966 }
 967
 968 void schedule_ptds(struct usb_hcd *hcd)
 969 {
 970         struct isp1760_hcd *priv;
 971         struct isp1760_qh *qh, *qh_next;
 972         struct list_head *ep_queue;
 973         struct usb_host_endpoint *ep;
 974         LIST_HEAD(urb_list);
 975         struct urb_listitem *urb_listitem, *urb_listitem_next;
 976
 977         if (!hcd) {
 978                 WARN_ON(1);
 979                 return;
 980         }
 981
 982         priv = hcd_to_priv(hcd);
 983
 984         /*
 985          * check finished/retired xfers, transfer payloads, call urb_done()
 986          */
 987         ep_queue = &priv->interruptqhs;
 988         while (ep_queue) {
 989                 list_for_each_entry_safe(qh, qh_next, ep_queue, qh_list) {
 990                         ep = list_entry(qh->qtd_list.next, struct isp1760_qtd,
 991                                                         qtd_list)->urb->ep;
 992                         collect_qtds(hcd, qh, &urb_list);
 993                         if (list_empty(&qh->qtd_list)) {
 994                                 list_del(&qh->qh_list);
 995                                 if (ep->hcpriv == NULL) {
 996                                         /* Endpoint has been disabled, so we
 997                                         can free the associated queue head. */
 998                                         qh_free(qh);
 999                                 }
1000                         }
1001                 }
1002
1003                 if (ep_queue == &priv->interruptqhs)
1004                         ep_queue = &priv->controlqhs;
1005                 else if (ep_queue == &priv->controlqhs)
1006                         ep_queue = &priv->bulkqhs;
1007                 else
1008                         ep_queue = NULL;
1009         }
1010
1011         list_for_each_entry_safe(urb_listitem, urb_listitem_next, &urb_list,
1012                                                                 urb_list) {
1013                 isp1760_urb_done(hcd, urb_listitem->urb);
1014                 kmem_cache_free(urb_listitem_cachep, urb_listitem);
1015         }
1016
1017         /*
1018          * Schedule packets for transfer.
1019          *
1020          * According to USB2.0 specification:
1021          *
1022          * 1st prio: interrupt xfers, up to 80 % of bandwidth
1023          * 2nd prio: control xfers
1024          * 3rd prio: bulk xfers
1025          *
1026          * ... but let's use a simpler scheme here (mostly because ISP1761 doc
1027          * is very unclear on how to prioritize traffic):
1028          *
1029          * 1) Enqueue any queued control transfers, as long as payload chip mem
1030          *    and PTD ATL slots are available.
1031          * 2) Enqueue any queued INT transfers, as long as payload chip mem
1032          *    and PTD INT slots are available.
1033          * 3) Enqueue any queued bulk transfers, as long as payload chip mem
1034          *    and PTD ATL slots are available.
1035          *
1036          * Use double buffering (ENQUEUE_DEPTH==2) as a compromise between
1037          * conservation of chip mem and performance.
1038          *
1039          * I'm sure this scheme could be improved upon!
1040          */
1041         ep_queue = &priv->controlqhs;
1042         while (ep_queue) {
1043                 list_for_each_entry_safe(qh, qh_next, ep_queue, qh_list)
1044                         enqueue_qtds(hcd, qh);
1045
1046                 if (ep_queue == &priv->controlqhs)
1047                         ep_queue = &priv->interruptqhs;
1048                 else if (ep_queue == &priv->interruptqhs)
1049                         ep_queue = &priv->bulkqhs;
1050                 else
1051                         ep_queue = NULL;
1052         }
1053 }
1054
1055 #define PTD_STATE_QTD_DONE      1
1056 #define PTD_STATE_QTD_RELOAD    2
1057 #define PTD_STATE_URB_RETIRE    3
1058
1059 static int check_int_transfer(struct usb_hcd *hcd, struct ptd *ptd,
1060                                                                 struct urb *urb)
1061 {
1062         __dw dw4;
1063         int i;
1064
1065         dw4 = ptd->dw4;
1066         dw4 >>= 8;
1067
1068         /* FIXME: ISP1761 datasheet does not say what to do with these. Do we
1069            need to handle these errors? Is it done in hardware? */
1070
1071         if (ptd->dw3 & DW3_HALT_BIT) {
1072
1073                 urb->status = -EPROTO; /* Default unknown error */
1074
1075                 for (i = 0; i < 8; i++) {
1076                         switch (dw4 & 0x7) {
1077                         case INT_UNDERRUN:
1078                                 dev_dbg(hcd->self.controller, "%s: underrun "
1079                                                 "during uFrame %d\n",
1080                                                 __func__, i);
1081                                 urb->status = -ECOMM; /* Could not write data */
1082                                 break;
1083                         case INT_EXACT:
1084                                 dev_dbg(hcd->self.controller, "%s: transaction "
1085                                                 "error during uFrame %d\n",
1086                                                 __func__, i);
1087                                 urb->status = -EPROTO; /* timeout, bad CRC, PID
1088                                                           error etc. */
1089                                 break;
1090                         case INT_BABBLE:
1091                                 dev_dbg(hcd->self.controller, "%s: babble "
1092                                                 "error during uFrame %d\n",
1093                                                 __func__, i);
1094                                 urb->status = -EOVERFLOW;
1095                                 break;
1096                         }
1097                         dw4 >>= 3;
1098                 }
1099
1100                 return PTD_STATE_URB_RETIRE;
1101         }
1102
1103         return PTD_STATE_QTD_DONE;
1104 }
1105
1106 static int check_atl_transfer(struct usb_hcd *hcd, struct ptd *ptd,
1107                                                                 struct urb *urb)
1108 {
1109         WARN_ON(!ptd);
1110         if (ptd->dw3 & DW3_HALT_BIT) {
1111                 if (ptd->dw3 & DW3_BABBLE_BIT)
1112                         urb->status = -EOVERFLOW;
1113                 else if (FROM_DW3_CERR(ptd->dw3))
1114                         urb->status = -EPIPE;  /* Stall */
1115                 else if (ptd->dw3 & DW3_ERROR_BIT)
1116                         urb->status = -EPROTO; /* XactErr */
1117                 else
1118                         urb->status = -EPROTO; /* Unknown */
1119 /*
1120                 dev_dbg(hcd->self.controller, "%s: ptd error:\n"
1121                         "        dw0: %08x dw1: %08x dw2: %08x dw3: %08x\n"
1122                         "        dw4: %08x dw5: %08x dw6: %08x dw7: %08x\n",
1123                         __func__,
1124                         ptd->dw0, ptd->dw1, ptd->dw2, ptd->dw3,
1125                         ptd->dw4, ptd->dw5, ptd->dw6, ptd->dw7);
1126 */
1127                 return PTD_STATE_URB_RETIRE;
1128         }
1129
1130         if ((ptd->dw3 & DW3_ERROR_BIT) && (ptd->dw3 & DW3_ACTIVE_BIT)) {
1131                 /* Transfer Error, *but* active and no HALT -> reload */
1132                 dev_dbg(hcd->self.controller, "PID error; reloading ptd\n");
1133                 return PTD_STATE_QTD_RELOAD;
1134         }
1135
1136         if (!FROM_DW3_NAKCOUNT(ptd->dw3) && (ptd->dw3 & DW3_ACTIVE_BIT)) {
1137                 /*
1138                  * NAKs are handled in HW by the chip. Usually if the
1139                  * device is not able to send data fast enough.
1140                  * This happens mostly on slower hardware.
1141                  */
1142                 return PTD_STATE_QTD_RELOAD;
1143         }
1144
1145         return PTD_STATE_QTD_DONE;
1146 }
1147
1148 static irqreturn_t isp1760_irq(struct usb_hcd *hcd)
1149 {
1150         struct isp1760_hcd *priv = hcd_to_priv(hcd);
1151         u32 imask;
1152         irqreturn_t irqret = IRQ_NONE;
1153         struct ptd ptd;
1154         struct isp1760_qh *qh;
1155         int int_done_map, atl_done_map;
1156         int slot;
1157         int state;
1158         struct slotinfo *slots;
1159         u32 ptd_offset;
1160         struct isp1760_qtd *qtd;
1161         int modified;
1162         static int last_active_ptds;
1163
1164         spin_lock(&priv->lock);
1165
1166         if (!(hcd->state & HC_STATE_RUNNING))
1167                 goto leave;
1168
1169         imask = reg_read32(hcd->regs, HC_INTERRUPT_REG);
1170         if (unlikely(!imask))
1171                 goto leave;
1172         reg_write32(hcd->regs, HC_INTERRUPT_REG, imask); /* Clear */
1173
1174         int_done_map = reg_read32(hcd->regs, HC_INT_PTD_DONEMAP_REG);
1175         atl_done_map = reg_read32(hcd->regs, HC_ATL_PTD_DONEMAP_REG);
1176         modified = int_done_map | atl_done_map;
1177
1178         while (int_done_map || atl_done_map) {
1179                 if (int_done_map) {
1180                         /* INT ptd */
1181                         slot = __ffs(int_done_map);
1182                         int_done_map &= ~(1 << slot);
1183                         slots = priv->int_slots;
1184                         if (!slots[slot].qh)
1185                                 continue;
1186                         ptd_offset = INT_PTD_OFFSET;
1187                         ptd_read(hcd->regs, INT_PTD_OFFSET, slot, &ptd);
1188                         state = check_int_transfer(hcd, &ptd,
1189                                                         slots[slot].qtd->urb);
1190                 } else {
1191                         /* ATL ptd */
1192                         slot = __ffs(atl_done_map);
1193                         atl_done_map &= ~(1 << slot);
1194                         slots = priv->atl_slots;
1195                         if (!slots[slot].qh)
1196                                 continue;
1197                         ptd_offset = ATL_PTD_OFFSET;
1198                         ptd_read(hcd->regs, ATL_PTD_OFFSET, slot, &ptd);
1199                         state = check_atl_transfer(hcd, &ptd,
1200                                                         slots[slot].qtd->urb);
1201                 }
1202
1203                 qtd = slots[slot].qtd;
1204                 slots[slot].qtd = NULL;
1205                 qh = slots[slot].qh;
1206                 slots[slot].qh = NULL;
1207                 priv->active_ptds--;
1208                 qh->slot = -1;
1209
1210                 WARN_ON(qtd->status != QTD_XFER_STARTED);
1211
1212                 switch (state) {
1213                 case PTD_STATE_QTD_DONE:
1214                         if ((usb_pipeint(qtd->urb->pipe)) &&
1215                                        (qtd->urb->dev->speed != USB_SPEED_HIGH))
1216                                 qtd->actual_length =
1217                                        FROM_DW3_SCS_NRBYTESTRANSFERRED(ptd.dw3);
1218                         else
1219                                 qtd->actual_length =
1220                                         FROM_DW3_NRBYTESTRANSFERRED(ptd.dw3);
1221
1222                         qtd->status = QTD_XFER_COMPLETE;
1223                         if (list_is_last(&qtd->qtd_list, &qh->qtd_list) ||
1224                                                         is_short_bulk(qtd))
1225                                 qtd = NULL;
1226                         else
1227                                 qtd = list_entry(qtd->qtd_list.next,
1228                                                         typeof(*qtd), qtd_list);
1229
1230                         qh->toggle = FROM_DW3_DATA_TOGGLE(ptd.dw3);
1231                         qh->ping = FROM_DW3_PING(ptd.dw3);
1232                         break;
1233
1234                 case PTD_STATE_QTD_RELOAD: /* QTD_RETRY, for atls only */
1235                         qtd->status = QTD_PAYLOAD_ALLOC;
1236                         ptd.dw0 |= DW0_VALID_BIT;
1237                         /* RL counter = ERR counter */
1238                         ptd.dw3 &= ~TO_DW3_NAKCOUNT(0xf);
1239                         ptd.dw3 |= TO_DW3_NAKCOUNT(FROM_DW2_RL(ptd.dw2));
1240                         ptd.dw3 &= ~TO_DW3_CERR(3);
1241                         ptd.dw3 |= TO_DW3_CERR(ERR_COUNTER);
1242                         qh->toggle = FROM_DW3_DATA_TOGGLE(ptd.dw3);
1243                         qh->ping = FROM_DW3_PING(ptd.dw3);
1244                         break;
1245
1246                 case PTD_STATE_URB_RETIRE:
1247                         qtd->status = QTD_RETIRE;
1248                         qtd = NULL;
1249                         qh->toggle = 0;
1250                         qh->ping = 0;
1251                         break;
1252
1253                 default:
1254                         WARN_ON(1);
1255                         continue;
1256                 }
1257
1258                 if (qtd && (qtd->status == QTD_PAYLOAD_ALLOC)) {
1259                         if (slots == priv->int_slots) {
1260                                 if (state == PTD_STATE_QTD_RELOAD)
1261                                         dev_err(hcd->self.controller,
1262                                                 "%s: PTD_STATE_QTD_RELOAD on "
1263                                                 "interrupt packet\n", __func__);
1264                                 if (state != PTD_STATE_QTD_RELOAD)
1265                                         create_ptd_int(qh, qtd, &ptd);
1266                         } else {
1267                                 if (state != PTD_STATE_QTD_RELOAD)
1268                                         create_ptd_atl(qh, qtd, &ptd);
1269                         }
1270
1271                         start_bus_transfer(hcd, ptd_offset, slot, slots, qtd,
1272                                 qh, &ptd);
1273                 }
1274         }
1275
1276         if (modified)
1277                 schedule_ptds(hcd);
1278
1279         /* ISP1760 Errata 2 explains that interrupts may be missed (or not
1280            happen?) if two USB devices are running simultaneously. Perhaps
1281            this happens when a PTD is finished during interrupt handling;
1282            enable SOF interrupts if PTDs are still scheduled when exiting this
1283            interrupt handler, just to be safe. */
1284
1285         if (priv->active_ptds != last_active_ptds) {
1286                 if (priv->active_ptds > 0)
1287                         reg_write32(hcd->regs, HC_INTERRUPT_ENABLE,
1288                                                 INTERRUPT_ENABLE_SOT_MASK);
1289                 else
1290                         reg_write32(hcd->regs, HC_INTERRUPT_ENABLE,
1291                                                 INTERRUPT_ENABLE_MASK);
1292                 last_active_ptds = priv->active_ptds;
1293         }
1294
1295         irqret = IRQ_HANDLED;
1296 leave:
1297         spin_unlock(&priv->lock);
1298
1299         return irqret;
1300 }
1301
1302 static int qtd_fill(struct isp1760_qtd *qtd, void *databuffer, size_t len)
1303 {
1304         qtd->data_buffer = databuffer;
1305
1306         if (len > MAX_PAYLOAD_SIZE)
1307                 len = MAX_PAYLOAD_SIZE;
1308         qtd->length = len;
1309
1310         return qtd->length;
1311 }
1312
1313 static void qtd_list_free(struct list_head *qtd_list)
1314 {
1315         struct isp1760_qtd *qtd, *qtd_next;
1316
1317         list_for_each_entry_safe(qtd, qtd_next, qtd_list, qtd_list) {
1318                 list_del(&qtd->qtd_list);
1319                 qtd_free(qtd);
1320         }
1321 }
1322
1323 /*
1324  * Packetize urb->transfer_buffer into list of packets of size wMaxPacketSize.
1325  * Also calculate the PID type (SETUP/IN/OUT) for each packet.
1326  */
1327 #define max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
1328 static void packetize_urb(struct usb_hcd *hcd,
1329                 struct urb *urb, struct list_head *head, gfp_t flags)
1330 {
1331         struct isp1760_qtd *qtd;
1332         void *buf;
1333         int len, maxpacketsize;
1334         u8 packet_type;
1335
1336         /*
1337          * URBs map to sequences of QTDs:  one logical transaction
1338          */
1339
1340         if (!urb->transfer_buffer && urb->transfer_buffer_length) {
1341                 /* XXX This looks like usb storage / SCSI bug */
1342                 dev_err(hcd->self.controller,
1343                                 "buf is null, dma is %08lx len is %d\n",
1344                                 (long unsigned)urb->transfer_dma,
1345                                 urb->transfer_buffer_length);
1346                 WARN_ON(1);
1347         }
1348
1349         if (usb_pipein(urb->pipe))
1350                 packet_type = IN_PID;
1351         else
1352                 packet_type = OUT_PID;
1353
1354         if (usb_pipecontrol(urb->pipe)) {
1355                 qtd = qtd_alloc(flags, urb, SETUP_PID);
1356                 if (!qtd)
1357                         goto cleanup;
1358                 qtd_fill(qtd, urb->setup_packet, sizeof(struct usb_ctrlrequest));
1359                 list_add_tail(&qtd->qtd_list, head);
1360
1361                 /* for zero length DATA stages, STATUS is always IN */
1362                 if (urb->transfer_buffer_length == 0)
1363                         packet_type = IN_PID;
1364         }
1365
1366         maxpacketsize = max_packet(usb_maxpacket(urb->dev, urb->pipe,
1367                                                 usb_pipeout(urb->pipe)));
1368
1369         /*
1370          * buffer gets wrapped in one or more qtds;
1371          * last one may be "short" (including zero len)
1372          * and may serve as a control status ack
1373          */
1374         buf = urb->transfer_buffer;
1375         len = urb->transfer_buffer_length;
1376
1377         for (;;) {
1378                 int this_qtd_len;
1379
1380                 qtd = qtd_alloc(flags, urb, packet_type);
1381                 if (!qtd)
1382                         goto cleanup;
1383                 this_qtd_len = qtd_fill(qtd, buf, len);
1384                 list_add_tail(&qtd->qtd_list, head);
1385
1386                 len -= this_qtd_len;
1387                 buf += this_qtd_len;
1388
1389                 if (len <= 0)
1390                         break;
1391         }
1392
1393         /*
1394          * control requests may need a terminating data "status" ack;
1395          * bulk ones may need a terminating short packet (zero length).
1396          */
1397         if (urb->transfer_buffer_length != 0) {
1398                 int one_more = 0;
1399
1400                 if (usb_pipecontrol(urb->pipe)) {
1401                         one_more = 1;
1402                         if (packet_type == IN_PID)
1403                                 packet_type = OUT_PID;
1404                         else
1405                                 packet_type = IN_PID;
1406                 } else if (usb_pipebulk(urb->pipe)
1407                                 && (urb->transfer_flags & URB_ZERO_PACKET)
1408                                 && !(urb->transfer_buffer_length %
1409                                                         maxpacketsize)) {
1410                         one_more = 1;
1411                 }
1412                 if (one_more) {
1413                         qtd = qtd_alloc(flags, urb, packet_type);
1414                         if (!qtd)
1415                                 goto cleanup;
1416
1417                         /* never any data in such packets */
1418                         qtd_fill(qtd, NULL, 0);
1419                         list_add_tail(&qtd->qtd_list, head);
1420                 }
1421         }
1422
1423         return;
1424
1425 cleanup:
1426         qtd_list_free(head);
1427 }
1428
1429 static int isp1760_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
1430                 gfp_t mem_flags)
1431 {
1432         struct isp1760_hcd *priv = hcd_to_priv(hcd);
1433         struct list_head *ep_queue;
1434         struct isp1760_qh *qh, *qhit;
1435         unsigned long spinflags;
1436         LIST_HEAD(new_qtds);
1437         int retval;
1438         int qh_in_queue;
1439
1440         switch (usb_pipetype(urb->pipe)) {
1441         case PIPE_CONTROL:
1442                 ep_queue = &priv->controlqhs;
1443                 break;
1444         case PIPE_BULK:
1445                 ep_queue = &priv->bulkqhs;
1446                 break;
1447         case PIPE_INTERRUPT:
1448                 if (urb->interval < 0)
1449                         return -EINVAL;
1450                 /* FIXME: Check bandwidth  */
1451                 ep_queue = &priv->interruptqhs;
1452                 break;
1453         case PIPE_ISOCHRONOUS:
1454                 dev_err(hcd->self.controller, "%s: isochronous USB packets "
1455                                                         "not yet supported\n",
1456                                                         __func__);
1457                 return -EPIPE;
1458         default:
1459                 dev_err(hcd->self.controller, "%s: unknown pipe type\n",
1460                                                         __func__);
1461                 return -EPIPE;
1462         }
1463
1464         if (usb_pipein(urb->pipe))
1465                 urb->actual_length = 0;
1466
1467         packetize_urb(hcd, urb, &new_qtds, mem_flags);
1468         if (list_empty(&new_qtds))
1469                 return -ENOMEM;
1470         urb->hcpriv = NULL; /* Used to signal unlink to interrupt handler */
1471
1472         retval = 0;
1473         spin_lock_irqsave(&priv->lock, spinflags);
1474
1475         if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) {
1476                 retval = -ESHUTDOWN;
1477                 goto out;
1478         }
1479         retval = usb_hcd_link_urb_to_ep(hcd, urb);
1480         if (retval)
1481                 goto out;
1482
1483         qh = urb->ep->hcpriv;
1484         if (qh) {
1485                 qh_in_queue = 0;
1486                 list_for_each_entry(qhit, ep_queue, qh_list) {
1487                         if (qhit == qh) {
1488                                 qh_in_queue = 1;
1489                                 break;
1490                         }
1491                 }
1492                 if (!qh_in_queue)
1493                         list_add_tail(&qh->qh_list, ep_queue);
1494         } else {
1495                 qh = qh_alloc(GFP_ATOMIC);
1496                 if (!qh) {
1497                         retval = -ENOMEM;
1498                         goto out;
1499                 }
1500                 list_add_tail(&qh->qh_list, ep_queue);
1501                 urb->ep->hcpriv = qh;
1502         }
1503
1504         list_splice_tail(&new_qtds, &qh->qtd_list);
1505         schedule_ptds(hcd);
1506
1507 out:
1508         spin_unlock_irqrestore(&priv->lock, spinflags);
1509         return retval;
1510 }
1511
1512 static int isp1760_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
1513                 int status)
1514 {
1515         struct isp1760_hcd *priv = hcd_to_priv(hcd);
1516         struct isp1760_qh *qh;
1517         struct isp1760_qtd *qtd;
1518         struct ptd ptd;
1519         unsigned long spinflags;
1520         int retval = 0;
1521
1522         spin_lock_irqsave(&priv->lock, spinflags);
1523
1524         qh = urb->ep->hcpriv;
1525         if (!qh) {
1526                 retval = -EINVAL;
1527                 goto out;
1528         }
1529
1530         /* We need to forcefully reclaim the slot since some transfers never
1531            return, e.g. interrupt transfers and NAKed bulk transfers. */
1532         if (qh->slot > -1) {
1533                 memset(&ptd, 0, sizeof(ptd));
1534                 if (usb_pipebulk(urb->pipe)) {
1535                         priv->atl_slots[qh->slot].qh = NULL;
1536                         priv->atl_slots[qh->slot].qtd = NULL;
1537                         ptd_write(hcd->regs, ATL_PTD_OFFSET, qh->slot, &ptd);
1538                 } else {
1539                         priv->int_slots[qh->slot].qh = NULL;
1540                         priv->int_slots[qh->slot].qtd = NULL;
1541                         ptd_write(hcd->regs, INT_PTD_OFFSET, qh->slot, &ptd);
1542                 }
1543                 priv->active_ptds--;
1544                 qh->slot = -1;
1545         }
1546
1547         list_for_each_entry(qtd, &qh->qtd_list, qtd_list) {
1548                 if (qtd->urb == urb)
1549                         qtd->status = QTD_RETIRE;
1550         }
1551
1552         urb->status = status;
1553         schedule_ptds(hcd);
1554
1555 out:
1556         spin_unlock_irqrestore(&priv->lock, spinflags);
1557
1558         return retval;
1559 }
1560
1561 static void isp1760_endpoint_disable(struct usb_hcd *hcd,
1562                 struct usb_host_endpoint *ep)
1563 {
1564         struct isp1760_hcd *priv = hcd_to_priv(hcd);
1565         struct isp1760_qh *qh;
1566         struct isp1760_qtd *qtd;
1567         unsigned long spinflags;
1568         int do_iter;
1569
1570         spin_lock_irqsave(&priv->lock, spinflags);
1571         qh = ep->hcpriv;
1572         if (!qh)
1573                 goto out;
1574
1575         do_iter = !list_empty(&qh->qtd_list);
1576         while (do_iter) {
1577                 do_iter = 0;
1578                 list_for_each_entry(qtd, &qh->qtd_list, qtd_list) {
1579                         if (qtd->urb->ep == ep) {
1580                                 spin_unlock_irqrestore(&priv->lock, spinflags);
1581                                 isp1760_urb_dequeue(hcd, qtd->urb, -ECONNRESET);
1582                                 spin_lock_irqsave(&priv->lock, spinflags);
1583                                 do_iter = 1;
1584                                 break; /* Restart iteration */
1585                         }
1586                 }
1587         }
1588         ep->hcpriv = NULL;
1589         /* Cannot free qh here since it will be parsed by schedule_ptds() */
1590
1591 out:
1592         spin_unlock_irqrestore(&priv->lock, spinflags);
1593 }
1594
1595 static int isp1760_hub_status_data(struct usb_hcd *hcd, char *buf)
1596 {
1597         struct isp1760_hcd *priv = hcd_to_priv(hcd);
1598         u32 temp, status = 0;
1599         u32 mask;
1600         int retval = 1;
1601         unsigned long flags;
1602
1603         /* if !USB_SUSPEND, root hub timers won't get shut down ... */
1604         if (!HC_IS_RUNNING(hcd->state))
1605                 return 0;
1606
1607         /* init status to no-changes */
1608         buf[0] = 0;
1609         mask = PORT_CSC;
1610
1611         spin_lock_irqsave(&priv->lock, flags);
1612         temp = reg_read32(hcd->regs, HC_PORTSC1);
1613
1614         if (temp & PORT_OWNER) {
1615                 if (temp & PORT_CSC) {
1616                         temp &= ~PORT_CSC;
1617                         reg_write32(hcd->regs, HC_PORTSC1, temp);
1618                         goto done;
1619                 }
1620         }
1621
1622         /*
1623          * Return status information even for ports with OWNER set.
1624          * Otherwise khubd wouldn't see the disconnect event when a
1625          * high-speed device is switched over to the companion
1626          * controller by the user.
1627          */
1628
1629         if ((temp & mask) != 0
1630                         || ((temp & PORT_RESUME) != 0
1631                                 && time_after_eq(jiffies,
1632                                         priv->reset_done))) {
1633                 buf [0] |= 1 << (0 + 1);
1634                 status = STS_PCD;
1635         }
1636         /* FIXME autosuspend idle root hubs */
1637 done:
1638         spin_unlock_irqrestore(&priv->lock, flags);
1639         return status ? retval : 0;
1640 }
1641
1642 static void isp1760_hub_descriptor(struct isp1760_hcd *priv,
1643                 struct usb_hub_descriptor *desc)
1644 {
1645         int ports = HCS_N_PORTS(priv->hcs_params);
1646         u16 temp;
1647
1648         desc->bDescriptorType = 0x29;
1649         /* priv 1.0, 2.3.9 says 20ms max */
1650         desc->bPwrOn2PwrGood = 10;
1651         desc->bHubContrCurrent = 0;
1652
1653         desc->bNbrPorts = ports;
1654         temp = 1 + (ports / 8);
1655         desc->bDescLength = 7 + 2 * temp;
1656
1657         /* ports removable, and usb 1.0 legacy PortPwrCtrlMask */
1658         memset(&desc->u.hs.DeviceRemovable[0], 0, temp);
1659         memset(&desc->u.hs.DeviceRemovable[temp], 0xff, temp);
1660
1661         /* per-port overcurrent reporting */
1662         temp = 0x0008;
1663         if (HCS_PPC(priv->hcs_params))
1664                 /* per-port power control */
1665                 temp |= 0x0001;
1666         else
1667                 /* no power switching */
1668                 temp |= 0x0002;
1669         desc->wHubCharacteristics = cpu_to_le16(temp);
1670 }
1671
1672 #define PORT_WAKE_BITS  (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E)
1673
1674 static int check_reset_complete(struct usb_hcd *hcd, int index,
1675                 int port_status)
1676 {
1677         if (!(port_status & PORT_CONNECT))
1678                 return port_status;
1679
1680         /* if reset finished and it's still not enabled -- handoff */
1681         if (!(port_status & PORT_PE)) {
1682
1683                 dev_info(hcd->self.controller,
1684                                         "port %d full speed --> companion\n",
1685                                         index + 1);
1686
1687                 port_status |= PORT_OWNER;
1688                 port_status &= ~PORT_RWC_BITS;
1689                 reg_write32(hcd->regs, HC_PORTSC1, port_status);
1690
1691         } else
1692                 dev_info(hcd->self.controller, "port %d high speed\n",
1693                                                                 index + 1);
1694
1695         return port_status;
1696 }
1697
1698 static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq,
1699                 u16 wValue, u16 wIndex, char *buf, u16 wLength)
1700 {
1701         struct isp1760_hcd *priv = hcd_to_priv(hcd);
1702         int ports = HCS_N_PORTS(priv->hcs_params);
1703         u32 temp, status;
1704         unsigned long flags;
1705         int retval = 0;
1706         unsigned selector;
1707
1708         /*
1709          * FIXME:  support SetPortFeatures USB_PORT_FEAT_INDICATOR.
1710          * HCS_INDICATOR may say we can change LEDs to off/amber/green.
1711          * (track current state ourselves) ... blink for diagnostics,
1712          * power, "this is the one", etc.  EHCI spec supports this.
1713          */
1714
1715         spin_lock_irqsave(&priv->lock, flags);
1716         switch (typeReq) {
1717         case ClearHubFeature:
1718                 switch (wValue) {
1719                 case C_HUB_LOCAL_POWER:
1720                 case C_HUB_OVER_CURRENT:
1721                         /* no hub-wide feature/status flags */
1722                         break;
1723                 default:
1724                         goto error;
1725                 }
1726                 break;
1727         case ClearPortFeature:
1728                 if (!wIndex || wIndex > ports)
1729                         goto error;
1730                 wIndex--;
1731                 temp = reg_read32(hcd->regs, HC_PORTSC1);
1732
1733                 /*
1734                  * Even if OWNER is set, so the port is owned by the
1735                  * companion controller, khubd needs to be able to clear
1736                  * the port-change status bits (especially
1737                  * USB_PORT_STAT_C_CONNECTION).
1738                  */
1739
1740                 switch (wValue) {
1741                 case USB_PORT_FEAT_ENABLE:
1742                         reg_write32(hcd->regs, HC_PORTSC1, temp & ~PORT_PE);
1743                         break;
1744                 case USB_PORT_FEAT_C_ENABLE:
1745                         /* XXX error? */
1746                         break;
1747                 case USB_PORT_FEAT_SUSPEND:
1748                         if (temp & PORT_RESET)
1749                                 goto error;
1750
1751                         if (temp & PORT_SUSPEND) {
1752                                 if ((temp & PORT_PE) == 0)
1753                                         goto error;
1754                                 /* resume signaling for 20 msec */
1755                                 temp &= ~(PORT_RWC_BITS);
1756                                 reg_write32(hcd->regs, HC_PORTSC1,
1757                                                         temp | PORT_RESUME);
1758                                 priv->reset_done = jiffies +
1759                                         msecs_to_jiffies(20);
1760                         }
1761                         break;
1762                 case USB_PORT_FEAT_C_SUSPEND:
1763                         /* we auto-clear this feature */
1764                         break;
1765                 case USB_PORT_FEAT_POWER:
1766                         if (HCS_PPC(priv->hcs_params))
1767                                 reg_write32(hcd->regs, HC_PORTSC1,
1768                                                         temp & ~PORT_POWER);
1769                         break;
1770                 case USB_PORT_FEAT_C_CONNECTION:
1771                         reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_CSC);
1772                         break;
1773                 case USB_PORT_FEAT_C_OVER_CURRENT:
1774                         /* XXX error ?*/
1775                         break;
1776                 case USB_PORT_FEAT_C_RESET:
1777                         /* GetPortStatus clears reset */
1778                         break;
1779                 default:
1780                         goto error;
1781                 }
1782                 reg_read32(hcd->regs, HC_USBCMD);
1783                 break;
1784         case GetHubDescriptor:
1785                 isp1760_hub_descriptor(priv, (struct usb_hub_descriptor *)
1786                         buf);
1787                 break;
1788         case GetHubStatus:
1789                 /* no hub-wide feature/status flags */
1790                 memset(buf, 0, 4);
1791                 break;
1792         case GetPortStatus:
1793                 if (!wIndex || wIndex > ports)
1794                         goto error;
1795                 wIndex--;
1796                 status = 0;
1797                 temp = reg_read32(hcd->regs, HC_PORTSC1);
1798
1799                 /* wPortChange bits */
1800                 if (temp & PORT_CSC)
1801                         status |= USB_PORT_STAT_C_CONNECTION << 16;
1802
1803
1804                 /* whoever resumes must GetPortStatus to complete it!! */
1805                 if (temp & PORT_RESUME) {
1806                         dev_err(hcd->self.controller, "Port resume should be skipped.\n");
1807
1808                         /* Remote Wakeup received? */
1809                         if (!priv->reset_done) {
1810                                 /* resume signaling for 20 msec */
1811                                 priv->reset_done = jiffies
1812                                                 + msecs_to_jiffies(20);
1813                                 /* check the port again */
1814                                 mod_timer(&hcd->rh_timer, priv->reset_done);
1815                         }
1816
1817                         /* resume completed? */
1818                         else if (time_after_eq(jiffies,
1819                                         priv->reset_done)) {
1820                                 status |= USB_PORT_STAT_C_SUSPEND << 16;
1821                                 priv->reset_done = 0;
1822
1823                                 /* stop resume signaling */
1824                                 temp = reg_read32(hcd->regs, HC_PORTSC1);
1825                                 reg_write32(hcd->regs, HC_PORTSC1,
1826                                         temp & ~(PORT_RWC_BITS | PORT_RESUME));
1827                                 retval = handshake(hcd, HC_PORTSC1,
1828                                            PORT_RESUME, 0, 2000 /* 2msec */);
1829                                 if (retval != 0) {
1830                                         dev_err(hcd->self.controller,
1831                                                 "port %d resume error %d\n",
1832                                                 wIndex + 1, retval);
1833                                         goto error;
1834                                 }
1835                                 temp &= ~(PORT_SUSPEND|PORT_RESUME|(3<<10));
1836                         }
1837                 }
1838
1839                 /* whoever resets must GetPortStatus to complete it!! */
1840                 if ((temp & PORT_RESET)
1841                                 && time_after_eq(jiffies,
1842                                         priv->reset_done)) {
1843                         status |= USB_PORT_STAT_C_RESET << 16;
1844                         priv->reset_done = 0;
1845
1846                         /* force reset to complete */
1847                         reg_write32(hcd->regs, HC_PORTSC1, temp & ~PORT_RESET);
1848                         /* REVISIT:  some hardware needs 550+ usec to clear
1849                          * this bit; seems too long to spin routinely...
1850                          */
1851                         retval = handshake(hcd, HC_PORTSC1,
1852                                         PORT_RESET, 0, 750);
1853                         if (retval != 0) {
1854                                 dev_err(hcd->self.controller, "port %d reset error %d\n",
1855                                                 wIndex + 1, retval);
1856                                 goto error;
1857                         }
1858
1859                         /* see what we found out */
1860                         temp = check_reset_complete(hcd, wIndex,
1861                                         reg_read32(hcd->regs, HC_PORTSC1));
1862                 }
1863                 /*
1864                  * Even if OWNER is set, there's no harm letting khubd
1865                  * see the wPortStatus values (they should all be 0 except
1866                  * for PORT_POWER anyway).
1867                  */
1868
1869                 if (temp & PORT_OWNER)
1870                         dev_err(hcd->self.controller, "PORT_OWNER is set\n");
1871
1872                 if (temp & PORT_CONNECT) {
1873                         status |= USB_PORT_STAT_CONNECTION;
1874                         /* status may be from integrated TT */
1875                         status |= USB_PORT_STAT_HIGH_SPEED;
1876                 }
1877                 if (temp & PORT_PE)
1878                         status |= USB_PORT_STAT_ENABLE;
1879                 if (temp & (PORT_SUSPEND|PORT_RESUME))
1880                         status |= USB_PORT_STAT_SUSPEND;
1881                 if (temp & PORT_RESET)
1882                         status |= USB_PORT_STAT_RESET;
1883                 if (temp & PORT_POWER)
1884                         status |= USB_PORT_STAT_POWER;
1885
1886                 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
1887                 break;
1888         case SetHubFeature:
1889                 switch (wValue) {
1890                 case C_HUB_LOCAL_POWER:
1891                 case C_HUB_OVER_CURRENT:
1892                         /* no hub-wide feature/status flags */
1893                         break;
1894                 default:
1895                         goto error;
1896                 }
1897                 break;
1898         case SetPortFeature:
1899                 selector = wIndex >> 8;
1900                 wIndex &= 0xff;
1901                 if (!wIndex || wIndex > ports)
1902                         goto error;
1903                 wIndex--;
1904                 temp = reg_read32(hcd->regs, HC_PORTSC1);
1905                 if (temp & PORT_OWNER)
1906                         break;
1907
1908 /*              temp &= ~PORT_RWC_BITS; */
1909                 switch (wValue) {
1910                 case USB_PORT_FEAT_ENABLE:
1911                         reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_PE);
1912                         break;
1913
1914                 case USB_PORT_FEAT_SUSPEND:
1915                         if ((temp & PORT_PE) == 0
1916                                         || (temp & PORT_RESET) != 0)
1917                                 goto error;
1918
1919                         reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_SUSPEND);
1920                         break;
1921                 case USB_PORT_FEAT_POWER:
1922                         if (HCS_PPC(priv->hcs_params))
1923                                 reg_write32(hcd->regs, HC_PORTSC1,
1924                                                         temp | PORT_POWER);
1925                         break;
1926                 case USB_PORT_FEAT_RESET:
1927                         if (temp & PORT_RESUME)
1928                                 goto error;
1929                         /* line status bits may report this as low speed,
1930                          * which can be fine if this root hub has a
1931                          * transaction translator built in.
1932                          */
1933                         if ((temp & (PORT_PE|PORT_CONNECT)) == PORT_CONNECT
1934                                         && PORT_USB11(temp)) {
1935                                 temp |= PORT_OWNER;
1936                         } else {
1937                                 temp |= PORT_RESET;
1938                                 temp &= ~PORT_PE;
1939
1940                                 /*
1941                                  * caller must wait, then call GetPortStatus
1942                                  * usb 2.0 spec says 50 ms resets on root
1943                                  */
1944                                 priv->reset_done = jiffies +
1945                                         msecs_to_jiffies(50);
1946                         }
1947                         reg_write32(hcd->regs, HC_PORTSC1, temp);
1948                         break;
1949                 default:
1950                         goto error;
1951                 }
1952                 reg_read32(hcd->regs, HC_USBCMD);
1953                 break;
1954
1955         default:
1956 error:
1957                 /* "stall" on error */
1958                 retval = -EPIPE;
1959         }
1960         spin_unlock_irqrestore(&priv->lock, flags);
1961         return retval;
1962 }
1963
1964 static int isp1760_get_frame(struct usb_hcd *hcd)
1965 {
1966         struct isp1760_hcd *priv = hcd_to_priv(hcd);
1967         u32 fr;
1968
1969         fr = reg_read32(hcd->regs, HC_FRINDEX);
1970         return (fr >> 3) % priv->periodic_size;
1971 }
1972
1973 static void isp1760_stop(struct usb_hcd *hcd)
1974 {
1975         struct isp1760_hcd *priv = hcd_to_priv(hcd);
1976         u32 temp;
1977
1978         isp1760_hub_control(hcd, ClearPortFeature, USB_PORT_FEAT_POWER, 1,
1979                         NULL, 0);
1980         mdelay(20);
1981
1982         spin_lock_irq(&priv->lock);
1983         ehci_reset(hcd);
1984         /* Disable IRQ */
1985         temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL);
1986         reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp &= ~HW_GLOBAL_INTR_EN);
1987         spin_unlock_irq(&priv->lock);
1988
1989         reg_write32(hcd->regs, HC_CONFIGFLAG, 0);
1990 }
1991
1992 static void isp1760_shutdown(struct usb_hcd *hcd)
1993 {
1994         u32 command, temp;
1995
1996         isp1760_stop(hcd);
1997         temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL);
1998         reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp &= ~HW_GLOBAL_INTR_EN);
1999
2000         command = reg_read32(hcd->regs, HC_USBCMD);
2001         command &= ~CMD_RUN;
2002         reg_write32(hcd->regs, HC_USBCMD, command);
2003 }
2004
2005 static const struct hc_driver isp1760_hc_driver = {
2006         .description            = "isp1760-hcd",
2007         .product_desc           = "NXP ISP1760 USB Host Controller",
2008         .hcd_priv_size          = sizeof(struct isp1760_hcd),
2009         .irq                    = isp1760_irq,
2010         .flags                  = HCD_MEMORY | HCD_USB2,
2011         .reset                  = isp1760_hc_setup,
2012         .start                  = isp1760_run,
2013         .stop                   = isp1760_stop,
2014         .shutdown               = isp1760_shutdown,
2015         .urb_enqueue            = isp1760_urb_enqueue,
2016         .urb_dequeue            = isp1760_urb_dequeue,
2017         .endpoint_disable       = isp1760_endpoint_disable,
2018         .get_frame_number       = isp1760_get_frame,
2019         .hub_status_data        = isp1760_hub_status_data,
2020         .hub_control            = isp1760_hub_control,
2021 };
2022
2023 int __init init_kmem_once(void)
2024 {
2025         urb_listitem_cachep = kmem_cache_create("isp1760 urb_listitem",
2026                         sizeof(struct urb_listitem), 0, SLAB_TEMPORARY |
2027                         SLAB_MEM_SPREAD, NULL);
2028
2029         if (!urb_listitem_cachep)
2030                 return -ENOMEM;
2031
2032         qtd_cachep = kmem_cache_create("isp1760_qtd",
2033                         sizeof(struct isp1760_qtd), 0, SLAB_TEMPORARY |
2034                         SLAB_MEM_SPREAD, NULL);
2035
2036         if (!qtd_cachep)
2037                 return -ENOMEM;
2038
2039         qh_cachep = kmem_cache_create("isp1760_qh", sizeof(struct isp1760_qh),
2040                         0, SLAB_TEMPORARY | SLAB_MEM_SPREAD, NULL);
2041
2042         if (!qh_cachep) {
2043                 kmem_cache_destroy(qtd_cachep);
2044                 return -ENOMEM;
2045         }
2046
2047         return 0;
2048 }
2049
2050 void deinit_kmem_cache(void)
2051 {
2052         kmem_cache_destroy(qtd_cachep);
2053         kmem_cache_destroy(qh_cachep);
2054         kmem_cache_destroy(urb_listitem_cachep);
2055 }
2056
2057 struct usb_hcd *isp1760_register(phys_addr_t res_start, resource_size_t res_len,
2058                                  int irq, unsigned long irqflags,
2059                                  struct device *dev, const char *busname,
2060                                  unsigned int devflags)
2061 {
2062         struct usb_hcd *hcd;
2063         struct isp1760_hcd *priv;
2064         int ret;
2065
2066         if (usb_disabled())
2067                 return ERR_PTR(-ENODEV);
2068
2069         /* prevent usb-core allocating DMA pages */
2070         dev->dma_mask = NULL;
2071
2072         hcd = usb_create_hcd(&isp1760_hc_driver, dev, dev_name(dev));
2073         if (!hcd)
2074                 return ERR_PTR(-ENOMEM);
2075
2076         priv = hcd_to_priv(hcd);
2077         priv->devflags = devflags;
2078         init_memory(priv);
2079         hcd->regs = ioremap(res_start, res_len);
2080         if (!hcd->regs) {
2081                 ret = -EIO;
2082                 goto err_put;
2083         }
2084
2085         hcd->irq = irq;
2086         hcd->rsrc_start = res_start;
2087         hcd->rsrc_len = res_len;
2088
2089         ret = usb_add_hcd(hcd, irq, irqflags);
2090         if (ret)
2091                 goto err_unmap;
2092
2093         return hcd;
2094
2095 err_unmap:
2096          iounmap(hcd->regs);
2097
2098 err_put:
2099          usb_put_hcd(hcd);
2100
2101          return ERR_PTR(ret);
2102 }
2103
2104 MODULE_DESCRIPTION("Driver for the ISP1760 USB-controller from NXP");
2105 MODULE_AUTHOR("Sebastian Siewior <bigeasy@linuxtronix.de>");
2106 MODULE_LICENSE("GPL v2");