2 * Driver for the NXP ISP1760 chip
4 * However, the code might contain some bugs. What doesn't work for sure is:
7 e The interrupt line is configured as active low, level.
9 * (c) 2007 Sebastian Siewior <bigeasy@linutronix.de>
12 #include <linux/module.h>
13 #include <linux/kernel.h>
14 #include <linux/slab.h>
15 #include <linux/list.h>
16 #include <linux/usb.h>
17 #include <linux/usb/hcd.h>
18 #include <linux/debugfs.h>
19 #include <linux/uaccess.h>
22 #include <asm/unaligned.h>
23 #include <asm/cacheflush.h>
25 #include "isp1760-hcd.h"
27 static struct kmem_cache *qtd_cachep;
28 static struct kmem_cache *qh_cachep;
33 struct inter_packet_info atl_ints[32];
34 struct inter_packet_info int_ints[32];
35 struct memory_chunk memory_pool[BLOCKS];
38 /* periodic schedule support */
39 #define DEFAULT_I_TDPS 1024
40 unsigned periodic_size;
42 unsigned long reset_done;
43 unsigned long next_statechange;
44 unsigned int devflags;
47 static inline struct isp1760_hcd *hcd_to_priv(struct usb_hcd *hcd)
49 return (struct isp1760_hcd *) (hcd->hcd_priv);
52 /* Section 2.2 Host Controller Capability Registers */
53 #define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */
54 #define HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */
55 #define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */
56 #define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */
57 #define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */
58 #define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */
59 #define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */
61 /* Section 2.3 Host Controller Operational Registers */
62 #define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */
63 #define CMD_RESET (1<<1) /* reset HC not bus */
64 #define CMD_RUN (1<<0) /* start/stop HC */
65 #define STS_PCD (1<<2) /* port change detect */
66 #define FLAG_CF (1<<0) /* true: we'll support "high speed" */
68 #define PORT_OWNER (1<<13) /* true: companion hc owns this port */
69 #define PORT_POWER (1<<12) /* true: has power (see PPC) */
70 #define PORT_USB11(x) (((x) & (3 << 10)) == (1 << 10)) /* USB 1.1 device */
71 #define PORT_RESET (1<<8) /* reset port */
72 #define PORT_SUSPEND (1<<7) /* suspend port */
73 #define PORT_RESUME (1<<6) /* resume it */
74 #define PORT_PE (1<<2) /* port enable */
75 #define PORT_CSC (1<<1) /* connect status change */
76 #define PORT_CONNECT (1<<0) /* device connected */
77 #define PORT_RWC_BITS (PORT_CSC)
84 /* the rest is HCD-private */
85 struct list_head qtd_list;
91 #define URB_ENQUEUED (1 << 1)
95 /* first part defined by EHCI spec */
96 struct list_head qtd_list;
103 * Access functions for isp176x registers (addresses 0..0x03FF).
105 static u32 reg_read32(void __iomem *base, u32 reg)
107 return readl(base + reg);
110 static void reg_write32(void __iomem *base, u32 reg, u32 val)
112 writel(val, base + reg);
116 * Access functions for isp176x memory (offset >= 0x0400).
118 * bank_reads8() reads memory locations prefetched by an earlier write to
119 * HC_MEMORY_REG (see isp176x datasheet). Unless you want to do fancy multi-
120 * bank optimizations, you should use the more generic mem_reads8() below.
122 * For access to ptd memory, use the specialized ptd_read() and ptd_write()
125 * These functions copy via MMIO data to/from the device. memcpy_{to|from}io()
126 * doesn't quite work because some people have to enforce 32-bit access
128 static void bank_reads8(void __iomem *src_base, u32 src_offset, u32 bank_addr,
129 __u32 *dst, u32 bytes)
136 src = src_base + (bank_addr | src_offset);
138 if (src_offset < PAYLOAD_OFFSET) {
140 *dst = le32_to_cpu(__raw_readl(src));
147 *dst = __raw_readl(src);
157 /* in case we have 3, 2 or 1 by left. The dst buffer may not be fully
160 if (src_offset < PAYLOAD_OFFSET)
161 val = le32_to_cpu(__raw_readl(src));
163 val = __raw_readl(src);
165 dst_byteptr = (void *) dst;
166 src_byteptr = (void *) &val;
168 *dst_byteptr = *src_byteptr;
175 static void mem_reads8(void __iomem *src_base, u32 src_offset, void *dst,
178 reg_write32(src_base, HC_MEMORY_REG, src_offset + ISP_BANK(0));
180 bank_reads8(src_base, src_offset, ISP_BANK(0), dst, bytes);
183 static void mem_writes8(void __iomem *dst_base, u32 dst_offset,
184 __u32 const *src, u32 bytes)
188 dst = dst_base + dst_offset;
190 if (dst_offset < PAYLOAD_OFFSET) {
192 __raw_writel(cpu_to_le32(*src), dst);
199 __raw_writel(*src, dst);
208 /* in case we have 3, 2 or 1 bytes left. The buffer is allocated and the
209 * extra bytes should not be read by the HW.
212 if (dst_offset < PAYLOAD_OFFSET)
213 __raw_writel(cpu_to_le32(*src), dst);
215 __raw_writel(*src, dst);
219 * Read and write ptds. 'ptd_offset' should be one of ISO_PTD_OFFSET,
220 * INT_PTD_OFFSET, and ATL_PTD_OFFSET. 'slot' should be less than 32.
222 static void ptd_read(void __iomem *base, u32 ptd_offset, u32 slot,
225 reg_write32(base, HC_MEMORY_REG,
226 ISP_BANK(0) + ptd_offset + slot*sizeof(*ptd));
228 bank_reads8(base, ptd_offset + slot*sizeof(*ptd), ISP_BANK(0),
229 (void *) ptd, sizeof(*ptd));
232 static void ptd_write(void __iomem *base, u32 ptd_offset, u32 slot,
235 mem_writes8(base, ptd_offset + slot*sizeof(*ptd) + sizeof(ptd->dw0),
236 &ptd->dw1, 7*sizeof(ptd->dw1));
237 /* Make sure dw0 gets written last (after other dw's and after payload)
238 since it contains the enable bit */
240 mem_writes8(base, ptd_offset + slot*sizeof(*ptd), &ptd->dw0,
245 /* memory management of the 60kb on the chip from 0x1000 to 0xffff */
246 static void init_memory(struct isp1760_hcd *priv)
251 payload_addr = PAYLOAD_OFFSET;
252 for (i = 0; i < BLOCK_1_NUM; i++) {
253 priv->memory_pool[i].start = payload_addr;
254 priv->memory_pool[i].size = BLOCK_1_SIZE;
255 priv->memory_pool[i].free = 1;
256 payload_addr += priv->memory_pool[i].size;
260 for (i = 0; i < BLOCK_2_NUM; i++) {
261 priv->memory_pool[curr + i].start = payload_addr;
262 priv->memory_pool[curr + i].size = BLOCK_2_SIZE;
263 priv->memory_pool[curr + i].free = 1;
264 payload_addr += priv->memory_pool[curr + i].size;
268 for (i = 0; i < BLOCK_3_NUM; i++) {
269 priv->memory_pool[curr + i].start = payload_addr;
270 priv->memory_pool[curr + i].size = BLOCK_3_SIZE;
271 priv->memory_pool[curr + i].free = 1;
272 payload_addr += priv->memory_pool[curr + i].size;
275 BUG_ON(payload_addr - priv->memory_pool[0].start > PAYLOAD_AREA_SIZE);
278 static void alloc_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd)
280 struct isp1760_hcd *priv = hcd_to_priv(hcd);
283 BUG_ON(qtd->payload_addr);
288 for (i = 0; i < BLOCKS; i++) {
289 if (priv->memory_pool[i].size >= qtd->length &&
290 priv->memory_pool[i].free) {
291 priv->memory_pool[i].free = 0;
292 qtd->payload_addr = priv->memory_pool[i].start;
297 dev_err(hcd->self.controller,
298 "%s: Cannot allocate %zu bytes of memory\n"
299 "Current memory map:\n",
300 __func__, qtd->length);
301 for (i = 0; i < BLOCKS; i++) {
302 dev_err(hcd->self.controller, "Pool %2d size %4d status: %d\n",
303 i, priv->memory_pool[i].size,
304 priv->memory_pool[i].free);
306 /* XXX maybe -ENOMEM could be possible */
311 static void free_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd)
313 struct isp1760_hcd *priv = hcd_to_priv(hcd);
316 if (!qtd->payload_addr)
319 for (i = 0; i < BLOCKS; i++) {
320 if (priv->memory_pool[i].start == qtd->payload_addr) {
321 BUG_ON(priv->memory_pool[i].free);
322 priv->memory_pool[i].free = 1;
323 qtd->payload_addr = 0;
328 dev_err(hcd->self.controller, "%s: Invalid pointer: %08x\n",
329 __func__, qtd->payload_addr);
333 static void isp1760_init_regs(struct usb_hcd *hcd)
335 reg_write32(hcd->regs, HC_BUFFER_STATUS_REG, 0);
336 reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
337 reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
338 reg_write32(hcd->regs, HC_ISO_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
340 reg_write32(hcd->regs, HC_ATL_PTD_DONEMAP_REG, ~NO_TRANSFER_ACTIVE);
341 reg_write32(hcd->regs, HC_INT_PTD_DONEMAP_REG, ~NO_TRANSFER_ACTIVE);
342 reg_write32(hcd->regs, HC_ISO_PTD_DONEMAP_REG, ~NO_TRANSFER_ACTIVE);
345 static int handshake(struct usb_hcd *hcd, u32 reg,
346 u32 mask, u32 done, int usec)
351 result = reg_read32(hcd->regs, reg);
363 /* reset a non-running (STS_HALT == 1) controller */
364 static int ehci_reset(struct usb_hcd *hcd)
367 struct isp1760_hcd *priv = hcd_to_priv(hcd);
369 u32 command = reg_read32(hcd->regs, HC_USBCMD);
371 command |= CMD_RESET;
372 reg_write32(hcd->regs, HC_USBCMD, command);
373 hcd->state = HC_STATE_HALT;
374 priv->next_statechange = jiffies;
375 retval = handshake(hcd, HC_USBCMD,
376 CMD_RESET, 0, 250 * 1000);
380 static void qh_destroy(struct isp1760_qh *qh)
382 BUG_ON(!list_empty(&qh->qtd_list));
383 kmem_cache_free(qh_cachep, qh);
386 static struct isp1760_qh *isp1760_qh_alloc(gfp_t flags)
388 struct isp1760_qh *qh;
390 qh = kmem_cache_zalloc(qh_cachep, flags);
394 INIT_LIST_HEAD(&qh->qtd_list);
398 /* magic numbers that can affect system performance */
399 #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
400 #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
401 #define EHCI_TUNE_RL_TT 0
402 #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
403 #define EHCI_TUNE_MULT_TT 1
404 #define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */
406 /* one-time init, only for memory state */
407 static int priv_init(struct usb_hcd *hcd)
409 struct isp1760_hcd *priv = hcd_to_priv(hcd);
412 spin_lock_init(&priv->lock);
415 * hw default: 1K periodic list heads, one per frame.
416 * periodic_size can shrink by USBCMD update if hcc_params allows.
418 priv->periodic_size = DEFAULT_I_TDPS;
420 /* controllers may cache some of the periodic schedule ... */
421 hcc_params = reg_read32(hcd->regs, HC_HCCPARAMS);
422 /* full frame cache */
423 if (HCC_ISOC_CACHE(hcc_params))
425 else /* N microframes cached */
426 priv->i_thresh = 2 + HCC_ISOC_THRES(hcc_params);
431 static int isp1760_hc_setup(struct usb_hcd *hcd)
433 struct isp1760_hcd *priv = hcd_to_priv(hcd);
437 /* Setup HW Mode Control: This assumes a level active-low interrupt */
438 hwmode = HW_DATA_BUS_32BIT;
440 if (priv->devflags & ISP1760_FLAG_BUS_WIDTH_16)
441 hwmode &= ~HW_DATA_BUS_32BIT;
442 if (priv->devflags & ISP1760_FLAG_ANALOG_OC)
443 hwmode |= HW_ANA_DIGI_OC;
444 if (priv->devflags & ISP1760_FLAG_DACK_POL_HIGH)
445 hwmode |= HW_DACK_POL_HIGH;
446 if (priv->devflags & ISP1760_FLAG_DREQ_POL_HIGH)
447 hwmode |= HW_DREQ_POL_HIGH;
448 if (priv->devflags & ISP1760_FLAG_INTR_POL_HIGH)
449 hwmode |= HW_INTR_HIGH_ACT;
450 if (priv->devflags & ISP1760_FLAG_INTR_EDGE_TRIG)
451 hwmode |= HW_INTR_EDGE_TRIG;
454 * We have to set this first in case we're in 16-bit mode.
455 * Write it twice to ensure correct upper bits if switching
458 reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode);
459 reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode);
461 reg_write32(hcd->regs, HC_SCRATCH_REG, 0xdeadbabe);
462 /* Change bus pattern */
463 scratch = reg_read32(hcd->regs, HC_CHIP_ID_REG);
464 scratch = reg_read32(hcd->regs, HC_SCRATCH_REG);
465 if (scratch != 0xdeadbabe) {
466 dev_err(hcd->self.controller, "Scratch test failed.\n");
471 isp1760_init_regs(hcd);
474 reg_write32(hcd->regs, HC_RESET_REG, SW_RESET_RESET_ALL);
477 reg_write32(hcd->regs, HC_RESET_REG, SW_RESET_RESET_HC);
480 result = ehci_reset(hcd);
486 dev_info(hcd->self.controller, "bus width: %d, oc: %s\n",
487 (priv->devflags & ISP1760_FLAG_BUS_WIDTH_16) ?
488 16 : 32, (priv->devflags & ISP1760_FLAG_ANALOG_OC) ?
489 "analog" : "digital");
492 reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode | ALL_ATX_RESET);
494 reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode);
496 reg_write32(hcd->regs, HC_INTERRUPT_REG, INTERRUPT_ENABLE_MASK);
497 reg_write32(hcd->regs, HC_INTERRUPT_ENABLE, INTERRUPT_ENABLE_MASK);
500 * PORT 1 Control register of the ISP1760 is the OTG control
501 * register on ISP1761. Since there is no OTG or device controller
502 * support in this driver, we use port 1 as a "normal" USB host port on
505 reg_write32(hcd->regs, HC_PORT1_CTRL, PORT1_POWER | PORT1_INIT2);
508 priv->hcs_params = reg_read32(hcd->regs, HC_HCSPARAMS);
510 return priv_init(hcd);
513 static void isp1760_init_maps(struct usb_hcd *hcd)
515 /*set last maps, for iso its only 1, else 32 tds bitmap*/
516 reg_write32(hcd->regs, HC_ATL_PTD_LASTPTD_REG, 0x80000000);
517 reg_write32(hcd->regs, HC_INT_PTD_LASTPTD_REG, 0x80000000);
518 reg_write32(hcd->regs, HC_ISO_PTD_LASTPTD_REG, 0x00000001);
521 static void isp1760_enable_interrupts(struct usb_hcd *hcd)
523 reg_write32(hcd->regs, HC_ATL_IRQ_MASK_AND_REG, 0);
524 reg_write32(hcd->regs, HC_ATL_IRQ_MASK_OR_REG, 0);
525 reg_write32(hcd->regs, HC_INT_IRQ_MASK_AND_REG, 0);
526 reg_write32(hcd->regs, HC_INT_IRQ_MASK_OR_REG, 0);
527 reg_write32(hcd->regs, HC_ISO_IRQ_MASK_AND_REG, 0);
528 reg_write32(hcd->regs, HC_ISO_IRQ_MASK_OR_REG, 0xffffffff);
532 static int isp1760_run(struct usb_hcd *hcd)
539 hcd->uses_new_polling = 1;
541 hcd->state = HC_STATE_RUNNING;
542 isp1760_enable_interrupts(hcd);
543 temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL);
544 reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp | HW_GLOBAL_INTR_EN);
546 command = reg_read32(hcd->regs, HC_USBCMD);
547 command &= ~(CMD_LRESET|CMD_RESET);
549 reg_write32(hcd->regs, HC_USBCMD, command);
551 retval = handshake(hcd, HC_USBCMD, CMD_RUN, CMD_RUN,
558 * Spec says to write FLAG_CF as last config action, priv code grabs
559 * the semaphore while doing so.
561 down_write(&ehci_cf_port_reset_rwsem);
562 reg_write32(hcd->regs, HC_CONFIGFLAG, FLAG_CF);
564 retval = handshake(hcd, HC_CONFIGFLAG, FLAG_CF, FLAG_CF, 250 * 1000);
565 up_write(&ehci_cf_port_reset_rwsem);
569 chipid = reg_read32(hcd->regs, HC_CHIP_ID_REG);
570 dev_info(hcd->self.controller, "USB ISP %04x HW rev. %d started\n",
571 chipid & 0xffff, chipid >> 16);
573 /* PTD Register Init Part 2, Step 28 */
575 isp1760_init_maps(hcd);
577 /* GRR this is run-once init(), being done every time the HC starts.
578 * So long as they're part of class devices, we can't do it init()
579 * since the class device isn't created that early.
584 static u32 base_to_chip(u32 base)
586 return ((base - 0x400) >> 3);
589 static int last_qtd_of_urb(struct isp1760_qtd *qtd, struct isp1760_qh *qh)
593 if (list_is_last(&qtd->qtd_list, &qh->qtd_list))
597 qtd = list_entry(qtd->qtd_list.next, typeof(*qtd), qtd_list);
598 return (qtd->urb != urb);
601 static void transform_into_atl(struct isp1760_qh *qh,
602 struct isp1760_qtd *qtd, struct ptd *ptd)
608 u32 nak = NAK_COUNTER;
610 memset(ptd, 0, sizeof(*ptd));
612 /* according to 3.6.2, max packet len can not be > 0x400 */
613 maxpacket = usb_maxpacket(qtd->urb->dev, qtd->urb->pipe,
614 usb_pipeout(qtd->urb->pipe));
615 multi = 1 + ((maxpacket >> 11) & 0x3);
619 ptd->dw0 = PTD_VALID;
620 ptd->dw0 |= PTD_LENGTH(qtd->length);
621 ptd->dw0 |= PTD_MAXPACKET(maxpacket);
622 ptd->dw0 |= PTD_ENDPOINT(usb_pipeendpoint(qtd->urb->pipe));
625 ptd->dw1 = usb_pipeendpoint(qtd->urb->pipe) >> 1;
626 ptd->dw1 |= PTD_DEVICE_ADDR(usb_pipedevice(qtd->urb->pipe));
628 pid_code = qtd->packet_type;
629 ptd->dw1 |= PTD_PID_TOKEN(pid_code);
631 if (usb_pipebulk(qtd->urb->pipe))
632 ptd->dw1 |= PTD_TRANS_BULK;
633 else if (usb_pipeint(qtd->urb->pipe))
634 ptd->dw1 |= PTD_TRANS_INT;
636 if (qtd->urb->dev->speed != USB_SPEED_HIGH) {
637 /* split transaction */
639 ptd->dw1 |= PTD_TRANS_SPLIT;
640 if (qtd->urb->dev->speed == USB_SPEED_LOW)
641 ptd->dw1 |= PTD_SE_USB_LOSPEED;
643 ptd->dw1 |= PTD_PORT_NUM(qtd->urb->dev->ttport);
644 ptd->dw1 |= PTD_HUB_NUM(qtd->urb->dev->tt->hub->devnum);
646 /* SE bit for Split INT transfers */
647 if (usb_pipeint(qtd->urb->pipe) &&
648 (qtd->urb->dev->speed == USB_SPEED_LOW))
655 ptd->dw0 |= PTD_MULTI(multi);
656 if (usb_pipecontrol(qtd->urb->pipe) ||
657 usb_pipebulk(qtd->urb->pipe))
664 ptd->dw2 |= PTD_DATA_START_ADDR(base_to_chip(qtd->payload_addr));
665 ptd->dw2 |= PTD_RL_CNT(rl);
666 ptd->dw3 |= PTD_NAC_CNT(nak);
669 ptd->dw3 |= qh->toggle;
670 if (usb_pipecontrol(qtd->urb->pipe)) {
671 if (qtd->data_buffer == qtd->urb->setup_packet)
672 ptd->dw3 &= ~PTD_DATA_TOGGLE(1);
673 else if (last_qtd_of_urb(qtd, qh))
674 ptd->dw3 |= PTD_DATA_TOGGLE(1);
677 ptd->dw3 |= PTD_ACTIVE;
679 ptd->dw3 |= PTD_CERR(ERR_COUNTER);
682 static void transform_add_int(struct isp1760_qh *qh,
683 struct isp1760_qtd *qtd, struct ptd *ptd)
689 * Most of this is guessing. ISP1761 datasheet is quite unclear, and
690 * the algorithm from the original Philips driver code, which was
691 * pretty much used in this driver before as well, is quite horrendous
692 * and, i believe, incorrect. The code below follows the datasheet and
693 * USB2.0 spec as far as I can tell, and plug/unplug seems to be much
694 * more reliable this way (fingers crossed...).
697 if (qtd->urb->dev->speed == USB_SPEED_HIGH) {
698 /* urb->interval is in units of microframes (1/8 ms) */
699 period = qtd->urb->interval >> 3;
701 if (qtd->urb->interval > 4)
702 usof = 0x01; /* One bit set =>
703 interval 1 ms * uFrame-match */
704 else if (qtd->urb->interval > 2)
705 usof = 0x22; /* Two bits set => interval 1/2 ms */
706 else if (qtd->urb->interval > 1)
707 usof = 0x55; /* Four bits set => interval 1/4 ms */
709 usof = 0xff; /* All bits set => interval 1/8 ms */
711 /* urb->interval is in units of frames (1 ms) */
712 period = qtd->urb->interval;
713 usof = 0x0f; /* Execute Start Split on any of the
714 four first uFrames */
717 * First 8 bits in dw5 is uSCS and "specifies which uSOF the
718 * complete split needs to be sent. Valid only for IN." Also,
719 * "All bits can be set to one for every transfer." (p 82,
720 * ISP1761 data sheet.) 0x1c is from Philips driver. Where did
721 * that number come from? 0xff seems to work fine...
723 /* ptd->dw5 = 0x1c; */
724 ptd->dw5 = 0xff; /* Execute Complete Split on any uFrame */
727 period = period >> 1;/* Ensure equal or shorter period than requested */
728 period &= 0xf8; /* Mask off too large values and lowest unused 3 bits */
734 static void transform_into_int(struct isp1760_qh *qh,
735 struct isp1760_qtd *qtd, struct ptd *ptd)
737 transform_into_atl(qh, qtd, ptd);
738 transform_add_int(qh, qtd, ptd);
741 static int qtd_fill(struct isp1760_qtd *qtd, void *databuffer, size_t len,
746 qtd->data_buffer = databuffer;
747 qtd->packet_type = GET_QTD_TOKEN_TYPE(token);
749 if (len > MAX_PAYLOAD_SIZE)
750 count = MAX_PAYLOAD_SIZE;
758 static int check_error(struct usb_hcd *hcd, struct ptd *ptd)
762 if (ptd->dw3 & DW3_HALT_BIT) {
765 if (ptd->dw3 & DW3_ERROR_BIT)
766 pr_err("error bit is set in DW3\n");
769 if (ptd->dw3 & DW3_QTD_ACTIVE) {
770 dev_err(hcd->self.controller, "Transfer active bit is set DW3\n"
771 "nak counter: %d, rl: %d\n",
772 (ptd->dw3 >> 19) & 0xf, (ptd->dw2 >> 25) & 0xf);
778 static void check_int_err_status(struct usb_hcd *hcd, u32 dw4)
784 for (i = 0; i < 8; i++) {
787 dev_err(hcd->self.controller, "Underrun (%d)\n", i);
791 dev_err(hcd->self.controller,
792 "Transaction error (%d)\n", i);
796 dev_err(hcd->self.controller, "Babble error (%d)\n", i);
803 static void enqueue_one_qtd(struct usb_hcd *hcd, struct isp1760_qtd *qtd)
805 if (qtd->length && (qtd->length <= MAX_PAYLOAD_SIZE)) {
806 switch (qtd->packet_type) {
811 mem_writes8(hcd->regs, qtd->payload_addr,
812 qtd->data_buffer, qtd->length);
817 static void enqueue_one_atl_qtd(struct usb_hcd *hcd, struct isp1760_qh *qh,
818 u32 slot, struct isp1760_qtd *qtd)
820 struct isp1760_hcd *priv = hcd_to_priv(hcd);
824 transform_into_atl(qh, qtd, &ptd);
825 ptd_write(hcd->regs, ATL_PTD_OFFSET, slot, &ptd);
826 enqueue_one_qtd(hcd, qtd);
828 priv->atl_ints[slot].qh = qh;
829 priv->atl_ints[slot].qtd = qtd;
830 qtd->status |= URB_ENQUEUED;
831 qtd->status |= slot << 16;
834 static void enqueue_one_int_qtd(struct usb_hcd *hcd, struct isp1760_qh *qh,
835 u32 slot, struct isp1760_qtd *qtd)
837 struct isp1760_hcd *priv = hcd_to_priv(hcd);
841 transform_into_int(qh, qtd, &ptd);
842 ptd_write(hcd->regs, INT_PTD_OFFSET, slot, &ptd);
843 enqueue_one_qtd(hcd, qtd);
845 priv->int_ints[slot].qh = qh;
846 priv->int_ints[slot].qtd = qtd;
847 qtd->status |= URB_ENQUEUED;
848 qtd->status |= slot << 16;
851 static void enqueue_an_ATL_packet(struct usb_hcd *hcd, struct isp1760_qh *qh,
852 struct isp1760_qtd *qtd)
854 struct isp1760_hcd *priv = hcd_to_priv(hcd);
855 u32 skip_map, or_map;
860 * When this function is called from the interrupt handler to enqueue
861 * a follow-up packet, the SKIP register gets written and read back
862 * almost immediately. With ISP1761, this register requires a delay of
863 * 195ns between a write and subsequent read (see section 15.1.1.3).
867 skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG);
870 slot = __ffs(skip_map);
872 enqueue_one_atl_qtd(hcd, qh, slot, qtd);
874 or_map = reg_read32(hcd->regs, HC_ATL_IRQ_MASK_OR_REG);
875 or_map |= (1 << slot);
876 reg_write32(hcd->regs, HC_ATL_IRQ_MASK_OR_REG, or_map);
878 skip_map &= ~(1 << slot);
879 reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, skip_map);
882 if (priv->atl_queued == 2)
883 reg_write32(hcd->regs, HC_INTERRUPT_ENABLE,
884 INTERRUPT_ENABLE_SOT_MASK);
886 buffstatus = reg_read32(hcd->regs, HC_BUFFER_STATUS_REG);
887 buffstatus |= ATL_BUFFER;
888 reg_write32(hcd->regs, HC_BUFFER_STATUS_REG, buffstatus);
891 static void enqueue_an_INT_packet(struct usb_hcd *hcd, struct isp1760_qh *qh,
892 struct isp1760_qtd *qtd)
894 u32 skip_map, or_map;
899 * When this function is called from the interrupt handler to enqueue
900 * a follow-up packet, the SKIP register gets written and read back
901 * almost immediately. With ISP1761, this register requires a delay of
902 * 195ns between a write and subsequent read (see section 15.1.1.3).
906 skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG);
909 slot = __ffs(skip_map);
911 enqueue_one_int_qtd(hcd, qh, slot, qtd);
913 or_map = reg_read32(hcd->regs, HC_INT_IRQ_MASK_OR_REG);
914 or_map |= (1 << slot);
915 reg_write32(hcd->regs, HC_INT_IRQ_MASK_OR_REG, or_map);
917 skip_map &= ~(1 << slot);
918 reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, skip_map);
920 buffstatus = reg_read32(hcd->regs, HC_BUFFER_STATUS_REG);
921 buffstatus |= INT_BUFFER;
922 reg_write32(hcd->regs, HC_BUFFER_STATUS_REG, buffstatus);
925 static void isp1760_urb_done(struct usb_hcd *hcd, struct urb *urb)
926 __releases(priv->lock)
927 __acquires(priv->lock)
929 struct isp1760_hcd *priv = hcd_to_priv(hcd);
931 if (!urb->unlinked) {
932 if (urb->status == -EINPROGRESS)
936 if (usb_pipein(urb->pipe) && usb_pipetype(urb->pipe) != PIPE_CONTROL) {
938 for (ptr = urb->transfer_buffer;
939 ptr < urb->transfer_buffer + urb->transfer_buffer_length;
941 flush_dcache_page(virt_to_page(ptr));
944 /* complete() can reenter this HCD */
945 usb_hcd_unlink_urb_from_ep(hcd, urb);
946 spin_unlock(&priv->lock);
947 usb_hcd_giveback_urb(hcd, urb, urb->status);
948 spin_lock(&priv->lock);
951 static void isp1760_qtd_free(struct isp1760_qtd *qtd)
953 BUG_ON(qtd->payload_addr);
954 kmem_cache_free(qtd_cachep, qtd);
957 static struct isp1760_qtd *clean_this_qtd(struct isp1760_qtd *qtd,
958 struct isp1760_qh *qh)
960 struct isp1760_qtd *tmp_qtd;
962 if (list_is_last(&qtd->qtd_list, &qh->qtd_list))
965 tmp_qtd = list_entry(qtd->qtd_list.next, struct isp1760_qtd,
967 list_del(&qtd->qtd_list);
968 isp1760_qtd_free(qtd);
973 * Remove this QTD from the QH list and free its memory. If this QTD
974 * isn't the last one than remove also his successor(s).
975 * Returns the QTD which is part of an new URB and should be enqueued.
977 static struct isp1760_qtd *clean_up_qtdlist(struct isp1760_qtd *qtd,
978 struct isp1760_qh *qh)
984 qtd = clean_this_qtd(qtd, qh);
985 } while (qtd && (qtd->urb == urb));
990 static void do_atl_int(struct usb_hcd *hcd)
992 struct isp1760_hcd *priv = hcd_to_priv(hcd);
993 u32 done_map, skip_map;
999 u32 status = -EINVAL;
1001 struct isp1760_qtd *qtd;
1002 struct isp1760_qh *qh;
1006 done_map = reg_read32(hcd->regs, HC_ATL_PTD_DONEMAP_REG);
1007 skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG);
1009 or_map = reg_read32(hcd->regs, HC_ATL_IRQ_MASK_OR_REG);
1010 or_map &= ~done_map;
1011 reg_write32(hcd->regs, HC_ATL_IRQ_MASK_OR_REG, or_map);
1017 slot = __ffs(done_map);
1018 done_map &= ~(1 << slot);
1019 skip_map |= (1 << slot);
1021 qtd = priv->atl_ints[slot].qtd;
1022 qh = priv->atl_ints[slot].qh;
1025 dev_err(hcd->self.controller, "qh is 0\n");
1028 ptd_read(hcd->regs, ATL_PTD_OFFSET, slot, &ptd);
1030 rl = (ptd.dw2 >> 25) & 0x0f;
1031 nakcount = (ptd.dw3 >> 19) & 0xf;
1033 /* Transfer Error, *but* active and no HALT -> reload */
1034 if ((ptd.dw3 & DW3_ERROR_BIT) && (ptd.dw3 & DW3_QTD_ACTIVE) &&
1035 !(ptd.dw3 & DW3_HALT_BIT)) {
1037 /* according to ppriv code, we have to
1038 * reload this one if trasfered bytes != requested bytes
1039 * else act like everything went smooth..
1040 * XXX This just doesn't feel right and hasn't
1044 length = PTD_XFERRED_LENGTH(ptd.dw3);
1045 dev_err(hcd->self.controller,
1046 "Should reload now... transferred %d "
1047 "of %zu\n", length, qtd->length);
1051 if (!nakcount && (ptd.dw3 & DW3_QTD_ACTIVE)) {
1055 * NAKs are handled in HW by the chip. Usually if the
1056 * device is not able to send data fast enough.
1057 * This happens mostly on slower hardware.
1060 /* RL counter = ERR counter */
1061 ptd.dw3 &= ~(0xf << 19);
1062 ptd.dw3 |= rl << 19;
1063 ptd.dw3 &= ~(3 << (55 - 32));
1064 ptd.dw3 |= ERR_COUNTER << (55 - 32);
1067 * It is not needed to write skip map back because it
1068 * is unchanged. Just make sure that this entry is
1069 * unskipped once it gets written to the HW.
1071 skip_map &= ~(1 << slot);
1072 or_map = reg_read32(hcd->regs, HC_ATL_IRQ_MASK_OR_REG);
1073 or_map |= 1 << slot;
1074 reg_write32(hcd->regs, HC_ATL_IRQ_MASK_OR_REG, or_map);
1076 ptd.dw0 |= PTD_VALID;
1077 ptd_write(hcd->regs, ATL_PTD_OFFSET, slot, &ptd);
1080 if (priv->atl_queued == 2)
1081 reg_write32(hcd->regs, HC_INTERRUPT_ENABLE,
1082 INTERRUPT_ENABLE_SOT_MASK);
1084 buffstatus = reg_read32(hcd->regs,
1085 HC_BUFFER_STATUS_REG);
1086 buffstatus |= ATL_BUFFER;
1087 reg_write32(hcd->regs, HC_BUFFER_STATUS_REG,
1092 error = check_error(hcd, &ptd);
1095 priv->atl_ints[slot].qh->toggle = 0;
1096 priv->atl_ints[slot].qh->ping = 0;
1097 qtd->urb->status = -EPIPE;
1100 printk(KERN_ERR "Error in %s().\n", __func__);
1101 printk(KERN_ERR "IN dw0: %08x dw1: %08x dw2: %08x "
1102 "dw3: %08x dw4: %08x dw5: %08x dw6: "
1104 ptd.dw0, ptd.dw1, ptd.dw2, ptd.dw3,
1105 ptd.dw4, ptd.dw5, ptd.dw6, ptd.dw7);
1108 priv->atl_ints[slot].qh->toggle = ptd.dw3 & (1 << 25);
1109 priv->atl_ints[slot].qh->ping = ptd.dw3 & (1 << 26);
1112 length = PTD_XFERRED_LENGTH(ptd.dw3);
1114 switch (DW1_GET_PID(ptd.dw1)) {
1116 mem_reads8(hcd->regs, qtd->payload_addr,
1117 qtd->data_buffer, length);
1121 qtd->urb->actual_length += length;
1128 priv->atl_ints[slot].qtd = NULL;
1129 priv->atl_ints[slot].qh = NULL;
1133 reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, skip_map);
1135 if (qtd->urb->status == -EPIPE) {
1136 /* HALT was received */
1139 qtd = clean_up_qtdlist(qtd, qh);
1140 isp1760_urb_done(hcd, urb);
1142 } else if (usb_pipebulk(qtd->urb->pipe) &&
1143 (length < qtd->length)) {
1144 /* short BULK received */
1146 if (qtd->urb->transfer_flags & URB_SHORT_NOT_OK) {
1147 qtd->urb->status = -EREMOTEIO;
1148 dev_dbg(hcd->self.controller,
1149 "short bulk, %d instead %zu "
1150 "with URB_SHORT_NOT_OK flag.\n",
1151 length, qtd->length);
1154 if (qtd->urb->status == -EINPROGRESS)
1155 qtd->urb->status = 0;
1158 qtd = clean_up_qtdlist(qtd, qh);
1159 isp1760_urb_done(hcd, urb);
1161 } else if (last_qtd_of_urb(qtd, qh)) {
1162 /* that was the last qtd of that URB */
1164 if (qtd->urb->status == -EINPROGRESS)
1165 qtd->urb->status = 0;
1168 qtd = clean_up_qtdlist(qtd, qh);
1169 isp1760_urb_done(hcd, urb);
1172 /* next QTD of this URB */
1174 qtd = clean_this_qtd(qtd, qh);
1179 enqueue_an_ATL_packet(hcd, qh, qtd);
1181 skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG);
1183 if (priv->atl_queued <= 1)
1184 reg_write32(hcd->regs, HC_INTERRUPT_ENABLE,
1185 INTERRUPT_ENABLE_MASK);
1188 static void do_intl_int(struct usb_hcd *hcd)
1190 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1191 u32 done_map, skip_map;
1198 struct isp1760_qtd *qtd;
1199 struct isp1760_qh *qh;
1201 done_map = reg_read32(hcd->regs, HC_INT_PTD_DONEMAP_REG);
1202 skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG);
1204 or_map = reg_read32(hcd->regs, HC_INT_IRQ_MASK_OR_REG);
1205 or_map &= ~done_map;
1206 reg_write32(hcd->regs, HC_INT_IRQ_MASK_OR_REG, or_map);
1209 slot = __ffs(done_map);
1210 done_map &= ~(1 << slot);
1211 skip_map |= (1 << slot);
1213 qtd = priv->int_ints[slot].qtd;
1214 qh = priv->int_ints[slot].qh;
1217 dev_err(hcd->self.controller, "(INT) qh is 0\n");
1221 ptd_read(hcd->regs, INT_PTD_OFFSET, slot, &ptd);
1222 check_int_err_status(hcd, ptd.dw4);
1224 error = check_error(hcd, &ptd);
1227 printk(KERN_ERR "Error in %s().\n", __func__);
1228 printk(KERN_ERR "IN dw0: %08x dw1: %08x dw2: %08x "
1229 "dw3: %08x dw4: %08x dw5: %08x dw6: "
1231 ptd.dw0, ptd.dw1, ptd.dw2, ptd.dw3,
1232 ptd.dw4, ptd.dw5, ptd.dw6, ptd.dw7);
1234 qtd->urb->status = -EPIPE;
1235 priv->int_ints[slot].qh->toggle = 0;
1236 priv->int_ints[slot].qh->ping = 0;
1239 priv->int_ints[slot].qh->toggle = ptd.dw3 & (1 << 25);
1240 priv->int_ints[slot].qh->ping = ptd.dw3 & (1 << 26);
1243 if (qtd->urb->dev->speed != USB_SPEED_HIGH)
1244 length = PTD_XFERRED_LENGTH_LO(ptd.dw3);
1246 length = PTD_XFERRED_LENGTH(ptd.dw3);
1249 switch (DW1_GET_PID(ptd.dw1)) {
1251 mem_reads8(hcd->regs, qtd->payload_addr,
1252 qtd->data_buffer, length);
1255 qtd->urb->actual_length += length;
1262 priv->int_ints[slot].qtd = NULL;
1263 priv->int_ints[slot].qh = NULL;
1265 reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, skip_map);
1268 if (qtd->urb->status == -EPIPE) {
1272 qtd = clean_up_qtdlist(qtd, qh);
1273 isp1760_urb_done(hcd, urb);
1275 } else if (last_qtd_of_urb(qtd, qh)) {
1277 if (qtd->urb->status == -EINPROGRESS)
1278 qtd->urb->status = 0;
1281 qtd = clean_up_qtdlist(qtd, qh);
1282 isp1760_urb_done(hcd, urb);
1285 /* next QTD of this URB */
1287 qtd = clean_this_qtd(qtd, qh);
1292 enqueue_an_INT_packet(hcd, qh, qtd);
1294 skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG);
1298 static struct isp1760_qh *qh_make(struct usb_hcd *hcd, struct urb *urb,
1301 struct isp1760_qh *qh;
1304 qh = isp1760_qh_alloc(flags);
1309 * init endpoint/device data for this QH
1311 is_input = usb_pipein(urb->pipe);
1312 type = usb_pipetype(urb->pipe);
1314 if (!usb_pipecontrol(urb->pipe))
1315 usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe), !is_input,
1321 * For control/bulk/interrupt, return QH with these TDs appended.
1322 * Allocates and initializes the QH if necessary.
1323 * Returns null if it can't allocate a QH it needs to.
1324 * If the QH has TDs (urbs) already, that's great.
1326 static struct isp1760_qh *qh_append_tds(struct usb_hcd *hcd,
1327 struct urb *urb, struct list_head *qtd_list, int epnum,
1330 struct isp1760_qh *qh;
1332 qh = (struct isp1760_qh *)*ptr;
1334 /* can't sleep here, we have priv->lock... */
1335 qh = qh_make(hcd, urb, GFP_ATOMIC);
1341 list_splice(qtd_list, qh->qtd_list.prev);
1346 static void qtd_list_free(struct urb *urb, struct list_head *qtd_list)
1348 struct list_head *entry, *temp;
1350 list_for_each_safe(entry, temp, qtd_list) {
1351 struct isp1760_qtd *qtd;
1353 qtd = list_entry(entry, struct isp1760_qtd, qtd_list);
1354 list_del(&qtd->qtd_list);
1355 isp1760_qtd_free(qtd);
1359 static int isp1760_prepare_enqueue(struct usb_hcd *hcd, struct urb *urb,
1360 struct list_head *qtd_list, gfp_t mem_flags, packet_enqueue *p)
1362 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1363 struct isp1760_qtd *qtd;
1365 unsigned long flags;
1366 struct isp1760_qh *qh = NULL;
1370 qtd = list_entry(qtd_list->next, struct isp1760_qtd, qtd_list);
1371 epnum = urb->ep->desc.bEndpointAddress;
1373 spin_lock_irqsave(&priv->lock, flags);
1374 if (!HCD_HW_ACCESSIBLE(hcd)) {
1378 rc = usb_hcd_link_urb_to_ep(hcd, urb);
1382 qh = urb->ep->hcpriv;
1384 qh_busy = !list_empty(&qh->qtd_list);
1388 qh = qh_append_tds(hcd, urb, qtd_list, epnum, &urb->ep->hcpriv);
1390 usb_hcd_unlink_urb_from_ep(hcd, urb);
1399 spin_unlock_irqrestore(&priv->lock, flags);
1401 qtd_list_free(urb, qtd_list);
1405 static struct isp1760_qtd *isp1760_qtd_alloc(gfp_t flags)
1407 struct isp1760_qtd *qtd;
1409 qtd = kmem_cache_zalloc(qtd_cachep, flags);
1411 INIT_LIST_HEAD(&qtd->qtd_list);
1417 * create a list of filled qtds for this URB; won't link into qh.
1419 #define max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
1420 static struct list_head *qh_urb_transaction(struct usb_hcd *hcd,
1421 struct urb *urb, struct list_head *head, gfp_t flags)
1423 struct isp1760_qtd *qtd;
1430 * URBs map to sequences of QTDs: one logical transaction
1432 qtd = isp1760_qtd_alloc(flags);
1436 list_add_tail(&qtd->qtd_list, head);
1438 urb->status = -EINPROGRESS;
1441 /* for split transactions, SplitXState initialized to zero */
1443 len = urb->transfer_buffer_length;
1444 is_input = usb_pipein(urb->pipe);
1445 if (usb_pipecontrol(urb->pipe)) {
1447 qtd_fill(qtd, urb->setup_packet,
1448 sizeof(struct usb_ctrlrequest),
1451 /* ... and always at least one more pid */
1452 qtd = isp1760_qtd_alloc(flags);
1456 list_add_tail(&qtd->qtd_list, head);
1458 /* for zero length DATA stages, STATUS is always IN */
1464 * data transfer stage: buffer setup
1466 buf = urb->transfer_buffer;
1473 maxpacket = max_packet(usb_maxpacket(urb->dev, urb->pipe, !is_input));
1476 * buffer gets wrapped in one or more qtds;
1477 * last one may be "short" (including zero len)
1478 * and may serve as a control status ack
1484 /* XXX This looks like usb storage / SCSI bug */
1485 dev_err(hcd->self.controller, "buf is null, dma is %08lx len is %d\n",
1486 (long unsigned)urb->transfer_dma, len);
1490 this_qtd_len = qtd_fill(qtd, buf, len, token);
1491 len -= this_qtd_len;
1492 buf += this_qtd_len;
1497 qtd = isp1760_qtd_alloc(flags);
1501 list_add_tail(&qtd->qtd_list, head);
1505 * control requests may need a terminating data "status" ack;
1506 * bulk ones may need a terminating short packet (zero length).
1508 if (urb->transfer_buffer_length != 0) {
1511 if (usb_pipecontrol(urb->pipe)) {
1513 /* "in" <--> "out" */
1515 } else if (usb_pipebulk(urb->pipe)
1516 && (urb->transfer_flags & URB_ZERO_PACKET)
1517 && !(urb->transfer_buffer_length % maxpacket)) {
1521 qtd = isp1760_qtd_alloc(flags);
1525 list_add_tail(&qtd->qtd_list, head);
1527 /* never any data in such packets */
1528 qtd_fill(qtd, NULL, 0, token);
1536 qtd_list_free(urb, head);
1540 static int isp1760_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
1543 struct list_head qtd_list;
1546 INIT_LIST_HEAD(&qtd_list);
1548 switch (usb_pipetype(urb->pipe)) {
1551 if (!qh_urb_transaction(hcd, urb, &qtd_list, mem_flags))
1553 pe = enqueue_an_ATL_packet;
1556 case PIPE_INTERRUPT:
1557 if (!qh_urb_transaction(hcd, urb, &qtd_list, mem_flags))
1559 pe = enqueue_an_INT_packet;
1562 case PIPE_ISOCHRONOUS:
1563 dev_err(hcd->self.controller, "PIPE_ISOCHRONOUS ain't supported\n");
1568 return isp1760_prepare_enqueue(hcd, urb, &qtd_list, mem_flags, pe);
1571 static int isp1760_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1573 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1574 struct inter_packet_info *ints;
1576 u32 reg_base, or_reg, skip_reg;
1577 unsigned long flags;
1581 switch (usb_pipetype(urb->pipe)) {
1582 case PIPE_ISOCHRONOUS:
1586 case PIPE_INTERRUPT:
1587 ints = priv->int_ints;
1588 reg_base = INT_PTD_OFFSET;
1589 or_reg = HC_INT_IRQ_MASK_OR_REG;
1590 skip_reg = HC_INT_PTD_SKIPMAP_REG;
1591 pe = enqueue_an_INT_packet;
1595 ints = priv->atl_ints;
1596 reg_base = ATL_PTD_OFFSET;
1597 or_reg = HC_ATL_IRQ_MASK_OR_REG;
1598 skip_reg = HC_ATL_PTD_SKIPMAP_REG;
1599 pe = enqueue_an_ATL_packet;
1603 memset(&ptd, 0, sizeof(ptd));
1604 spin_lock_irqsave(&priv->lock, flags);
1606 for (i = 0; i < 32; i++) {
1609 BUG_ON(!ints[i].qtd);
1611 if (ints[i].qtd->urb == urb) {
1614 struct isp1760_qtd *qtd;
1615 struct isp1760_qh *qh;
1617 skip_map = reg_read32(hcd->regs, skip_reg);
1619 reg_write32(hcd->regs, skip_reg, skip_map);
1621 or_map = reg_read32(hcd->regs, or_reg);
1622 or_map &= ~(1 << i);
1623 reg_write32(hcd->regs, or_reg, or_map);
1625 ptd_write(hcd->regs, reg_base, i, &ptd);
1631 qtd = clean_up_qtdlist(qtd, qh);
1636 urb->status = status;
1637 isp1760_urb_done(hcd, urb);
1643 struct isp1760_qtd *qtd;
1645 list_for_each_entry(qtd, &ints[i].qtd->qtd_list,
1647 if (qtd->urb == urb) {
1648 clean_up_qtdlist(qtd, ints[i].qh);
1649 isp1760_urb_done(hcd, urb);
1655 /* We found the urb before the last slot */
1661 spin_unlock_irqrestore(&priv->lock, flags);
1665 static irqreturn_t isp1760_irq(struct usb_hcd *hcd)
1667 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1669 irqreturn_t irqret = IRQ_NONE;
1671 spin_lock(&priv->lock);
1673 if (!(hcd->state & HC_STATE_RUNNING))
1676 imask = reg_read32(hcd->regs, HC_INTERRUPT_REG);
1677 if (unlikely(!imask))
1680 reg_write32(hcd->regs, HC_INTERRUPT_REG, imask);
1681 if (imask & (HC_ATL_INT | HC_SOT_INT))
1684 if (imask & HC_INTL_INT)
1687 irqret = IRQ_HANDLED;
1689 spin_unlock(&priv->lock);
1693 static int isp1760_hub_status_data(struct usb_hcd *hcd, char *buf)
1695 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1696 u32 temp, status = 0;
1699 unsigned long flags;
1701 /* if !USB_SUSPEND, root hub timers won't get shut down ... */
1702 if (!HC_IS_RUNNING(hcd->state))
1705 /* init status to no-changes */
1709 spin_lock_irqsave(&priv->lock, flags);
1710 temp = reg_read32(hcd->regs, HC_PORTSC1);
1712 if (temp & PORT_OWNER) {
1713 if (temp & PORT_CSC) {
1715 reg_write32(hcd->regs, HC_PORTSC1, temp);
1721 * Return status information even for ports with OWNER set.
1722 * Otherwise khubd wouldn't see the disconnect event when a
1723 * high-speed device is switched over to the companion
1724 * controller by the user.
1727 if ((temp & mask) != 0
1728 || ((temp & PORT_RESUME) != 0
1729 && time_after_eq(jiffies,
1730 priv->reset_done))) {
1731 buf [0] |= 1 << (0 + 1);
1734 /* FIXME autosuspend idle root hubs */
1736 spin_unlock_irqrestore(&priv->lock, flags);
1737 return status ? retval : 0;
1740 static void isp1760_hub_descriptor(struct isp1760_hcd *priv,
1741 struct usb_hub_descriptor *desc)
1743 int ports = HCS_N_PORTS(priv->hcs_params);
1746 desc->bDescriptorType = 0x29;
1747 /* priv 1.0, 2.3.9 says 20ms max */
1748 desc->bPwrOn2PwrGood = 10;
1749 desc->bHubContrCurrent = 0;
1751 desc->bNbrPorts = ports;
1752 temp = 1 + (ports / 8);
1753 desc->bDescLength = 7 + 2 * temp;
1755 /* ports removable, and usb 1.0 legacy PortPwrCtrlMask */
1756 memset(&desc->u.hs.DeviceRemovable[0], 0, temp);
1757 memset(&desc->u.hs.DeviceRemovable[temp], 0xff, temp);
1759 /* per-port overcurrent reporting */
1761 if (HCS_PPC(priv->hcs_params))
1762 /* per-port power control */
1765 /* no power switching */
1767 desc->wHubCharacteristics = cpu_to_le16(temp);
1770 #define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E)
1772 static int check_reset_complete(struct usb_hcd *hcd, int index,
1775 if (!(port_status & PORT_CONNECT))
1778 /* if reset finished and it's still not enabled -- handoff */
1779 if (!(port_status & PORT_PE)) {
1781 dev_err(hcd->self.controller,
1782 "port %d full speed --> companion\n",
1785 port_status |= PORT_OWNER;
1786 port_status &= ~PORT_RWC_BITS;
1787 reg_write32(hcd->regs, HC_PORTSC1, port_status);
1790 dev_err(hcd->self.controller, "port %d high speed\n",
1796 static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq,
1797 u16 wValue, u16 wIndex, char *buf, u16 wLength)
1799 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1800 int ports = HCS_N_PORTS(priv->hcs_params);
1802 unsigned long flags;
1807 * FIXME: support SetPortFeatures USB_PORT_FEAT_INDICATOR.
1808 * HCS_INDICATOR may say we can change LEDs to off/amber/green.
1809 * (track current state ourselves) ... blink for diagnostics,
1810 * power, "this is the one", etc. EHCI spec supports this.
1813 spin_lock_irqsave(&priv->lock, flags);
1815 case ClearHubFeature:
1817 case C_HUB_LOCAL_POWER:
1818 case C_HUB_OVER_CURRENT:
1819 /* no hub-wide feature/status flags */
1825 case ClearPortFeature:
1826 if (!wIndex || wIndex > ports)
1829 temp = reg_read32(hcd->regs, HC_PORTSC1);
1832 * Even if OWNER is set, so the port is owned by the
1833 * companion controller, khubd needs to be able to clear
1834 * the port-change status bits (especially
1835 * USB_PORT_STAT_C_CONNECTION).
1839 case USB_PORT_FEAT_ENABLE:
1840 reg_write32(hcd->regs, HC_PORTSC1, temp & ~PORT_PE);
1842 case USB_PORT_FEAT_C_ENABLE:
1845 case USB_PORT_FEAT_SUSPEND:
1846 if (temp & PORT_RESET)
1849 if (temp & PORT_SUSPEND) {
1850 if ((temp & PORT_PE) == 0)
1852 /* resume signaling for 20 msec */
1853 temp &= ~(PORT_RWC_BITS);
1854 reg_write32(hcd->regs, HC_PORTSC1,
1855 temp | PORT_RESUME);
1856 priv->reset_done = jiffies +
1857 msecs_to_jiffies(20);
1860 case USB_PORT_FEAT_C_SUSPEND:
1861 /* we auto-clear this feature */
1863 case USB_PORT_FEAT_POWER:
1864 if (HCS_PPC(priv->hcs_params))
1865 reg_write32(hcd->regs, HC_PORTSC1,
1866 temp & ~PORT_POWER);
1868 case USB_PORT_FEAT_C_CONNECTION:
1869 reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_CSC);
1871 case USB_PORT_FEAT_C_OVER_CURRENT:
1874 case USB_PORT_FEAT_C_RESET:
1875 /* GetPortStatus clears reset */
1880 reg_read32(hcd->regs, HC_USBCMD);
1882 case GetHubDescriptor:
1883 isp1760_hub_descriptor(priv, (struct usb_hub_descriptor *)
1887 /* no hub-wide feature/status flags */
1891 if (!wIndex || wIndex > ports)
1895 temp = reg_read32(hcd->regs, HC_PORTSC1);
1897 /* wPortChange bits */
1898 if (temp & PORT_CSC)
1899 status |= USB_PORT_STAT_C_CONNECTION << 16;
1902 /* whoever resumes must GetPortStatus to complete it!! */
1903 if (temp & PORT_RESUME) {
1904 dev_err(hcd->self.controller, "Port resume should be skipped.\n");
1906 /* Remote Wakeup received? */
1907 if (!priv->reset_done) {
1908 /* resume signaling for 20 msec */
1909 priv->reset_done = jiffies
1910 + msecs_to_jiffies(20);
1911 /* check the port again */
1912 mod_timer(&hcd->rh_timer, priv->reset_done);
1915 /* resume completed? */
1916 else if (time_after_eq(jiffies,
1917 priv->reset_done)) {
1918 status |= USB_PORT_STAT_C_SUSPEND << 16;
1919 priv->reset_done = 0;
1921 /* stop resume signaling */
1922 temp = reg_read32(hcd->regs, HC_PORTSC1);
1923 reg_write32(hcd->regs, HC_PORTSC1,
1924 temp & ~(PORT_RWC_BITS | PORT_RESUME));
1925 retval = handshake(hcd, HC_PORTSC1,
1926 PORT_RESUME, 0, 2000 /* 2msec */);
1928 dev_err(hcd->self.controller,
1929 "port %d resume error %d\n",
1930 wIndex + 1, retval);
1933 temp &= ~(PORT_SUSPEND|PORT_RESUME|(3<<10));
1937 /* whoever resets must GetPortStatus to complete it!! */
1938 if ((temp & PORT_RESET)
1939 && time_after_eq(jiffies,
1940 priv->reset_done)) {
1941 status |= USB_PORT_STAT_C_RESET << 16;
1942 priv->reset_done = 0;
1944 /* force reset to complete */
1945 reg_write32(hcd->regs, HC_PORTSC1, temp & ~PORT_RESET);
1946 /* REVISIT: some hardware needs 550+ usec to clear
1947 * this bit; seems too long to spin routinely...
1949 retval = handshake(hcd, HC_PORTSC1,
1950 PORT_RESET, 0, 750);
1952 dev_err(hcd->self.controller, "port %d reset error %d\n",
1953 wIndex + 1, retval);
1957 /* see what we found out */
1958 temp = check_reset_complete(hcd, wIndex,
1959 reg_read32(hcd->regs, HC_PORTSC1));
1962 * Even if OWNER is set, there's no harm letting khubd
1963 * see the wPortStatus values (they should all be 0 except
1964 * for PORT_POWER anyway).
1967 if (temp & PORT_OWNER)
1968 dev_err(hcd->self.controller, "PORT_OWNER is set\n");
1970 if (temp & PORT_CONNECT) {
1971 status |= USB_PORT_STAT_CONNECTION;
1972 /* status may be from integrated TT */
1973 status |= USB_PORT_STAT_HIGH_SPEED;
1976 status |= USB_PORT_STAT_ENABLE;
1977 if (temp & (PORT_SUSPEND|PORT_RESUME))
1978 status |= USB_PORT_STAT_SUSPEND;
1979 if (temp & PORT_RESET)
1980 status |= USB_PORT_STAT_RESET;
1981 if (temp & PORT_POWER)
1982 status |= USB_PORT_STAT_POWER;
1984 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
1988 case C_HUB_LOCAL_POWER:
1989 case C_HUB_OVER_CURRENT:
1990 /* no hub-wide feature/status flags */
1996 case SetPortFeature:
1997 selector = wIndex >> 8;
1999 if (!wIndex || wIndex > ports)
2002 temp = reg_read32(hcd->regs, HC_PORTSC1);
2003 if (temp & PORT_OWNER)
2006 /* temp &= ~PORT_RWC_BITS; */
2008 case USB_PORT_FEAT_ENABLE:
2009 reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_PE);
2012 case USB_PORT_FEAT_SUSPEND:
2013 if ((temp & PORT_PE) == 0
2014 || (temp & PORT_RESET) != 0)
2017 reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_SUSPEND);
2019 case USB_PORT_FEAT_POWER:
2020 if (HCS_PPC(priv->hcs_params))
2021 reg_write32(hcd->regs, HC_PORTSC1,
2024 case USB_PORT_FEAT_RESET:
2025 if (temp & PORT_RESUME)
2027 /* line status bits may report this as low speed,
2028 * which can be fine if this root hub has a
2029 * transaction translator built in.
2031 if ((temp & (PORT_PE|PORT_CONNECT)) == PORT_CONNECT
2032 && PORT_USB11(temp)) {
2039 * caller must wait, then call GetPortStatus
2040 * usb 2.0 spec says 50 ms resets on root
2042 priv->reset_done = jiffies +
2043 msecs_to_jiffies(50);
2045 reg_write32(hcd->regs, HC_PORTSC1, temp);
2050 reg_read32(hcd->regs, HC_USBCMD);
2055 /* "stall" on error */
2058 spin_unlock_irqrestore(&priv->lock, flags);
2062 static void isp1760_endpoint_disable(struct usb_hcd *hcd,
2063 struct usb_host_endpoint *ep)
2065 struct isp1760_hcd *priv = hcd_to_priv(hcd);
2066 struct isp1760_qh *qh;
2067 struct isp1760_qtd *qtd;
2068 unsigned long flags;
2070 spin_lock_irqsave(&priv->lock, flags);
2077 /* more than entry might get removed */
2078 if (list_empty(&qh->qtd_list))
2081 qtd = list_first_entry(&qh->qtd_list, struct isp1760_qtd,
2084 if (qtd->status & URB_ENQUEUED) {
2085 spin_unlock_irqrestore(&priv->lock, flags);
2086 isp1760_urb_dequeue(hcd, qtd->urb, -ECONNRESET);
2087 spin_lock_irqsave(&priv->lock, flags);
2092 clean_up_qtdlist(qtd, qh);
2093 urb->status = -ECONNRESET;
2094 isp1760_urb_done(hcd, urb);
2099 /* remove requests and leak them.
2100 * ATL are pretty fast done, INT could take a while...
2101 * The latter shoule be removed
2104 spin_unlock_irqrestore(&priv->lock, flags);
2107 static int isp1760_get_frame(struct usb_hcd *hcd)
2109 struct isp1760_hcd *priv = hcd_to_priv(hcd);
2112 fr = reg_read32(hcd->regs, HC_FRINDEX);
2113 return (fr >> 3) % priv->periodic_size;
2116 static void isp1760_stop(struct usb_hcd *hcd)
2118 struct isp1760_hcd *priv = hcd_to_priv(hcd);
2121 isp1760_hub_control(hcd, ClearPortFeature, USB_PORT_FEAT_POWER, 1,
2125 spin_lock_irq(&priv->lock);
2128 temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL);
2129 reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp &= ~HW_GLOBAL_INTR_EN);
2130 spin_unlock_irq(&priv->lock);
2132 reg_write32(hcd->regs, HC_CONFIGFLAG, 0);
2135 static void isp1760_shutdown(struct usb_hcd *hcd)
2140 temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL);
2141 reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp &= ~HW_GLOBAL_INTR_EN);
2143 command = reg_read32(hcd->regs, HC_USBCMD);
2144 command &= ~CMD_RUN;
2145 reg_write32(hcd->regs, HC_USBCMD, command);
2148 static const struct hc_driver isp1760_hc_driver = {
2149 .description = "isp1760-hcd",
2150 .product_desc = "NXP ISP1760 USB Host Controller",
2151 .hcd_priv_size = sizeof(struct isp1760_hcd),
2153 .flags = HCD_MEMORY | HCD_USB2,
2154 .reset = isp1760_hc_setup,
2155 .start = isp1760_run,
2156 .stop = isp1760_stop,
2157 .shutdown = isp1760_shutdown,
2158 .urb_enqueue = isp1760_urb_enqueue,
2159 .urb_dequeue = isp1760_urb_dequeue,
2160 .endpoint_disable = isp1760_endpoint_disable,
2161 .get_frame_number = isp1760_get_frame,
2162 .hub_status_data = isp1760_hub_status_data,
2163 .hub_control = isp1760_hub_control,
2166 int __init init_kmem_once(void)
2168 qtd_cachep = kmem_cache_create("isp1760_qtd",
2169 sizeof(struct isp1760_qtd), 0, SLAB_TEMPORARY |
2170 SLAB_MEM_SPREAD, NULL);
2175 qh_cachep = kmem_cache_create("isp1760_qh", sizeof(struct isp1760_qh),
2176 0, SLAB_TEMPORARY | SLAB_MEM_SPREAD, NULL);
2179 kmem_cache_destroy(qtd_cachep);
2186 void deinit_kmem_cache(void)
2188 kmem_cache_destroy(qtd_cachep);
2189 kmem_cache_destroy(qh_cachep);
2192 struct usb_hcd *isp1760_register(phys_addr_t res_start, resource_size_t res_len,
2193 int irq, unsigned long irqflags,
2194 struct device *dev, const char *busname,
2195 unsigned int devflags)
2197 struct usb_hcd *hcd;
2198 struct isp1760_hcd *priv;
2202 return ERR_PTR(-ENODEV);
2204 /* prevent usb-core allocating DMA pages */
2205 dev->dma_mask = NULL;
2207 hcd = usb_create_hcd(&isp1760_hc_driver, dev, dev_name(dev));
2209 return ERR_PTR(-ENOMEM);
2211 priv = hcd_to_priv(hcd);
2212 priv->devflags = devflags;
2214 hcd->regs = ioremap(res_start, res_len);
2221 hcd->rsrc_start = res_start;
2222 hcd->rsrc_len = res_len;
2224 ret = usb_add_hcd(hcd, irq, irqflags);
2236 return ERR_PTR(ret);
2239 MODULE_DESCRIPTION("Driver for the ISP1760 USB-controller from NXP");
2240 MODULE_AUTHOR("Sebastian Siewior <bigeasy@linuxtronix.de>");
2241 MODULE_LICENSE("GPL v2");