2 * Driver for the NXP ISP1760 chip
4 * However, the code might contain some bugs. What doesn't work for sure is:
7 e The interrupt line is configured as active low, level.
9 * (c) 2007 Sebastian Siewior <bigeasy@linutronix.de>
11 * (c) 2011 Arvid Brodin <arvid.brodin@enea.com>
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/slab.h>
17 #include <linux/list.h>
18 #include <linux/usb.h>
19 #include <linux/usb/hcd.h>
20 #include <linux/debugfs.h>
21 #include <linux/uaccess.h>
24 #include <asm/unaligned.h>
25 #include <asm/cacheflush.h>
27 #include "isp1760-hcd.h"
29 static struct kmem_cache *qtd_cachep;
30 static struct kmem_cache *qh_cachep;
31 static struct kmem_cache *urb_listitem_cachep;
36 struct slotinfo atl_slots[32];
37 struct slotinfo int_slots[32];
38 struct memory_chunk memory_pool[BLOCKS];
39 struct list_head controlqhs, bulkqhs, interruptqhs;
42 /* periodic schedule support */
43 #define DEFAULT_I_TDPS 1024
44 unsigned periodic_size;
46 unsigned long reset_done;
47 unsigned long next_statechange;
48 unsigned int devflags;
51 static inline struct isp1760_hcd *hcd_to_priv(struct usb_hcd *hcd)
53 return (struct isp1760_hcd *) (hcd->hcd_priv);
56 /* Section 2.2 Host Controller Capability Registers */
57 #define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */
58 #define HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */
59 #define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */
60 #define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */
61 #define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */
62 #define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */
63 #define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */
65 /* Section 2.3 Host Controller Operational Registers */
66 #define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */
67 #define CMD_RESET (1<<1) /* reset HC not bus */
68 #define CMD_RUN (1<<0) /* start/stop HC */
69 #define STS_PCD (1<<2) /* port change detect */
70 #define FLAG_CF (1<<0) /* true: we'll support "high speed" */
72 #define PORT_OWNER (1<<13) /* true: companion hc owns this port */
73 #define PORT_POWER (1<<12) /* true: has power (see PPC) */
74 #define PORT_USB11(x) (((x) & (3 << 10)) == (1 << 10)) /* USB 1.1 device */
75 #define PORT_RESET (1<<8) /* reset port */
76 #define PORT_SUSPEND (1<<7) /* suspend port */
77 #define PORT_RESUME (1<<6) /* resume it */
78 #define PORT_PE (1<<2) /* port enable */
79 #define PORT_CSC (1<<1) /* connect status change */
80 #define PORT_CONNECT (1<<0) /* device connected */
81 #define PORT_RWC_BITS (PORT_CSC)
88 /* the rest is HCD-private */
89 struct list_head qtd_list;
94 /* QTD_ENQUEUED: waiting for transfer (inactive) */
95 /* QTD_PAYLOAD_ALLOC: chip mem has been allocated for payload */
96 /* QTD_XFER_STARTED: valid ptd has been written to isp176x - only
97 interrupt handler may touch this qtd! */
98 /* QTD_XFER_COMPLETE: payload has been transferred successfully */
99 /* QTD_RETIRE: transfer error/abort qtd */
100 #define QTD_ENQUEUED 0
101 #define QTD_PAYLOAD_ALLOC 1
102 #define QTD_XFER_STARTED 2
103 #define QTD_XFER_COMPLETE 3
108 /* Queue head, one for each active endpoint */
110 struct list_head qh_list;
111 struct list_head qtd_list;
117 struct urb_listitem {
118 struct list_head urb_list;
123 * Access functions for isp176x registers (addresses 0..0x03FF).
125 static u32 reg_read32(void __iomem *base, u32 reg)
127 return readl(base + reg);
130 static void reg_write32(void __iomem *base, u32 reg, u32 val)
132 writel(val, base + reg);
136 * Access functions for isp176x memory (offset >= 0x0400).
138 * bank_reads8() reads memory locations prefetched by an earlier write to
139 * HC_MEMORY_REG (see isp176x datasheet). Unless you want to do fancy multi-
140 * bank optimizations, you should use the more generic mem_reads8() below.
142 * For access to ptd memory, use the specialized ptd_read() and ptd_write()
145 * These functions copy via MMIO data to/from the device. memcpy_{to|from}io()
146 * doesn't quite work because some people have to enforce 32-bit access
148 static void bank_reads8(void __iomem *src_base, u32 src_offset, u32 bank_addr,
149 __u32 *dst, u32 bytes)
156 src = src_base + (bank_addr | src_offset);
158 if (src_offset < PAYLOAD_OFFSET) {
160 *dst = le32_to_cpu(__raw_readl(src));
167 *dst = __raw_readl(src);
177 /* in case we have 3, 2 or 1 by left. The dst buffer may not be fully
180 if (src_offset < PAYLOAD_OFFSET)
181 val = le32_to_cpu(__raw_readl(src));
183 val = __raw_readl(src);
185 dst_byteptr = (void *) dst;
186 src_byteptr = (void *) &val;
188 *dst_byteptr = *src_byteptr;
195 static void mem_reads8(void __iomem *src_base, u32 src_offset, void *dst,
198 reg_write32(src_base, HC_MEMORY_REG, src_offset + ISP_BANK(0));
200 bank_reads8(src_base, src_offset, ISP_BANK(0), dst, bytes);
203 static void mem_writes8(void __iomem *dst_base, u32 dst_offset,
204 __u32 const *src, u32 bytes)
208 dst = dst_base + dst_offset;
210 if (dst_offset < PAYLOAD_OFFSET) {
212 __raw_writel(cpu_to_le32(*src), dst);
219 __raw_writel(*src, dst);
228 /* in case we have 3, 2 or 1 bytes left. The buffer is allocated and the
229 * extra bytes should not be read by the HW.
232 if (dst_offset < PAYLOAD_OFFSET)
233 __raw_writel(cpu_to_le32(*src), dst);
235 __raw_writel(*src, dst);
239 * Read and write ptds. 'ptd_offset' should be one of ISO_PTD_OFFSET,
240 * INT_PTD_OFFSET, and ATL_PTD_OFFSET. 'slot' should be less than 32.
242 static void ptd_read(void __iomem *base, u32 ptd_offset, u32 slot,
245 reg_write32(base, HC_MEMORY_REG,
246 ISP_BANK(0) + ptd_offset + slot*sizeof(*ptd));
248 bank_reads8(base, ptd_offset + slot*sizeof(*ptd), ISP_BANK(0),
249 (void *) ptd, sizeof(*ptd));
252 static void ptd_write(void __iomem *base, u32 ptd_offset, u32 slot,
255 mem_writes8(base, ptd_offset + slot*sizeof(*ptd) + sizeof(ptd->dw0),
256 &ptd->dw1, 7*sizeof(ptd->dw1));
257 /* Make sure dw0 gets written last (after other dw's and after payload)
258 since it contains the enable bit */
260 mem_writes8(base, ptd_offset + slot*sizeof(*ptd), &ptd->dw0,
265 /* memory management of the 60kb on the chip from 0x1000 to 0xffff */
266 static void init_memory(struct isp1760_hcd *priv)
271 payload_addr = PAYLOAD_OFFSET;
272 for (i = 0; i < BLOCK_1_NUM; i++) {
273 priv->memory_pool[i].start = payload_addr;
274 priv->memory_pool[i].size = BLOCK_1_SIZE;
275 priv->memory_pool[i].free = 1;
276 payload_addr += priv->memory_pool[i].size;
280 for (i = 0; i < BLOCK_2_NUM; i++) {
281 priv->memory_pool[curr + i].start = payload_addr;
282 priv->memory_pool[curr + i].size = BLOCK_2_SIZE;
283 priv->memory_pool[curr + i].free = 1;
284 payload_addr += priv->memory_pool[curr + i].size;
288 for (i = 0; i < BLOCK_3_NUM; i++) {
289 priv->memory_pool[curr + i].start = payload_addr;
290 priv->memory_pool[curr + i].size = BLOCK_3_SIZE;
291 priv->memory_pool[curr + i].free = 1;
292 payload_addr += priv->memory_pool[curr + i].size;
295 WARN_ON(payload_addr - priv->memory_pool[0].start > PAYLOAD_AREA_SIZE);
298 static void alloc_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd)
300 struct isp1760_hcd *priv = hcd_to_priv(hcd);
303 WARN_ON(qtd->payload_addr);
308 for (i = 0; i < BLOCKS; i++) {
309 if (priv->memory_pool[i].size >= qtd->length &&
310 priv->memory_pool[i].free) {
311 priv->memory_pool[i].free = 0;
312 qtd->payload_addr = priv->memory_pool[i].start;
318 static void free_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd)
320 struct isp1760_hcd *priv = hcd_to_priv(hcd);
323 if (!qtd->payload_addr)
326 for (i = 0; i < BLOCKS; i++) {
327 if (priv->memory_pool[i].start == qtd->payload_addr) {
328 WARN_ON(priv->memory_pool[i].free);
329 priv->memory_pool[i].free = 1;
330 qtd->payload_addr = 0;
335 dev_err(hcd->self.controller, "%s: Invalid pointer: %08x\n",
336 __func__, qtd->payload_addr);
338 qtd->payload_addr = 0;
341 static int handshake(struct usb_hcd *hcd, u32 reg,
342 u32 mask, u32 done, int usec)
347 result = reg_read32(hcd->regs, reg);
359 /* reset a non-running (STS_HALT == 1) controller */
360 static int ehci_reset(struct usb_hcd *hcd)
363 struct isp1760_hcd *priv = hcd_to_priv(hcd);
365 u32 command = reg_read32(hcd->regs, HC_USBCMD);
367 command |= CMD_RESET;
368 reg_write32(hcd->regs, HC_USBCMD, command);
369 hcd->state = HC_STATE_HALT;
370 priv->next_statechange = jiffies;
371 retval = handshake(hcd, HC_USBCMD,
372 CMD_RESET, 0, 250 * 1000);
376 static struct isp1760_qh *qh_alloc(gfp_t flags)
378 struct isp1760_qh *qh;
380 qh = kmem_cache_zalloc(qh_cachep, flags);
384 INIT_LIST_HEAD(&qh->qh_list);
385 INIT_LIST_HEAD(&qh->qtd_list);
391 static void qh_free(struct isp1760_qh *qh)
393 WARN_ON(!list_empty(&qh->qtd_list));
394 WARN_ON(qh->slot > -1);
395 kmem_cache_free(qh_cachep, qh);
398 /* one-time init, only for memory state */
399 static int priv_init(struct usb_hcd *hcd)
401 struct isp1760_hcd *priv = hcd_to_priv(hcd);
404 spin_lock_init(&priv->lock);
406 INIT_LIST_HEAD(&priv->interruptqhs);
407 INIT_LIST_HEAD(&priv->controlqhs);
408 INIT_LIST_HEAD(&priv->bulkqhs);
411 * hw default: 1K periodic list heads, one per frame.
412 * periodic_size can shrink by USBCMD update if hcc_params allows.
414 priv->periodic_size = DEFAULT_I_TDPS;
416 /* controllers may cache some of the periodic schedule ... */
417 hcc_params = reg_read32(hcd->regs, HC_HCCPARAMS);
418 /* full frame cache */
419 if (HCC_ISOC_CACHE(hcc_params))
421 else /* N microframes cached */
422 priv->i_thresh = 2 + HCC_ISOC_THRES(hcc_params);
427 static int isp1760_hc_setup(struct usb_hcd *hcd)
429 struct isp1760_hcd *priv = hcd_to_priv(hcd);
433 /* Setup HW Mode Control: This assumes a level active-low interrupt */
434 hwmode = HW_DATA_BUS_32BIT;
436 if (priv->devflags & ISP1760_FLAG_BUS_WIDTH_16)
437 hwmode &= ~HW_DATA_BUS_32BIT;
438 if (priv->devflags & ISP1760_FLAG_ANALOG_OC)
439 hwmode |= HW_ANA_DIGI_OC;
440 if (priv->devflags & ISP1760_FLAG_DACK_POL_HIGH)
441 hwmode |= HW_DACK_POL_HIGH;
442 if (priv->devflags & ISP1760_FLAG_DREQ_POL_HIGH)
443 hwmode |= HW_DREQ_POL_HIGH;
444 if (priv->devflags & ISP1760_FLAG_INTR_POL_HIGH)
445 hwmode |= HW_INTR_HIGH_ACT;
446 if (priv->devflags & ISP1760_FLAG_INTR_EDGE_TRIG)
447 hwmode |= HW_INTR_EDGE_TRIG;
450 * We have to set this first in case we're in 16-bit mode.
451 * Write it twice to ensure correct upper bits if switching
454 reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode);
455 reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode);
457 reg_write32(hcd->regs, HC_SCRATCH_REG, 0xdeadbabe);
458 /* Change bus pattern */
459 scratch = reg_read32(hcd->regs, HC_CHIP_ID_REG);
460 scratch = reg_read32(hcd->regs, HC_SCRATCH_REG);
461 if (scratch != 0xdeadbabe) {
462 dev_err(hcd->self.controller, "Scratch test failed.\n");
467 reg_write32(hcd->regs, HC_BUFFER_STATUS_REG, 0);
468 reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
469 reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
470 reg_write32(hcd->regs, HC_ISO_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
473 reg_write32(hcd->regs, HC_RESET_REG, SW_RESET_RESET_ALL);
476 reg_write32(hcd->regs, HC_RESET_REG, SW_RESET_RESET_HC);
479 result = ehci_reset(hcd);
485 dev_info(hcd->self.controller, "bus width: %d, oc: %s\n",
486 (priv->devflags & ISP1760_FLAG_BUS_WIDTH_16) ?
487 16 : 32, (priv->devflags & ISP1760_FLAG_ANALOG_OC) ?
488 "analog" : "digital");
490 /* This is weird: at the first plug-in of a device there seems to be
491 one packet queued that never gets returned? */
492 priv->active_ptds = -1;
495 reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode | ALL_ATX_RESET);
497 reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode);
499 reg_write32(hcd->regs, HC_INTERRUPT_ENABLE, INTERRUPT_ENABLE_MASK);
502 * PORT 1 Control register of the ISP1760 is the OTG control
503 * register on ISP1761. Since there is no OTG or device controller
504 * support in this driver, we use port 1 as a "normal" USB host port on
507 reg_write32(hcd->regs, HC_PORT1_CTRL, PORT1_POWER | PORT1_INIT2);
510 priv->hcs_params = reg_read32(hcd->regs, HC_HCSPARAMS);
512 return priv_init(hcd);
515 static void isp1760_init_maps(struct usb_hcd *hcd)
517 /*set last maps, for iso its only 1, else 32 tds bitmap*/
518 reg_write32(hcd->regs, HC_ATL_PTD_LASTPTD_REG, 0x80000000);
519 reg_write32(hcd->regs, HC_INT_PTD_LASTPTD_REG, 0x80000000);
520 reg_write32(hcd->regs, HC_ISO_PTD_LASTPTD_REG, 0x00000001);
522 reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, 0);
523 reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, 0);
524 reg_write32(hcd->regs, HC_ISO_PTD_SKIPMAP_REG, 0);
526 reg_write32(hcd->regs, HC_BUFFER_STATUS_REG,
527 ATL_BUF_FILL | INT_BUF_FILL);
530 static void isp1760_enable_interrupts(struct usb_hcd *hcd)
532 reg_write32(hcd->regs, HC_ATL_IRQ_MASK_AND_REG, 0);
533 reg_write32(hcd->regs, HC_ATL_IRQ_MASK_OR_REG, 0xffffffff);
534 reg_write32(hcd->regs, HC_INT_IRQ_MASK_AND_REG, 0);
535 reg_write32(hcd->regs, HC_INT_IRQ_MASK_OR_REG, 0xffffffff);
536 reg_write32(hcd->regs, HC_ISO_IRQ_MASK_AND_REG, 0);
537 reg_write32(hcd->regs, HC_ISO_IRQ_MASK_OR_REG, 0xffffffff);
541 static int isp1760_run(struct usb_hcd *hcd)
548 hcd->uses_new_polling = 1;
550 hcd->state = HC_STATE_RUNNING;
551 isp1760_enable_interrupts(hcd);
552 temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL);
553 reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp | HW_GLOBAL_INTR_EN);
555 command = reg_read32(hcd->regs, HC_USBCMD);
556 command &= ~(CMD_LRESET|CMD_RESET);
558 reg_write32(hcd->regs, HC_USBCMD, command);
560 retval = handshake(hcd, HC_USBCMD, CMD_RUN, CMD_RUN, 250 * 1000);
566 * Spec says to write FLAG_CF as last config action, priv code grabs
567 * the semaphore while doing so.
569 down_write(&ehci_cf_port_reset_rwsem);
570 reg_write32(hcd->regs, HC_CONFIGFLAG, FLAG_CF);
572 retval = handshake(hcd, HC_CONFIGFLAG, FLAG_CF, FLAG_CF, 250 * 1000);
573 up_write(&ehci_cf_port_reset_rwsem);
577 chipid = reg_read32(hcd->regs, HC_CHIP_ID_REG);
578 dev_info(hcd->self.controller, "USB ISP %04x HW rev. %d started\n",
579 chipid & 0xffff, chipid >> 16);
581 /* PTD Register Init Part 2, Step 28 */
583 isp1760_init_maps(hcd);
585 /* GRR this is run-once init(), being done every time the HC starts.
586 * So long as they're part of class devices, we can't do it init()
587 * since the class device isn't created that early.
592 static u32 base_to_chip(u32 base)
594 return ((base - 0x400) >> 3);
597 static int last_qtd_of_urb(struct isp1760_qtd *qtd, struct isp1760_qh *qh)
601 if (list_is_last(&qtd->qtd_list, &qh->qtd_list))
605 qtd = list_entry(qtd->qtd_list.next, typeof(*qtd), qtd_list);
606 return (qtd->urb != urb);
609 /* magic numbers that can affect system performance */
610 #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
611 #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
612 #define EHCI_TUNE_RL_TT 0
613 #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
614 #define EHCI_TUNE_MULT_TT 1
615 #define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */
617 static void create_ptd_atl(struct isp1760_qh *qh,
618 struct isp1760_qtd *qtd, struct ptd *ptd)
623 u32 nak = NAK_COUNTER;
625 memset(ptd, 0, sizeof(*ptd));
627 /* according to 3.6.2, max packet len can not be > 0x400 */
628 maxpacket = usb_maxpacket(qtd->urb->dev, qtd->urb->pipe,
629 usb_pipeout(qtd->urb->pipe));
630 multi = 1 + ((maxpacket >> 11) & 0x3);
634 ptd->dw0 = DW0_VALID_BIT;
635 ptd->dw0 |= TO_DW0_LENGTH(qtd->length);
636 ptd->dw0 |= TO_DW0_MAXPACKET(maxpacket);
637 ptd->dw0 |= TO_DW0_ENDPOINT(usb_pipeendpoint(qtd->urb->pipe));
640 ptd->dw1 = usb_pipeendpoint(qtd->urb->pipe) >> 1;
641 ptd->dw1 |= TO_DW1_DEVICE_ADDR(usb_pipedevice(qtd->urb->pipe));
642 ptd->dw1 |= TO_DW1_PID_TOKEN(qtd->packet_type);
644 if (usb_pipebulk(qtd->urb->pipe))
645 ptd->dw1 |= DW1_TRANS_BULK;
646 else if (usb_pipeint(qtd->urb->pipe))
647 ptd->dw1 |= DW1_TRANS_INT;
649 if (qtd->urb->dev->speed != USB_SPEED_HIGH) {
650 /* split transaction */
652 ptd->dw1 |= DW1_TRANS_SPLIT;
653 if (qtd->urb->dev->speed == USB_SPEED_LOW)
654 ptd->dw1 |= DW1_SE_USB_LOSPEED;
656 ptd->dw1 |= TO_DW1_PORT_NUM(qtd->urb->dev->ttport);
657 ptd->dw1 |= TO_DW1_HUB_NUM(qtd->urb->dev->tt->hub->devnum);
659 /* SE bit for Split INT transfers */
660 if (usb_pipeint(qtd->urb->pipe) &&
661 (qtd->urb->dev->speed == USB_SPEED_LOW))
667 ptd->dw0 |= TO_DW0_MULTI(multi);
668 if (usb_pipecontrol(qtd->urb->pipe) ||
669 usb_pipebulk(qtd->urb->pipe))
670 ptd->dw3 |= TO_DW3_PING(qh->ping);
674 ptd->dw2 |= TO_DW2_DATA_START_ADDR(base_to_chip(qtd->payload_addr));
675 ptd->dw2 |= TO_DW2_RL(rl);
678 ptd->dw3 |= TO_DW3_NAKCOUNT(nak);
679 ptd->dw3 |= TO_DW3_DATA_TOGGLE(qh->toggle);
680 if (usb_pipecontrol(qtd->urb->pipe)) {
681 if (qtd->data_buffer == qtd->urb->setup_packet)
682 ptd->dw3 &= ~TO_DW3_DATA_TOGGLE(1);
683 else if (last_qtd_of_urb(qtd, qh))
684 ptd->dw3 |= TO_DW3_DATA_TOGGLE(1);
687 ptd->dw3 |= DW3_ACTIVE_BIT;
689 ptd->dw3 |= TO_DW3_CERR(ERR_COUNTER);
692 static void transform_add_int(struct isp1760_qh *qh,
693 struct isp1760_qtd *qtd, struct ptd *ptd)
699 * Most of this is guessing. ISP1761 datasheet is quite unclear, and
700 * the algorithm from the original Philips driver code, which was
701 * pretty much used in this driver before as well, is quite horrendous
702 * and, i believe, incorrect. The code below follows the datasheet and
703 * USB2.0 spec as far as I can tell, and plug/unplug seems to be much
704 * more reliable this way (fingers crossed...).
707 if (qtd->urb->dev->speed == USB_SPEED_HIGH) {
708 /* urb->interval is in units of microframes (1/8 ms) */
709 period = qtd->urb->interval >> 3;
711 if (qtd->urb->interval > 4)
712 usof = 0x01; /* One bit set =>
713 interval 1 ms * uFrame-match */
714 else if (qtd->urb->interval > 2)
715 usof = 0x22; /* Two bits set => interval 1/2 ms */
716 else if (qtd->urb->interval > 1)
717 usof = 0x55; /* Four bits set => interval 1/4 ms */
719 usof = 0xff; /* All bits set => interval 1/8 ms */
721 /* urb->interval is in units of frames (1 ms) */
722 period = qtd->urb->interval;
723 usof = 0x0f; /* Execute Start Split on any of the
724 four first uFrames */
727 * First 8 bits in dw5 is uSCS and "specifies which uSOF the
728 * complete split needs to be sent. Valid only for IN." Also,
729 * "All bits can be set to one for every transfer." (p 82,
730 * ISP1761 data sheet.) 0x1c is from Philips driver. Where did
731 * that number come from? 0xff seems to work fine...
733 /* ptd->dw5 = 0x1c; */
734 ptd->dw5 = 0xff; /* Execute Complete Split on any uFrame */
737 period = period >> 1;/* Ensure equal or shorter period than requested */
738 period &= 0xf8; /* Mask off too large values and lowest unused 3 bits */
744 static void create_ptd_int(struct isp1760_qh *qh,
745 struct isp1760_qtd *qtd, struct ptd *ptd)
747 create_ptd_atl(qh, qtd, ptd);
748 transform_add_int(qh, qtd, ptd);
751 static void isp1760_urb_done(struct usb_hcd *hcd, struct urb *urb)
752 __releases(priv->lock)
753 __acquires(priv->lock)
755 struct isp1760_hcd *priv = hcd_to_priv(hcd);
757 if (!urb->unlinked) {
758 if (urb->status == -EINPROGRESS)
762 if (usb_pipein(urb->pipe) && usb_pipetype(urb->pipe) != PIPE_CONTROL) {
764 for (ptr = urb->transfer_buffer;
765 ptr < urb->transfer_buffer + urb->transfer_buffer_length;
767 flush_dcache_page(virt_to_page(ptr));
770 /* complete() can reenter this HCD */
771 usb_hcd_unlink_urb_from_ep(hcd, urb);
772 spin_unlock(&priv->lock);
773 usb_hcd_giveback_urb(hcd, urb, urb->status);
774 spin_lock(&priv->lock);
777 static struct isp1760_qtd *qtd_alloc(gfp_t flags, struct urb *urb,
780 struct isp1760_qtd *qtd;
782 qtd = kmem_cache_zalloc(qtd_cachep, flags);
786 INIT_LIST_HEAD(&qtd->qtd_list);
788 qtd->packet_type = packet_type;
789 qtd->status = QTD_ENQUEUED;
790 qtd->actual_length = 0;
795 static void qtd_free(struct isp1760_qtd *qtd)
797 WARN_ON(qtd->payload_addr);
798 kmem_cache_free(qtd_cachep, qtd);
801 static void start_bus_transfer(struct usb_hcd *hcd, u32 ptd_offset, int slot,
802 struct slotinfo *slots, struct isp1760_qtd *qtd,
803 struct isp1760_qh *qh, struct ptd *ptd)
805 struct isp1760_hcd *priv = hcd_to_priv(hcd);
806 WARN_ON((slot < 0) || (slot > 31));
807 WARN_ON(qtd->length && !qtd->payload_addr);
808 WARN_ON(slots[slot].qtd);
809 WARN_ON(slots[slot].qh);
810 WARN_ON(qtd->status != QTD_PAYLOAD_ALLOC);
812 slots[slot].qtd = qtd;
815 qtd->status = QTD_XFER_STARTED; /* Set this before writing ptd, since
816 interrupt routine may preempt and expects this value. */
817 ptd_write(hcd->regs, ptd_offset, slot, ptd);
821 static int is_short_bulk(struct isp1760_qtd *qtd)
823 return (usb_pipebulk(qtd->urb->pipe) &&
824 (qtd->actual_length < qtd->length));
827 static void collect_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh,
828 struct list_head *urb_list)
831 struct isp1760_qtd *qtd, *qtd_next;
832 struct urb_listitem *urb_listitem;
834 list_for_each_entry_safe(qtd, qtd_next, &qh->qtd_list, qtd_list) {
835 if (qtd->status < QTD_XFER_COMPLETE)
838 if (list_is_last(&qtd->qtd_list, &qh->qtd_list))
841 last_qtd = qtd->urb != qtd_next->urb;
843 if ((!last_qtd) && (qtd->status == QTD_RETIRE))
844 qtd_next->status = QTD_RETIRE;
846 if (qtd->status == QTD_XFER_COMPLETE) {
847 if (qtd->actual_length) {
848 switch (qtd->packet_type) {
850 mem_reads8(hcd->regs, qtd->payload_addr,
853 /* Fall through (?) */
855 qtd->urb->actual_length +=
857 /* Fall through ... */
863 if (is_short_bulk(qtd)) {
864 if (qtd->urb->transfer_flags & URB_SHORT_NOT_OK)
865 qtd->urb->status = -EREMOTEIO;
867 qtd_next->status = QTD_RETIRE;
871 if (qtd->payload_addr)
875 if ((qtd->status == QTD_RETIRE) &&
876 (qtd->urb->status == -EINPROGRESS))
877 qtd->urb->status = -EPIPE;
878 /* Defer calling of urb_done() since it releases lock */
879 urb_listitem = kmem_cache_zalloc(urb_listitem_cachep,
881 if (unlikely(!urb_listitem))
883 urb_listitem->urb = qtd->urb;
884 list_add_tail(&urb_listitem->urb_list, urb_list);
887 list_del(&qtd->qtd_list);
892 #define ENQUEUE_DEPTH 2
893 static void enqueue_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh)
895 struct isp1760_hcd *priv = hcd_to_priv(hcd);
897 struct slotinfo *slots;
898 int curr_slot, free_slot;
901 struct isp1760_qtd *qtd;
903 if (unlikely(list_empty(&qh->qtd_list))) {
908 if (usb_pipeint(list_entry(qh->qtd_list.next, struct isp1760_qtd,
909 qtd_list)->urb->pipe)) {
910 ptd_offset = INT_PTD_OFFSET;
911 slots = priv->int_slots;
913 ptd_offset = ATL_PTD_OFFSET;
914 slots = priv->atl_slots;
918 for (curr_slot = 0; curr_slot < 32; curr_slot++) {
919 if ((free_slot == -1) && (slots[curr_slot].qtd == NULL))
920 free_slot = curr_slot;
921 if (slots[curr_slot].qh == qh)
926 list_for_each_entry(qtd, &qh->qtd_list, qtd_list) {
927 if (qtd->status == QTD_ENQUEUED) {
928 WARN_ON(qtd->payload_addr);
930 if ((qtd->length) && (!qtd->payload_addr))
934 ((qtd->packet_type == SETUP_PID) ||
935 (qtd->packet_type == OUT_PID))) {
936 mem_writes8(hcd->regs, qtd->payload_addr,
937 qtd->data_buffer, qtd->length);
940 qtd->status = QTD_PAYLOAD_ALLOC;
943 if (qtd->status == QTD_PAYLOAD_ALLOC) {
945 if ((curr_slot > 31) && (free_slot == -1))
946 dev_dbg(hcd->self.controller, "%s: No slot "
947 "available for transfer\n", __func__);
949 /* Start xfer for this endpoint if not already done */
950 if ((curr_slot > 31) && (free_slot > -1)) {
951 if (usb_pipeint(qtd->urb->pipe))
952 create_ptd_int(qh, qtd, &ptd);
954 create_ptd_atl(qh, qtd, &ptd);
956 start_bus_transfer(hcd, ptd_offset, free_slot,
957 slots, qtd, qh, &ptd);
958 curr_slot = free_slot;
962 if (n >= ENQUEUE_DEPTH)
968 void schedule_ptds(struct usb_hcd *hcd)
970 struct isp1760_hcd *priv;
971 struct isp1760_qh *qh, *qh_next;
972 struct list_head *ep_queue;
973 struct usb_host_endpoint *ep;
975 struct urb_listitem *urb_listitem, *urb_listitem_next;
982 priv = hcd_to_priv(hcd);
985 * check finished/retired xfers, transfer payloads, call urb_done()
987 ep_queue = &priv->interruptqhs;
989 list_for_each_entry_safe(qh, qh_next, ep_queue, qh_list) {
990 ep = list_entry(qh->qtd_list.next, struct isp1760_qtd,
992 collect_qtds(hcd, qh, &urb_list);
993 if (list_empty(&qh->qtd_list)) {
994 list_del(&qh->qh_list);
995 if (ep->hcpriv == NULL) {
996 /* Endpoint has been disabled, so we
997 can free the associated queue head. */
1003 if (ep_queue == &priv->interruptqhs)
1004 ep_queue = &priv->controlqhs;
1005 else if (ep_queue == &priv->controlqhs)
1006 ep_queue = &priv->bulkqhs;
1011 list_for_each_entry_safe(urb_listitem, urb_listitem_next, &urb_list,
1013 isp1760_urb_done(hcd, urb_listitem->urb);
1014 kmem_cache_free(urb_listitem_cachep, urb_listitem);
1018 * Schedule packets for transfer.
1020 * According to USB2.0 specification:
1022 * 1st prio: interrupt xfers, up to 80 % of bandwidth
1023 * 2nd prio: control xfers
1024 * 3rd prio: bulk xfers
1026 * ... but let's use a simpler scheme here (mostly because ISP1761 doc
1027 * is very unclear on how to prioritize traffic):
1029 * 1) Enqueue any queued control transfers, as long as payload chip mem
1030 * and PTD ATL slots are available.
1031 * 2) Enqueue any queued INT transfers, as long as payload chip mem
1032 * and PTD INT slots are available.
1033 * 3) Enqueue any queued bulk transfers, as long as payload chip mem
1034 * and PTD ATL slots are available.
1036 * Use double buffering (ENQUEUE_DEPTH==2) as a compromise between
1037 * conservation of chip mem and performance.
1039 * I'm sure this scheme could be improved upon!
1041 ep_queue = &priv->controlqhs;
1043 list_for_each_entry_safe(qh, qh_next, ep_queue, qh_list)
1044 enqueue_qtds(hcd, qh);
1046 if (ep_queue == &priv->controlqhs)
1047 ep_queue = &priv->interruptqhs;
1048 else if (ep_queue == &priv->interruptqhs)
1049 ep_queue = &priv->bulkqhs;
1055 #define PTD_STATE_QTD_DONE 1
1056 #define PTD_STATE_QTD_RELOAD 2
1057 #define PTD_STATE_URB_RETIRE 3
1059 static int check_int_transfer(struct usb_hcd *hcd, struct ptd *ptd,
1068 /* FIXME: ISP1761 datasheet does not say what to do with these. Do we
1069 need to handle these errors? Is it done in hardware? */
1071 if (ptd->dw3 & DW3_HALT_BIT) {
1073 urb->status = -EPROTO; /* Default unknown error */
1075 for (i = 0; i < 8; i++) {
1076 switch (dw4 & 0x7) {
1078 dev_dbg(hcd->self.controller, "%s: underrun "
1079 "during uFrame %d\n",
1081 urb->status = -ECOMM; /* Could not write data */
1084 dev_dbg(hcd->self.controller, "%s: transaction "
1085 "error during uFrame %d\n",
1087 urb->status = -EPROTO; /* timeout, bad CRC, PID
1091 dev_dbg(hcd->self.controller, "%s: babble "
1092 "error during uFrame %d\n",
1094 urb->status = -EOVERFLOW;
1100 return PTD_STATE_URB_RETIRE;
1103 return PTD_STATE_QTD_DONE;
1106 static int check_atl_transfer(struct usb_hcd *hcd, struct ptd *ptd,
1110 if (ptd->dw3 & DW3_HALT_BIT) {
1111 if (ptd->dw3 & DW3_BABBLE_BIT)
1112 urb->status = -EOVERFLOW;
1113 else if (FROM_DW3_CERR(ptd->dw3))
1114 urb->status = -EPIPE; /* Stall */
1115 else if (ptd->dw3 & DW3_ERROR_BIT)
1116 urb->status = -EPROTO; /* XactErr */
1118 urb->status = -EPROTO; /* Unknown */
1120 dev_dbg(hcd->self.controller, "%s: ptd error:\n"
1121 " dw0: %08x dw1: %08x dw2: %08x dw3: %08x\n"
1122 " dw4: %08x dw5: %08x dw6: %08x dw7: %08x\n",
1124 ptd->dw0, ptd->dw1, ptd->dw2, ptd->dw3,
1125 ptd->dw4, ptd->dw5, ptd->dw6, ptd->dw7);
1127 return PTD_STATE_URB_RETIRE;
1130 if ((ptd->dw3 & DW3_ERROR_BIT) && (ptd->dw3 & DW3_ACTIVE_BIT)) {
1131 /* Transfer Error, *but* active and no HALT -> reload */
1132 dev_dbg(hcd->self.controller, "PID error; reloading ptd\n");
1133 return PTD_STATE_QTD_RELOAD;
1136 if (!FROM_DW3_NAKCOUNT(ptd->dw3) && (ptd->dw3 & DW3_ACTIVE_BIT)) {
1138 * NAKs are handled in HW by the chip. Usually if the
1139 * device is not able to send data fast enough.
1140 * This happens mostly on slower hardware.
1142 return PTD_STATE_QTD_RELOAD;
1145 return PTD_STATE_QTD_DONE;
1148 static irqreturn_t isp1760_irq(struct usb_hcd *hcd)
1150 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1152 irqreturn_t irqret = IRQ_NONE;
1154 struct isp1760_qh *qh;
1155 int int_done_map, atl_done_map;
1158 struct slotinfo *slots;
1160 struct isp1760_qtd *qtd;
1162 static int last_active_ptds;
1164 spin_lock(&priv->lock);
1166 if (!(hcd->state & HC_STATE_RUNNING))
1169 imask = reg_read32(hcd->regs, HC_INTERRUPT_REG);
1170 if (unlikely(!imask))
1172 reg_write32(hcd->regs, HC_INTERRUPT_REG, imask); /* Clear */
1174 int_done_map = reg_read32(hcd->regs, HC_INT_PTD_DONEMAP_REG);
1175 atl_done_map = reg_read32(hcd->regs, HC_ATL_PTD_DONEMAP_REG);
1176 modified = int_done_map | atl_done_map;
1178 while (int_done_map || atl_done_map) {
1181 slot = __ffs(int_done_map);
1182 int_done_map &= ~(1 << slot);
1183 slots = priv->int_slots;
1184 if (!slots[slot].qh)
1186 ptd_offset = INT_PTD_OFFSET;
1187 ptd_read(hcd->regs, INT_PTD_OFFSET, slot, &ptd);
1188 state = check_int_transfer(hcd, &ptd,
1189 slots[slot].qtd->urb);
1192 slot = __ffs(atl_done_map);
1193 atl_done_map &= ~(1 << slot);
1194 slots = priv->atl_slots;
1195 if (!slots[slot].qh)
1197 ptd_offset = ATL_PTD_OFFSET;
1198 ptd_read(hcd->regs, ATL_PTD_OFFSET, slot, &ptd);
1199 state = check_atl_transfer(hcd, &ptd,
1200 slots[slot].qtd->urb);
1203 qtd = slots[slot].qtd;
1204 slots[slot].qtd = NULL;
1205 qh = slots[slot].qh;
1206 slots[slot].qh = NULL;
1207 priv->active_ptds--;
1210 WARN_ON(qtd->status != QTD_XFER_STARTED);
1213 case PTD_STATE_QTD_DONE:
1214 if ((usb_pipeint(qtd->urb->pipe)) &&
1215 (qtd->urb->dev->speed != USB_SPEED_HIGH))
1216 qtd->actual_length =
1217 FROM_DW3_SCS_NRBYTESTRANSFERRED(ptd.dw3);
1219 qtd->actual_length =
1220 FROM_DW3_NRBYTESTRANSFERRED(ptd.dw3);
1222 qtd->status = QTD_XFER_COMPLETE;
1223 if (list_is_last(&qtd->qtd_list, &qh->qtd_list) ||
1227 qtd = list_entry(qtd->qtd_list.next,
1228 typeof(*qtd), qtd_list);
1230 qh->toggle = FROM_DW3_DATA_TOGGLE(ptd.dw3);
1231 qh->ping = FROM_DW3_PING(ptd.dw3);
1234 case PTD_STATE_QTD_RELOAD: /* QTD_RETRY, for atls only */
1235 qtd->status = QTD_PAYLOAD_ALLOC;
1236 ptd.dw0 |= DW0_VALID_BIT;
1237 /* RL counter = ERR counter */
1238 ptd.dw3 &= ~TO_DW3_NAKCOUNT(0xf);
1239 ptd.dw3 |= TO_DW3_NAKCOUNT(FROM_DW2_RL(ptd.dw2));
1240 ptd.dw3 &= ~TO_DW3_CERR(3);
1241 ptd.dw3 |= TO_DW3_CERR(ERR_COUNTER);
1242 qh->toggle = FROM_DW3_DATA_TOGGLE(ptd.dw3);
1243 qh->ping = FROM_DW3_PING(ptd.dw3);
1246 case PTD_STATE_URB_RETIRE:
1247 qtd->status = QTD_RETIRE;
1258 if (qtd && (qtd->status == QTD_PAYLOAD_ALLOC)) {
1259 if (slots == priv->int_slots) {
1260 if (state == PTD_STATE_QTD_RELOAD)
1261 dev_err(hcd->self.controller,
1262 "%s: PTD_STATE_QTD_RELOAD on "
1263 "interrupt packet\n", __func__);
1264 if (state != PTD_STATE_QTD_RELOAD)
1265 create_ptd_int(qh, qtd, &ptd);
1267 if (state != PTD_STATE_QTD_RELOAD)
1268 create_ptd_atl(qh, qtd, &ptd);
1271 start_bus_transfer(hcd, ptd_offset, slot, slots, qtd,
1279 /* ISP1760 Errata 2 explains that interrupts may be missed (or not
1280 happen?) if two USB devices are running simultaneously. Perhaps
1281 this happens when a PTD is finished during interrupt handling;
1282 enable SOF interrupts if PTDs are still scheduled when exiting this
1283 interrupt handler, just to be safe. */
1285 if (priv->active_ptds != last_active_ptds) {
1286 if (priv->active_ptds > 0)
1287 reg_write32(hcd->regs, HC_INTERRUPT_ENABLE,
1288 INTERRUPT_ENABLE_SOT_MASK);
1290 reg_write32(hcd->regs, HC_INTERRUPT_ENABLE,
1291 INTERRUPT_ENABLE_MASK);
1292 last_active_ptds = priv->active_ptds;
1295 irqret = IRQ_HANDLED;
1297 spin_unlock(&priv->lock);
1302 static int qtd_fill(struct isp1760_qtd *qtd, void *databuffer, size_t len)
1304 qtd->data_buffer = databuffer;
1306 if (len > MAX_PAYLOAD_SIZE)
1307 len = MAX_PAYLOAD_SIZE;
1313 static void qtd_list_free(struct list_head *qtd_list)
1315 struct isp1760_qtd *qtd, *qtd_next;
1317 list_for_each_entry_safe(qtd, qtd_next, qtd_list, qtd_list) {
1318 list_del(&qtd->qtd_list);
1324 * Packetize urb->transfer_buffer into list of packets of size wMaxPacketSize.
1325 * Also calculate the PID type (SETUP/IN/OUT) for each packet.
1327 #define max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
1328 static void packetize_urb(struct usb_hcd *hcd,
1329 struct urb *urb, struct list_head *head, gfp_t flags)
1331 struct isp1760_qtd *qtd;
1333 int len, maxpacketsize;
1337 * URBs map to sequences of QTDs: one logical transaction
1340 if (!urb->transfer_buffer && urb->transfer_buffer_length) {
1341 /* XXX This looks like usb storage / SCSI bug */
1342 dev_err(hcd->self.controller,
1343 "buf is null, dma is %08lx len is %d\n",
1344 (long unsigned)urb->transfer_dma,
1345 urb->transfer_buffer_length);
1349 if (usb_pipein(urb->pipe))
1350 packet_type = IN_PID;
1352 packet_type = OUT_PID;
1354 if (usb_pipecontrol(urb->pipe)) {
1355 qtd = qtd_alloc(flags, urb, SETUP_PID);
1358 qtd_fill(qtd, urb->setup_packet, sizeof(struct usb_ctrlrequest));
1359 list_add_tail(&qtd->qtd_list, head);
1361 /* for zero length DATA stages, STATUS is always IN */
1362 if (urb->transfer_buffer_length == 0)
1363 packet_type = IN_PID;
1366 maxpacketsize = max_packet(usb_maxpacket(urb->dev, urb->pipe,
1367 usb_pipeout(urb->pipe)));
1370 * buffer gets wrapped in one or more qtds;
1371 * last one may be "short" (including zero len)
1372 * and may serve as a control status ack
1374 buf = urb->transfer_buffer;
1375 len = urb->transfer_buffer_length;
1380 qtd = qtd_alloc(flags, urb, packet_type);
1383 this_qtd_len = qtd_fill(qtd, buf, len);
1384 list_add_tail(&qtd->qtd_list, head);
1386 len -= this_qtd_len;
1387 buf += this_qtd_len;
1394 * control requests may need a terminating data "status" ack;
1395 * bulk ones may need a terminating short packet (zero length).
1397 if (urb->transfer_buffer_length != 0) {
1400 if (usb_pipecontrol(urb->pipe)) {
1402 if (packet_type == IN_PID)
1403 packet_type = OUT_PID;
1405 packet_type = IN_PID;
1406 } else if (usb_pipebulk(urb->pipe)
1407 && (urb->transfer_flags & URB_ZERO_PACKET)
1408 && !(urb->transfer_buffer_length %
1413 qtd = qtd_alloc(flags, urb, packet_type);
1417 /* never any data in such packets */
1418 qtd_fill(qtd, NULL, 0);
1419 list_add_tail(&qtd->qtd_list, head);
1426 qtd_list_free(head);
1429 static int isp1760_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
1432 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1433 struct list_head *ep_queue;
1434 struct isp1760_qh *qh, *qhit;
1435 unsigned long spinflags;
1436 LIST_HEAD(new_qtds);
1440 switch (usb_pipetype(urb->pipe)) {
1442 ep_queue = &priv->controlqhs;
1445 ep_queue = &priv->bulkqhs;
1447 case PIPE_INTERRUPT:
1448 if (urb->interval < 0)
1450 /* FIXME: Check bandwidth */
1451 ep_queue = &priv->interruptqhs;
1453 case PIPE_ISOCHRONOUS:
1454 dev_err(hcd->self.controller, "%s: isochronous USB packets "
1455 "not yet supported\n",
1459 dev_err(hcd->self.controller, "%s: unknown pipe type\n",
1464 if (usb_pipein(urb->pipe))
1465 urb->actual_length = 0;
1467 packetize_urb(hcd, urb, &new_qtds, mem_flags);
1468 if (list_empty(&new_qtds))
1470 urb->hcpriv = NULL; /* Used to signal unlink to interrupt handler */
1473 spin_lock_irqsave(&priv->lock, spinflags);
1475 if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) {
1476 retval = -ESHUTDOWN;
1479 retval = usb_hcd_link_urb_to_ep(hcd, urb);
1483 qh = urb->ep->hcpriv;
1486 list_for_each_entry(qhit, ep_queue, qh_list) {
1493 list_add_tail(&qh->qh_list, ep_queue);
1495 qh = qh_alloc(GFP_ATOMIC);
1500 list_add_tail(&qh->qh_list, ep_queue);
1501 urb->ep->hcpriv = qh;
1504 list_splice_tail(&new_qtds, &qh->qtd_list);
1508 spin_unlock_irqrestore(&priv->lock, spinflags);
1512 static int isp1760_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
1515 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1516 struct isp1760_qh *qh;
1517 struct isp1760_qtd *qtd;
1519 unsigned long spinflags;
1522 spin_lock_irqsave(&priv->lock, spinflags);
1524 qh = urb->ep->hcpriv;
1530 /* We need to forcefully reclaim the slot since some transfers never
1531 return, e.g. interrupt transfers and NAKed bulk transfers. */
1532 if (qh->slot > -1) {
1533 memset(&ptd, 0, sizeof(ptd));
1534 if (usb_pipebulk(urb->pipe)) {
1535 priv->atl_slots[qh->slot].qh = NULL;
1536 priv->atl_slots[qh->slot].qtd = NULL;
1537 ptd_write(hcd->regs, ATL_PTD_OFFSET, qh->slot, &ptd);
1539 priv->int_slots[qh->slot].qh = NULL;
1540 priv->int_slots[qh->slot].qtd = NULL;
1541 ptd_write(hcd->regs, INT_PTD_OFFSET, qh->slot, &ptd);
1543 priv->active_ptds--;
1547 list_for_each_entry(qtd, &qh->qtd_list, qtd_list) {
1548 if (qtd->urb == urb)
1549 qtd->status = QTD_RETIRE;
1552 urb->status = status;
1556 spin_unlock_irqrestore(&priv->lock, spinflags);
1561 static int isp1760_hub_status_data(struct usb_hcd *hcd, char *buf)
1563 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1564 u32 temp, status = 0;
1567 unsigned long flags;
1569 /* if !USB_SUSPEND, root hub timers won't get shut down ... */
1570 if (!HC_IS_RUNNING(hcd->state))
1573 /* init status to no-changes */
1577 spin_lock_irqsave(&priv->lock, flags);
1578 temp = reg_read32(hcd->regs, HC_PORTSC1);
1580 if (temp & PORT_OWNER) {
1581 if (temp & PORT_CSC) {
1583 reg_write32(hcd->regs, HC_PORTSC1, temp);
1589 * Return status information even for ports with OWNER set.
1590 * Otherwise khubd wouldn't see the disconnect event when a
1591 * high-speed device is switched over to the companion
1592 * controller by the user.
1595 if ((temp & mask) != 0
1596 || ((temp & PORT_RESUME) != 0
1597 && time_after_eq(jiffies,
1598 priv->reset_done))) {
1599 buf [0] |= 1 << (0 + 1);
1602 /* FIXME autosuspend idle root hubs */
1604 spin_unlock_irqrestore(&priv->lock, flags);
1605 return status ? retval : 0;
1608 static void isp1760_hub_descriptor(struct isp1760_hcd *priv,
1609 struct usb_hub_descriptor *desc)
1611 int ports = HCS_N_PORTS(priv->hcs_params);
1614 desc->bDescriptorType = 0x29;
1615 /* priv 1.0, 2.3.9 says 20ms max */
1616 desc->bPwrOn2PwrGood = 10;
1617 desc->bHubContrCurrent = 0;
1619 desc->bNbrPorts = ports;
1620 temp = 1 + (ports / 8);
1621 desc->bDescLength = 7 + 2 * temp;
1623 /* ports removable, and usb 1.0 legacy PortPwrCtrlMask */
1624 memset(&desc->u.hs.DeviceRemovable[0], 0, temp);
1625 memset(&desc->u.hs.DeviceRemovable[temp], 0xff, temp);
1627 /* per-port overcurrent reporting */
1629 if (HCS_PPC(priv->hcs_params))
1630 /* per-port power control */
1633 /* no power switching */
1635 desc->wHubCharacteristics = cpu_to_le16(temp);
1638 #define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E)
1640 static int check_reset_complete(struct usb_hcd *hcd, int index,
1643 if (!(port_status & PORT_CONNECT))
1646 /* if reset finished and it's still not enabled -- handoff */
1647 if (!(port_status & PORT_PE)) {
1649 dev_info(hcd->self.controller,
1650 "port %d full speed --> companion\n",
1653 port_status |= PORT_OWNER;
1654 port_status &= ~PORT_RWC_BITS;
1655 reg_write32(hcd->regs, HC_PORTSC1, port_status);
1658 dev_info(hcd->self.controller, "port %d high speed\n",
1664 static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq,
1665 u16 wValue, u16 wIndex, char *buf, u16 wLength)
1667 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1668 int ports = HCS_N_PORTS(priv->hcs_params);
1670 unsigned long flags;
1675 * FIXME: support SetPortFeatures USB_PORT_FEAT_INDICATOR.
1676 * HCS_INDICATOR may say we can change LEDs to off/amber/green.
1677 * (track current state ourselves) ... blink for diagnostics,
1678 * power, "this is the one", etc. EHCI spec supports this.
1681 spin_lock_irqsave(&priv->lock, flags);
1683 case ClearHubFeature:
1685 case C_HUB_LOCAL_POWER:
1686 case C_HUB_OVER_CURRENT:
1687 /* no hub-wide feature/status flags */
1693 case ClearPortFeature:
1694 if (!wIndex || wIndex > ports)
1697 temp = reg_read32(hcd->regs, HC_PORTSC1);
1700 * Even if OWNER is set, so the port is owned by the
1701 * companion controller, khubd needs to be able to clear
1702 * the port-change status bits (especially
1703 * USB_PORT_STAT_C_CONNECTION).
1707 case USB_PORT_FEAT_ENABLE:
1708 reg_write32(hcd->regs, HC_PORTSC1, temp & ~PORT_PE);
1710 case USB_PORT_FEAT_C_ENABLE:
1713 case USB_PORT_FEAT_SUSPEND:
1714 if (temp & PORT_RESET)
1717 if (temp & PORT_SUSPEND) {
1718 if ((temp & PORT_PE) == 0)
1720 /* resume signaling for 20 msec */
1721 temp &= ~(PORT_RWC_BITS);
1722 reg_write32(hcd->regs, HC_PORTSC1,
1723 temp | PORT_RESUME);
1724 priv->reset_done = jiffies +
1725 msecs_to_jiffies(20);
1728 case USB_PORT_FEAT_C_SUSPEND:
1729 /* we auto-clear this feature */
1731 case USB_PORT_FEAT_POWER:
1732 if (HCS_PPC(priv->hcs_params))
1733 reg_write32(hcd->regs, HC_PORTSC1,
1734 temp & ~PORT_POWER);
1736 case USB_PORT_FEAT_C_CONNECTION:
1737 reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_CSC);
1739 case USB_PORT_FEAT_C_OVER_CURRENT:
1742 case USB_PORT_FEAT_C_RESET:
1743 /* GetPortStatus clears reset */
1748 reg_read32(hcd->regs, HC_USBCMD);
1750 case GetHubDescriptor:
1751 isp1760_hub_descriptor(priv, (struct usb_hub_descriptor *)
1755 /* no hub-wide feature/status flags */
1759 if (!wIndex || wIndex > ports)
1763 temp = reg_read32(hcd->regs, HC_PORTSC1);
1765 /* wPortChange bits */
1766 if (temp & PORT_CSC)
1767 status |= USB_PORT_STAT_C_CONNECTION << 16;
1770 /* whoever resumes must GetPortStatus to complete it!! */
1771 if (temp & PORT_RESUME) {
1772 dev_err(hcd->self.controller, "Port resume should be skipped.\n");
1774 /* Remote Wakeup received? */
1775 if (!priv->reset_done) {
1776 /* resume signaling for 20 msec */
1777 priv->reset_done = jiffies
1778 + msecs_to_jiffies(20);
1779 /* check the port again */
1780 mod_timer(&hcd->rh_timer, priv->reset_done);
1783 /* resume completed? */
1784 else if (time_after_eq(jiffies,
1785 priv->reset_done)) {
1786 status |= USB_PORT_STAT_C_SUSPEND << 16;
1787 priv->reset_done = 0;
1789 /* stop resume signaling */
1790 temp = reg_read32(hcd->regs, HC_PORTSC1);
1791 reg_write32(hcd->regs, HC_PORTSC1,
1792 temp & ~(PORT_RWC_BITS | PORT_RESUME));
1793 retval = handshake(hcd, HC_PORTSC1,
1794 PORT_RESUME, 0, 2000 /* 2msec */);
1796 dev_err(hcd->self.controller,
1797 "port %d resume error %d\n",
1798 wIndex + 1, retval);
1801 temp &= ~(PORT_SUSPEND|PORT_RESUME|(3<<10));
1805 /* whoever resets must GetPortStatus to complete it!! */
1806 if ((temp & PORT_RESET)
1807 && time_after_eq(jiffies,
1808 priv->reset_done)) {
1809 status |= USB_PORT_STAT_C_RESET << 16;
1810 priv->reset_done = 0;
1812 /* force reset to complete */
1813 reg_write32(hcd->regs, HC_PORTSC1, temp & ~PORT_RESET);
1814 /* REVISIT: some hardware needs 550+ usec to clear
1815 * this bit; seems too long to spin routinely...
1817 retval = handshake(hcd, HC_PORTSC1,
1818 PORT_RESET, 0, 750);
1820 dev_err(hcd->self.controller, "port %d reset error %d\n",
1821 wIndex + 1, retval);
1825 /* see what we found out */
1826 temp = check_reset_complete(hcd, wIndex,
1827 reg_read32(hcd->regs, HC_PORTSC1));
1830 * Even if OWNER is set, there's no harm letting khubd
1831 * see the wPortStatus values (they should all be 0 except
1832 * for PORT_POWER anyway).
1835 if (temp & PORT_OWNER)
1836 dev_err(hcd->self.controller, "PORT_OWNER is set\n");
1838 if (temp & PORT_CONNECT) {
1839 status |= USB_PORT_STAT_CONNECTION;
1840 /* status may be from integrated TT */
1841 status |= USB_PORT_STAT_HIGH_SPEED;
1844 status |= USB_PORT_STAT_ENABLE;
1845 if (temp & (PORT_SUSPEND|PORT_RESUME))
1846 status |= USB_PORT_STAT_SUSPEND;
1847 if (temp & PORT_RESET)
1848 status |= USB_PORT_STAT_RESET;
1849 if (temp & PORT_POWER)
1850 status |= USB_PORT_STAT_POWER;
1852 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
1856 case C_HUB_LOCAL_POWER:
1857 case C_HUB_OVER_CURRENT:
1858 /* no hub-wide feature/status flags */
1864 case SetPortFeature:
1865 selector = wIndex >> 8;
1867 if (!wIndex || wIndex > ports)
1870 temp = reg_read32(hcd->regs, HC_PORTSC1);
1871 if (temp & PORT_OWNER)
1874 /* temp &= ~PORT_RWC_BITS; */
1876 case USB_PORT_FEAT_ENABLE:
1877 reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_PE);
1880 case USB_PORT_FEAT_SUSPEND:
1881 if ((temp & PORT_PE) == 0
1882 || (temp & PORT_RESET) != 0)
1885 reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_SUSPEND);
1887 case USB_PORT_FEAT_POWER:
1888 if (HCS_PPC(priv->hcs_params))
1889 reg_write32(hcd->regs, HC_PORTSC1,
1892 case USB_PORT_FEAT_RESET:
1893 if (temp & PORT_RESUME)
1895 /* line status bits may report this as low speed,
1896 * which can be fine if this root hub has a
1897 * transaction translator built in.
1899 if ((temp & (PORT_PE|PORT_CONNECT)) == PORT_CONNECT
1900 && PORT_USB11(temp)) {
1907 * caller must wait, then call GetPortStatus
1908 * usb 2.0 spec says 50 ms resets on root
1910 priv->reset_done = jiffies +
1911 msecs_to_jiffies(50);
1913 reg_write32(hcd->regs, HC_PORTSC1, temp);
1918 reg_read32(hcd->regs, HC_USBCMD);
1923 /* "stall" on error */
1926 spin_unlock_irqrestore(&priv->lock, flags);
1930 static void isp1760_endpoint_disable(struct usb_hcd *hcd,
1931 struct usb_host_endpoint *ep)
1933 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1934 struct isp1760_qh *qh;
1935 struct isp1760_qtd *qtd;
1936 unsigned long spinflags;
1939 spin_lock_irqsave(&priv->lock, spinflags);
1944 do_iter = !list_empty(&qh->qtd_list);
1947 list_for_each_entry(qtd, &qh->qtd_list, qtd_list) {
1948 if (qtd->urb->ep == ep) {
1949 spin_unlock_irqrestore(&priv->lock, spinflags);
1950 isp1760_urb_dequeue(hcd, qtd->urb, -ECONNRESET);
1951 spin_lock_irqsave(&priv->lock, spinflags);
1953 break; /* Restart iteration */
1958 /* Cannot free qh here since it will be parsed by schedule_ptds() */
1961 spin_unlock_irqrestore(&priv->lock, spinflags);
1964 static int isp1760_get_frame(struct usb_hcd *hcd)
1966 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1969 fr = reg_read32(hcd->regs, HC_FRINDEX);
1970 return (fr >> 3) % priv->periodic_size;
1973 static void isp1760_stop(struct usb_hcd *hcd)
1975 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1978 isp1760_hub_control(hcd, ClearPortFeature, USB_PORT_FEAT_POWER, 1,
1982 spin_lock_irq(&priv->lock);
1985 temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL);
1986 reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp &= ~HW_GLOBAL_INTR_EN);
1987 spin_unlock_irq(&priv->lock);
1989 reg_write32(hcd->regs, HC_CONFIGFLAG, 0);
1992 static void isp1760_shutdown(struct usb_hcd *hcd)
1997 temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL);
1998 reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp &= ~HW_GLOBAL_INTR_EN);
2000 command = reg_read32(hcd->regs, HC_USBCMD);
2001 command &= ~CMD_RUN;
2002 reg_write32(hcd->regs, HC_USBCMD, command);
2005 static const struct hc_driver isp1760_hc_driver = {
2006 .description = "isp1760-hcd",
2007 .product_desc = "NXP ISP1760 USB Host Controller",
2008 .hcd_priv_size = sizeof(struct isp1760_hcd),
2010 .flags = HCD_MEMORY | HCD_USB2,
2011 .reset = isp1760_hc_setup,
2012 .start = isp1760_run,
2013 .stop = isp1760_stop,
2014 .shutdown = isp1760_shutdown,
2015 .urb_enqueue = isp1760_urb_enqueue,
2016 .urb_dequeue = isp1760_urb_dequeue,
2017 .endpoint_disable = isp1760_endpoint_disable,
2018 .get_frame_number = isp1760_get_frame,
2019 .hub_status_data = isp1760_hub_status_data,
2020 .hub_control = isp1760_hub_control,
2023 int __init init_kmem_once(void)
2025 urb_listitem_cachep = kmem_cache_create("isp1760 urb_listitem",
2026 sizeof(struct urb_listitem), 0, SLAB_TEMPORARY |
2027 SLAB_MEM_SPREAD, NULL);
2029 if (!urb_listitem_cachep)
2032 qtd_cachep = kmem_cache_create("isp1760_qtd",
2033 sizeof(struct isp1760_qtd), 0, SLAB_TEMPORARY |
2034 SLAB_MEM_SPREAD, NULL);
2039 qh_cachep = kmem_cache_create("isp1760_qh", sizeof(struct isp1760_qh),
2040 0, SLAB_TEMPORARY | SLAB_MEM_SPREAD, NULL);
2043 kmem_cache_destroy(qtd_cachep);
2050 void deinit_kmem_cache(void)
2052 kmem_cache_destroy(qtd_cachep);
2053 kmem_cache_destroy(qh_cachep);
2054 kmem_cache_destroy(urb_listitem_cachep);
2057 struct usb_hcd *isp1760_register(phys_addr_t res_start, resource_size_t res_len,
2058 int irq, unsigned long irqflags,
2059 struct device *dev, const char *busname,
2060 unsigned int devflags)
2062 struct usb_hcd *hcd;
2063 struct isp1760_hcd *priv;
2067 return ERR_PTR(-ENODEV);
2069 /* prevent usb-core allocating DMA pages */
2070 dev->dma_mask = NULL;
2072 hcd = usb_create_hcd(&isp1760_hc_driver, dev, dev_name(dev));
2074 return ERR_PTR(-ENOMEM);
2076 priv = hcd_to_priv(hcd);
2077 priv->devflags = devflags;
2079 hcd->regs = ioremap(res_start, res_len);
2086 hcd->rsrc_start = res_start;
2087 hcd->rsrc_len = res_len;
2089 ret = usb_add_hcd(hcd, irq, irqflags);
2101 return ERR_PTR(ret);
2104 MODULE_DESCRIPTION("Driver for the ISP1760 USB-controller from NXP");
2105 MODULE_AUTHOR("Sebastian Siewior <bigeasy@linuxtronix.de>");
2106 MODULE_LICENSE("GPL v2");