drivers/usb/host/isp1760-hcd.c

   1 /*
   2  * Driver for the NXP ISP1760 chip
   3  *
   4  * However, the code might contain some bugs. What doesn't work for sure is:
   5  * - ISO
   6  * - OTG
   7  e The interrupt line is configured as active low, level.
   8  *
   9  * (c) 2007 Sebastian Siewior <bigeasy@linutronix.de>
  10  *
  11  */
  12 #include <linux/module.h>
  13 #include <linux/kernel.h>
  14 #include <linux/slab.h>
  15 #include <linux/list.h>
  16 #include <linux/usb.h>
  17 #include <linux/usb/hcd.h>
  18 #include <linux/debugfs.h>
  19 #include <linux/uaccess.h>
  20 #include <linux/io.h>
  21 #include <linux/mm.h>
  22 #include <asm/unaligned.h>
  23 #include <asm/cacheflush.h>
  24
  25 #include "isp1760-hcd.h"
  26
  27 static struct kmem_cache *qtd_cachep;
  28 static struct kmem_cache *qh_cachep;
  29
  30 struct isp1760_hcd {
  31         u32 hcs_params;
  32         spinlock_t              lock;
  33         struct inter_packet_info atl_ints[32];
  34         struct inter_packet_info int_ints[32];
  35         struct memory_chunk memory_pool[BLOCKS];
  36         u32 atl_queued;
  37
  38         /* periodic schedule support */
  39 #define DEFAULT_I_TDPS          1024
  40         unsigned                periodic_size;
  41         unsigned                i_thresh;
  42         unsigned long           reset_done;
  43         unsigned long           next_statechange;
  44         unsigned int            devflags;
  45 };
  46
  47 static inline struct isp1760_hcd *hcd_to_priv(struct usb_hcd *hcd)
  48 {
  49         return (struct isp1760_hcd *) (hcd->hcd_priv);
  50 }
  51
  52 /* Section 2.2 Host Controller Capability Registers */
  53 #define HC_LENGTH(p)            (((p)>>00)&0x00ff)      /* bits 7:0 */
  54 #define HC_VERSION(p)           (((p)>>16)&0xffff)      /* bits 31:16 */
  55 #define HCS_INDICATOR(p)        ((p)&(1 << 16)) /* true: has port indicators */
  56 #define HCS_PPC(p)              ((p)&(1 << 4))  /* true: port power control */
  57 #define HCS_N_PORTS(p)          (((p)>>0)&0xf)  /* bits 3:0, ports on HC */
  58 #define HCC_ISOC_CACHE(p)       ((p)&(1 << 7))  /* true: can cache isoc frame */
  59 #define HCC_ISOC_THRES(p)       (((p)>>4)&0x7)  /* bits 6:4, uframes cached */
  60
  61 /* Section 2.3 Host Controller Operational Registers */
  62 #define CMD_LRESET      (1<<7)          /* partial reset (no ports, etc) */
  63 #define CMD_RESET       (1<<1)          /* reset HC not bus */
  64 #define CMD_RUN         (1<<0)          /* start/stop HC */
  65 #define STS_PCD         (1<<2)          /* port change detect */
  66 #define FLAG_CF         (1<<0)          /* true: we'll support "high speed" */
  67
  68 #define PORT_OWNER      (1<<13)         /* true: companion hc owns this port */
  69 #define PORT_POWER      (1<<12)         /* true: has power (see PPC) */
  70 #define PORT_USB11(x) (((x) & (3 << 10)) == (1 << 10))  /* USB 1.1 device */
  71 #define PORT_RESET      (1<<8)          /* reset port */
  72 #define PORT_SUSPEND    (1<<7)          /* suspend port */
  73 #define PORT_RESUME     (1<<6)          /* resume it */
  74 #define PORT_PE         (1<<2)          /* port enable */
  75 #define PORT_CSC        (1<<1)          /* connect status change */
  76 #define PORT_CONNECT    (1<<0)          /* device connected */
  77 #define PORT_RWC_BITS   (PORT_CSC)
  78
  79 struct isp1760_qtd {
  80         u8 packet_type;
  81         u8 toggle;
  82
  83         void *data_buffer;
  84         u32 payload_addr;
  85
  86         /* the rest is HCD-private */
  87         struct list_head qtd_list;
  88         struct urb *urb;
  89         size_t length;
  90
  91         /* isp special*/
  92         u32 status;
  93 #define URB_ENQUEUED            (1 << 1)
  94 };
  95
  96 struct isp1760_qh {
  97         /* first part defined by EHCI spec */
  98         struct list_head qtd_list;
  99
 100         u32 toggle;
 101         u32 ping;
 102 };
 103
 104 /*
 105  * Access functions for isp176x registers (addresses 0..0x03FF).
 106  */
 107 static u32 reg_read32(void __iomem *base, u32 reg)
 108 {
 109         return readl(base + reg);
 110 }
 111
 112 static void reg_write32(void __iomem *base, u32 reg, u32 val)
 113 {
 114         writel(val, base + reg);
 115 }
 116
 117 /*
 118  * Access functions for isp176x memory (offset >= 0x0400).
 119  *
 120  * bank_reads8() reads memory locations prefetched by an earlier write to
 121  * HC_MEMORY_REG (see isp176x datasheet). Unless you want to do fancy multi-
 122  * bank optimizations, you should use the more generic mem_reads8() below.
 123  *
 124  * For access to ptd memory, use the specialized ptd_read() and ptd_write()
 125  * below.
 126  *
 127  * These functions copy via MMIO data to/from the device. memcpy_{to|from}io()
 128  * doesn't quite work because some people have to enforce 32-bit access
 129  */
 130 static void bank_reads8(void __iomem *src_base, u32 src_offset, u32 bank_addr,
 131                                                         __u32 *dst, u32 bytes)
 132 {
 133         __u32 __iomem *src;
 134         u32 val;
 135         __u8 *src_byteptr;
 136         __u8 *dst_byteptr;
 137
 138         src = src_base + (bank_addr | src_offset);
 139
 140         if (src_offset < PAYLOAD_OFFSET) {
 141                 while (bytes >= 4) {
 142                         *dst = le32_to_cpu(__raw_readl(src));
 143                         bytes -= 4;
 144                         src++;
 145                         dst++;
 146                 }
 147         } else {
 148                 while (bytes >= 4) {
 149                         *dst = __raw_readl(src);
 150                         bytes -= 4;
 151                         src++;
 152                         dst++;
 153                 }
 154         }
 155
 156         if (!bytes)
 157                 return;
 158
 159         /* in case we have 3, 2 or 1 by left. The dst buffer may not be fully
 160          * allocated.
 161          */
 162         if (src_offset < PAYLOAD_OFFSET)
 163                 val = le32_to_cpu(__raw_readl(src));
 164         else
 165                 val = __raw_readl(src);
 166
 167         dst_byteptr = (void *) dst;
 168         src_byteptr = (void *) &val;
 169         while (bytes > 0) {
 170                 *dst_byteptr = *src_byteptr;
 171                 dst_byteptr++;
 172                 src_byteptr++;
 173                 bytes--;
 174         }
 175 }
 176
 177 static void mem_reads8(void __iomem *src_base, u32 src_offset, void *dst,
 178                                                                 u32 bytes)
 179 {
 180         reg_write32(src_base, HC_MEMORY_REG, src_offset + ISP_BANK(0));
 181         ndelay(90);
 182         bank_reads8(src_base, src_offset, ISP_BANK(0), dst, bytes);
 183 }
 184
 185 static void mem_writes8(void __iomem *dst_base, u32 dst_offset,
 186                                                 __u32 const *src, u32 bytes)
 187 {
 188         __u32 __iomem *dst;
 189
 190         dst = dst_base + dst_offset;
 191
 192         if (dst_offset < PAYLOAD_OFFSET) {
 193                 while (bytes >= 4) {
 194                         __raw_writel(cpu_to_le32(*src), dst);
 195                         bytes -= 4;
 196                         src++;
 197                         dst++;
 198                 }
 199         } else {
 200                 while (bytes >= 4) {
 201                         __raw_writel(*src, dst);
 202                         bytes -= 4;
 203                         src++;
 204                         dst++;
 205                 }
 206         }
 207
 208         if (!bytes)
 209                 return;
 210         /* in case we have 3, 2 or 1 bytes left. The buffer is allocated and the
 211          * extra bytes should not be read by the HW.
 212          */
 213
 214         if (dst_offset < PAYLOAD_OFFSET)
 215                 __raw_writel(cpu_to_le32(*src), dst);
 216         else
 217                 __raw_writel(*src, dst);
 218 }
 219
 220 /*
 221  * Read and write ptds. 'ptd_offset' should be one of ISO_PTD_OFFSET,
 222  * INT_PTD_OFFSET, and ATL_PTD_OFFSET. 'slot' should be less than 32.
 223  */
 224 static void ptd_read(void __iomem *base, u32 ptd_offset, u32 slot,
 225                                                                 struct ptd *ptd)
 226 {
 227         reg_write32(base, HC_MEMORY_REG,
 228                                 ISP_BANK(0) + ptd_offset + slot*sizeof(*ptd));
 229         ndelay(90);
 230         bank_reads8(base, ptd_offset + slot*sizeof(*ptd), ISP_BANK(0),
 231                                                 (void *) ptd, sizeof(*ptd));
 232 }
 233
 234 static void ptd_write(void __iomem *base, u32 ptd_offset, u32 slot,
 235                                                                 struct ptd *ptd)
 236 {
 237         mem_writes8(base, ptd_offset + slot*sizeof(*ptd) + sizeof(ptd->dw0),
 238                                                 &ptd->dw1, 7*sizeof(ptd->dw1));
 239         /* Make sure dw0 gets written last (after other dw's and after payload)
 240            since it contains the enable bit */
 241         wmb();
 242         mem_writes8(base, ptd_offset + slot*sizeof(*ptd), &ptd->dw0,
 243                                                         sizeof(ptd->dw0));
 244 }
 245
 246
 247 /* memory management of the 60kb on the chip from 0x1000 to 0xffff */
 248 static void init_memory(struct isp1760_hcd *priv)
 249 {
 250         int i, curr;
 251         u32 payload_addr;
 252
 253         payload_addr = PAYLOAD_OFFSET;
 254         for (i = 0; i < BLOCK_1_NUM; i++) {
 255                 priv->memory_pool[i].start = payload_addr;
 256                 priv->memory_pool[i].size = BLOCK_1_SIZE;
 257                 priv->memory_pool[i].free = 1;
 258                 payload_addr += priv->memory_pool[i].size;
 259         }
 260
 261         curr = i;
 262         for (i = 0; i < BLOCK_2_NUM; i++) {
 263                 priv->memory_pool[curr + i].start = payload_addr;
 264                 priv->memory_pool[curr + i].size = BLOCK_2_SIZE;
 265                 priv->memory_pool[curr + i].free = 1;
 266                 payload_addr += priv->memory_pool[curr + i].size;
 267         }
 268
 269         curr = i;
 270         for (i = 0; i < BLOCK_3_NUM; i++) {
 271                 priv->memory_pool[curr + i].start = payload_addr;
 272                 priv->memory_pool[curr + i].size = BLOCK_3_SIZE;
 273                 priv->memory_pool[curr + i].free = 1;
 274                 payload_addr += priv->memory_pool[curr + i].size;
 275         }
 276
 277         BUG_ON(payload_addr - priv->memory_pool[0].start > PAYLOAD_AREA_SIZE);
 278 }
 279
 280 static void alloc_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd)
 281 {
 282         struct isp1760_hcd *priv = hcd_to_priv(hcd);
 283         int i;
 284
 285         BUG_ON(qtd->payload_addr);
 286
 287         if (!qtd->length)
 288                 return;
 289
 290         for (i = 0; i < BLOCKS; i++) {
 291                 if (priv->memory_pool[i].size >= qtd->length &&
 292                                 priv->memory_pool[i].free) {
 293                         priv->memory_pool[i].free = 0;
 294                         qtd->payload_addr = priv->memory_pool[i].start;
 295                         return;
 296                 }
 297         }
 298
 299         dev_err(hcd->self.controller,
 300                                 "%s: Can not allocate %lu bytes of memory\n"
 301                                 "Current memory map:\n",
 302                                 __func__, qtd->length);
 303         for (i = 0; i < BLOCKS; i++) {
 304                 dev_err(hcd->self.controller, "Pool %2d size %4d status: %d\n",
 305                                 i, priv->memory_pool[i].size,
 306                                 priv->memory_pool[i].free);
 307         }
 308         /* XXX maybe -ENOMEM could be possible */
 309         BUG();
 310         return;
 311 }
 312
 313 static void free_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd)
 314 {
 315         struct isp1760_hcd *priv = hcd_to_priv(hcd);
 316         int i;
 317
 318         if (!qtd->payload_addr)
 319                 return;
 320
 321         for (i = 0; i < BLOCKS; i++) {
 322                 if (priv->memory_pool[i].start == qtd->payload_addr) {
 323                         BUG_ON(priv->memory_pool[i].free);
 324                         priv->memory_pool[i].free = 1;
 325                         qtd->payload_addr = 0;
 326                         return;
 327                 }
 328         }
 329
 330         dev_err(hcd->self.controller, "%s: Invalid pointer: %08x\n",
 331                                                 __func__, qtd->payload_addr);
 332         BUG();
 333 }
 334
 335 static void isp1760_init_regs(struct usb_hcd *hcd)
 336 {
 337         reg_write32(hcd->regs, HC_BUFFER_STATUS_REG, 0);
 338         reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
 339         reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
 340         reg_write32(hcd->regs, HC_ISO_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
 341
 342         reg_write32(hcd->regs, HC_ATL_PTD_DONEMAP_REG, ~NO_TRANSFER_ACTIVE);
 343         reg_write32(hcd->regs, HC_INT_PTD_DONEMAP_REG, ~NO_TRANSFER_ACTIVE);
 344         reg_write32(hcd->regs, HC_ISO_PTD_DONEMAP_REG, ~NO_TRANSFER_ACTIVE);
 345 }
 346
 347 static int handshake(struct usb_hcd *hcd, u32 reg,
 348                       u32 mask, u32 done, int usec)
 349 {
 350         u32 result;
 351
 352         do {
 353                 result = reg_read32(hcd->regs, reg);
 354                 if (result == ~0)
 355                         return -ENODEV;
 356                 result &= mask;
 357                 if (result == done)
 358                         return 0;
 359                 udelay(1);
 360                 usec--;
 361         } while (usec > 0);
 362         return -ETIMEDOUT;
 363 }
 364
 365 /* reset a non-running (STS_HALT == 1) controller */
 366 static int ehci_reset(struct usb_hcd *hcd)
 367 {
 368         int retval;
 369         struct isp1760_hcd *priv = hcd_to_priv(hcd);
 370
 371         u32 command = reg_read32(hcd->regs, HC_USBCMD);
 372
 373         command |= CMD_RESET;
 374         reg_write32(hcd->regs, HC_USBCMD, command);
 375         hcd->state = HC_STATE_HALT;
 376         priv->next_statechange = jiffies;
 377         retval = handshake(hcd, HC_USBCMD,
 378                             CMD_RESET, 0, 250 * 1000);
 379         return retval;
 380 }
 381
 382 static void qh_destroy(struct isp1760_qh *qh)
 383 {
 384         BUG_ON(!list_empty(&qh->qtd_list));
 385         kmem_cache_free(qh_cachep, qh);
 386 }
 387
 388 static struct isp1760_qh *isp1760_qh_alloc(gfp_t flags)
 389 {
 390         struct isp1760_qh *qh;
 391
 392         qh = kmem_cache_zalloc(qh_cachep, flags);
 393         if (!qh)
 394                 return qh;
 395
 396         INIT_LIST_HEAD(&qh->qtd_list);
 397         return qh;
 398 }
 399
 400 /* magic numbers that can affect system performance */
 401 #define EHCI_TUNE_CERR          3       /* 0-3 qtd retries; 0 == don't stop */
 402 #define EHCI_TUNE_RL_HS         4       /* nak throttle; see 4.9 */
 403 #define EHCI_TUNE_RL_TT         0
 404 #define EHCI_TUNE_MULT_HS       1       /* 1-3 transactions/uframe; 4.10.3 */
 405 #define EHCI_TUNE_MULT_TT       1
 406 #define EHCI_TUNE_FLS           2       /* (small) 256 frame schedule */
 407
 408 /* one-time init, only for memory state */
 409 static int priv_init(struct usb_hcd *hcd)
 410 {
 411         struct isp1760_hcd              *priv = hcd_to_priv(hcd);
 412         u32                     hcc_params;
 413
 414         spin_lock_init(&priv->lock);
 415
 416         /*
 417          * hw default: 1K periodic list heads, one per frame.
 418          * periodic_size can shrink by USBCMD update if hcc_params allows.
 419          */
 420         priv->periodic_size = DEFAULT_I_TDPS;
 421
 422         /* controllers may cache some of the periodic schedule ... */
 423         hcc_params = reg_read32(hcd->regs, HC_HCCPARAMS);
 424         /* full frame cache */
 425         if (HCC_ISOC_CACHE(hcc_params))
 426                 priv->i_thresh = 8;
 427         else /* N microframes cached */
 428                 priv->i_thresh = 2 + HCC_ISOC_THRES(hcc_params);
 429
 430         return 0;
 431 }
 432
 433 static int isp1760_hc_setup(struct usb_hcd *hcd)
 434 {
 435         struct isp1760_hcd *priv = hcd_to_priv(hcd);
 436         int result;
 437         u32 scratch, hwmode;
 438
 439         /* Setup HW Mode Control: This assumes a level active-low interrupt */
 440         hwmode = HW_DATA_BUS_32BIT;
 441
 442         if (priv->devflags & ISP1760_FLAG_BUS_WIDTH_16)
 443                 hwmode &= ~HW_DATA_BUS_32BIT;
 444         if (priv->devflags & ISP1760_FLAG_ANALOG_OC)
 445                 hwmode |= HW_ANA_DIGI_OC;
 446         if (priv->devflags & ISP1760_FLAG_DACK_POL_HIGH)
 447                 hwmode |= HW_DACK_POL_HIGH;
 448         if (priv->devflags & ISP1760_FLAG_DREQ_POL_HIGH)
 449                 hwmode |= HW_DREQ_POL_HIGH;
 450         if (priv->devflags & ISP1760_FLAG_INTR_POL_HIGH)
 451                 hwmode |= HW_INTR_HIGH_ACT;
 452         if (priv->devflags & ISP1760_FLAG_INTR_EDGE_TRIG)
 453                 hwmode |= HW_INTR_EDGE_TRIG;
 454
 455         /*
 456          * We have to set this first in case we're in 16-bit mode.
 457          * Write it twice to ensure correct upper bits if switching
 458          * to 16-bit mode.
 459          */
 460         reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode);
 461         reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode);
 462
 463         reg_write32(hcd->regs, HC_SCRATCH_REG, 0xdeadbabe);
 464         /* Change bus pattern */
 465         scratch = reg_read32(hcd->regs, HC_CHIP_ID_REG);
 466         scratch = reg_read32(hcd->regs, HC_SCRATCH_REG);
 467         if (scratch != 0xdeadbabe) {
 468                 dev_err(hcd->self.controller, "Scratch test failed.\n");
 469                 return -ENODEV;
 470         }
 471
 472         /* pre reset */
 473         isp1760_init_regs(hcd);
 474
 475         /* reset */
 476         reg_write32(hcd->regs, HC_RESET_REG, SW_RESET_RESET_ALL);
 477         mdelay(100);
 478
 479         reg_write32(hcd->regs, HC_RESET_REG, SW_RESET_RESET_HC);
 480         mdelay(100);
 481
 482         result = ehci_reset(hcd);
 483         if (result)
 484                 return result;
 485
 486         /* Step 11 passed */
 487
 488         dev_info(hcd->self.controller, "bus width: %d, oc: %s\n",
 489                            (priv->devflags & ISP1760_FLAG_BUS_WIDTH_16) ?
 490                            16 : 32, (priv->devflags & ISP1760_FLAG_ANALOG_OC) ?
 491                            "analog" : "digital");
 492
 493         /* ATL reset */
 494         reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode | ALL_ATX_RESET);
 495         mdelay(10);
 496         reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode);
 497
 498         reg_write32(hcd->regs, HC_INTERRUPT_REG, INTERRUPT_ENABLE_MASK);
 499         reg_write32(hcd->regs, HC_INTERRUPT_ENABLE, INTERRUPT_ENABLE_MASK);
 500
 501         /*
 502          * PORT 1 Control register of the ISP1760 is the OTG control
 503          * register on ISP1761. Since there is no OTG or device controller
 504          * support in this driver, we use port 1 as a "normal" USB host port on
 505          * both chips.
 506          */
 507         reg_write32(hcd->regs, HC_PORT1_CTRL, PORT1_POWER | PORT1_INIT2);
 508         mdelay(10);
 509
 510         priv->hcs_params = reg_read32(hcd->regs, HC_HCSPARAMS);
 511
 512         return priv_init(hcd);
 513 }
 514
 515 static void isp1760_init_maps(struct usb_hcd *hcd)
 516 {
 517         /*set last maps, for iso its only 1, else 32 tds bitmap*/
 518         reg_write32(hcd->regs, HC_ATL_PTD_LASTPTD_REG, 0x80000000);
 519         reg_write32(hcd->regs, HC_INT_PTD_LASTPTD_REG, 0x80000000);
 520         reg_write32(hcd->regs, HC_ISO_PTD_LASTPTD_REG, 0x00000001);
 521 }
 522
 523 static void isp1760_enable_interrupts(struct usb_hcd *hcd)
 524 {
 525         reg_write32(hcd->regs, HC_ATL_IRQ_MASK_AND_REG, 0);
 526         reg_write32(hcd->regs, HC_ATL_IRQ_MASK_OR_REG, 0);
 527         reg_write32(hcd->regs, HC_INT_IRQ_MASK_AND_REG, 0);
 528         reg_write32(hcd->regs, HC_INT_IRQ_MASK_OR_REG, 0);
 529         reg_write32(hcd->regs, HC_ISO_IRQ_MASK_AND_REG, 0);
 530         reg_write32(hcd->regs, HC_ISO_IRQ_MASK_OR_REG, 0xffffffff);
 531         /* step 23 passed */
 532 }
 533
 534 static int isp1760_run(struct usb_hcd *hcd)
 535 {
 536         int retval;
 537         u32 temp;
 538         u32 command;
 539         u32 chipid;
 540
 541         hcd->uses_new_polling = 1;
 542
 543         hcd->state = HC_STATE_RUNNING;
 544         isp1760_enable_interrupts(hcd);
 545         temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL);
 546         reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp | HW_GLOBAL_INTR_EN);
 547
 548         command = reg_read32(hcd->regs, HC_USBCMD);
 549         command &= ~(CMD_LRESET|CMD_RESET);
 550         command |= CMD_RUN;
 551         reg_write32(hcd->regs, HC_USBCMD, command);
 552
 553         retval = handshake(hcd, HC_USBCMD, CMD_RUN, CMD_RUN,
 554                         250 * 1000);
 555         if (retval)
 556                 return retval;
 557
 558         /*
 559          * XXX
 560          * Spec says to write FLAG_CF as last config action, priv code grabs
 561          * the semaphore while doing so.
 562          */
 563         down_write(&ehci_cf_port_reset_rwsem);
 564         reg_write32(hcd->regs, HC_CONFIGFLAG, FLAG_CF);
 565
 566         retval = handshake(hcd, HC_CONFIGFLAG, FLAG_CF, FLAG_CF, 250 * 1000);
 567         up_write(&ehci_cf_port_reset_rwsem);
 568         if (retval)
 569                 return retval;
 570
 571         chipid = reg_read32(hcd->regs, HC_CHIP_ID_REG);
 572         dev_info(hcd->self.controller, "USB ISP %04x HW rev. %d started\n",
 573                                         chipid & 0xffff, chipid >> 16);
 574
 575         /* PTD Register Init Part 2, Step 28 */
 576         /* enable INTs */
 577         isp1760_init_maps(hcd);
 578
 579         /* GRR this is run-once init(), being done every time the HC starts.
 580          * So long as they're part of class devices, we can't do it init()
 581          * since the class device isn't created that early.
 582          */
 583         return 0;
 584 }
 585
 586 static u32 base_to_chip(u32 base)
 587 {
 588         return ((base - 0x400) >> 3);
 589 }
 590
 591 static void transform_into_atl(struct isp1760_qh *qh,
 592                         struct isp1760_qtd *qtd, struct ptd *ptd)
 593 {
 594         u32 maxpacket;
 595         u32 multi;
 596         u32 pid_code;
 597         u32 rl = RL_COUNTER;
 598         u32 nak = NAK_COUNTER;
 599
 600         memset(ptd, 0, sizeof(*ptd));
 601
 602         /* according to 3.6.2, max packet len can not be > 0x400 */
 603         maxpacket = usb_maxpacket(qtd->urb->dev, qtd->urb->pipe,
 604                                                 usb_pipeout(qtd->urb->pipe));
 605         multi =  1 + ((maxpacket >> 11) & 0x3);
 606         maxpacket &= 0x7ff;
 607
 608         /* DW0 */
 609         ptd->dw0 = PTD_VALID;
 610         ptd->dw0 |= PTD_LENGTH(qtd->length);
 611         ptd->dw0 |= PTD_MAXPACKET(maxpacket);
 612         ptd->dw0 |= PTD_ENDPOINT(usb_pipeendpoint(qtd->urb->pipe));
 613
 614         /* DW1 */
 615         ptd->dw1 = usb_pipeendpoint(qtd->urb->pipe) >> 1;
 616         ptd->dw1 |= PTD_DEVICE_ADDR(usb_pipedevice(qtd->urb->pipe));
 617
 618         pid_code = qtd->packet_type;
 619         ptd->dw1 |= PTD_PID_TOKEN(pid_code);
 620
 621         if (usb_pipebulk(qtd->urb->pipe))
 622                 ptd->dw1 |= PTD_TRANS_BULK;
 623         else if  (usb_pipeint(qtd->urb->pipe))
 624                 ptd->dw1 |= PTD_TRANS_INT;
 625
 626         if (qtd->urb->dev->speed != USB_SPEED_HIGH) {
 627                 /* split transaction */
 628
 629                 ptd->dw1 |= PTD_TRANS_SPLIT;
 630                 if (qtd->urb->dev->speed == USB_SPEED_LOW)
 631                         ptd->dw1 |= PTD_SE_USB_LOSPEED;
 632
 633                 ptd->dw1 |= PTD_PORT_NUM(qtd->urb->dev->ttport);
 634                 ptd->dw1 |= PTD_HUB_NUM(qtd->urb->dev->tt->hub->devnum);
 635
 636                 /* SE bit for Split INT transfers */
 637                 if (usb_pipeint(qtd->urb->pipe) &&
 638                                 (qtd->urb->dev->speed == USB_SPEED_LOW))
 639                         ptd->dw1 |= 2 << 16;
 640
 641                 ptd->dw3 = 0;
 642                 rl = 0;
 643                 nak = 0;
 644         } else {
 645                 ptd->dw0 |= PTD_MULTI(multi);
 646                 if (usb_pipecontrol(qtd->urb->pipe) ||
 647                                                 usb_pipebulk(qtd->urb->pipe))
 648                         ptd->dw3 = qh->ping;
 649                 else
 650                         ptd->dw3 = 0;
 651         }
 652         /* DW2 */
 653         ptd->dw2 = 0;
 654         ptd->dw2 |= PTD_DATA_START_ADDR(base_to_chip(qtd->payload_addr));
 655         ptd->dw2 |= PTD_RL_CNT(rl);
 656         ptd->dw3 |= PTD_NAC_CNT(nak);
 657
 658         /* DW3 */
 659         if (usb_pipecontrol(qtd->urb->pipe))
 660                 ptd->dw3 |= PTD_DATA_TOGGLE(qtd->toggle);
 661         else
 662                 ptd->dw3 |= qh->toggle;
 663
 664
 665         ptd->dw3 |= PTD_ACTIVE;
 666         /* Cerr */
 667         ptd->dw3 |= PTD_CERR(ERR_COUNTER);
 668 }
 669
 670 static void transform_add_int(struct isp1760_qh *qh,
 671                         struct isp1760_qtd *qtd, struct ptd *ptd)
 672 {
 673         u32 usof;
 674         u32 period;
 675
 676         /*
 677          * Most of this is guessing. ISP1761 datasheet is quite unclear, and
 678          * the algorithm from the original Philips driver code, which was
 679          * pretty much used in this driver before as well, is quite horrendous
 680          * and, i believe, incorrect. The code below follows the datasheet and
 681          * USB2.0 spec as far as I can tell, and plug/unplug seems to be much
 682          * more reliable this way (fingers crossed...).
 683          */
 684
 685         if (qtd->urb->dev->speed == USB_SPEED_HIGH) {
 686                 /* urb->interval is in units of microframes (1/8 ms) */
 687                 period = qtd->urb->interval >> 3;
 688
 689                 if (qtd->urb->interval > 4)
 690                         usof = 0x01; /* One bit set =>
 691                                                 interval 1 ms * uFrame-match */
 692                 else if (qtd->urb->interval > 2)
 693                         usof = 0x22; /* Two bits set => interval 1/2 ms */
 694                 else if (qtd->urb->interval > 1)
 695                         usof = 0x55; /* Four bits set => interval 1/4 ms */
 696                 else
 697                         usof = 0xff; /* All bits set => interval 1/8 ms */
 698         } else {
 699                 /* urb->interval is in units of frames (1 ms) */
 700                 period = qtd->urb->interval;
 701                 usof = 0x0f;            /* Execute Start Split on any of the
 702                                            four first uFrames */
 703
 704                 /*
 705                  * First 8 bits in dw5 is uSCS and "specifies which uSOF the
 706                  * complete split needs to be sent. Valid only for IN." Also,
 707                  * "All bits can be set to one for every transfer." (p 82,
 708                  * ISP1761 data sheet.) 0x1c is from Philips driver. Where did
 709                  * that number come from? 0xff seems to work fine...
 710                  */
 711                 /* ptd->dw5 = 0x1c; */
 712                 ptd->dw5 = 0xff; /* Execute Complete Split on any uFrame */
 713         }
 714
 715         period = period >> 1;/* Ensure equal or shorter period than requested */
 716         period &= 0xf8; /* Mask off too large values and lowest unused 3 bits */
 717
 718         ptd->dw2 |= period;
 719         ptd->dw4 = usof;
 720 }
 721
 722 static void transform_into_int(struct isp1760_qh *qh,
 723                         struct isp1760_qtd *qtd, struct ptd *ptd)
 724 {
 725         transform_into_atl(qh, qtd, ptd);
 726         transform_add_int(qh, qtd, ptd);
 727 }
 728
 729 static int qtd_fill(struct isp1760_qtd *qtd, void *databuffer, size_t len,
 730                 u32 token)
 731 {
 732         int count;
 733
 734         qtd->data_buffer = databuffer;
 735         qtd->packet_type = GET_QTD_TOKEN_TYPE(token);
 736         qtd->toggle = GET_DATA_TOGGLE(token);
 737
 738         if (len > MAX_PAYLOAD_SIZE)
 739                 count = MAX_PAYLOAD_SIZE;
 740         else
 741                 count = len;
 742
 743         qtd->length = count;
 744         return count;
 745 }
 746
 747 static int check_error(struct usb_hcd *hcd, struct ptd *ptd)
 748 {
 749         int error = 0;
 750
 751         if (ptd->dw3 & DW3_HALT_BIT) {
 752                 error = -EPIPE;
 753
 754                 if (ptd->dw3 & DW3_ERROR_BIT)
 755                         pr_err("error bit is set in DW3\n");
 756         }
 757
 758         if (ptd->dw3 & DW3_QTD_ACTIVE) {
 759                 dev_err(hcd->self.controller, "Transfer active bit is set DW3\n"
 760                         "nak counter: %d, rl: %d\n",
 761                         (ptd->dw3 >> 19) & 0xf, (ptd->dw2 >> 25) & 0xf);
 762         }
 763
 764         return error;
 765 }
 766
 767 static void check_int_err_status(struct usb_hcd *hcd, u32 dw4)
 768 {
 769         u32 i;
 770
 771         dw4 >>= 8;
 772
 773         for (i = 0; i < 8; i++) {
 774                 switch (dw4 & 0x7) {
 775                 case INT_UNDERRUN:
 776                         dev_err(hcd->self.controller, "Underrun (%d)\n", i);
 777                         break;
 778
 779                 case INT_EXACT:
 780                         dev_err(hcd->self.controller,
 781                                                 "Transaction error (%d)\n", i);
 782                         break;
 783
 784                 case INT_BABBLE:
 785                         dev_err(hcd->self.controller, "Babble error (%d)\n", i);
 786                         break;
 787                 }
 788                 dw4 >>= 3;
 789         }
 790 }
 791
 792 static void enqueue_one_qtd(struct usb_hcd *hcd, struct isp1760_qtd *qtd)
 793 {
 794         if (qtd->length && (qtd->length <= MAX_PAYLOAD_SIZE)) {
 795                 switch (qtd->packet_type) {
 796                 case IN_PID:
 797                         break;
 798                 case OUT_PID:
 799                 case SETUP_PID:
 800                         mem_writes8(hcd->regs, qtd->payload_addr,
 801                                                 qtd->data_buffer, qtd->length);
 802                 }
 803         }
 804 }
 805
 806 static void enqueue_one_atl_qtd(struct usb_hcd *hcd, struct isp1760_qh *qh,
 807                                         u32 slot, struct isp1760_qtd *qtd)
 808 {
 809         struct isp1760_hcd *priv = hcd_to_priv(hcd);
 810         struct ptd ptd;
 811
 812         alloc_mem(hcd, qtd);
 813         transform_into_atl(qh, qtd, &ptd);
 814         ptd_write(hcd->regs, ATL_PTD_OFFSET, slot, &ptd);
 815         enqueue_one_qtd(hcd, qtd);
 816
 817         priv->atl_ints[slot].qh = qh;
 818         priv->atl_ints[slot].qtd = qtd;
 819         qtd->status |= URB_ENQUEUED;
 820         qtd->status |= slot << 16;
 821 }
 822
 823 static void enqueue_one_int_qtd(struct usb_hcd *hcd, struct isp1760_qh *qh,
 824                                         u32 slot, struct isp1760_qtd *qtd)
 825 {
 826         struct isp1760_hcd *priv = hcd_to_priv(hcd);
 827         struct ptd ptd;
 828
 829         alloc_mem(hcd, qtd);
 830         transform_into_int(qh, qtd, &ptd);
 831         ptd_write(hcd->regs, INT_PTD_OFFSET, slot, &ptd);
 832         enqueue_one_qtd(hcd, qtd);
 833
 834         priv->int_ints[slot].qh = qh;
 835         priv->int_ints[slot].qtd = qtd;
 836         qtd->status |= URB_ENQUEUED;
 837         qtd->status |= slot << 16;
 838 }
 839
 840 static void enqueue_an_ATL_packet(struct usb_hcd *hcd, struct isp1760_qh *qh,
 841                                   struct isp1760_qtd *qtd)
 842 {
 843         struct isp1760_hcd *priv = hcd_to_priv(hcd);
 844         u32 skip_map, or_map;
 845         u32 slot;
 846         u32 buffstatus;
 847
 848         /*
 849          * When this function is called from the interrupt handler to enqueue
 850          * a follow-up packet, the SKIP register gets written and read back
 851          * almost immediately. With ISP1761, this register requires a delay of
 852          * 195ns between a write and subsequent read (see section 15.1.1.3).
 853          */
 854         mmiowb();
 855         ndelay(195);
 856         skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG);
 857
 858         BUG_ON(!skip_map);
 859         slot = __ffs(skip_map);
 860
 861         enqueue_one_atl_qtd(hcd, qh, slot, qtd);
 862
 863         or_map = reg_read32(hcd->regs, HC_ATL_IRQ_MASK_OR_REG);
 864         or_map |= (1 << slot);
 865         reg_write32(hcd->regs, HC_ATL_IRQ_MASK_OR_REG, or_map);
 866
 867         skip_map &= ~(1 << slot);
 868         reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, skip_map);
 869
 870         priv->atl_queued++;
 871         if (priv->atl_queued == 2)
 872                 reg_write32(hcd->regs, HC_INTERRUPT_ENABLE,
 873                                 INTERRUPT_ENABLE_SOT_MASK);
 874
 875         buffstatus = reg_read32(hcd->regs, HC_BUFFER_STATUS_REG);
 876         buffstatus |= ATL_BUFFER;
 877         reg_write32(hcd->regs, HC_BUFFER_STATUS_REG, buffstatus);
 878 }
 879
 880 static void enqueue_an_INT_packet(struct usb_hcd *hcd, struct isp1760_qh *qh,
 881                                   struct isp1760_qtd *qtd)
 882 {
 883         u32 skip_map, or_map;
 884         u32 slot;
 885         u32 buffstatus;
 886
 887         /*
 888          * When this function is called from the interrupt handler to enqueue
 889          * a follow-up packet, the SKIP register gets written and read back
 890          * almost immediately. With ISP1761, this register requires a delay of
 891          * 195ns between a write and subsequent read (see section 15.1.1.3).
 892          */
 893         mmiowb();
 894         ndelay(195);
 895         skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG);
 896
 897         BUG_ON(!skip_map);
 898         slot = __ffs(skip_map);
 899
 900         enqueue_one_int_qtd(hcd, qh, slot, qtd);
 901
 902         or_map = reg_read32(hcd->regs, HC_INT_IRQ_MASK_OR_REG);
 903         or_map |= (1 << slot);
 904         reg_write32(hcd->regs, HC_INT_IRQ_MASK_OR_REG, or_map);
 905
 906         skip_map &= ~(1 << slot);
 907         reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, skip_map);
 908
 909         buffstatus = reg_read32(hcd->regs, HC_BUFFER_STATUS_REG);
 910         buffstatus |= INT_BUFFER;
 911         reg_write32(hcd->regs, HC_BUFFER_STATUS_REG, buffstatus);
 912 }
 913
 914 static void isp1760_urb_done(struct usb_hcd *hcd, struct urb *urb)
 915 __releases(priv->lock)
 916 __acquires(priv->lock)
 917 {
 918         struct isp1760_hcd *priv = hcd_to_priv(hcd);
 919
 920         if (!urb->unlinked) {
 921                 if (urb->status == -EINPROGRESS)
 922                         urb->status = 0;
 923         }
 924
 925         if (usb_pipein(urb->pipe) && usb_pipetype(urb->pipe) != PIPE_CONTROL) {
 926                 void *ptr;
 927                 for (ptr = urb->transfer_buffer;
 928                      ptr < urb->transfer_buffer + urb->transfer_buffer_length;
 929                      ptr += PAGE_SIZE)
 930                         flush_dcache_page(virt_to_page(ptr));
 931         }
 932
 933         /* complete() can reenter this HCD */
 934         usb_hcd_unlink_urb_from_ep(hcd, urb);
 935         spin_unlock(&priv->lock);
 936         usb_hcd_giveback_urb(hcd, urb, urb->status);
 937         spin_lock(&priv->lock);
 938 }
 939
 940 static void isp1760_qtd_free(struct isp1760_qtd *qtd)
 941 {
 942         BUG_ON(qtd->payload_addr);
 943         kmem_cache_free(qtd_cachep, qtd);
 944 }
 945
 946 static struct isp1760_qtd *clean_this_qtd(struct isp1760_qtd *qtd,
 947                                                         struct isp1760_qh *qh)
 948 {
 949         struct isp1760_qtd *tmp_qtd;
 950
 951         if (list_is_last(&qtd->qtd_list, &qh->qtd_list))
 952                 tmp_qtd = NULL;
 953         else
 954                 tmp_qtd = list_entry(qtd->qtd_list.next, struct isp1760_qtd,
 955                                                                 qtd_list);
 956         list_del(&qtd->qtd_list);
 957         isp1760_qtd_free(qtd);
 958         return tmp_qtd;
 959 }
 960
 961 /*
 962  * Remove this QTD from the QH list and free its memory. If this QTD
 963  * isn't the last one than remove also his successor(s).
 964  * Returns the QTD which is part of an new URB and should be enqueued.
 965  */
 966 static struct isp1760_qtd *clean_up_qtdlist(struct isp1760_qtd *qtd,
 967                                                         struct isp1760_qh *qh)
 968 {
 969         struct urb *urb;
 970
 971         urb = qtd->urb;
 972         do {
 973                 qtd = clean_this_qtd(qtd, qh);
 974         } while (qtd && (qtd->urb == urb));
 975
 976         return qtd;
 977 }
 978
 979 static int last_qtd_of_urb(struct isp1760_qtd *qtd, struct isp1760_qh *qh)
 980 {
 981         struct urb *urb;
 982
 983         if (list_is_last(&qtd->qtd_list, &qh->qtd_list))
 984                 return 1;
 985
 986         urb = qtd->urb;
 987         qtd = list_entry(qtd->qtd_list.next, typeof(*qtd), qtd_list);
 988         return (qtd->urb != urb);
 989 }
 990
 991 static void do_atl_int(struct usb_hcd *hcd)
 992 {
 993         struct isp1760_hcd *priv = hcd_to_priv(hcd);
 994         u32 done_map, skip_map;
 995         struct ptd ptd;
 996         struct urb *urb;
 997         u32 slot;
 998         u32 length;
 999         u32 or_map;
1000         u32 status = -EINVAL;
1001         int error;
1002         struct isp1760_qtd *qtd;
1003         struct isp1760_qh *qh;
1004         u32 rl;
1005         u32 nakcount;
1006
1007         done_map = reg_read32(hcd->regs, HC_ATL_PTD_DONEMAP_REG);
1008         skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG);
1009
1010         or_map = reg_read32(hcd->regs, HC_ATL_IRQ_MASK_OR_REG);
1011         or_map &= ~done_map;
1012         reg_write32(hcd->regs, HC_ATL_IRQ_MASK_OR_REG, or_map);
1013
1014         while (done_map) {
1015                 status = 0;
1016                 priv->atl_queued--;
1017
1018                 slot = __ffs(done_map);
1019                 done_map &= ~(1 << slot);
1020                 skip_map |= (1 << slot);
1021
1022                 qtd = priv->atl_ints[slot].qtd;
1023                 qh = priv->atl_ints[slot].qh;
1024
1025                 if (!qh) {
1026                         dev_err(hcd->self.controller, "qh is 0\n");
1027                         continue;
1028                 }
1029                 ptd_read(hcd->regs, ATL_PTD_OFFSET, slot, &ptd);
1030
1031                 rl = (ptd.dw2 >> 25) & 0x0f;
1032                 nakcount = (ptd.dw3 >> 19) & 0xf;
1033
1034                 /* Transfer Error, *but* active and no HALT -> reload */
1035                 if ((ptd.dw3 & DW3_ERROR_BIT) && (ptd.dw3 & DW3_QTD_ACTIVE) &&
1036                                 !(ptd.dw3 & DW3_HALT_BIT)) {
1037
1038                         /* according to ppriv code, we have to
1039                          * reload this one if trasfered bytes != requested bytes
1040                          * else act like everything went smooth..
1041                          * XXX This just doesn't feel right and hasn't
1042                          * triggered so far.
1043                          */
1044
1045                         length = PTD_XFERRED_LENGTH(ptd.dw3);
1046                         dev_err(hcd->self.controller,
1047                                         "Should reload now... transferred %d "
1048                                         "of %zu\n", length, qtd->length);
1049                         BUG();
1050                 }
1051
1052                 if (!nakcount && (ptd.dw3 & DW3_QTD_ACTIVE)) {
1053                         u32 buffstatus;
1054
1055                         /*
1056                          * NAKs are handled in HW by the chip. Usually if the
1057                          * device is not able to send data fast enough.
1058                          * This happens mostly on slower hardware.
1059                          */
1060
1061                         /* RL counter = ERR counter */
1062                         ptd.dw3 &= ~(0xf << 19);
1063                         ptd.dw3 |= rl << 19;
1064                         ptd.dw3 &= ~(3 << (55 - 32));
1065                         ptd.dw3 |= ERR_COUNTER << (55 - 32);
1066
1067                         /*
1068                          * It is not needed to write skip map back because it
1069                          * is unchanged. Just make sure that this entry is
1070                          * unskipped once it gets written to the HW.
1071                          */
1072                         skip_map &= ~(1 << slot);
1073                         or_map = reg_read32(hcd->regs, HC_ATL_IRQ_MASK_OR_REG);
1074                         or_map |= 1 << slot;
1075                         reg_write32(hcd->regs, HC_ATL_IRQ_MASK_OR_REG, or_map);
1076
1077                         ptd.dw0 |= PTD_VALID;
1078                         ptd_write(hcd->regs, ATL_PTD_OFFSET, slot, &ptd);
1079
1080                         priv->atl_queued++;
1081                         if (priv->atl_queued == 2)
1082                                 reg_write32(hcd->regs, HC_INTERRUPT_ENABLE,
1083                                                 INTERRUPT_ENABLE_SOT_MASK);
1084
1085                         buffstatus = reg_read32(hcd->regs,
1086                                                         HC_BUFFER_STATUS_REG);
1087                         buffstatus |= ATL_BUFFER;
1088                         reg_write32(hcd->regs, HC_BUFFER_STATUS_REG,
1089                                                                 buffstatus);
1090                         continue;
1091                 }
1092
1093                 error = check_error(hcd, &ptd);
1094                 if (error) {
1095                         status = error;
1096                         priv->atl_ints[slot].qh->toggle = 0;
1097                         priv->atl_ints[slot].qh->ping = 0;
1098                         qtd->urb->status = -EPIPE;
1099
1100 #if 0
1101                         printk(KERN_ERR "Error in %s().\n", __func__);
1102                         printk(KERN_ERR "IN dw0: %08x dw1: %08x dw2: %08x "
1103                                         "dw3: %08x dw4: %08x dw5: %08x dw6: "
1104                                         "%08x dw7: %08x\n",
1105                                         ptd.dw0, ptd.dw1, ptd.dw2, ptd.dw3,
1106                                         ptd.dw4, ptd.dw5, ptd.dw6, ptd.dw7);
1107 #endif
1108                 } else {
1109                         if (usb_pipetype(qtd->urb->pipe) == PIPE_BULK) {
1110                                 priv->atl_ints[slot].qh->toggle =
1111                                                         ptd.dw3 & (1 << 25);
1112                                 priv->atl_ints[slot].qh->ping =
1113                                                         ptd.dw3 & (1 << 26);
1114                         }
1115                 }
1116
1117                 length = PTD_XFERRED_LENGTH(ptd.dw3);
1118                 if (length) {
1119                         switch (DW1_GET_PID(ptd.dw1)) {
1120                         case IN_PID:
1121                                 mem_reads8(hcd->regs, qtd->payload_addr,
1122                                                 qtd->data_buffer, length);
1123
1124                         case OUT_PID:
1125
1126                                 qtd->urb->actual_length += length;
1127
1128                         case SETUP_PID:
1129                                 break;
1130                         }
1131                 }
1132
1133                 priv->atl_ints[slot].qtd = NULL;
1134                 priv->atl_ints[slot].qh = NULL;
1135
1136                 free_mem(hcd, qtd);
1137
1138                 reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, skip_map);
1139
1140                 if (qtd->urb->status == -EPIPE) {
1141                         /* HALT was received */
1142
1143                         urb = qtd->urb;
1144                         qtd = clean_up_qtdlist(qtd, qh);
1145                         isp1760_urb_done(hcd, urb);
1146
1147                 } else if (usb_pipebulk(qtd->urb->pipe) &&
1148                                                 (length < qtd->length)) {
1149                         /* short BULK received */
1150
1151                         if (qtd->urb->transfer_flags & URB_SHORT_NOT_OK) {
1152                                 qtd->urb->status = -EREMOTEIO;
1153                                 dev_dbg(hcd->self.controller,
1154                                                 "short bulk, %d instead %zu "
1155                                                 "with URB_SHORT_NOT_OK flag.\n",
1156                                                 length, qtd->length);
1157                         }
1158
1159                         if (qtd->urb->status == -EINPROGRESS)
1160                                 qtd->urb->status = 0;
1161
1162                         urb = qtd->urb;
1163                         qtd = clean_up_qtdlist(qtd, qh);
1164                         isp1760_urb_done(hcd, urb);
1165
1166                 } else if (last_qtd_of_urb(qtd, qh)) {
1167                         /* that was the last qtd of that URB */
1168
1169                         if (qtd->urb->status == -EINPROGRESS)
1170                                 qtd->urb->status = 0;
1171
1172                         urb = qtd->urb;
1173                         qtd = clean_up_qtdlist(qtd, qh);
1174                         isp1760_urb_done(hcd, urb);
1175
1176                 } else {
1177                         /* next QTD of this URB */
1178
1179                         qtd = clean_this_qtd(qtd, qh);
1180                         BUG_ON(!qtd);
1181                 }
1182
1183                 if (qtd)
1184                         enqueue_an_ATL_packet(hcd, qh, qtd);
1185
1186                 skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG);
1187         }
1188         if (priv->atl_queued <= 1)
1189                 reg_write32(hcd->regs, HC_INTERRUPT_ENABLE,
1190                                                         INTERRUPT_ENABLE_MASK);
1191 }
1192
1193 static void do_intl_int(struct usb_hcd *hcd)
1194 {
1195         struct isp1760_hcd *priv = hcd_to_priv(hcd);
1196         u32 done_map, skip_map;
1197         struct ptd ptd;
1198         struct urb *urb;
1199         u32 length;
1200         u32 or_map;
1201         int error;
1202         u32 slot;
1203         struct isp1760_qtd *qtd;
1204         struct isp1760_qh *qh;
1205
1206         done_map = reg_read32(hcd->regs, HC_INT_PTD_DONEMAP_REG);
1207         skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG);
1208
1209         or_map = reg_read32(hcd->regs, HC_INT_IRQ_MASK_OR_REG);
1210         or_map &= ~done_map;
1211         reg_write32(hcd->regs, HC_INT_IRQ_MASK_OR_REG, or_map);
1212
1213         while (done_map) {
1214                 slot = __ffs(done_map);
1215                 done_map &= ~(1 << slot);
1216                 skip_map |= (1 << slot);
1217
1218                 qtd = priv->int_ints[slot].qtd;
1219                 qh = priv->int_ints[slot].qh;
1220
1221                 if (!qh) {
1222                         dev_err(hcd->self.controller, "(INT) qh is 0\n");
1223                         continue;
1224                 }
1225
1226                 ptd_read(hcd->regs, INT_PTD_OFFSET, slot, &ptd);
1227                 check_int_err_status(hcd, ptd.dw4);
1228
1229                 error = check_error(hcd, &ptd);
1230                 if (error) {
1231 #if 0
1232                         printk(KERN_ERR "Error in %s().\n", __func__);
1233                         printk(KERN_ERR "IN dw0: %08x dw1: %08x dw2: %08x "
1234                                         "dw3: %08x dw4: %08x dw5: %08x dw6: "
1235                                         "%08x dw7: %08x\n",
1236                                         ptd.dw0, ptd.dw1, ptd.dw2, ptd.dw3,
1237                                         ptd.dw4, ptd.dw5, ptd.dw6, ptd.dw7);
1238 #endif
1239                         qtd->urb->status = -EPIPE;
1240                         priv->int_ints[slot].qh->toggle = 0;
1241                         priv->int_ints[slot].qh->ping = 0;
1242
1243                 } else {
1244                         priv->int_ints[slot].qh->toggle = ptd.dw3 & (1 << 25);
1245                         priv->int_ints[slot].qh->ping = ptd.dw3 & (1 << 26);
1246                 }
1247
1248                 if (qtd->urb->dev->speed != USB_SPEED_HIGH)
1249                         length = PTD_XFERRED_LENGTH_LO(ptd.dw3);
1250                 else
1251                         length = PTD_XFERRED_LENGTH(ptd.dw3);
1252
1253                 if (length) {
1254                         switch (DW1_GET_PID(ptd.dw1)) {
1255                         case IN_PID:
1256                                 mem_reads8(hcd->regs, qtd->payload_addr,
1257                                                 qtd->data_buffer, length);
1258                         case OUT_PID:
1259
1260                                 qtd->urb->actual_length += length;
1261
1262                         case SETUP_PID:
1263                                 break;
1264                         }
1265                 }
1266
1267                 priv->int_ints[slot].qtd = NULL;
1268                 priv->int_ints[slot].qh = NULL;
1269
1270                 reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, skip_map);
1271                 free_mem(hcd, qtd);
1272
1273                 if (qtd->urb->status == -EPIPE) {
1274                         /* HALT received */
1275
1276                         urb = qtd->urb;
1277                         qtd = clean_up_qtdlist(qtd, qh);
1278                         isp1760_urb_done(hcd, urb);
1279
1280                 } else if (last_qtd_of_urb(qtd, qh)) {
1281
1282                         if (qtd->urb->status == -EINPROGRESS)
1283                                 qtd->urb->status = 0;
1284
1285                         urb = qtd->urb;
1286                         qtd = clean_up_qtdlist(qtd, qh);
1287                         isp1760_urb_done(hcd, urb);
1288
1289                 } else {
1290                         /* next QTD of this URB */
1291
1292                         qtd = clean_this_qtd(qtd, qh);
1293                         BUG_ON(!qtd);
1294                 }
1295
1296                 if (qtd)
1297                         enqueue_an_INT_packet(hcd, qh, qtd);
1298
1299                 skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG);
1300         }
1301 }
1302
1303 static struct isp1760_qh *qh_make(struct usb_hcd *hcd, struct urb *urb,
1304                 gfp_t flags)
1305 {
1306         struct isp1760_qh *qh;
1307         int is_input, type;
1308
1309         qh = isp1760_qh_alloc(flags);
1310         if (!qh)
1311                 return qh;
1312
1313         /*
1314          * init endpoint/device data for this QH
1315          */
1316         is_input = usb_pipein(urb->pipe);
1317         type = usb_pipetype(urb->pipe);
1318
1319         if (!usb_pipecontrol(urb->pipe))
1320                 usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe), !is_input,
1321                                 1);
1322         return qh;
1323 }
1324
1325 /*
1326  * For control/bulk/interrupt, return QH with these TDs appended.
1327  * Allocates and initializes the QH if necessary.
1328  * Returns null if it can't allocate a QH it needs to.
1329  * If the QH has TDs (urbs) already, that's great.
1330  */
1331 static struct isp1760_qh *qh_append_tds(struct usb_hcd *hcd,
1332                 struct urb *urb, struct list_head *qtd_list, int epnum,
1333                 void **ptr)
1334 {
1335         struct isp1760_qh *qh;
1336
1337         qh = (struct isp1760_qh *)*ptr;
1338         if (!qh) {
1339                 /* can't sleep here, we have priv->lock... */
1340                 qh = qh_make(hcd, urb, GFP_ATOMIC);
1341                 if (!qh)
1342                         return qh;
1343                 *ptr = qh;
1344         }
1345
1346         list_splice(qtd_list, qh->qtd_list.prev);
1347
1348         return qh;
1349 }
1350
1351 static void qtd_list_free(struct urb *urb, struct list_head *qtd_list)
1352 {
1353         struct list_head *entry, *temp;
1354
1355         list_for_each_safe(entry, temp, qtd_list) {
1356                 struct isp1760_qtd      *qtd;
1357
1358                 qtd = list_entry(entry, struct isp1760_qtd, qtd_list);
1359                 list_del(&qtd->qtd_list);
1360                 isp1760_qtd_free(qtd);
1361         }
1362 }
1363
1364 static int isp1760_prepare_enqueue(struct usb_hcd *hcd, struct urb *urb,
1365                 struct list_head *qtd_list, gfp_t mem_flags, packet_enqueue *p)
1366 {
1367         struct isp1760_hcd *priv = hcd_to_priv(hcd);
1368         struct isp1760_qtd         *qtd;
1369         int                     epnum;
1370         unsigned long           flags;
1371         struct isp1760_qh          *qh = NULL;
1372         int                     rc;
1373         int qh_busy;
1374
1375         qtd = list_entry(qtd_list->next, struct isp1760_qtd, qtd_list);
1376         epnum = urb->ep->desc.bEndpointAddress;
1377
1378         spin_lock_irqsave(&priv->lock, flags);
1379         if (!HCD_HW_ACCESSIBLE(hcd)) {
1380                 rc = -ESHUTDOWN;
1381                 goto done;
1382         }
1383         rc = usb_hcd_link_urb_to_ep(hcd, urb);
1384         if (rc)
1385                 goto done;
1386
1387         qh = urb->ep->hcpriv;
1388         if (qh)
1389                 qh_busy = !list_empty(&qh->qtd_list);
1390         else
1391                 qh_busy = 0;
1392
1393         qh = qh_append_tds(hcd, urb, qtd_list, epnum, &urb->ep->hcpriv);
1394         if (!qh) {
1395                 usb_hcd_unlink_urb_from_ep(hcd, urb);
1396                 rc = -ENOMEM;
1397                 goto done;
1398         }
1399
1400         if (!qh_busy)
1401                 p(hcd, qh, qtd);
1402
1403 done:
1404         spin_unlock_irqrestore(&priv->lock, flags);
1405         if (!qh)
1406                 qtd_list_free(urb, qtd_list);
1407         return rc;
1408 }
1409
1410 static struct isp1760_qtd *isp1760_qtd_alloc(gfp_t flags)
1411 {
1412         struct isp1760_qtd *qtd;
1413
1414         qtd = kmem_cache_zalloc(qtd_cachep, flags);
1415         if (qtd)
1416                 INIT_LIST_HEAD(&qtd->qtd_list);
1417
1418         return qtd;
1419 }
1420
1421 /*
1422  * create a list of filled qtds for this URB; won't link into qh.
1423  */
1424 #define max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
1425 static struct list_head *qh_urb_transaction(struct usb_hcd *hcd,
1426                 struct urb *urb, struct list_head *head, gfp_t flags)
1427 {
1428         struct isp1760_qtd *qtd;
1429         void *buf;
1430         int len, maxpacket;
1431         int is_input;
1432         u32 token;
1433
1434         /*
1435          * URBs map to sequences of QTDs:  one logical transaction
1436          */
1437         qtd = isp1760_qtd_alloc(flags);
1438         if (!qtd)
1439                 return NULL;
1440
1441         list_add_tail(&qtd->qtd_list, head);
1442         qtd->urb = urb;
1443         urb->status = -EINPROGRESS;
1444
1445         token = 0;
1446         /* for split transactions, SplitXState initialized to zero */
1447
1448         len = urb->transfer_buffer_length;
1449         is_input = usb_pipein(urb->pipe);
1450         if (usb_pipecontrol(urb->pipe)) {
1451                 /* SETUP pid */
1452                 qtd_fill(qtd, urb->setup_packet,
1453                                 sizeof(struct usb_ctrlrequest),
1454                                 token | SETUP_PID);
1455
1456                 /* ... and always at least one more pid */
1457                 token ^= DATA_TOGGLE;
1458                 qtd = isp1760_qtd_alloc(flags);
1459                 if (!qtd)
1460                         goto cleanup;
1461                 qtd->urb = urb;
1462                 list_add_tail(&qtd->qtd_list, head);
1463
1464                 /* for zero length DATA stages, STATUS is always IN */
1465                 if (len == 0)
1466                         token |= IN_PID;
1467         }
1468
1469         /*
1470          * data transfer stage:  buffer setup
1471          */
1472         buf = urb->transfer_buffer;
1473
1474         if (is_input)
1475                 token |= IN_PID;
1476         else
1477                 token |= OUT_PID;
1478
1479         maxpacket = max_packet(usb_maxpacket(urb->dev, urb->pipe, !is_input));
1480
1481         /*
1482          * buffer gets wrapped in one or more qtds;
1483          * last one may be "short" (including zero len)
1484          * and may serve as a control status ack
1485          */
1486         for (;;) {
1487                 int this_qtd_len;
1488
1489                 if (!buf && len) {
1490                         /* XXX This looks like usb storage / SCSI bug */
1491                         dev_err(hcd->self.controller, "buf is null, dma is %08lx len is %d\n",
1492                                         (long unsigned)urb->transfer_dma, len);
1493                         WARN_ON(1);
1494                 }
1495
1496                 this_qtd_len = qtd_fill(qtd, buf, len, token);
1497                 len -= this_qtd_len;
1498                 buf += this_qtd_len;
1499
1500                 /* qh makes control packets use qtd toggle; maybe switch it */
1501                 if ((maxpacket & (this_qtd_len + (maxpacket - 1))) == 0)
1502                         token ^= DATA_TOGGLE;
1503
1504                 if (len <= 0)
1505                         break;
1506
1507                 qtd = isp1760_qtd_alloc(flags);
1508                 if (!qtd)
1509                         goto cleanup;
1510                 qtd->urb = urb;
1511                 list_add_tail(&qtd->qtd_list, head);
1512         }
1513
1514         /*
1515          * control requests may need a terminating data "status" ack;
1516          * bulk ones may need a terminating short packet (zero length).
1517          */
1518         if (urb->transfer_buffer_length != 0) {
1519                 int one_more = 0;
1520
1521                 if (usb_pipecontrol(urb->pipe)) {
1522                         one_more = 1;
1523                         /* "in" <--> "out"  */
1524                         token ^= IN_PID;
1525                         /* force DATA1 */
1526                         token |= DATA_TOGGLE;
1527                 } else if (usb_pipebulk(urb->pipe)
1528                                 && (urb->transfer_flags & URB_ZERO_PACKET)
1529                                 && !(urb->transfer_buffer_length % maxpacket)) {
1530                         one_more = 1;
1531                 }
1532                 if (one_more) {
1533                         qtd = isp1760_qtd_alloc(flags);
1534                         if (!qtd)
1535                                 goto cleanup;
1536                         qtd->urb = urb;
1537                         list_add_tail(&qtd->qtd_list, head);
1538
1539                         /* never any data in such packets */
1540                         qtd_fill(qtd, NULL, 0, token);
1541                 }
1542         }
1543
1544         qtd->status = 0;
1545         return head;
1546
1547 cleanup:
1548         qtd_list_free(urb, head);
1549         return NULL;
1550 }
1551
1552 static int isp1760_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
1553                 gfp_t mem_flags)
1554 {
1555         struct list_head qtd_list;
1556         packet_enqueue *pe;
1557
1558         INIT_LIST_HEAD(&qtd_list);
1559
1560         switch (usb_pipetype(urb->pipe)) {
1561         case PIPE_CONTROL:
1562         case PIPE_BULK:
1563                 if (!qh_urb_transaction(hcd, urb, &qtd_list, mem_flags))
1564                         return -ENOMEM;
1565                 pe =  enqueue_an_ATL_packet;
1566                 break;
1567
1568         case PIPE_INTERRUPT:
1569                 if (!qh_urb_transaction(hcd, urb, &qtd_list, mem_flags))
1570                         return -ENOMEM;
1571                 pe = enqueue_an_INT_packet;
1572                 break;
1573
1574         case PIPE_ISOCHRONOUS:
1575                 dev_err(hcd->self.controller, "PIPE_ISOCHRONOUS ain't supported\n");
1576         default:
1577                 return -EPIPE;
1578         }
1579
1580         return isp1760_prepare_enqueue(hcd, urb, &qtd_list, mem_flags, pe);
1581 }
1582
1583 static int isp1760_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1584 {
1585         struct isp1760_hcd *priv = hcd_to_priv(hcd);
1586         struct inter_packet_info *ints;
1587         u32 i;
1588         u32 reg_base, or_reg, skip_reg;
1589         unsigned long flags;
1590         struct ptd ptd;
1591         packet_enqueue *pe;
1592
1593         switch (usb_pipetype(urb->pipe)) {
1594         case PIPE_ISOCHRONOUS:
1595                 return -EPIPE;
1596                 break;
1597
1598         case PIPE_INTERRUPT:
1599                 ints = priv->int_ints;
1600                 reg_base = INT_PTD_OFFSET;
1601                 or_reg = HC_INT_IRQ_MASK_OR_REG;
1602                 skip_reg = HC_INT_PTD_SKIPMAP_REG;
1603                 pe = enqueue_an_INT_packet;
1604                 break;
1605
1606         default:
1607                 ints = priv->atl_ints;
1608                 reg_base = ATL_PTD_OFFSET;
1609                 or_reg = HC_ATL_IRQ_MASK_OR_REG;
1610                 skip_reg = HC_ATL_PTD_SKIPMAP_REG;
1611                 pe =  enqueue_an_ATL_packet;
1612                 break;
1613         }
1614
1615         memset(&ptd, 0, sizeof(ptd));
1616         spin_lock_irqsave(&priv->lock, flags);
1617
1618         for (i = 0; i < 32; i++) {
1619                 if (!ints[i].qh)
1620                         continue;
1621                 BUG_ON(!ints[i].qtd);
1622
1623                 if (ints[i].qtd->urb == urb) {
1624                         u32 skip_map;
1625                         u32 or_map;
1626                         struct isp1760_qtd *qtd;
1627                         struct isp1760_qh *qh;
1628
1629                         skip_map = reg_read32(hcd->regs, skip_reg);
1630                         skip_map |= 1 << i;
1631                         reg_write32(hcd->regs, skip_reg, skip_map);
1632
1633                         or_map = reg_read32(hcd->regs, or_reg);
1634                         or_map &= ~(1 << i);
1635                         reg_write32(hcd->regs, or_reg, or_map);
1636
1637                         ptd_write(hcd->regs, reg_base, i, &ptd);
1638
1639                         qtd = ints->qtd;
1640                         qh = ints[i].qh;
1641
1642                         free_mem(hcd, qtd);
1643                         qtd = clean_up_qtdlist(qtd, qh);
1644
1645                         ints->qh = NULL;
1646                         ints->qtd = NULL;
1647
1648                         isp1760_urb_done(hcd, urb);
1649                         if (qtd)
1650                                 pe(hcd, qh, qtd);
1651                         break;
1652
1653                 } else {
1654                         struct isp1760_qtd *qtd;
1655
1656                         list_for_each_entry(qtd, &ints[i].qtd->qtd_list,
1657                                                                 qtd_list) {
1658                                 if (qtd->urb == urb) {
1659                                         clean_up_qtdlist(qtd, ints[i].qh);
1660                                         isp1760_urb_done(hcd, urb);
1661                                         qtd = NULL;
1662                                         break;
1663                                 }
1664                         }
1665
1666                         /* We found the urb before the last slot */
1667                         if (!qtd)
1668                                 break;
1669                 }
1670                 ints++;
1671         }
1672
1673         spin_unlock_irqrestore(&priv->lock, flags);
1674         return 0;
1675 }
1676
1677 static irqreturn_t isp1760_irq(struct usb_hcd *hcd)
1678 {
1679         struct isp1760_hcd *priv = hcd_to_priv(hcd);
1680         u32 imask;
1681         irqreturn_t irqret = IRQ_NONE;
1682
1683         spin_lock(&priv->lock);
1684
1685         if (!(hcd->state & HC_STATE_RUNNING))
1686                 goto leave;
1687
1688         imask = reg_read32(hcd->regs, HC_INTERRUPT_REG);
1689         if (unlikely(!imask))
1690                 goto leave;
1691
1692         reg_write32(hcd->regs, HC_INTERRUPT_REG, imask);
1693         if (imask & (HC_ATL_INT | HC_SOT_INT))
1694                 do_atl_int(hcd);
1695
1696         if (imask & HC_INTL_INT)
1697                 do_intl_int(hcd);
1698
1699         irqret = IRQ_HANDLED;
1700 leave:
1701         spin_unlock(&priv->lock);
1702         return irqret;
1703 }
1704
1705 static int isp1760_hub_status_data(struct usb_hcd *hcd, char *buf)
1706 {
1707         struct isp1760_hcd *priv = hcd_to_priv(hcd);
1708         u32 temp, status = 0;
1709         u32 mask;
1710         int retval = 1;
1711         unsigned long flags;
1712
1713         /* if !USB_SUSPEND, root hub timers won't get shut down ... */
1714         if (!HC_IS_RUNNING(hcd->state))
1715                 return 0;
1716
1717         /* init status to no-changes */
1718         buf[0] = 0;
1719         mask = PORT_CSC;
1720
1721         spin_lock_irqsave(&priv->lock, flags);
1722         temp = reg_read32(hcd->regs, HC_PORTSC1);
1723
1724         if (temp & PORT_OWNER) {
1725                 if (temp & PORT_CSC) {
1726                         temp &= ~PORT_CSC;
1727                         reg_write32(hcd->regs, HC_PORTSC1, temp);
1728                         goto done;
1729                 }
1730         }
1731
1732         /*
1733          * Return status information even for ports with OWNER set.
1734          * Otherwise khubd wouldn't see the disconnect event when a
1735          * high-speed device is switched over to the companion
1736          * controller by the user.
1737          */
1738
1739         if ((temp & mask) != 0
1740                         || ((temp & PORT_RESUME) != 0
1741                                 && time_after_eq(jiffies,
1742                                         priv->reset_done))) {
1743                 buf [0] |= 1 << (0 + 1);
1744                 status = STS_PCD;
1745         }
1746         /* FIXME autosuspend idle root hubs */
1747 done:
1748         spin_unlock_irqrestore(&priv->lock, flags);
1749         return status ? retval : 0;
1750 }
1751
1752 static void isp1760_hub_descriptor(struct isp1760_hcd *priv,
1753                 struct usb_hub_descriptor *desc)
1754 {
1755         int ports = HCS_N_PORTS(priv->hcs_params);
1756         u16 temp;
1757
1758         desc->bDescriptorType = 0x29;
1759         /* priv 1.0, 2.3.9 says 20ms max */
1760         desc->bPwrOn2PwrGood = 10;
1761         desc->bHubContrCurrent = 0;
1762
1763         desc->bNbrPorts = ports;
1764         temp = 1 + (ports / 8);
1765         desc->bDescLength = 7 + 2 * temp;
1766
1767         /* two bitmaps:  ports removable, and usb 1.0 legacy PortPwrCtrlMask */
1768         memset(&desc->bitmap[0], 0, temp);
1769         memset(&desc->bitmap[temp], 0xff, temp);
1770
1771         /* per-port overcurrent reporting */
1772         temp = 0x0008;
1773         if (HCS_PPC(priv->hcs_params))
1774                 /* per-port power control */
1775                 temp |= 0x0001;
1776         else
1777                 /* no power switching */
1778                 temp |= 0x0002;
1779         desc->wHubCharacteristics = cpu_to_le16(temp);
1780 }
1781
1782 #define PORT_WAKE_BITS  (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E)
1783
1784 static int check_reset_complete(struct usb_hcd *hcd, int index,
1785                 int port_status)
1786 {
1787         if (!(port_status & PORT_CONNECT))
1788                 return port_status;
1789
1790         /* if reset finished and it's still not enabled -- handoff */
1791         if (!(port_status & PORT_PE)) {
1792
1793                 dev_err(hcd->self.controller,
1794                                         "port %d full speed --> companion\n",
1795                                         index + 1);
1796
1797                 port_status |= PORT_OWNER;
1798                 port_status &= ~PORT_RWC_BITS;
1799                 reg_write32(hcd->regs, HC_PORTSC1, port_status);
1800
1801         } else
1802                 dev_err(hcd->self.controller, "port %d high speed\n",
1803                                                                 index + 1);
1804
1805         return port_status;
1806 }
1807
1808 static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq,
1809                 u16 wValue, u16 wIndex, char *buf, u16 wLength)
1810 {
1811         struct isp1760_hcd *priv = hcd_to_priv(hcd);
1812         int ports = HCS_N_PORTS(priv->hcs_params);
1813         u32 temp, status;
1814         unsigned long flags;
1815         int retval = 0;
1816         unsigned selector;
1817
1818         /*
1819          * FIXME:  support SetPortFeatures USB_PORT_FEAT_INDICATOR.
1820          * HCS_INDICATOR may say we can change LEDs to off/amber/green.
1821          * (track current state ourselves) ... blink for diagnostics,
1822          * power, "this is the one", etc.  EHCI spec supports this.
1823          */
1824
1825         spin_lock_irqsave(&priv->lock, flags);
1826         switch (typeReq) {
1827         case ClearHubFeature:
1828                 switch (wValue) {
1829                 case C_HUB_LOCAL_POWER:
1830                 case C_HUB_OVER_CURRENT:
1831                         /* no hub-wide feature/status flags */
1832                         break;
1833                 default:
1834                         goto error;
1835                 }
1836                 break;
1837         case ClearPortFeature:
1838                 if (!wIndex || wIndex > ports)
1839                         goto error;
1840                 wIndex--;
1841                 temp = reg_read32(hcd->regs, HC_PORTSC1);
1842
1843                 /*
1844                  * Even if OWNER is set, so the port is owned by the
1845                  * companion controller, khubd needs to be able to clear
1846                  * the port-change status bits (especially
1847                  * USB_PORT_STAT_C_CONNECTION).
1848                  */
1849
1850                 switch (wValue) {
1851                 case USB_PORT_FEAT_ENABLE:
1852                         reg_write32(hcd->regs, HC_PORTSC1, temp & ~PORT_PE);
1853                         break;
1854                 case USB_PORT_FEAT_C_ENABLE:
1855                         /* XXX error? */
1856                         break;
1857                 case USB_PORT_FEAT_SUSPEND:
1858                         if (temp & PORT_RESET)
1859                                 goto error;
1860
1861                         if (temp & PORT_SUSPEND) {
1862                                 if ((temp & PORT_PE) == 0)
1863                                         goto error;
1864                                 /* resume signaling for 20 msec */
1865                                 temp &= ~(PORT_RWC_BITS);
1866                                 reg_write32(hcd->regs, HC_PORTSC1,
1867                                                         temp | PORT_RESUME);
1868                                 priv->reset_done = jiffies +
1869                                         msecs_to_jiffies(20);
1870                         }
1871                         break;
1872                 case USB_PORT_FEAT_C_SUSPEND:
1873                         /* we auto-clear this feature */
1874                         break;
1875                 case USB_PORT_FEAT_POWER:
1876                         if (HCS_PPC(priv->hcs_params))
1877                                 reg_write32(hcd->regs, HC_PORTSC1,
1878                                                         temp & ~PORT_POWER);
1879                         break;
1880                 case USB_PORT_FEAT_C_CONNECTION:
1881                         reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_CSC);
1882                         break;
1883                 case USB_PORT_FEAT_C_OVER_CURRENT:
1884                         /* XXX error ?*/
1885                         break;
1886                 case USB_PORT_FEAT_C_RESET:
1887                         /* GetPortStatus clears reset */
1888                         break;
1889                 default:
1890                         goto error;
1891                 }
1892                 reg_read32(hcd->regs, HC_USBCMD);
1893                 break;
1894         case GetHubDescriptor:
1895                 isp1760_hub_descriptor(priv, (struct usb_hub_descriptor *)
1896                         buf);
1897                 break;
1898         case GetHubStatus:
1899                 /* no hub-wide feature/status flags */
1900                 memset(buf, 0, 4);
1901                 break;
1902         case GetPortStatus:
1903                 if (!wIndex || wIndex > ports)
1904                         goto error;
1905                 wIndex--;
1906                 status = 0;
1907                 temp = reg_read32(hcd->regs, HC_PORTSC1);
1908
1909                 /* wPortChange bits */
1910                 if (temp & PORT_CSC)
1911                         status |= USB_PORT_STAT_C_CONNECTION << 16;
1912
1913
1914                 /* whoever resumes must GetPortStatus to complete it!! */
1915                 if (temp & PORT_RESUME) {
1916                         dev_err(hcd->self.controller, "Port resume should be skipped.\n");
1917
1918                         /* Remote Wakeup received? */
1919                         if (!priv->reset_done) {
1920                                 /* resume signaling for 20 msec */
1921                                 priv->reset_done = jiffies
1922                                                 + msecs_to_jiffies(20);
1923                                 /* check the port again */
1924                                 mod_timer(&hcd->rh_timer, priv->reset_done);
1925                         }
1926
1927                         /* resume completed? */
1928                         else if (time_after_eq(jiffies,
1929                                         priv->reset_done)) {
1930                                 status |= USB_PORT_STAT_C_SUSPEND << 16;
1931                                 priv->reset_done = 0;
1932
1933                                 /* stop resume signaling */
1934                                 temp = reg_read32(hcd->regs, HC_PORTSC1);
1935                                 reg_write32(hcd->regs, HC_PORTSC1,
1936                                         temp & ~(PORT_RWC_BITS | PORT_RESUME));
1937                                 retval = handshake(hcd, HC_PORTSC1,
1938                                            PORT_RESUME, 0, 2000 /* 2msec */);
1939                                 if (retval != 0) {
1940                                         dev_err(hcd->self.controller,
1941                                                 "port %d resume error %d\n",
1942                                                 wIndex + 1, retval);
1943                                         goto error;
1944                                 }
1945                                 temp &= ~(PORT_SUSPEND|PORT_RESUME|(3<<10));
1946                         }
1947                 }
1948
1949                 /* whoever resets must GetPortStatus to complete it!! */
1950                 if ((temp & PORT_RESET)
1951                                 && time_after_eq(jiffies,
1952                                         priv->reset_done)) {
1953                         status |= USB_PORT_STAT_C_RESET << 16;
1954                         priv->reset_done = 0;
1955
1956                         /* force reset to complete */
1957                         reg_write32(hcd->regs, HC_PORTSC1, temp & ~PORT_RESET);
1958                         /* REVISIT:  some hardware needs 550+ usec to clear
1959                          * this bit; seems too long to spin routinely...
1960                          */
1961                         retval = handshake(hcd, HC_PORTSC1,
1962                                         PORT_RESET, 0, 750);
1963                         if (retval != 0) {
1964                                 dev_err(hcd->self.controller, "port %d reset error %d\n",
1965                                                 wIndex + 1, retval);
1966                                 goto error;
1967                         }
1968
1969                         /* see what we found out */
1970                         temp = check_reset_complete(hcd, wIndex,
1971                                         reg_read32(hcd->regs, HC_PORTSC1));
1972                 }
1973                 /*
1974                  * Even if OWNER is set, there's no harm letting khubd
1975                  * see the wPortStatus values (they should all be 0 except
1976                  * for PORT_POWER anyway).
1977                  */
1978
1979                 if (temp & PORT_OWNER)
1980                         dev_err(hcd->self.controller, "PORT_OWNER is set\n");
1981
1982                 if (temp & PORT_CONNECT) {
1983                         status |= USB_PORT_STAT_CONNECTION;
1984                         /* status may be from integrated TT */
1985                         status |= USB_PORT_STAT_HIGH_SPEED;
1986                 }
1987                 if (temp & PORT_PE)
1988                         status |= USB_PORT_STAT_ENABLE;
1989                 if (temp & (PORT_SUSPEND|PORT_RESUME))
1990                         status |= USB_PORT_STAT_SUSPEND;
1991                 if (temp & PORT_RESET)
1992                         status |= USB_PORT_STAT_RESET;
1993                 if (temp & PORT_POWER)
1994                         status |= USB_PORT_STAT_POWER;
1995
1996                 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
1997                 break;
1998         case SetHubFeature:
1999                 switch (wValue) {
2000                 case C_HUB_LOCAL_POWER:
2001                 case C_HUB_OVER_CURRENT:
2002                         /* no hub-wide feature/status flags */
2003                         break;
2004                 default:
2005                         goto error;
2006                 }
2007                 break;
2008         case SetPortFeature:
2009                 selector = wIndex >> 8;
2010                 wIndex &= 0xff;
2011                 if (!wIndex || wIndex > ports)
2012                         goto error;
2013                 wIndex--;
2014                 temp = reg_read32(hcd->regs, HC_PORTSC1);
2015                 if (temp & PORT_OWNER)
2016                         break;
2017
2018 /*              temp &= ~PORT_RWC_BITS; */
2019                 switch (wValue) {
2020                 case USB_PORT_FEAT_ENABLE:
2021                         reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_PE);
2022                         break;
2023
2024                 case USB_PORT_FEAT_SUSPEND:
2025                         if ((temp & PORT_PE) == 0
2026                                         || (temp & PORT_RESET) != 0)
2027                                 goto error;
2028
2029                         reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_SUSPEND);
2030                         break;
2031                 case USB_PORT_FEAT_POWER:
2032                         if (HCS_PPC(priv->hcs_params))
2033                                 reg_write32(hcd->regs, HC_PORTSC1,
2034                                                         temp | PORT_POWER);
2035                         break;
2036                 case USB_PORT_FEAT_RESET:
2037                         if (temp & PORT_RESUME)
2038                                 goto error;
2039                         /* line status bits may report this as low speed,
2040                          * which can be fine if this root hub has a
2041                          * transaction translator built in.
2042                          */
2043                         if ((temp & (PORT_PE|PORT_CONNECT)) == PORT_CONNECT
2044                                         && PORT_USB11(temp)) {
2045                                 temp |= PORT_OWNER;
2046                         } else {
2047                                 temp |= PORT_RESET;
2048                                 temp &= ~PORT_PE;
2049
2050                                 /*
2051                                  * caller must wait, then call GetPortStatus
2052                                  * usb 2.0 spec says 50 ms resets on root
2053                                  */
2054                                 priv->reset_done = jiffies +
2055                                         msecs_to_jiffies(50);
2056                         }
2057                         reg_write32(hcd->regs, HC_PORTSC1, temp);
2058                         break;
2059                 default:
2060                         goto error;
2061                 }
2062                 reg_read32(hcd->regs, HC_USBCMD);
2063                 break;
2064
2065         default:
2066 error:
2067                 /* "stall" on error */
2068                 retval = -EPIPE;
2069         }
2070         spin_unlock_irqrestore(&priv->lock, flags);
2071         return retval;
2072 }
2073
2074 static void isp1760_endpoint_disable(struct usb_hcd *hcd,
2075                 struct usb_host_endpoint *ep)
2076 {
2077         struct isp1760_hcd *priv = hcd_to_priv(hcd);
2078         struct isp1760_qh *qh;
2079         struct isp1760_qtd *qtd;
2080         unsigned long flags;
2081
2082         spin_lock_irqsave(&priv->lock, flags);
2083         qh = ep->hcpriv;
2084         if (!qh)
2085                 goto out;
2086
2087         ep->hcpriv = NULL;
2088         do {
2089                 /* more than entry might get removed */
2090                 if (list_empty(&qh->qtd_list))
2091                         break;
2092
2093                 qtd = list_first_entry(&qh->qtd_list, struct isp1760_qtd,
2094                                 qtd_list);
2095
2096                 if (qtd->status & URB_ENQUEUED) {
2097                         spin_unlock_irqrestore(&priv->lock, flags);
2098                         isp1760_urb_dequeue(hcd, qtd->urb, -ECONNRESET);
2099                         spin_lock_irqsave(&priv->lock, flags);
2100                 } else {
2101                         struct urb *urb;
2102
2103                         urb = qtd->urb;
2104                         clean_up_qtdlist(qtd, qh);
2105                         urb->status = -ECONNRESET;
2106                         isp1760_urb_done(hcd, urb);
2107                 }
2108         } while (1);
2109
2110         qh_destroy(qh);
2111         /* remove requests and leak them.
2112          * ATL are pretty fast done, INT could take a while...
2113          * The latter shoule be removed
2114          */
2115 out:
2116         spin_unlock_irqrestore(&priv->lock, flags);
2117 }
2118
2119 static int isp1760_get_frame(struct usb_hcd *hcd)
2120 {
2121         struct isp1760_hcd *priv = hcd_to_priv(hcd);
2122         u32 fr;
2123
2124         fr = reg_read32(hcd->regs, HC_FRINDEX);
2125         return (fr >> 3) % priv->periodic_size;
2126 }
2127
2128 static void isp1760_stop(struct usb_hcd *hcd)
2129 {
2130         struct isp1760_hcd *priv = hcd_to_priv(hcd);
2131         u32 temp;
2132
2133         isp1760_hub_control(hcd, ClearPortFeature, USB_PORT_FEAT_POWER, 1,
2134                         NULL, 0);
2135         mdelay(20);
2136
2137         spin_lock_irq(&priv->lock);
2138         ehci_reset(hcd);
2139         /* Disable IRQ */
2140         temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL);
2141         reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp &= ~HW_GLOBAL_INTR_EN);
2142         spin_unlock_irq(&priv->lock);
2143
2144         reg_write32(hcd->regs, HC_CONFIGFLAG, 0);
2145 }
2146
2147 static void isp1760_shutdown(struct usb_hcd *hcd)
2148 {
2149         u32 command, temp;
2150
2151         isp1760_stop(hcd);
2152         temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL);
2153         reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp &= ~HW_GLOBAL_INTR_EN);
2154
2155         command = reg_read32(hcd->regs, HC_USBCMD);
2156         command &= ~CMD_RUN;
2157         reg_write32(hcd->regs, HC_USBCMD, command);
2158 }
2159
2160 static const struct hc_driver isp1760_hc_driver = {
2161         .description            = "isp1760-hcd",
2162         .product_desc           = "NXP ISP1760 USB Host Controller",
2163         .hcd_priv_size          = sizeof(struct isp1760_hcd),
2164         .irq                    = isp1760_irq,
2165         .flags                  = HCD_MEMORY | HCD_USB2,
2166         .reset                  = isp1760_hc_setup,
2167         .start                  = isp1760_run,
2168         .stop                   = isp1760_stop,
2169         .shutdown               = isp1760_shutdown,
2170         .urb_enqueue            = isp1760_urb_enqueue,
2171         .urb_dequeue            = isp1760_urb_dequeue,
2172         .endpoint_disable       = isp1760_endpoint_disable,
2173         .get_frame_number       = isp1760_get_frame,
2174         .hub_status_data        = isp1760_hub_status_data,
2175         .hub_control            = isp1760_hub_control,
2176 };
2177
2178 int __init init_kmem_once(void)
2179 {
2180         qtd_cachep = kmem_cache_create("isp1760_qtd",
2181                         sizeof(struct isp1760_qtd), 0, SLAB_TEMPORARY |
2182                         SLAB_MEM_SPREAD, NULL);
2183
2184         if (!qtd_cachep)
2185                 return -ENOMEM;
2186
2187         qh_cachep = kmem_cache_create("isp1760_qh", sizeof(struct isp1760_qh),
2188                         0, SLAB_TEMPORARY | SLAB_MEM_SPREAD, NULL);
2189
2190         if (!qh_cachep) {
2191                 kmem_cache_destroy(qtd_cachep);
2192                 return -ENOMEM;
2193         }
2194
2195         return 0;
2196 }
2197
2198 void deinit_kmem_cache(void)
2199 {
2200         kmem_cache_destroy(qtd_cachep);
2201         kmem_cache_destroy(qh_cachep);
2202 }
2203
2204 struct usb_hcd *isp1760_register(phys_addr_t res_start, resource_size_t res_len,
2205                                  int irq, unsigned long irqflags,
2206                                  struct device *dev, const char *busname,
2207                                  unsigned int devflags)
2208 {
2209         struct usb_hcd *hcd;
2210         struct isp1760_hcd *priv;
2211         int ret;
2212
2213         if (usb_disabled())
2214                 return ERR_PTR(-ENODEV);
2215
2216         /* prevent usb-core allocating DMA pages */
2217         dev->dma_mask = NULL;
2218
2219         hcd = usb_create_hcd(&isp1760_hc_driver, dev, dev_name(dev));
2220         if (!hcd)
2221                 return ERR_PTR(-ENOMEM);
2222
2223         priv = hcd_to_priv(hcd);
2224         priv->devflags = devflags;
2225         init_memory(priv);
2226         hcd->regs = ioremap(res_start, res_len);
2227         if (!hcd->regs) {
2228                 ret = -EIO;
2229                 goto err_put;
2230         }
2231
2232         hcd->irq = irq;
2233         hcd->rsrc_start = res_start;
2234         hcd->rsrc_len = res_len;
2235
2236         ret = usb_add_hcd(hcd, irq, irqflags);
2237         if (ret)
2238                 goto err_unmap;
2239
2240         return hcd;
2241
2242 err_unmap:
2243          iounmap(hcd->regs);
2244
2245 err_put:
2246          usb_put_hcd(hcd);
2247
2248          return ERR_PTR(ret);
2249 }
2250
2251 MODULE_DESCRIPTION("Driver for the ISP1760 USB-controller from NXP");
2252 MODULE_AUTHOR("Sebastian Siewior <bigeasy@linuxtronix.de>");
2253 MODULE_LICENSE("GPL v2");